LTC1063 DC Accurate, Clock-Tunable 5th Order Butterworth Lowpass Filter U FEATURES DESCRIPTIO The LTC(R)1063 is the first monolithic filter providing both clock-tunability, low DC output offset and over 12-bit DC accuracy. The frequency response of the LTC1063 closely approximates a 5th order Butterworth polynomial. With appropriate PCB layout techniques the output DC offset is typically 1mV and is constant over a wide range of clock frequencies. With 5V supplies and 4V input voltage range, the CMR of the device is 80dB. Clock-Tunable Cutoff Frequency 1mV DC Offset (Typical) 80dB CMRR (Typical) Internal or External Clock 50VRMS Clock Feedthrough 100:1 Clock-to-Cutoff Frequency Ratio 95VRMS Total Wideband Noise 0.01% THD at 2VRMS Output Level 50kHz Maximum Cutoff Frequency Cascadable for Faster Roll-Off Operates from 2.375 to 8V Power Supplies Self-Clocking with 1 RC Available in 8-Pin DIP and 16-Pin SO Wide Packages U APPLICATIO S The filter cutoff frequency is controlled either by an internal or external clock. The clock-to-cutoff frequency ratio is 100:1. The on-board clock is power supply independent, and it is programmed via an external RC. The 50VRMS clock feedthrough is considerably reduced over existing monolithic filters. The LTC1063 wideband noise is 95VRMS, and it can process large AC input signals with low distortion. With 7.5V supplies, for instance, the filter handles up to 4VRMS (92dB S/N ratio) while the standard 1kHz THD is below 0.02%; 80dB dynamic ranges (S/N +THD) is obtained with input levels between 1VRMS and 2.3VRMS. Audio Strain Gauge Amplifiers Anti-Aliasing Filters Low Level Filtering Digital Voltmeters 60Hz Lowpass Filters Smoothing Filters Reconstruction Filters The LTC1063 is available in 8-pin miniDIP and 16-pin SO wide packages. For a linear phase response, see LTC1065 data sheet. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO Frequency Response 10 2.5kHz 5th Order Lowpass Filter -5V LTC1063 *19.1k -20 VOUT 6 5V 0.1F 5 4 0.1F -10 GAIN (dB) 7 2 3 0 8 VIN** 1 -30 -40 -50 -60 200pF* -70 -80 * SELF-CLOCKING SCHEME ** IF THE INPUT VOLTAGE CAN EXCEED V +, -90 CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V +. 1 10 FREQUENCY (kHz) 100 1063 TA01 1063 TA02 1063fa 1 LTC1063 W W U W ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V + to V -) .......................... 16.5V Power Dissipation ............................................. 400mW Voltage at Any Input .... (V - - 0.3V) VIN (V + + 0.3V) Burn-In Voltage ...................................................... 16V Operating Temperature Range ............... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW VIN 1 8 VOS ADJ GND 2 7 VOUT V- 3 6 V+ CLK OUT 4 5 CLK IN LTC1063CN8 N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 100C, JA = 110C/W (N) J8 PACKAGE 8-LEAD CERAMIC DIP TJMAX = 150C, JA = 100C/W (J) ORDER PART NUMBER TOP VIEW NC 1 16 VOS ADJ VIN 2 15 NC NC 4 13 NC V- 5 12 V + NC 6 11 NC NC 7 10 NC 9 CLK OUT 8 LTC1063CJ8 LTC1063MJ8 LTC1063CSW 14 VOUT GND 3 CLK IN SW PACKAGE 16-LEAD PLASTIC SO WIDE TJMAX = 100C, JA = 85C/W OBSOLETE PACKAGE Consider the N8 Package for Alternate Source Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VS = 5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25C, unless otherwise specified. PARAMETER CONDITIONS Clock-to-Cutoff Frequency Ratio (fCLK / fC) 2.375V VS 7.5V Maximum Clock Frequency (Note 2) VS = 7.5V VS = 5V VS = 2.5V Minimum Clock Frequency (Note 3) 2.5V VS 7.5V, TA < 85C MIN 5 4 3 - 3.5 - 3.6 VS = 5V, fCLK = 500kHz, fC = 5kHz fIN = 100Hz fIN = 1kHz = 0.2fC fIN = 2.5kHz = 0.5fC fIN = 4kHz = 0.8fC UNITS MHz MHz MHz 30 0 VS = 5V, fCLK = 25kHz, fC = 250Hz fIN = 250Hz MAX 100 0.5 Input Frequency Range Filter Gain TYP Hz 0.9fCLK - 3.0 - 3.0 - 2.5 - 2.4 0 - 0.06 - 0.075 - 0.09 - 0.14 - 0.5 - 0.6 - 0.01 - 0.01 0.16 0.16 - 0.2 - 0.2 dB dB dB 0.04 0.055 dB dB 0.41 0.46 dB dB 0.1 0.2 dB dB 1063fa 2 LTC1063 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VS = 5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25C, unless otherwise specified. PARAMETER CONDITIONS MIN fIN = 5kHz = fC MAX UNITS - 3.5 - 3.6 - 3.0 - 3.0 - 2.5 - 2.4 dB dB - 57.5 - 57.0 - 60.0 - 60.0 - 62.0 - 62.5 dB dB - 0.066 - 0.081 0.004 0.004 0.074 0.089 dB dB - 0.24 - 0.29 0.16 0.16 0.56 0.61 dB dB - 0.6 - 0.7 - 0.2 - 0.2 0.2 0.3 dB dB - 3.5 - 3.6 - 3.0 - 3.0 - 2.5 - 2.4 dB dB fIN = 20kHz = 4fC Filter Gain TYP VS = 2.375V, fCLK = 500kHz, fC = 5kHz fIN = 1kHz fIN = 2.5kHz fIN = 4kHz fIN = 5kHz Clock Feedthrough 2.375 VS 7.5V 50 VRMS Wideband Noise (Note 4) 2.375 VS 7.5V, 1Hz < f < fCLK 100 VRMS THD + Wideband Noise (Note 5) VS = 7.5V, fC = 20kHz, fIN = 1kHz, 1VRMS VIN 2.3VRMS -80 dB Filter Output DC Swing VS = 2.375V 1.6/- 2.0 1.4/- 1.8 1.7/- 2.2 V V 4.0/- 4.5 3.8/- 4.3 4.3/- 4.8 V V 6.5/- 7.0 6.3/- 6.8 6.8/- 7.3 V V VS = 5V VS = 7.5V Input Bias Current 10 nA Dynamic Input Impedance 800 M VS = 2.375V VS = 5V VS = 7.5V 2 0 -4 Output DC Offset Drift VS = 2.375V VS = 5V VS = 7.5V 10 20 25 Self-Clocking Frequency (fOSC) R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF VS = 2.375V Output DC Offset (Note 6) mV mV mV V/C V/C V/C 99 95 105 103 112 114 kHz kHz 102 98 108 106 114 114 kHz kHz 104 101 110 109 116 116 kHz kHz VS = 5V VS = 7.5V External CLK Pin Logic Thresholds 5 VS = 2.375V Min Logical "1" Max Logical "0" 1.43 0.47 V V VS = 5V Min Logical "1" Max Logical "0" 3 1 V V VS = 7.5V Min Logical "1" Max Logical "0" 4.5 1.5 V V 1063fa 3 LTC1063 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VS = 5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25C, unless otherwise specified. PARAMETER CONDITIONS MIN Power Supply Current VS = 2.375V, fCLK = 500kHz TYP MAX UNITS 2.7 4.0 5.5 mA mA VS = 5V, fCLK = 500kHz 5.5 8 11 mA mA 7.0 11 14.5 mA mA VS = 7.5V, fCLK = 500kHz Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The maximum clock frequency criterion is arbitrarily defined as: The frequency at which the filter AC response exhibits 1dB of gain peaking. Note 3: At limited temperature ranges (i.e., TA 50C) the minimum clock frequency can be as low as 10Hz. The minimum clock frequency is arbitrarily defined as: the clock frequency at which the output DC offset changes by more than 1mV. Note 4: The wideband noise specification does not include the clock feedthrough. Note 5: To properly evaluate the filter's harmonic distortion an inverting output buffer is recommended as shown in the Test Circuit. An output buffer is not necessarily needed when measuring output DC offset or wideband noise. Note 6: The output DC offset is optimized for 5V supply. The output DC offset shifts when the power supplies change; however this phenomenon is repeatable and predictable. U W TYPICAL PERFOR A CE CHARACTERISTICS Output Offset vs Clock, Low Clock Rates Self-Clocking Frequency vs R 110 50 100 45 Output Offset vs Clock, Medium Clock Rates 5 VS = 5V 4 VS = 7.5V LTC1063 5 80 R C = 200pF fOSC 1/RC 70 C 60 50 40 30 35 30 25 20 15 B 5 100 300 FREQUENCY (kHz) 500 1063 G01 0 2 1 VS = 5V 0 -1 -2 -3 10 20 10 3 A: TA = 25C B: TA = 85C OUTPUT OFFSET (mV) 4 40 OUTPUT OFFSET (mV) R PINS 4 TO 5 (k) 90 -5 10 VS = 2.5V -4 A 110 EXTERNAL CLOCK FREQUENCY (Hz) 210 1063 G02 0 500 1000 EXTERNAL CLOCK FREQUENCY (kHz) 1063 G03 1063fa 4 LTC1063 U W TYPICAL PERFOR A CE CHARACTERISTICS Gain vs Frequency; VS = 5V Gain vs Frequency; VS = 2.5V 10 10 0 0 0 -10 -10 -10 -40 -50 B C A. fCLK = 0.5MHz B. fCLK = 1MHz C. fCLK = 2MHz -60 -30 A -40 B C D A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz -50 -60 VIN = 750mVRMS TA = 25C -80 1 10 INPUT FREQUENCY (kHz) 100 200 A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz E. fCLK = 5MHz -40 -50 VIN = 2.5VRMS TA = 25C -80 -90 -90 -90 1 10 INPUT FREQUENCY (kHz) 1 100 200 1063 G04 THD + Noise vs Input Voltage; VS = 5V 1 1 fIN = 1kHz, TA = 25C 5 REPRESENTATIVE UNITS VIN = 0.75VRMS fC = 5kHz, fCLK = 500kHz S/N = 78dB, TA = 25C 5 REPRESENTATIVE UNITS 0.1 fIN = 1kHz, TA = 25C 5 REPRESENTATIVE UNITS THD (%) THD + NOISE (%) 0.1 A 0.01 0.01 0.1 B A 0.01 A. fC = 5kHz, fCLK = 0.5MHz B. fC = 10kHz, fCLK = 1MHz A. fC = 10kHz, fCLK = 1MHz B. fC = 20kHz, fCLK = 2MHz 0.001 1 100 200 1063 G06 THD vs Frequency; VS = Single 5V 1 0.001 0.1 10 INPUT FREQUENCY (kHz) 1063 G05 THD + Noise vs Input Voltage; VS = Single 5V B E -70 VIN = 1.5VRMS TA = 25C -80 B C -30 -60 -70 -70 THD + NOISE (%) GAIN (dB) A GAIN (dB) -30 D A -20 -20 -20 GAIN (dB) Gain vs Frequency; VS = 7.5V 10 1 5 INPUT (VRMS) 2 3 FREQUENCY (kHz) 5 4 1063 G07 0.001 0.1 1063 G08 THD vs Frequency; VS = 7.5V 1 1 VIN = 1.5VRMS fC = 10kHz, fCLK = 1MHz S/N = 83.5dB, TA = 25C 5 REPRESENTATIVE UNITS 1 VIN = 2.5VRMS fC = 10kHz, fCLK = 1MHz S/N = 88dB, TA = 25C 5 REPRESENTATIVE UNITS THD (%) 0.1 0.1 THD (%) THD + NOISE (%) fIN = 1kHz, TA = 25C 5 REPRESENTATIVE UNITS 0.01 5 1063 G09 THD + Noise vs Input Voltage; VS = 7.5V THD vs Frequency; VS = 5V 0.1 1 INPUT (VRMS) B A 0.01 0.01 A. fC = 10kHz, fCLK = 1MHz B. fC = 20kHz, fCLK = 2MHz 0.001 1 5 FREQUENCY (kHz) 10 0.001 0.1 0.001 1 5 INPUT (VRMS) 1063 G10 1063 G11 1 5 FREQUENCY (kHz) 10 1063 G12 1063fa 5 LTC1063 U W TYPICAL PERFOR A CE CHARACTERISTICS Passband Gain and Phase vs Input Frequency Phase Matching 2.5V VS 7.5V, TA = 25C 1.1 -20 -1 -60 A -2 PHASE B B -100 PHASE -3 -140 -4 -180 fCLK =100kHz fC =1kHz -5 -6 100 fCLK =1MHz fC =10kHz -220 -260 100k 1k 10k INPUT FREQUENCY (Hz) 1.0 PHASE MISMATCH (DEG) 0 A 1.2 0 PHASE (DEG) PASSBAND GAIN (dB) 1 0.9 VS = 7.5V VIN = 1VRMS fCLK = 2MHz fC = 20kHz 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 INPUT FREQUENCY (kHz) 1063 G14 1063 G13 Power Supply Current vs Power Supply Voltage Transient Response 10 -40C POWER SUPPLY CURRENT (mA) 9 8 7 25C 6 85C 5 4 3 2 HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV VS = 5V, fC = 10kHz, VIN = 1kHz 3VP SQUARE WAVE 1 0 0 2 4 6 8 10 12 14 16 18 20 TOTAL POWER SUPPLY VOLTAGE (V) 1063 G16 1063 G15 1063fa 6 LTC1063 U U U PI FU CTIO S Power Supply Pins (Pins 6, 3, N Package) The positive and negative supply pin should be bypassed with a high quality 0.1F ceramic capacitor. In applications where the clock pin (5) is externally swept to provide several cutoff frequencies, the output DC offset variation is minimized by connecting an additional 1F solid tantalum capacitor in parallel with the 0.1F disc ceramic. This technique was used to generate the graphs of the output DC offset variation versus clock; they are illustrated in the Typical Performance Characteristics section. When the power supply voltage exceeds 7V, and when V - is applied before V +, if V+ is allowed to go below ground, connect a signal diode between the positive supply pin and ground to prevent latch-up (see Typical Applications). Ground Pin (Pin 2, N Package) The ground pin merges the internal analog and digital ground paths. The potential of the ground pin is the reference for the internal switched-capacitor resistors, and the reference for the external clock. The positive input of the internal op amp is also tied to the ground pin. DC level. The DC gain from the VOS adjust pin to the filter output pin equals two. Any DC voltage applied to this pin will reflect at the output pin of the filter multiplied by two. If the VOS adjust pin is not used, it should be shorted to the ground pin. The DC bias current flowing into the VOS adjust pin is typically 10pA. Pin 8 should always be connected to an AC ground; AC signals applied to this pin will degrade the filter response. Input Pin (Pin 1, N Package) Pin 1 is the filter input and it is connected to an internal switched-capacitor resistor. If the input pin is left floating, the filter output will saturate. The DC input impedance of pin 1 is very high; with 5V supplies and 1MHz clock, the DC input impedance is typically 1G. A resistor, RIN, in series, with the input pin will not alter the value of the filter's DC output offset (Figure 1). RIN should, however, be limited to a maximum value (Table 1), otherwise the filter's passband flatness will be affected. Refer to the Applications Information section for more details. For dual supply operation, the ground pin should be connected to a high quality AC and DC ground. A ground plane, if possible, should be used. A poor ground will degrade DC offset and it will increase clock feedthrough, noise and distortion. A small amount of AC current flows out of the ground pin whether or not the internal oscillator is used. The frequency of the ground current equals the frequency of the internal or external clock. The average value of this current is approximately 55A, 110A, 170A for 2.5V, 5V and 7.5V supplies respectively. For single supply operation, the ground pin should be preferably biased at half supply (see Typical Applications). VOS Adjust Pin (Pin 8, N Package) The VOS adjust pin can be used to trim any small amount of output DC offset voltage or to introduce a desired output VIN RIN 1 8 7 2 3 V- LTC1063 6 VOUT V+ 5 f CLK 4 1063 F01 Figure 1. Table 1. RIN(MAX) vs Clock and Power Supply RIN(MAX) VS = 7.5V VS = 5V VS = 2.5V fCLK = 4MHz 2.2k - - fCLK = 3MHz 3.4k 2.9k - fCLK = 2MHz fCLK = 1MHz fCLK = 500kHz fCLK = 100kHz 5.5k 11k 24k 120k 5k 11k 23k 120k 2.7k 9.2k 21k 110k 1063fa 7 LTC1063 U U U PI FU CTIO S Output Pin (Pin 7, N Package) Clock Output Pin (Pin 4, N Package) Pin 7 is the filter output. This pin can typically source over 20mA and sink 2mA. Pin 7 should not drive long coax cables, otherwise the filter's total harmonic distortion will degrade. Any external clock applied to the clock input pin appears at the clock output pin. The duty cycle of the clock output equals the duty cycle of the external clock applied to the clock input pin. The clock output pin swings to the power supply rails. When the LTC1063 is used in a self-clocking mode, the clock of the internal oscillator appears at the clock output pin with a 30% duty cycle. The clock output pin can be used to drive other LTC1063s or other ICs. The maximum capacitance, CL(MAX), the clock output pin can drive is illustrated in Figure 2. Clock Input Pin (Pin 5, N Package) An external clock when applied to pin 5 tunes the filter cutoff frequency. The clock-to-cutoff frequency ratio is 100:1. The high (VHIGH) and low (VLOW) clock logic threshold levels are illustrated in Table 2. Square wave clocks with duty cycles between 30% and 50% are strongly recommended. Sinewave clocks are not recommended. MAXIMUM LOAD CAPACITANCE (pF ) 200 Table 2. Clock Pin Threshold Levels POWER SUPPLY VS = 2.5V VS = 5V VS = 7.5V VS = 8V VS = 5V, 0V VS = 12, 0V VS =15V, 0V VHIGH 1.5V 3V 4.5V 4.8V 4V 9.6V 12V VLOW 0.5V 1V 1.5V 1.6V 3V 7.2V 9V VS = 2.5V 180 TA = 25C 160 140 120 VS = 5V 100 VS = 7.5V 80 60 40 20 0 1 3 2 4 5 6 7 8 9 10 CLOCK FREQUENCY (MHz) 1063 F02 Figure 2. Maximum Load Capacitance at the Clock Output Pin TEST CIRCUIT + VOUT LT1022 VIN 1 8 2 7 3 V- 4 LTC1063 - 50k 50k 6 V+ 5 0.1F 20pF 0.1F CLOCK IN 1063 TC01 Figure 3. Test Circuit for THD 1063fa 8 LTC1063 U W U U APPLICATIO S I FOR ATIO The LTC1063 features an internal oscillator which can be tuned via an external RC. The LTC1063's internal oscillator is primarily intended for generation of clock frequencies below 500kHz. The first curve of the Typical Performance Characteristics section shows how to quickly choose the value of the RC for a given frequency. More precisely, the frequency of the internal oscillator is equal to: fCLK = K/RC For clock frequencies (fCLK) below 100kHz, K equals 1.07. Figure 4b shows the variation of the parameter K versus clock frequency and power supply. First choose the desired clock frequency, (fCLK < 500kHz), then through Figure 4b pick the right value of K, set C = 200pF and solve for R. Note a 4pF parasitic capacitance is assumed in parallel with the external 200pF timing capacitor. Figure 5 shows the clock frequency variation from - 40C to 85C. The 200kHz clock of Example 1 will change by -1.75% at 85C. 4 C = 200pF 3 fCLK CHANGE NORMALIZED TO ITS 25C VALUE (%) Self-Clocking Operation 2 VS = 2.5V 1 R = (1.0)/(200kHz x 204pF) = 24.5k. VIN 8 1 7 2 3 V- LTC1063 6 VOUT V+ 5 4 R VS = 7.5V TA = 85C -1 VS = 7.5V -2 C 1063 F04a -4 0 100 300 400 200 CLOCK FREQUENCY (kHz) 500 1063 F05 Figure 5. fCLK vs Temperature For a very limited temperature range, the internal oscillator of the LTC1063 can be used to generate clock frequencies above 500kHz (Figures 6 and 7). The data of Figure 6 is derived from several devices. For a given external (RC) value, the observed device-to-device clock frequency variation was 1% (VS = 5V), and 1.25% for VS = 2.5V. fCUTOFF = 20kHz, fCLK = 2MHz, VS = 7.5V, TA = 25C, C = 10pF from Figure 6, K = 0.575, and, R = (0.575)/(2MHz x 14pF) = 20.5k. 0.80 1.25 1.15 VS = 5V VS = 2.5V -3 Example 2: Figure 4a. 1.20 VS = 5V 0 Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = 5V, TA = 25C, K = 1.0, C = 200pF then, TA = -40C FCLK = K/RC C = 200pF TA = 25C fCLK = K/RC C = 10pF TA = 25C 0.75 0.70 1.10 0.65 1.00 VS = 7.5V 0.95 0.90 0.85 K K 1.05 VS = 5V VS = 5V 0.55 0.50 VS = 2.5V VS = 2.5V 0.45 0.80 0.75 VS = 7.5V 0.60 400 100 300 500 200 INTERNAL CLOCK FREQUENCY (kHz) 0.40 0.5 1.0 2.0 2.5 1.5 CLOCK FREQUENCY (MHz) 3.0 1063 F06 1063 F04b Figure 4b. fCLK vs K Figure 6. fCLK vs K 1063fa 9 LTC1063 U W U U APPLICATIO S I FOR ATIO 0.80 Common Mode Rejection Ratio fCLK = K/RC C = 10pF TA = 70C 0.75 0.70 The common mode rejection ratio is defined as the change of the output DC offset with respect to the DC change of the input voltage applied to the filter. K 0.65 0.60 VS = 7.5V CMRR = 20log (VOS OUT /VIN)(dB) 0.55 VS = 5V 0.50 0.45 0.40 0.5 VS = 2.5V 1.0 2.0 2.5 1.5 CLOCK FREQUENCY (MHz) 3.0 Table 3 illustrates the common mode rejection for three power supplies and three temperatures. The common mode rejection improves if the output offset is adjusted to approximately 0V. The output offset can be adjusted via pin 8 (N package) (see Typical Applications). 1063 F07 Figure 7. fCLK vs K A 4pF parasitic capacitance is assumed in parallel with the external 10pF capacitor. A 1% clock frequency variation from device to device can be expected. The 2MHz clock frequency designed above will typically drift to 1.74MHz at 70C (Figure 7). The internal clock of the LTC1063 can be overridden by an external clock provided that the external clock source can drive the timing capacitor, C, which is connected from the clock input pin to ground. Output Offset The DC output offset of the LTC1063 is trimmed to typically less than 1mV . The trimming is done at VS = 5V. To obtain optimum DC offset performance, appropriate PC layout techniques should be used and the filter IC should be soldered to the PC board. A socket will degrade the output DC offset by typically 1mV. The output DC offset is sensitive to the coupling of the clock output pin 4 (N package) to the negative power supply pin 3 (N package). The negative supply pin should be well decoupled. When the surface mount package is used, all the unused pins should be grounded. When the power supplies are fixed, the output DC offset should not change by more than 100V over 10Hz to 1MHz clock frequency variation. When the filter clock frequency is fixed, the output DC offset will typically change by - 4mV (2mV) when the power supply varies from 5V to 7.5V (2.5V). See Typical Performance Characteristics. Table 3. CMRR Data, fCLK = 100kHz POWER SUPPLY VIN - 40C 25C 85C 25C (VOS Nulled) 2.5V 1.8V 76dB 78dB 76dB 85dB 5V 4V 74dB 79dB 75dB 82dB 7.5V 6V 70dB 72dB 74dB 76dB The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for VS = 2.5V, 5V, 7.5V respectively. Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics which are present at the filter's output pin. The clock feedthrough is tested with the filter input grounded and it depends on the quality of the PC board layout and power supply decoupling. Any parasitic switching transients, during the rise and fall of the incoming clock, are not part of the clock feedthrough specifications; their amplitude strongly depends on scope probing techniques as well as ground quality and power supply bypassing. For a power supply VS = 5V, the clock feedthrough of the LTC1063 is 50VRMS; for VS = 7.5V, the clock feedthrough approaches 75VRMS. Figure 8 shows a typical scope photo of the LTC1063 output pin when the input pin is grounded. The filter cutoff frequency was 1kHz, while scope bandwidth was chosen to be 1MHz such as switching transients above the 100kHz clock frequency will show. Wideband Noise The wideband noise of the filter is the RMS value of the device's output noise spectral density. The wideband noise data is used to determine the operating signal-to1063fa 10 LTC1063 U W U U APPLICATIO S I FOR ATIO noise ratio at a given distortion level. The wideband noise (VRMS) is nearly independent of the value of the clock frequency and excludes the clock feedthrough. The LTC1063's typical wideband noise is 95VRMS. Figure 9 shows the same scope photo as Figure 8 but with a more sensitive vertical scale: The clock feedthrough is imbedded in the filter's wideband noise. The peak-to-peak wideband noise of the filter can be clearly seen; it is approximately 500VP-P. Note that 500VP-P equals the 95VRMS wideband noise of the part, multiplied by a crest factor or 5.25. Aliasing Aliasing is an inherent phenomenon of sampled data filters and it primarily occurs when the frequency of an input signal approaches the sampling frequency. For the LTC1063, an input signal whose frequency is in the range of fCLK 6% will generate an alias signal into the filter's passband and stopband. Table 4 shows details. LTC1063, fCLK = 20kHz, fC = 200kHz, fIN = (19.6kHz, 100mVRMS) fALIAS = (400Hz, 3.16mVRMS) Example: An input RC can be used to attenuate incoming signals close to the filter clock frequency (Figure 10). A Butterworth passband response will be maintained if the value of the input resistor follows Table 1. 5mV/DIV Table 4. Aliasing Data INPUT FREQUENCY 2s/DIV fCLK = 100kHz, fC = 1kHz, VS = 5V, 1MHz SCOPE BW 1063 F08 0.5mV/DIV Figure 8. LTC1063 Output Clock Feedthrough + Noise 0.0005 fCLK 0.005 fCLK 0.01 fCLK 0.0125 fCLK 0.015 fCLK 0.0175 fCLK 0.02 fCLK 0.025 fCLK 0.03 fCLK 0.035 fCLK 0.04 fCLK 0.045 fCLK 0.05 fCLK 0.06 fCLK 0.07 fCLK 0.1 fCLK R C fCLK = 100kHz, fC = 1kHz, VS = 5V, 1MHz SCOPE BW OUTPUT FREQUENCY 0.9995fCLK 0.995 fCLK 0.99 fCLK 0.9875fCLK 0.985 fCLK 0.9825fCLK 0.98 fCLK 0.975 fCLK 0.97 fCLK 0.965 fCLK 0.96 fCLK 0.955 fCLK 0.95 fCLK 0.94 fCLK 0.93 fCLK 0.9 fCLK VIN 2s/DIV OUTPUT AMPLITUDE REFERENCED TO INPUT SIGNAL 8 1 7 2 V- 3 0.1F 4 0 dB 0 dB - 3 dB - 10.2 dB - 17.7 dB - 24.3 dB - 30 dB - 40 dB - 48 dB - 54.5 dB - 60.4 dB - 65.5 dB - 70.16 dB - 78.25 dB - 85.3 dB - 100.3 dB LTC1063 VOUT 6 V+ 1063 F09 Figure 9. LTC1063 Output Clock Feedthrough + Noise 5 fCLK 1 f CLK 20 2RC 10 fCLK 0.1F 1063 F10 Figure 10. Adding an Input Anti-Aliasing RC 1063fa 11 LTC1063 U W U U APPLICATIO S I FOR ATIO 100 Group Delay 90 The group delay of the LTC1063 closely approximates the delay of an ideal 5-pole Butterworth lowpass filter (Figure 11, Curve A). To linearize the group delay of the LTC1063 (Figure 11, Curve B), use an input resistor about six times higher than the maximum value of RIN, shown in Table 1. The passband response of the group delay corrected filter approximates a 5-pole Bessel response while its transition band rolls off like a Butterworth. (A) LTC1063 BUTTERWORTH 80 (ms) 70 (B) GROUP DELAY CORRECTED 60 50 40 30 20 0 1 2 3 4 5 6 7 8 INPUT FREQUENCY (kHz) 9 10 1063 F11 Figure 11. Group Delay U TYPICAL APPLICATIO S Adjusting VOS(OUT) for 7.5 Supply Operation Single 5V Supply Operation (fC = 3.4kHz) 7.5V 10k 5V VIN 4.99k 1F TANT + 1 8 2 7 0.1F 3 4.53k LTC1063 6 5 4 10k LT1009 VOUT VIN 5V 0.1F V- -7.5V 13k 200pF 1F TANT 1 8 2 7 3 LTC1063 VOUT V+ 7.5V 6 5 4 + 2.5mV fCLK 0.1F 0.1F * * OPTIONAL, 1N4148 1063 TA03 1063 TA05 Cascading Two LTC1063s for Steeper Roll-Off VIN* 1 8 2 7 3 -5V LTC1063 Sharing Clock for Multichannel Applications VIN* 5V 3 -5V 0.1F C LTC1063 8 2 7 3 -5V 4 LTC1063 5V 0.1F 0.1F R 1 VOUT 6 5 4 0.1F R 7 2 6 5 4 8 1 VIN* VOUT 6 3 0.1F fC (1/RC)(1/100) WIDEBAND NOISE = 140VRMS ATTENUATION AT f = 2fC = 60dB * IF THE INPUT VOLTAGE CAN EXCEED V +, CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V +. 7 2 5 0.1F 8 1 5V -5V 4 C LTC1063 VOUT 6 0.1F 1063 TA04 5V 5 * IF THE INPUT VOLTAGE CAN EXCEED V +, CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V +. 0.1F 1063 TA06 1063fa 12 LTC1063 U PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) CORNER LEADS OPTION (4 PLCS) .023 - .045 (0.584 - 1.143) HALF LEAD OPTION .045 - .068 (1.143 - 1.650) FULL LEAD OPTION .005 (0.127) MIN .405 (10.287) MAX 8 7 6 5 .025 (0.635) RAD TYP .220 - .310 (5.588 - 7.874) 1 .300 BSC (7.62 BSC) 2 3 4 .200 (5.080) MAX .015 - .060 (0.381 - 1.524) .008 - .018 (0.203 - 0.457) 0 - 15 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS .045 - .065 (1.143 - 1.651) .014 - .026 (0.360 - 0.660) .100 (2.54) BSC .125 3.175 MIN J8 0801 OBSOLETE PACKAGE 1063fa 13 LTC1063 U PACKAGE DESCRIPTIO N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 .015* (6.477 0.381) .300 - .325 (7.620 - 8.255) .008 - .015 (0.203 - 0.381) ( +.035 .325 -.015 8.255 +0.889 -0.381 ) .045 - .065 (1.143 - 1.651) .130 .005 (3.302 0.127) .065 (1.651) TYP .100 (2.54) BSC .120 (3.048) .020 MIN (0.508) MIN .018 .003 (0.457 0.076) N8 1002 NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1063fa 14 LTC1063 U PACKAGE DESCRIPTIO SW Package 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 .005 .030 .005 TYP .398 - .413 (10.109 - 10.490) NOTE 4 16 N 15 14 13 12 11 10 9 N .325 .005 .420 MIN .394 - .419 (10.007 - 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 .005 (0.127) RAD MIN .009 - .013 (0.229 - 0.330) .291 - .299 (7.391 - 7.595) NOTE 4 .010 - .029 x 45 (0.254 - 0.737) 3 4 5 6 7 .093 - .104 (2.362 - 2.642) 8 .037 - .045 (0.940 - 1.143) 0 - 8 TYP NOTE 3 .016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN 2 .050 (1.270) BSC .004 - .012 (0.102 - 0.305) .014 - .019 (0.356 - 0.482) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) S16 (WIDE) 0502 1063fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1063 U TYPICAL APPLICATIO S Low Noise DC Accurate Clock-Tunable Notch R1 10k 0.1% 8 2 7 3 -5V 1F TANT 1 LTC1063 4 + - R2 9.53k 0.1% + V+ 5V 6 5 0 fCLK 0.1F 0.1F fCLK 119.04 * fNOTCH = LT1007 -10 GAIN (dB) VIN 81Hz -20 -30 -40 -50 * NOTCH DEPTH > 50dB (LTC1063)VOS * OUPUT DC OFFSET = 500V 2 * OUTPUT NOISE = 50VRMS fNOTCH 10.4 = * f(-20dB)BW 1 fCLK = 100kHz fn = 840Hz -60 -70 215 340 465 590 715 840 965 1090 INPUT FREQUENCY (Hz) 1215 1340 1465 1063 TA07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1065 Clock-Tunable 5th Order Bessel Lowpass Filter 1mV Offset, 80dB CMR LTC1565-31 650kHz Linear Phase Lowpass Filter Continuous Time, Fully Differential In/Out LTC1566-1 Low Noise, 2.3MHz Lowpass Filter Continuous Time, Fully Differential In/Out LT1567 Low Noise Op Amp and Inverter Building Block Single Ended to Differential Conv LT1568 Low Noise, 10MHz 4th Order Building Block Lowpass or Bandpass, Differential Outputs LTC1569-6 Linear Phase, DC Accurate, 10th Order Lowpass Resistor Set Clock, FC < 64kHz LTC1569-7 Linear Phase, DC Accurate, 10th Order Lowpass Resistor Set Clock, FC < 300kHz LT6600-2.5 Low Noise Differential Amp and 10MHz Lowpass 55VRMS Noise 100kHz-10MHz 3V Supply LT6600-10 Low Noise Differential Amp and 20MHz Lowpass 86VRMS Noise 100kHz-20MHz 3V Supply 1063fa 16 Linear Technology Corporation LT/LT 0905 REV A * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 1993