TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUAR Y 2000 – REVISED JULY 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DOpen Drain Power-On Reset With 220-ms
Delay (TPS773xx)
DOpen Drain Power-Good (PG) Status
Output (TPS774xx)
D250-mA Low-Dropout Voltage Regulator
DAvailable in 1.5-V, 1.6-V (TPS77316 Only),
1.8-V, 2.7-V, 2.8-V, 3.3-V, 5.0-V Fixed Output
and Adjustable Versions
DDropout Voltage Typically 200 mV
at 250 mA (TPS77333, TPS77433)
DUltralow 92-µA Quiescent Current (Typ)
D8-Pin MSOP (DGK) Package
DLow Noise (55 µVrms) Without an External
Filter (Bypass) Capacitor (TPS77318,
TPS77418)
D2% Tolerance Over Specified Conditions
For Fixed-Output Versions
DFast Transient Response
DThermal Shutdown Protection
DSee the TPS779xx Family of Devices for
Active High Enable
description
The TPS773xx and TPS774xx are low-dropout
regulators with integrated power-on reset and
power good (PG) function respectively. These
devices are capable of supplying 250 mA of output
current with a dropout of 200 mV (TPS77333,
TPS77433). Quiescent current is 92 µA at full load
dropping down to 1 µA when device is disabled.
These devices are optimized to be stable with a
wide range of output capacitors including low ESR
ceramic (10 µF) or low capacitance (1 µF)
tantalum capacitors. These devices have ex-
tremely low noise output performance (55 µVrms)
without using any added filter capacitors.
TPS773xx and TPS774xx are designed to have
fast transient response for larger load current
changes.
The TPS773xx or TPS774xx is offered in 1.5-V, 1.6 V (TPS77316 only), 1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0-V
fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output
voltage tolerance is 2% over line, load, and temperature ranges. The TPS773xx and TPS774xx families are
available in 8-pin MSOP (DGK) packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
–50
0
50
100
150
200
250
300
–40 0 40 80 120 160
TPS77x33
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
– Dropout Voltage – mV
VDO
IO = 250 mA
IO = 10 mA
IO = 0 A
OUT
OUT
IN
IN
8
7
6
5
1
2
3
4
FB/SENSE
RESET
EN
GND
TPS773xx
DGK Package
(TOP VIEW)
OUT
OUT
IN
IN
8
7
6
5
1
2
3
4
FB/SENSE
PG
EN
GND
TPS774xx
DGK Package
(TOP VIEW)
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV
at an output current of 250 mA for 3.3-volt option) and is directly proportional to the output current. Additionally ,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 92 µA over the full range of output current, 0 mA to 250 mA). These two key
specifications yield a significant improvement in operating life for battery-powered systems.
The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features
a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent
current to less than 1 µA at TJ = 25°C.
The TPS773xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS),
or reset output voltage. The RESET output of the TPS773xx initiates a reset in DSP, microcomputer or
microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in
the TPS773xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated
output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after
a 220-ms delay . RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition)
of its regulated voltage.
For the TPS774xx, the power good terminal (PG) is an active high output, which can be used to implement a
power-on reset or a low-battery indicator . An internal comparator in the TPS774xx monitors the output voltage
of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82%
of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT
is above 82% of its regulated voltage.
AVAILABLE OPTIONS
OUTPUT VOLTAGE (V) PACKAGED DEVICES MSOP (DGK)
TJTYP TPS773xx
SYMBOL TPS774xx
SYMBOL
5.0 TPS77350DGK AGN TPS77450DGK AGW
3.3 TPS77333DGK AGM TPS77433DGK AGV
2.8 TPS77328DGK AGK TPS77428DGK AGT
2.7 TPS77327DGK AGJ TPS77427DGK AGS
–40°C to 125°C1.8 TPS77318DGK AGH TPS77418DGK AGQ
1.6 TPS77316DGK AWF — —
1.5 TPS77315DGK AGG TPS77415DGK AGP
Adjustable
1.5 V to 5.5 V TPS77301DGK AGF TPS77401DGK AGO
NOTE: The TPS77301 and TPS77401 are programmable using an external resistor divider (see application information).
The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77301DGKR).
OUT
SENSE
6
5
3
IN
IN
EN
GND
4
7
1
VI
0.1 µF
10 µF
+
OUT 8VO
PG or RESET Output
PG or
RESET 2
Figure 1. Typical Application Configuration (For Fixed Output Options)
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
adjustable version
220 ms Delay
(for TPS773xx Option)
_
+
Vref = 1.183 V
OUT
FB/SENSE
EN
GND
PG or RESET
_
+
IN
External to the Device
R1
R2
fixed-voltage version
_
+
Vref = 1.183 V
OUT
EN
GND
R1
R2
PG or RESET
_
+
IN
SENSE
220 ms Delay
(for TPS773xx Option)
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
TPS773XX
FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
RESET 2 O Reset output
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 IInput voltage
OUT 7, 8 ORegulated output voltage
TPS774XX
FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
PG 2 O Power good
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 IInput voltage
OUT 7, 8 ORegulated output voltage
TPS773xx RESET timing diagram
†Vres is the minimum input voltage for a valid RESET . The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor
symbology.
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
VI
Vres†
t
t
t
VO
Threshold
Voltage
RESET
Output 220 ms
Delay 220 ms
Delay
Output
Undefined
Output
Undefined
VIT+‡
VIT–‡VIT–‡
VIT+‡
‡VIT – T rip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.
Vres†
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS774xx PG timing diagram
†Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor
symbology.
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
VI
Vres†
t
t
t
VO
Threshold
Voltage
PG
Output
Output
Undefined
Output
Undefined
VIT+‡
VIT–‡VIT–‡
VIT+‡
‡VIT – T rip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage.
Vres†
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range‡, VI –0.3 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at EN –0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum RESET voltage (TPS773xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum PG voltage (TPS774xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO (OUT, FB) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
‡All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES
PACKAGE AIR FLOW
(CFM) θJA
(°C/W) θJC
(°C/W) TA < 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
0 266.2 3.84 376 mW 3.76 mW/°C207 mW 150 mW
DGK 150 255.2 3.92 392 mW 3.92 mW/°C 216 mW 157 mW
DGK
250 242.8 4.21 412 mW 4.12 mW/°C227 mW 165 mW
recommended operating conditions
MIN MAX UNIT
Input voltage, VI§2.7 10 V
Output voltage range, VO1.5 5.5 V
Output current, IO (see Note 1) 0 250 mA
Operating virtual junction temperature, TJ (see Note 1) –40 125 °C
§ To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range (TJ = –40°C to
125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Adjustable 1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C VO
V
Adjustable
voltage 1.5 V ≤ VO ≤ 5.5 V 0.98VO1.02VOV
1 5 V Output
TJ = 25°C, 2.7 V < VIN < 10 V 1.5
V
1.5-V Output 2.7 V < VIN < 10 V 1.470 1.530 V
1 6 V Output
TJ = 25°C, 2.7 V < VIN < 10 V 1.6
V
1.6-V Output 2.7 V < VIN < 10 V 1.568 1.632 V
1 8 V Output
TJ = 25°C, 2.8 V < VIN < 10 V 1.8
Output voltage (see Notes 2 and 4)
1.8-V Output 2.8 V < VIN < 10 V 1.764 1.836
Output voltage (see Notes 2 and 4)
2 7 V Output
TJ = 25°C, 3.7 V < VIN < 10 V 2.7
2.7-V Output 3.7 V < VIN < 10 V 2.646 2.754
V
2 8 V Output
TJ = 25°C, 3.8 V < VIN < 10 V 2.8 V
2.8-V Output 3.8 V < VIN < 10 V 2.744 2.856
3 3 V Output
TJ = 25°C, 4.3 V < VIN < 10 V 3.3
3.3-V Output 4.3 V < VIN < 10 V 3.234 3.366
5 0 V Output
TJ = 25°C, 6.0 V < VIN < 10 V 5.0
V
5.0-V Output 6.0 V < VIN < 10 V 4.900 5.100 V
Quiescent current (GND current) (see Notes 2 and 4)
TJ = 25°C 92
A
Quiescent current (GND current) (see Notes 2 and 4) 125 µA
Output voltage line regulation (∆V/V)(see Note 3)
VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.005 %/V
Output voltage line regulation (∆VO/VO)(see Note 3) VO + 1 V < VI ≤ 10 V 0.05 %/V
Load regulation TJ = 25°C 1 mV
Output noise voltage BW = 300 Hz to 100 kHz, TJ = 25°C,
TPS77318, TPS77418 55 µVrms
Output current limit VO = 0 V 0.9 1.3 A
Peak output current 2 ms pulse width, 50% duty cycle 400 mA
Thermal shutdown junction temperature 144 °C
Standby current
EN = VI, TJ = 25°C 1 µA
Standby current EN = VI3µA
FB input current Adjustable
voltage FB = 1.5 V 1µA
High level enable input voltage 2 V
Low level enable input voltage 0.7 V
Enable input current –1 1 µA
Power supply ripple rejection (TPS77318, TPS77418) f = 1 kHz, TJ = 25°C 55 dB
NOTES: 2. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output
current 1 mA.
3. If VO < 1.8 V then VI(max) = 10 V, VI(min) = 2.7 V:
Line regulation (mV) +ǒ%ńVǓ
VOǒVI(max) *2.7 VǓ
100 1000
If VO > 2.5 V then VI(max) = 10 V, VI(min) = VO + 1 V:
Line regulation (mV) +ǒ%ńVǓ
VOǒVI(max) *ǒVO)1ǓǓ
100 1000
4. IO = 1 mA to 250 mA
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range (TJ = –40°C to
125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Minimum input voltage for valid PG I(PG) = 300 µA, V(PG) ≤ 0.8 V 1.1 V
PG
T rip threshold voltage VO decreasing 79 85 %VO
PG
(TPS774xx)
Hysteresis voltage Measured at VO0.5 %VO
(TPS774
xx
)
Output low voltage VI = 2.7 V, I(PG) = 1 mA 0.15 0.4 V
Leakage current V(PG) = 5 V 1µA
Minimum input voltage for valid RESET I(RESET) = 300 µA 1.1 V
T rip threshold voltage VO decreasing 92 98 %VO
Reset Hysteresis voltage Measured at VO0.5 %VO
Reset
(TPS773xx) Output low voltage VI = 2.7 V, I(RESET) = 1 mA 0.15 0.4 V
Leakage current V(RESET) = 5 V 1µA
RESET time-out delay 220 ms
2 8 V Output
IO = 250 mA, TJ = 25°C 270
V
Dropout voltage (see Note 5)
2.8-V Output IO = 250 mA 475
VDO Dropout voltage (see Note 5)
3 3 V Output
IO = 250 mA, TJ = 25°C 200
mV
3.3-V Output IO = 250 mA 330 mV
V
Dropout voltage (see Note 5)
5 0 V Output
IO = 250 mA, TJ = 25°C 125
VDO Dropout voltage (see Note 5) 5.0-V Output IO = 250 mA 190
NOTE 5: IN voltage equals VO(typ) – 100 mV; 1.5 V, 1.6 V, 1.8-V, and 2.7-V dropout voltage limited by input voltage range limitations (i.e., 3.3
V input voltage needs to drop to 3.2 V for purpose of this test).
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Output voltage
vs Output current 2, 3
VOOutput voltage vs Junction temperature 4, 5
Ground current vs Junction temperature 6
Power supply rejection ratio vs Frequency 7
Output spectral noise density vs Frequency 8
ZoOutput impedance vs Frequency 9
V
Dropout voltage
vs Input voltage 10
VDO Dropout voltage vs Junction temperature 11
Line transient response 12, 14
Load transient response 13, 15
Output voltage and enable pulse vs Time 16
Equivalent series resistance (ESR) vs Output current 18 – 21
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
3.3
3.299
0 50 100 150
3.301
200 250
TPS77x33
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
IO – Output Current – mA
3.302
3.298
– Output Voltage – V
VO
Figure 3
1.800
1.7980 50 100 150
1.802
200 250
TPS77x18
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
IO – Output Current – mA
1.799
1.801
– Output Voltage – V
VO
Figure 4
3.29
3.27
3.25
–40 0 40 80
3.31
3.33
3.35
120 160
TJ – Junction Temperature – °C
TPS77x33
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
VI = 4.3 V
IO = 250 mA
– Output Voltage – V
VO
Figure 5
TJ – Junction Temperature – °C
TPS77x18
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
1.80
1.78
1.76
1.84
1.82
–40 0 40 80 120
VI = 2.8 V
160
IO = 1 mA
IO = 50 mA
IO = 250 mA
1.86
– Output Voltage – V
VO
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
TPS77xxx
GROUND CURRENT
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
Ground Current – Aµ
95
90
85
80
–40 10 60
100
105
115
110 160
110
IO = 1 mA
IO = 250 mA
Figure 6
Figure 7
50
10
20
010 100 1k 10k
PSRR – Power Supply Rejection Ratio – dB
70
90
f – Frequency – Hz
TPS77x33
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
100
100k 10M
80
30
40
60
1M
IO = 1 mA
IO = 250 mA
CO = 10 µF
TJ = 25 °C
Figure 8
TPS77x33
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
f – Frequency – Hz
100 1k 10k 100k
10
1IO = 1 mA
IO = 250 mA
V HzOutput Spectral Noise Density – µ
0.1
0.01
CO = 10 µF
TJ = 25 °C
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
f – Frequency – Hz
– Output Impedance –ZoΩ
10 100 100k 10M
10
1
10k1k
IO = 250 mA
TPS77x33
OUTPUT IMPEDANCE
vs
FREQUENCY
0.1
0.01 1M
TJ = 25 °C
IO = 1 mA
Figure 9
Figure 10
200
150
100
02.7 3.2 3.7 4.2
300
350
400
4.7
250
50
TPS77x01
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
VI – Input Voltage – V
– Dropout Voltage – mV
VDO
TJ = 125 °C
TJ = –40 °C
TJ = 25 °C
IO = 250 mA
Figure 11
–50
0
50
100
150
200
250
300
–40 0 40 80 120 160
TPS77x33
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
– Dropout Voltage – mV
VDO
IO = 250 mA
IO = 10 mA
IO = 0 A
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
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TYPICAL CHARACTERISTICS
Figure 12
TPS77x18
LINE TRANSIENT RESPONSE
t – Time – ms
VO– Change in VI– Input Voltage – V
∆
Output Voltage – mV
3.8
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1
CO = 10 µF
TJ = 25 °C
IO = 250 mA
0
0
2.8
10
–10
Figure 13
TPS77x18
LOAD TRANSIENT RESPONSE
t – Time – ms
VO– Change in IO– Output Current – mA
∆
Output Voltage – mV
250
0.60.40.2 0.8 1 1.41.2 1.6 1.8 2
CO = 10 µF
TJ = 25 °C
IO = 250 mA
0
–50
+50
0
0
Figure 14
TPS77x33
LINE TRANSIENT RESPONSE
t – Time – ms
VO– Change in VI– Input Voltage – V
∆
Output Voltage – mV
5.3
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1
CO = 10 µF
TJ = 25 °C
IO = 250 mA
0
0
4.3
10
–10
Figure 15
TPS77x33
LOAD TRANSIENT RESPONSE
t – Time – ms
VO– Change in∆
Output Voltage – mV
0
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1
CO = 10 µF
TJ = 25 °C
IO = 250 mA
0
0
250
–50
–100
IO– Output Current – mA
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
t – Time – ms
TPS77x33
OUTPUT VOLTAGE AND
ENABLE PULSE
vs
TIME (AT STARTUP)
0 2.0
0
0
EN
0.2 1.81.61.41.21.00.4 0.6 0.8
– Output Voltage – V
VOEnable Pulse – V
CO = 10 µF
TJ = 25 °C
Figure 16
IN
EN
OUT
+
GND CO
ESR
RL
VITo Load
Figure 17. Test Circuit for Typical Regions of Stability (Figures 18 through 21) (Fixed Output Options)
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
0.10 50 100 150 200 250
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO – Output Current – mA
ESR – Equivalent Series Resistance –Ω
1
VO = 3.3 V
CO = 1 µF
VI = 4.3 V
TJ = 25°C
Region of Stability
Region of Instability
Region of Instability
Figure 19
0.1
0 50 100 150 200 250
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO – Output Current – mA
ESR – Equivalent Series Resistance –Ω
1
Region of Stability
Region of Instability
Region of Instability
VO = 3.3 V
CO = 10 µF
VI = 4.3 V
TJ = 25°C
0.01
Figure 20
0.10 50 100 150 200 250
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO – Output Current – mA
ESR – Equivalent Series Resistance –Ω
1
VO = 3.3 V
CO = 1 µF
VI = 4.3 V
TJ = 125 °C
Region of Stability
Region of Instability
Region of Instability
Figure 21
0.1
0 50 100 150 200 250
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO – Output Current – mA
ESR – Equivalent Series Resistance –Ω
1
Region of Stability
Region of Instability
0.01 Region of Instability
VO = 3.3 V
CO = 10 µF
VI = 4.3 V
TJ = 125°C
†Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
pin functions
enable (EN)
The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in
shutdown mode. When EN goes to logic low, then the device will be enabled.
power good (PG) (TPS774xx)
The PG terminal is an open drain, active high output that indicates the status of V out (output of the LDO). When
Vout reaches 82% of the regulated voltage, PG will go to a high-impedance state. It will go to a low-impedance
state when V out falls below 82% (i.e. over load condition) of the regulated voltage. The open drain output of the
PG terminal requires a pullup resistor.
sense (SENSE)
The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier
through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route
the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE
terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate.
feedback (FB)
FB is an input terminal used for the adjustable-output options and must be connected to an external feedback
resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to
minimize/avoid noise pickup. Adding RC networks between FB terminal and Vout to filter noise is not
recommended because it may cause the regulator to oscillate.
reset (RESET) (TPS773xx)
The RESET terminal is an open drain, active low output that indicates the status of Vout. When Vout reaches 95%
of the regulated voltage, RESET will go to a high-impedance state after a 220-ms delay. RESET will go to a
low-impedance state when Vout is below 95% of the regulated voltage. The open-drain output of the RESET
terminal requires a pullup resistor.
external capacitor requirements
An input capacitor is not usually required; however, a bypass capacitor (0.047 µF or larger) improves load
transient response and noise rejection if the TPS773xx or TPS774xx is located more than a few inches from
the power supply. A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Most low noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board
space. The TPS773xx and TPS774xx have very low noise specification requirements without using any external
components.
Like all low dropout regulators, the TPS773xx or TPS774xx requires an output capacitor connected between
OUT (output of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum
recommended capacitance value is 1 µF provided the ESR meets the requirement in Figures 19 and 21. In
addition, a low-ESR capacitor can be used if the capacitance is at least 10 µF and the ESR meets the
requirements in Figures 18 and 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic
capacitors are all suitable, provided they meet the requirements described previously.
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
external capacitor requirements (continued)
Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and
voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type
capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable
over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U
and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature;
therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type
of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the
requirement specified in Figures 18 – 21.
Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
–
+
LDO
VI
VESR
IO
RESR
CO
RLOAD VO
+
–
Figure 22. LDO Output Stage With Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (VCout = Vout). This means no current is flowing into the Cout
branch. If Iout suddenly increases (transient condition), the following occurs:
DThe LDO is not able to supply the sudden current need due to its response time (t1 in Figure 23). Therefore,
capacitor Cout provides the current for the new load condition (dashed arrow). Cout now acts like a battery
with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur
at RESR. This voltage is shown as VESR in Figure 22.
DWhen Cout is conducting current to the load, initial voltage at the load will be V out = VCout – VESR. Due to
the discharge of Cout, the output voltage Vout will drop continuously until the response time t1 of the LDO
is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again
until it reaches the regulated voltage. This period is shown as t2 in Figure 23.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
DThe higher the ESR, the larger the droop at the beginning of load transient.
DThe smaller the output capacitor , the faster the discharge time and the bigger the voltage droop during the
LDO response period.
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
ESR 1
ESR 2
ESR 3
3
1
2
t1t2
Iout
Vout
Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of Vout at a
Load Step From Low-to-High Output Current
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
programming the TPS77x01 adjustable LDO regulator
The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as
shown in Figure 24. The output voltage is calculated using:
VO+Vref ǒ1)R1
R2Ǔ(1
)
Where:
Vref = 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using:
R1 +ǒVO
Vref *1Ǔ R2 (2)
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
UNIT
33.5
53.8
61.5
30.1
30.1
30.1
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VIPG or
RESET
OUT
FB/SENSE
R1
R2
GND
EN
IN
TPS77x01
PG or RESET Output
0.1 µF250 kΩ
CONOTE: To reduce noise and prevent
oscillation, R1 and R2 need to be as
close as possible to the FB/SENSE
terminal.
Figure 24. TPS77x01 Adjustable LDO Regulator Programming
TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
regulator protection
The TPS773xx or TPS774xx PMOS-pass transistor has a built-in back diode that conducts reverse currents
when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from
the output to the input and is not internally limited. When extended reverse voltage is anticipated, external
limiting may be appropriate.
The TPS773xx or TPS774xx also features internal current limiting and thermal protection. During normal
operation, the TPS773xx or TPS774xx limits output current to approximately 0.9 A. When current limiting
engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is
designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of
the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down.
Once the device has cooled below 130°C(typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. T o ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
PD(max) +TJmax *TA
RqJA
Where:
TJmax is the maximum allowable junction temperature.
TA is the ambient temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 266.2°C/W for the 8-terminal
MSOP with no airflow.
The regulator dissipation is calculated using:
PD+ǒVI*VOǓ IO
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77301DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77301DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77301DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77301DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77315DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77315DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77315DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77315DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77316DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77316DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77316DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77316DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77318DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77318DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77318DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77318DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77327DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77327DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77328DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77328DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77333DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77333DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77333DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77333DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77350DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77350DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77350DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77350DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77401DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77401DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77401DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77401DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77415DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77415DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77418DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS77418DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77428DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77428DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77433DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77433DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77433DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77433DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77450DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS77450DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 4
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS77401 :
•Enhanced Product: TPS77401-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS77301DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS77315DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS77316DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS77318DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS77333DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS77350DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS77401DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS77433DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS77301DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TPS77315DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TPS77316DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TPS77318DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TPS77333DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TPS77350DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TPS77401DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TPS77433DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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