VN7E010AJ Datasheet High-side driver with CurrentSense analog feedback for automotive applications Features PowerSSO-16 Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 10.5 m Current limitation (typ) ILIMH 88 A Standby current (max) ISTBY 0.5 A VUSD_cranking 2.85 V Minimum cranking supply voltage (VCC decreasing) * * * * Product status link VN7E010AJ * AEC-Q100 qualified Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013) General - Single channel smart high-side driver with CurrentSense analog feedback - Very low standby current - Compatible with 3 V and 5 V CMOS outputs CurrentSense diagnostic functions - Analog feedback of load current with high precision proportional current mirror - Overload and short to ground (power limitation) indication - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection - Sense enable/disable Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Configurable latch-off on overtemperature or power limitation - Loss of ground and loss of VCC - - Reverse battery with external components Electrostatic discharge protection Applications * * * Automotive resistive, inductive and capacitive loads Protected supply for ADAS systems: radars and sensors Automotive headlamp DS11954 - Rev 5 - November 2018 For further information contact your local STMicroelectronics sales office. www.st.com VN7E010AJ Description The device is a single channel high-side driver manufactured with proprietary ST VIPower(R) M0-7 technology, in a PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A current sense pin delivers high precision proportional load current sense in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module lowpower mode as well as external sense resistor sharing among similar devices. DS11954 - Rev 5 page 2/46 VN7E010AJ Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC VCC -GND Clamp Internal supply Undervoltage shut-down Control & Diagnostic VCC -OUT Clamp FaultRST Gate Driver INPUT T Current Limitation SEn MUX CS Power Limitation Overtemperature Short to VCC Open-Load in OFF Current Sense Fault GND VSENSEH OUTPUT Table 1. Pin functions Name VCC Function Battery connection. OUTPUT Power output; all the pins must be connected together. GND INPUT Ground connection; must be reverse battery protected by an external diode / resistor network. Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs; controls output switch state. CS Analog current sense output pin; delivers a current proportional to the selected load current. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; enables the CS diagnostic pin. Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault - if kept low, sets FaultRST the output to auto-restart mode. DS11954 - Rev 5 page 3/46 VN7E010AJ Block diagram and pin description Figure 2. Configuration diagram (top view) PowerSSO-16 INPUT FaultRST SEn GND N.C. N.C. CS N.C. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT TAB = V CC Note: Pins 9, 10, 11 and 12 are internally connected; Pins 13, 14, 15 and 16 are internally connected; all output pins must be connected together on PCB. Table 2. Suggested connections for unused and not connected pins Connection / pin CS N.C. Output Input SEn, FaultRST Floating Not allowed X (1) X X X To ground Through 1 k resistor X Not allowed Through 15 k resistor Through 15 k resistor 1. X: do not care. DS11954 - Rev 5 page 4/46 VN7E010AJ Electrical specification 2 Electrical specification Figure 3. Current and voltage conventions IS VCC IOUT FaultRST ISEn VCC VFn IFR OUTPUT VOUT ISENSE VFR SEn CS VSEn VSENSE IIN VIN INPUT IGND Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Forcing the device to operate above absolute maximum ratings may cause permanent damage. These are stress ratings only and operation of the device at these or any other conditions outside those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Value Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 ) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT DC output current Internally limited -IOUT Reverse DC output current 35 IIN INPUT DC input current ISEn SEn DC input current IFR FaultRST DC input current ISENSE EMAX DS11954 - Rev 5 Parameter V A -1 to 10 mA -1 to 1.5 mA CS pin DC output current (VGND = VCC and VSENSE < 0 V) 10 CS pin DC output current in reverse (VCC < 0 V) -20 Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 C) 118 mA mJ page 5/46 VN7E010AJ Thermal data Symbol Parameter Value Unit Electrostatic discharge (JEDEC 22A-114F) VESD VESD Tj Tstg 2.2 INPUT 4000 CS, SEn 2000 FaultRST 4000 OUTPUT 4000 VCC 4000 Charge device model (CDM-AEC-Q100-011) 750 Junction operating temperature -40 to 150 Storage temperature -55 to 150 V V C Thermal data Table 4. Thermal data Symbol Parameter Typ. value Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1) 4.2 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(2) 55 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7)(1) 21.4 Rthj-top Thermal resistance junction-top (JEDEC JESD 51-7)(1) 12.1 Unit C/W 1. Device mounted on four-layer 2s2p PCB 2. Device mounted on two-layer 2s0p PCB with 2 cm heatsink copper trace 2.3 Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5. Electrical characteristics during cranking Symbol VUSD_Cranking RON TTSD (1) Parameter Test conditions Min. Typ. Minimum cranking supply voltage (VCC decreasing) On-state resistance IOUT = 1 A; VCC = 2.85 V; VCC decreasing Shutdown temperature (VCC decreasing) VCC = 2.85 V Max. Unit 2.85 V 31.5 m 140 C 1. Parameter guaranteed by design and characterization; not subject to production test Table 6. Power section Symbol VCC Operating supply voltage VUSD Undervoltage shutdown VUSDReset DS11954 - Rev 5 Parameter Undervoltage shutdown reset Test conditions Min. Typ. Max. Unit 4 13 28 V 2.85 V 5 V page 6/46 VN7E010AJ Main electrical characteristics Symbol VUSDhyst Parameter Test conditions Min. Typ. Undervoltage shutdown hysteresis 0.3 IOUT = 5 A; Tj = 25C RON On-state resistance ISTBY tD_STBY IS(ON) IGND(ON) IL(off) (2) VF Clamp voltage Supply current in standby at VCC = 13 V (2) IOUT = 5 A; Tj = 150C IS = 20 mA; Tj = -40C 38 52 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; Tj = 85C (3) 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; Tj = 125C 3 Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = 0 V; VIN = 5 V; IOUT = 5 A 60 VIN = VOUT = 0 V; VCC = 13 V; Tj = 25C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125C 0 V V 0.5 VCC = 13 V; VSEn = VFR = 0 V; VIN = 5 V; IOUT = 0 A Output - VCC diode voltage at Tj = 150C 46 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; Tj = 25C Supply current m 17 41 VCC = 13 V; VIN = 5; VSEn = VFR = 0 V; IOUT = 0 A Off-state output current at VCC = 13 V V 22.5 IS = 20 mA; 25C < Tj < 150C Standby mode blanking time Unit 10.5 IOUT = 5 A; VCC = 4 V; Tj = 25C(1) Vclamp Max. A 300 550 s 3 5 mA 6 mA 0.01 0.5 A 3 IOUT = -5 A; Tj = 150C 0.7 V 1. Parameter guaranteed only at VCC = 4 V and Tj = 25 C 2. PowerMOS leakage included 3. Parameter specified by design; not subject to production test. Table 7. Switching VCC = 13 V; -40C < Tj < 150C, unless otherwise specified Symbol Parameter td(on) (1) Turn-on delay time at Tj = 25 C td(off) (1) Turn-off delay time at Tj = 25 C (dVOUT/dt)on (1) (dVOUT/dt)off (1) WON DS11954 - Rev 5 Turn-on voltage slope at Tj = 25 C Turn-off voltage slope at Tj = 25 C Switching energy losses at turn-on (twon) Test conditions Min. Typ. Max. 10 50 120 10 50 100 0.1 0.25 0.7 0.1 0.3 0.7 -- 0.8 1.2 (2) RL = 2.6 s RL = 2.6 RL = 2.6 Unit V/s mJ page 7/46 VN7E010AJ Main electrical characteristics VCC = 13 V; -40C < Tj < 150C, unless otherwise specified Symbol Parameter Test conditions Min. Typ. Max. Unit WOFF Switching energy losses at turn-off (twoff) RL = 2.6 -- 0.7 1.1(2) mJ tSKEW Differential pulse skew (tPHL tPLH) RL = 2.6 -50 0 +50 s 1. See Figure 6. Switching time and pulse skew 2. Parameter guaranteed by design and characterization; not subject to production test. Table 8. Logic inputs 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V INPUT characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V 5.3 IIN = -1 mA A 7.2 -0.7 V FaultRST characteristics VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V V 5.3 IIN = -1 mA A 7.5 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL DS11954 - Rev 5 Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA IIN = -1 mA V A V 5.3 7.2 -0.7 V page 8/46 VN7E010AJ Main electrical characteristics Table 9. Protections 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter ILIMH DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature TR Reset TRS Thermal reset of fault diagnostic indication Test conditions Thermal hysteresis (TTSD TR)(1) TJ_SD Dynamic temperature Typ. 63 88 VCC = 13 V 4 V < VCC < 18 V Max. Unit 126 (1) A VCC = 13 V; 29 TR < Tj < TTSD temperature(1) THYST Min. 150 175 TRS + 1 TRS + 7 VFR = 0 V; VSEn = 5 V 200 C 135 7 Tj = -40C; VCC = 13 V 60 K VFR = 5 V to 0 V; VSEn = 5 V; tLATCH_RST Fault reset time for output unlatch(1) - E.g. Ch0 3 10 20 s VIN = 5 V VDEMAG Turn-off output voltage clamp IOUT = 2 A; L = 6 mH; Tj = -40C VCC - 38 IOUT = 2 A; L = 6 mH; Tj = 25C to 150C VCC - 41 V VCC - 46 VCC - 52 V Max. Unit 1. Parameter guaranteed by design and characterization; not subject to production test. Table 10. CurrentSense 7 V < VCC < 18 V; -40C < Tj < 150C Symbol VSENSE_CL Parameter CurrentSense clamp voltage Test conditions VSEn = 0 V; ISENSE = 1 mA Min. Typ. -17 VSEn = 0 V; ISENSE = -1 mA -12 7 V CurrentSense characteristics K0 dK0/K0 IOUT/ISENSE (1) (2) K1 IOUT/ISENSE dK1/K1 (1) (2) K2 dK2/K2 CurrentSense ratio drift IOUT/ISENSE (1) (2) K3 dK3/K3 (1) (2) ISENSE_OL DS11954 - Rev 5 CurrentSense ratio drift CurrentSense ratio drift IOUT/ISENSE CurrentSense ratio drift CS current for OL detection IOUT = 0.1 A; VSENSE = 0.5 V; VSEn = 5 V -40% IOUT = 0.25 A; VSENSE = 0.5 V; VSEn = 5 V -25% IOUT = 6 A; VSENSE = 4 V; VSEn = 5 V IOUT = 18 A; VSENSE = 4 V; VSEn = 5 V IOUT = 0.01 A; VSENSE = 0.5 V; VSEn = 5 V 5000 -20 20 5000 -15 -7% 5000 -6 % 7% 6 5000 % 25% 15 -6 -7% +40% % 7% 6 % 11.5 A page 9/46 VN7E010AJ Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions CS disabled: VSEn = 0 V CS disabled: -1 V < VSENSE < 5 V(1) ISENSE0 CurrentSense leakage current CS enabled: VSEn = 5 V; all channel ON; IOUT = 0 A; diagnostic selected; Min. Typ. Max. 0 0.5 -0.5 0.5 0 10 0 2 Unit A VIN = 5 V; IOUT = 0 A CS enabled: VSEn = 5 V; channel OFF; diagnostic selected; VIN = 0 V VOUT_MSD (1) Output voltage for CurrentSense shutdown VIN = 5 V; VSEn = 5 V; RSENSE = 2.7 k; IOUT = 5 A VSENSE_SAT CurrentSense saturation voltage VCC = 7 V; RSENSE = 2.7 k; VSEn = 5 V; VIN = 5 V; IOUT = 18 A; Tj = -40C 4.8 V CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; Tj = 150C 4 mA Output saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; Tj = 150C 22 A ISENSE_SAT (1) IOUT_SAT (1) 5 V OFF-state diagnostic VOL OFF-state open-load voltage detection threshold IL(off2) (3) OFF-state output sink current tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 8. TDSTKON ) tD_OL_V Settling time for valid OFFstate open load diagnostic indication from rising edge of SEn tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VIN = 0 V; VSEn = 0 V VIN = 0 V; VOUT = VOL; Tj = -40C to 125C 2 3 -100 4 V -15 A 700 s 60 s 30 s 6.6 V 30 mA VIN = 5 V to 0 V; VSEn = 5 V; IOUT = 0 A; 100 350 VOUT = 4 V VIN = 0 V; VFR = 0 V; VOUT = 4 V; VSEn = 0 V to 5 V VIN = 0 V; VSEn = 5 V; 5 VOUT = 0 V to 4 V Fault diagnostic feedback (see Table 11. Truth table) VCC = 13 V; VSENSEH CurrentSense output voltage in fault condition VIN = 0 V; VSEn = 5 V; IOUT = 0 A; VOUT = 4 V; 5 RSENSE = 1 k ISENSEH CurrentSense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 CurrentSense timings (current sense mode - see Figure 7. CurrentSense timings (current sense mode))(4) tDSENSE1H DS11954 - Rev 5 Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 k; RL = 2.6 60 s page 10/46 VN7E010AJ Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions tDSENSE1L Current sense disable delay time from falling edge of SEn tDSENSE2H Min. Typ. Max. Unit VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 k; RL = 2.6 5 20 s Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 k; RL = 2.6 100 250 s tDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 k; ISENSE = 90 % of ISENSEMAX; RL = 2.6 100 s tDSENSE2L Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 k; RL = 2.6 250 s 50 1. Parameter specified by design; not subject to production test. 2. All values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. 3. Parameter granted at -40 C < Tj< 125 C 4. Transition delay are measured up to +/- 10% of final conditions. Figure 4. IOUT/ISENSE versus IOUT Max 7500 Min Typ K-factor 6500 5500 4500 3500 2500 0 DS11954 - Rev 5 2 4 6 8 10 IOUT [A] 12 14 16 18 20 page 11/46 VN7E010AJ Main electrical characteristics Figure 5. Current sense accuracy versus IOUT 50 45 40 35 30 Current sense uncalibrated precision % 25 Current sense calibrated precision 20 15 10 5 0 0 2 4 6 8 10 IOUT [A] 12 14 16 18 20 Figure 6. Switching time and pulse skew twon VOUT twoff Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpLH tpHL t DS11954 - Rev 5 page 12/46 VN7E010AJ Main electrical characteristics Figure 7. CurrentSense timings (current sense mode) IN High SEn Low IOUT CURRENT SENSE tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L GAPG1003141014CFT Figure 8. TDSTKON VINPUT VOUT VOUT > VOL MultiSense TDSTKON GAPG2609141140CFT Table 11. Truth table Mode Standby Normal Overload DS11954 - Rev 5 Conditions All logic inputs low Nominal load connected; Tj < 150 C Overload or short to GND causing: Tj > TTSD or Tj > Tj _SD INX FR SEn L OUTX CurrentSense L L L L X H L H H H L X L H L H H Hi-Z Comments Low quiescent current consumption L See (1) See (1) H H L See (1) Outputs configured for auto-restart Outputs configured for Latch-off See (1) Output cycles with temperature hysteresis Output latches-off page 13/46 VN7E010AJ Waveforms Mode Undervoltage OFF-state diagnostics Negative output voltage Conditions VCC < VUSD (falling) INX FR X X Short to VCC L X Open-load L X Inductive loads turn-off L X SEn OUTX CurrentSense X L Hi-Z L Hi-Z H See (1) H See (1) < 0 V See (1) Comments Re-start when VCC > VUSD + VUSDhyst (rising) External pull-up See (1) 1. Refer to Table 12. CurrentSense multiplexer addressing Table 12. CurrentSense multiplexer addressing SEn MUX channel CurrentSense output Normal mode L H Overload OFF-state diag. Negative output VSENSE = VSENSEH Hi-Z Hi-Z output diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH Note: If the output channel for the selected MUX channel is latched off while the relevant input is low, the CS pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; CS = 0. Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH 2.4 Waveforms Figure 9. Latch functionality: behavior in hard short-circuit condition (TAMB << TTSD) DS11954 - Rev 5 page 14/46 VN7E010AJ Waveforms Figure 10. Latch functionality: behavior in hard short-circuit condition Figure 11. Latch functionality: behavior in hard short-circuit condition (autorestart mode + latch off) DS11954 - Rev 5 page 15/46 VN7E010AJ Waveforms Figure 12. Standby mode activation Figure 13. Standby state diagram Normal Operation { t > t D_STBY INx = Low AND FaultRST = Low AND SEn = Low INx = High OR FaultRST = High OR SEn = High Stand-by Mode GAPG1003141053CFT DS11954 - Rev 5 page 16/46 VN7E010AJ Electrical characteristics curves 2.5 Electrical characteristics curves Figure 14. OFF-state output current Iloff [nA] 1800 1600 1400 1200 GADG111020180937OSOC Figure 15. Standby current ISTBY [A] 2 1.8 Off State VCC = 13 V Vin = Vout = 0 VCC = 13 V 1.6 1.4 1.2 1000 1 800 0.8 600 0.6 400 0.4 200 0.2 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 16. IGND(ON) vs. Iout IGND[on] [mA] GADG111020180950IGIO 0 -50 -25 Figure 17. Logic input high level voltage ViH , VFRH , VSELH , VSEnH [V] GADG111020180953LILV 1.4 3 1.2 2.5 1 VCC = 13 V 2 0.8 IOUT = 5 A 1.5 0.6 1 0.4 0.5 0.2 0 25 50 75 100 125 150 175 T [C] Figure 18. Logic input low level voltage VilL ,VFRL ,VSELL ,VSEnL [V] 2 GADG111020180959LILLV 1.8 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 19. High level logic input current IiH ,IFRH ,ISELH ,ISEnH [A] 4 GADG111020181002HLLIC 3.5 1.6 3 1.4 2.5 1.2 1 2 0.8 1.5 0.6 1 0.4 0.5 0.2 0 -50 -25 25 50 75 100 125 150 175 T [C] 1.6 3.5 0 -50 -25 0 1.8 4 DS11954 - Rev 5 GADG111020180943STBC 0 25 50 75 100 125 150 175 T [C] 0 -50 -25 0 25 50 75 100 125 150 175 T [C] page 17/46 VN7E010AJ Electrical characteristics curves Figure 20. Low level logic input current IiL ,IFRL ,ISELL ,ISEnL [A] 4 GADG111020181015LLLIC Figure 21. Logic input hysteresis voltage Vi(hyst) ,VFR(hyst) ,VSEL(hyst), V SEn(hyst) 1 0.8 3 0.7 2.5 0.6 2 0.5 1.5 0.4 0.3 1 0.2 0.5 0.1 0 25 50 75 100 125 150 175 T [C] Figure 22. FaultRST Input clamp voltage VFRCL [V] 8 GADG111020181021FICV 7 6 5 GADG111020181017LIHV 0.9 3.5 0 -50 -25 [V] 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 23. Undervoltage shutdown VUSD [V] 8 GADG111020181024UNSH 7 6 IIN = 1 mA 5 4 4 3 3 2 2 1 IIN = -1 mA 0 -1 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 24. On-state resistance vs. Tcase RDS[on] [m] 50 45 GADG111020181028OSRT IOUT = 5 A 40 VCC = 13 V 35 1 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 25. On-state resistance vs. VCC RDS[on] [m] 25 GADG111020181032ONRV T= 150 C 20 T= 125 C 15 30 25 T= 25 C 10 20 15 T= -40 C 5 10 5 0 -50 -25 DS11954 - Rev 5 0 25 50 75 100 125 150 175 T [C] 0 0 5 10 15 20 25 VCC [V] 30 35 40 page 18/46 VN7E010AJ Electrical characteristics curves Figure 26. Turn-on voltage slope [dVout/dt ]On [V/s] 1 0.9 GADG111020181043TONVS 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 -50 -25 0 25 50 75 100 125 150 175 T [C] 0 -50 -25 Figure 28. Won vs. Tcase Won [mJ] GADG111020181053WONT 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 25 50 75 100 125 150 175 T [C] Figure 29. Woff vs. Tcase Woff [mJ] 1 GADG111020181054WOFFT 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 25 50 75 100 125 150 175 T [C] Ilimh [A] 110 GADG111020181058ILT 105 VCC = 13 V 100 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 31. OFF-state open-load voltage detection threshold VOL [V] 4 GADG111020181101OFFOL 3.5 3 95 2.5 90 2 85 1.5 80 1 75 DS11954 - Rev 5 0 0.9 Figure 30. ILIMH vs. Tcase 70 -50 -25 RI = 2.6 0.7 0.6 GADG111020181047TOFVS VCC = 13 V 0.8 RI = 2.6 0.7 [dVout/dt ]Off [V/s] 1 0.9 VCC = 13 V 0.8 Figure 27. Turn-off voltage slope 0.5 0 25 50 75 100 125 150 T [C] 0 -50 -25 0 25 50 75 100 125 150 T [C] page 19/46 VN7E010AJ Electrical characteristics curves Figure 32. Vsense clamp vs. Tcase VSENSE_CL [V] 10 GADG111020181104VCT Figure 33. Vsenseh vs. Tcase VSENSEH [V] 10 GADG111020181105VST 9 5 IIN = 1 mA 8 7 0 6 5 -5 4 -10 3 2 -15 -20 -50 -25 DS11954 - Rev 5 IIN = -1 mA 0 25 50 75 100 125 150 T [C] 1 0 -50 -25 0 25 50 75 100 125 150 T [C] page 20/46 VN7E010AJ Protections 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of Tj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. DS11954 - Rev 5 page 21/46 VN7E010AJ Application information 4 Application information Figure 34. Application diagram +5V VDD OUT VCC Rprot OUT FaultRST INPUT Rprot OUT Logic OUT Rprot SEn Rprot SEL Dld OUTPUT Rprot ADC in CS Current mirror GND Cext Rsense OUT R GND GND D GND GND GND GND GND GND DS11954 - Rev 5 page 22/46 VN7E010AJ GND protection network against reverse battery 4.1 GND protection network against reverse battery Figure 35. Simplified internal structure 5V Vcc Rprot Rprot INPUT SEn MCU Dld Rprot FaultRST OUTPUT Rprot CS GND Rsense D GND R GND GND 4.1.1 GAPGCFT00830 Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 13. ISO 7637-2 - electrical transient conduction along supply line. Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". DS11954 - Rev 5 page 23/46 VN7E010AJ MCU I/Os protection Table 13. ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US (1) III -112 V 500 pulses 0.5 s III +55 V 500 pulses 0.2 s 5s 50 s, 2 3a IV -220 V 1h 90 ms 100 ms 0.1 s, 50 3b IV +150 V 1h 90 ms 100 ms 0.1 s, 50 IV -7 V 1 pulse 1 2a 4 (3) (2) min max 2 ms, 10 100 ms, 0.01 Load dump according to ISO 16750-2:2010 Test B (3) 40 V 5 pulse 1 min 400 ms, 2 1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. 2. Test pulse from ISO 7637-2:2004(E). 3. With 40 V external suppressor referred to ground (-40C < Tj < 150 C). 4.3 MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20 mA; VOHC 4.5 V 7.5 k Rprot 140 k. Recommended values: Rprot = 15 k 4.4 CS - analog current sense Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the following signals: * Current monitor: current mirror of channel output current Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. DS11954 - Rev 5 page 24/46 VN7E010AJ CS - analog current sense Figure 36. CurrectSense and diagnostic - block diagram VCC VCC - GND Clamp Internal Supply Undervoltage shut-down Control & Diagnostic FaultRST VCC - OUT Clamp INPUT Gate Driver T SEL1 SEL 0 VON Limitation SE n RPROT Current Limitation I SENSE CS Fault Diagnostic MUX Short to VCC Open-Load in OFF To C ADC R SENSE CURRENT MONITOR GND Power Limitation Overtemperature K factor Current Sense Fault IOUT OUT VSENSEH GADG0504171037PS DS11954 - Rev 5 page 25/46 VN7E010AJ CS - analog current sense 4.4.1 Principle of CurrentSense signal generation Figure 37. CurrentSense block diagram Vcc INPUT Sense MOS Main MOS OUT Current sense Current sense Switch Block Fault CS To uC ADC RPROT RSENSE GAPG2307131200CFT Current sense The output is able to provide: * Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to a known ratio named K * Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted into a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by CS output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K Where: * VSENSE is the voltage measurable on RSENSE resistor DS11954 - Rev 5 page 26/46 VN7E010AJ CS - analog current sense * ISENSE is the current provided from CS pin in current output mode * IOUT is the current flowing through output * K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of the overall circuitry, specifying the ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a "current limited" voltage source, VSENSEH. In any case, the current sourced by the CS in this condition is limited to ISENSEH. Figure 38. Analog HSD - open-load detection in off-state +5V Vbat Vbat 100nF/ 50V 100nF Rpull-up GND Microcontroller GND VDD V CC OUT FaultRST 15k INPUT External Pull -Up switch OUT Logic 15k SEn OUT SEL 15k OUT OUTPUT OUTPUT CS Cu rrent mirror 15k GND ADC in 15k Rsense R GN D 4.7k DGN D 10nF /100V OUT 15k GND GND CEXT GND GND GND GND GAPG1201151432CFT DS11954 - Rev 5 page 27/46 VN7E010AJ CS - analog current sense Figure 39. Open-load / short to VCC condition VIN VSENSE VSENSEH Pull-up connected Open-load VSENSE = 0 VSENSE Pull-up disconnected tDSTKON Short to VCC VSENSEH Table 14. CurrentSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL CS SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: DS11954 - Rev 5 page 28/46 VN7E010AJ CS - analog current sense Equation RPU < DS11954 - Rev 5 VPU - 4 IL(off2)min @ 4V page 29/46 VN7E010AJ Maximum demagnetization energy (VCC = 16 V) 5 Maximum demagnetization energy (VCC = 16 V) Figure 41. Maximum turn off current versus inductance 100 10 I (A) VN7E010AJ - Single Pulse Repetitive pulse Tjstart=100C Repetitive pulse Tjstart=125C 1 0.1 L (mH) 1 10 100 1000 Figure 42. Maximum turn off energy versus inductance 10000 1000 EI (mJ) 100 VN7E010AJ - Single Pulse 10 Repetitive pulse Tjstart=100C Repetitive pulse Tjstart=125C 1 0.1 Note: L (mH) 1 10 100 1000 Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DS11954 - Rev 5 page 30/46 VN7E010AJ Package and PCB thermal data 6 Package and PCB thermal data 6.1 PowerSSO-16 thermal data Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) DS11954 - Rev 5 page 31/46 VN7E010AJ PowerSSO-16 thermal data Table 15. PCB properties Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Footprint, 2 cm2 or 8 cm2 Heatsink copper area dimension (bottom layer) Figure 45. Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 90 RTHjamb 80 70 60 50 40 30 0 DS11954 - Rev 5 2 4 6 8 10 page 32/46 VN7E010AJ PowerSSO-16 thermal data Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) 100 ZTH (C/W) 10 1 Cu=foot print Cu=2 cm2 Cu=8 cm2 4 Layer 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T Figure 47. Thermal fitting model of a double-channel HSD in PowerSSO-16 Note: DS11954 - Rev 5 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. page 33/46 VN7E010AJ PowerSSO-16 thermal data Table 16. Thermal parameters DS11954 - Rev 5 Area/island (cm) FP 2 8 4L R1 (C/W) 0.4 R2 (C/W) 3 R3 (C/W) 5.6 5.6 5.6 4 R4 (C/W) 16 6 6 4 R5 (C/W) 30 20 10 3 R6 (C/W) 26 20 18 7 C1 (W*s/C) 0.0007 C2 (W*s/C) 0.009 C3 (W*s/C) 0.13 C4 (W*s/C) 0.2 0.3 0.3 0.4 C5 (W*s/C) 0.4 1 1 4 C6 (W*s/C) 3 5 7 18 page 34/46 VN7E010AJ Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO-16 package information Figure 48. PowerSSO-16 package dimensions ggg D2 D3 Bottom view C A-B D ggg C A-B D minimum solderable area Section A-A E3 E2 h 2 h 1 R1 H B for dual gauge only eee C GAUGE PLANE S A2 A R B L 3 ccc C e L1 SEATING PLANE A1 b ddd C CD 2x f f f C A-B D A N Section B-B D A b WITH PLATING 1.2 for dual gauge only c c1 E1 E index area (0.25D x 0.75E1) b1 2x BASE METAL aaa C D Top view 2x N/2 TIPS bbb C 1 2 3 A N/2 B 8017965_Rev_9 DS11954 - Rev 5 GAPG1605141159CFT page 35/46 VN7E010AJ PowerSSO-16 package information Table 17. PowerSSO-16 mechanical data Symbol Millimeters Min. Typ. Max. 0 8 1 0 2 5 15 3 5 15 A 1.70 A1 0.00 0.10 A2 1.10 1.60 b 0.20 0.30 b1 0.20 c 0.19 c1 0.19 D 0.25 0.28 0.25 0.20 0.23 4.90 BSC D2 3.31 D3 2.61 3.91 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 2.20 E3 1.49 h 0.25 L 0.40 2.80 0.50 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 0.85 Tolerance of form and position DS11954 - Rev 5 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 page 36/46 VN7E010AJ PowerSSO-16 packing information 7.2 PowerSSO-16 packing information Figure 49. PowerSSO-16 reel 13" Access Hole at Slot Location ( 40 mm min.) W2 N D A C W1 B If present, tape slot in core for tape start: 2.5 mm min. width x 10.0 mm min. depth TAPG2004151655CFT Table 18. Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 1. All dimensions are in mm. DS11954 - Rev 5 page 37/46 VN7E010AJ PowerSSO-16 packing information Figure 50. PowerSSO-16 carrier tape P0 P2 4.0 0.1 2.0 0.1 0.30 0.05 X 1.55 0.05 1.75 0.1 1.6 0.1 F W B0 R 0.5 Typical Y K1 Y X K0 P1 A0 SECTION X - X REF 4.18 REF 0.6 REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 19. PowerSSO-16 carrier tape dimensions Description Value(1) A0 6.50 0.1 B0 5.25 0.1 K0 2.10 0.1 K1 1.80 0.1 F 5.50 0.1 P1 8.00 0.1 W 12.00 0.3 1. All dimensions are in mm. Figure 51. PowerSSO-16 schematic drawing of leader and trailer tape Embossed carrier Punched carrier 8 mm & 12 mm only END Carrier tape Round sprocket holes START Top cover tape Elongated sprocket holes (32 mm tape and wider) Trailer 160 mm minimum Top cover tape Components 100 mm min. Leader 400 mm minimum User direction feed GAPG2004151511CFT DS11954 - Rev 5 page 38/46 VN7E010AJ PowerSSO-16 marking information 7.3 PowerSSO-16 marking information Figure 52. PowerSSO-16 marking information Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not to scale) GADG0310161234SMD Parts marked as `&' are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS11954 - Rev 5 page 39/46 VN7E010AJ Ordering information 8 Ordering information Table 20. Ordering information Package VN7E010AJTR DS11954 - Rev 5 Order codes Tape and reel PowerSSO-16 page 40/46 VN7E010AJ Revision history Table 21. Document revision history Date Revision 18-Jan-2017 1 Initial release. 2 Updated Figure 3: "Current and voltage conventions" Updated value for EMAX Table 3: "Absolute maximum ratings" Updated Table 6: "Power section" Updated Table 7: "Switching". Updated Table 10: "CurrentSense" Updated Table 13: "ISO 7637-2 - electrical transient conduction along supply line" 09-Oct-2017 Changes Updated applications in cover page. 19-Jun-2018 3 Updated Table 3. Absolute maximum ratings, Section 2.2 Thermal data and Section 8 Ordering information. Inserted Section 5 Maximum demagnetization energy (VCC = 16 V) and Section 6 Package and PCB thermal data. DS11954 - Rev 5 11-Oct-2018 4 08-Nov-2018 5 Updated Table 5. Electrical characteristics during cranking and Table 7. Switching. Added Section 2.5 Electrical characteristics curves . Updated features in cover page, Table 4. Thermal data and Section 7.1 PowerSSO-16 package information. page 41/46 VN7E010AJ Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.1 Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.1 GND protection network against reverse battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.1 Diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 CS - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.1 Principle of CurrentSense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4.2 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 Maximum demagnetization energy (VCC = 16 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6.1 7 8 PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 7.1 PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 PowerSSO-16 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DS11954 - Rev 5 page 42/46 VN7E010AJ List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested connections for unused and not connected pins . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics during cranking . . . . . . . . . . . . . . . Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrentSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrentSense multiplexer addressing . . . . . . . . . . . . . . . . . ISO 7637-2 - electrical transient conduction along supply line CurrentSense pin levels in off-state . . . . . . . . . . . . . . . . . . PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 carrier tape dimensions . . . . . . . . . . . . . . . . Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . DS11954 - Rev 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 6 . 6 . 6 . 7 . 8 . 9 . 9 13 14 24 28 32 34 36 37 38 40 41 page 43/46 VN7E010AJ List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. DS11954 - Rev 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching time and pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrentSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latch functionality: behavior in hard short-circuit condition (TAMB << TTSD). . . . . . . . . . Latch functionality: behavior in hard short-circuit condition . . . . . . . . . . . . . . . . . . . . . Latch functionality: behavior in hard short-circuit condition (autorestart mode + latch off) Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGND(ON) vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultRST Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF-state open-load voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrectSense and diagnostic - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrentSense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog HSD - open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum turn off energy versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . . . . . . PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 reel 13" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 11 12 12 13 13 14 15 15 16 16 17 17 17 17 17 17 18 18 18 18 18 18 19 19 19 19 19 19 20 20 22 23 25 26 27 28 30 30 31 31 32 33 33 35 37 38 38 page 44/46 VN7E010AJ List of figures Figure 52. DS11954 - Rev 5 PowerSSO-16 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 page 45/46 VN7E010AJ IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved DS11954 - Rev 5 page 46/46