High Performance, 4-/8-Channel, Fault-Protected Analog Multiplexers ADG438F/ADG439F FEATURES FUNCTIONAL BLOCK DIAGRAM All switches off with power supply off Analog output of on channel clamped within power supplies if an overvoltage occurs Latch-up proof construction Fast switching times tON 250 ns maximum tOFF 150 ns maximum Fault and overvoltage protection: -40 V to +55 V Break-before-make construction TTL- and CMOS-compatible inputs ADG438F S1 D S8 APPLICATIONS A0 A1 A2 EN Data acquisition systems Industrial and process control systems Avionics test equipment Signal routing between systems High reliability control systems Figure 1. ADG439F S1A DA S4A GENERAL DESCRIPTION The ADG438F switches one of eight inputs to a common output as determined by the 3-bit binary address lines, A0, A1, and A2. The ADG439F switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines, A0 and A1. An EN input on each device is used to enable or disable the device. When disabled, all channels are switched off. S1B DB S4B 1 OF 4 DECODER A0 A1 EN 00468-101 The ADG438F and ADG439F are CMOS analog multiplexers, with the ADG438F comprising eight single channels and the ADG439F comprising four differential channels. These multiplexers provide fault protection. Using a series n-channel, p-channel, and n-channel MOSFET structure, both device and signal source protection is provided in the event of an overvoltage or power loss. The multiplexer can withstand continuous overvoltage inputs from -40 V to +55 V. During fault conditions with power supplies off, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current flows. This protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources which drive the multiplexer. 00468-001 1 OF 8 DECODER Figure 2. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Fault Protection. The ADG438F and ADG439F can withstand continuous voltage inputs up to -40 V or +55 V. When a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nanoamperes flows. On channel saturates while fault exists. Low RON. Fast Switching Times. Break-Before-Make Switching. Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. Trench Isolation Eliminates Latch-Up. A dielectric trench separates the p-channel and n-channel MOSFETs thereby preventing latch-up. Improved Off Isolation. Trench isolation enhances the channel-to-channel isolation of the ADG438F/ADG439F. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011 Analog Devices, Inc. All rights reserved. ADG438F/ADG439F TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications....................................................................................... 1 Pin Configuration and Function Descriptions..............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Test Circuits........................................................................................9 Product Highlights ........................................................................... 1 Terminology .................................................................................... 12 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 13 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 14 Dual Supply ................................................................................... 3 Ordering Guide .......................................................................... 15 Absolute Maximum Ratings............................................................ 5 REVISION HISTORY 7/11--Rev. D to Rev. E Updated Format..................................................................Universal Changes to Product Highlights Section and General Description ........................................................................................ 1 Changes to Specification Section and Table 1 .............................. 3 Changes to Table 2............................................................................ 5 Added Table 3 and Table 4; Renumbered Sequentially ............... 6 Changes to Figure 5 to Figure 10.................................................... 7 Changes to Figure 11 to Figure 13.................................................. 8 Added Figure 14 to Figure 16.......................................................... 8 Changes to Figure 18 to Figure 20, Figure 23, and Figure 24 ..... 9 Changes to Terminology Section.................................................. 12 Changes to Theory of Operation Section, Figure 29, and Figure 30 .......................................................................................... 13 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 2/00--Rev. C to Rev. D Rev. E | Page 2 of 16 ADG438F/ADG439F SPECIFICATIONS DUAL SUPPLY VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range RON On-Resistance Flatness, RFLAT (ON) RON Drift On-Resistance Match Between Channels, RON LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) ADG438F ADG439F Channel On Leakage, ID, IS (On) ADG438F/ADG439F FAULT Source Leakage Current, IS (Fault) (With Overvoltage) Drain Leakage Current, ID (Fault) (With Overvoltage) Source Leakage Current, IS (Fault) (Power Supplies Off ) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tTRANSITION tOPEN tON (EN) tOFF (EN) +25C B Version -40C to -40C to +85C +105C -40C to +125C VSS + 1.4 VDD - 1.4 VSS + 2.2 VDD - 2.2 270 9 10 0.6 3 0.01 0.5 0.01 0.5 0.01 0.5 390 420 450 10 10 10 3 3 3 1.5 1.5 4 5 5 20 5 5 20 0.02 Unit Test Conditions/Comments V typ V typ V typ V typ typ max % typ % max %/C typ % max Output open circuit Output loaded, 1 mA -10 V VS +10 V, IS = 1 mA See Figure 17 -10 V VS +10 V, IS = 1 mA VS = 0 V, IS = 1 mA VS = 10 V, IS = 1 mA nA typ nA max nA typ nA max nA typ nA max VD = 10 V, VS = m 10 V See Figure 18 VD = 10 V, VS = m 10 V See Figure 19 VS = VD = 10 V See Figure 20 nA typ VS = +55 V or -40 V, VD = 0 V; see Figure 21 0.05 0.05 0.05 30 0.1 0.2 0.2 0.1 0.2 0.2 0.1 0.2 0.3 1 A max 2.4 0.8 2.4 0.8 2.4 0.8 V min V max 1 1 1 A max pF typ VIN = 0 V or VDD 300 300 330 ns typ ns max RL = 1 M, CL = 35 pF VS1 = 10 V, VS8 = m 10 V; see Figure 25 40 40 40 ns min 300 300 345 150 150 173 RL = 1 k, CL = 35 pF, VS = 5 V; see Figure 26 RL = 1 k, CL = 35 pF VS = 5 V; see Figure 27 RL = 1 k, CL = 35 pF VS = 5 V; see Figure 27 5 175 220 90 60 180 230 100 130 Rev. E | Page 3 of 16 A max nA typ A max nA typ ns typ ns max ns typ ns max VS = 25 V, VD = m 10 V; see Figure 19 VS = 25 V, VD = VEN, A0, A1, A2 = 0 V See Figure 22 ADG438F/ADG439F Parameter Settling Time, tSETT 0.1% 0.01% Charge Injection 1 2.5 1 2.5 Test Conditions/Comments 15 s typ s typ pC typ Off Isolation 93 dB typ Channel-to-Channel Crosstalk 93 dB typ RL = 1 k, CL = 35 pF VS = 5 V VS = 0 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 1 k, CL = 15 pF, f = 100 kHz, VS = 7 V rms; see Figure 23 RL = 1 k, CL = 15 pF, f = 100 kHz, VS = 7 rms; see Figure 24 3 pF typ 22 12 pF typ pF typ ISS 1 -40C to +125C Unit CS (Off ) CD (Off ) ADG438F ADG439F POWER REQUIREMENTS IDD +25C B Version -40C to -40C to +85C +105C 0.05 0.1 0.1 1 2.5 0.2 0.2 0.2 1 1 1 Guaranteed by design, not subject to production test. Rev. E | Page 4 of 16 mA typ mA max A typ A max VIN = 0 V or 5 V ADG438F/ADG439F ABSOLUTE MAXIMUM RATINGS TA = 25C unless otherwise noted. Table 2. Parameter Rating VDD to VSS VDD to GND VSS to GND Digital Input, EN, Ax 48 V -0.3 V to +48 V +0.3 V to -48 V -0.3 V to VDD + 0.3 V or 20 mA, whichever occurs first VSS - 25 V to VDD + 40 V VS, Analog Input Overvoltage with Power On (VDD = +15 V, VSS = -15 V) VS, Analog Input Overvoltage with Power Off (VDD = 0 V, VSS = 0 V) Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Plastic DIP Package JA, Thermal Impedance SOIC Package JA, Thermal Impedance Narrow Body Wide Body Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -40 V to +55 V 20 mA 40 mA -40C to +125C -65C to +150C 150C 117C/W 125C/W 90C/W Rev. E | Page 5 of 16 ADG438F/ADG439F PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A0 1 16 A1 A0 1 16 A1 EN 2 15 A2 EN 2 15 GND 14 VDD S2 5 VSS 3 14 GND S1A 4 13 VDD TOP VIEW (Not to Scale) 12 S5 S3 6 11 S6 S4 7 10 S7 D 8 9 S8 ADG439F 13 S1B TOP VIEW S2A 5 (Not to Scale) 12 S2B S3A 6 11 S3B S4A 7 10 S4B DA 8 9 DB 00468-005 S1 4 ADG438F 00468-004 VSS 3 Figure 3. ADG438F Pin Configuration Figure 4. ADG439F Pin Configuration Table 3. ADG438F Pin Function Description Table 4. ADG439F Pin Function Description Pin No. 1 2 Mnemonic A0 EN Pin No. 1 2 Mnemonic A0 EN 3 VSS 3 VSS 4 S1 4 S1A 5 S2 5 S2A 6 S3 6 S3A 7 S4 7 S4A 8 D 8 DA 9 S8 9 DB 10 S7 10 S4B 11 S6 11 S3B 12 S5 12 S2B 13 14 15 16 VDD GND A2 A1 13 S1B 14 15 16 VDD GND A1 Description Logic Control Input. Active High Digital Input. When low, the device is disabled, and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1. This pin can be an input or an output. Source Terminal 2. This pin can be an input or an output. Source Terminal 3. This pin can be an input or an output. Source Terminal 4. This pin can be an input or an output. Drain Terminal. This pin can be an input or an output. Source Terminal 8. This pin can be an input or an output. Source Terminal 7. This pin can be an input or an output. Source Terminal 6. This pin can be an input or an output. Source Terminal 5. This pin can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Logic Control Input. Table 5. ADG438F Truth Table1 A2 X 0 0 0 0 1 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 Description Logic Control Input. Active High Digital Input. When low, the device is disabled, and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1A. This pin can be an input or an output. Source Terminal 2A. This pin can be an input or an output. Source Terminal 3A. This pin can be an input or an output. Source Terminal 4A. This pin can be an input or an output. Drain Terminal A. This pin can be an input or an output. Drain Terminal B. This pin can be an input or an output. Source Terminal 4B. This pin can be an input or an output. Source Terminal 3B. This pin can be an input or an output. Source Terminal 2B. This pin can be an input or an output. Source Terminal 1B. This pin can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Table 6. ADG439F Truth Table1 On Switch None 1 2 3 4 5 6 7 8 A1 X 0 0 1 1 1 A0 X 0 1 0 1 X = don't care. X = don't care. Rev. E | Page 6 of 16 EN 0 1 1 1 1 On Switch Pair None 1 2 3 4 ADG438F/ADG439F TYPICAL PERFORMANCE CHARACTERISTICS 2000 2000 TA = 25C 1750 VDD = +5V VSS = -5V 1250 RON () VDD = +10V VSS = -10V 1000 VDD = +15V VSS = -15V 750 500 500 250 250 0 -15 -10 -5 0 VD, VS (V) 5 10 15 Figure 5. On Resistance as a Function of VD (VS) 0 -15 0 VD, VS (V) 5 10 15 100 IS INPUT LEAKAGE (A) 1 OPERATING RANGE 100n 10n 1n 1 100n 10n OPERATING RANGE 1n 100p 100p 10p 10p -30 -20 -10 0 10 20 30 VS SOURCE VOLTAGE (V) 40 50 60 1p -50 00468-009 -40 VDD = +15V VSS = -15V VD = 0V 10 Figure 6. Source Input Leakage Current as a Function of VS (Power Supplies Off) During Overvoltage Conditions -40 -30 -20 -10 0 10 20 30 VS SOURCE VOLTAGE (V) 40 50 60 00468-012 VDD = 0V VSS = 0V VD = 0V 10 Figure 9. Source Input Leakage Current as a Function of VS (Power Supplies On) During Overvoltage Conditions 1m 0.3 100 VDD = +15V VSS = -15V VD = 0V LEAKAGE CURRENTS (nA) 10 0.2 1 100n 10n 1n OPERATING RANGE 100p VDD = +15V VSS = -15V VS (VD) = 10V TA = 25C 0.1 ID (OFF) 0.0 IS (OFF) -0.1 -0.2 -40 -30 -20 -10 0 10 20 30 VS SOURCE VOLTAGE (V) 40 50 60 00468-010 10p Figure 7. Drain Output Leakage Current as a Function of VS (Power Supplies On) During Overvoltage Conditions Rev. E | Page 7 of 16 -0.3 -14 ID, IS (ON) -10 -6 -2 2 VS, VD (V) 6 10 Figure 10. Leakage Currents as a Function of VD (VS) 14 00468-013 IS INPUT LEAKAGE (A) -5 1m 100 1p -50 -10 Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures 1m ID INPUT LEAKAGE (A) 1000 750 00468-008 RON () 1250 TA = 125C TA = 105C TA = 85C TA = 25C 1500 00468-011 1500 1p -50 VDD = +15V VSS = -15V 1750 ADG438F/ADG439F 100 0 VDD = +15V VSS = -15V VD = +10V VS = -10V -20 OFF ISOLATION (dB) LEAKAGE CURRENTS (nA) 10 TA = 25C VDD = +15V VSS = -15V ID (OFF) 1 ID (ON) -40 -60 -80 IS (OFF) 0.1 45 55 65 75 85 95 TEMPERATURE (C) 105 115 125 -120 40 240 35 tTRANSITION PIN CAPACITANCE (pF) 220 tON (EN) 180 160 140 tOFF (EN) 100 10 11 12 13 POWER SUPPLY (V) 14 15 25 100M 1G DRAIN OFF 20 15 10 0 -15 SOURCE OFF -10 -5 0 5 10 15 VS (V) Figure 15. Capacitance vs. Source Voltage 300 30 VDD = +15V VSS = -15V tON (EN) 250 200 20 QINJ (pC) 150 tOFF (EN) 100 VDD = +15V VSS = -15V TA = 25C 10 tTRANSITION 0 -10 50 -20 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 -30 -15 00468-016 SWITCHING TIME (ns) 10M 30 Figure 12. Switching Time vs. Dual Power Supply 0 -40 1M TA = 25C VDD = +15V VSS = -15V 5 00468-015 120 100k Figure 14. Off Isolation vs. Frequency, 15 V Dual Supply 260 200 10k FREQUENCY (Hz) Figure 11. Leakage Currents as a Function of Temperature SWITCHING TIME (ns) 1k 00468-114 35 Figure 13. Switching Time vs. Temperature -10 -5 0 VS (V) 5 10 Figure 16. Charge Injection vs. Source Voltage Rev. E | Page 8 of 16 15 00468-115 25 00468-014 0.01 00468-113 -100 ADG438F/ADG439F TEST CIRCUITS IDS VDD VSS VDD VSS V1 A D S2 D S S1 00468-021 EN RON = V1/IDS Figure 17. On Resistance VDD VD Figure 21. Input Leakage Current (with Overvoltage) VSS 0V S1 A VDD 0V VDD VSS A2 VSS A1 A0 D S2 VS 0V S1 VS A ADG438F* S8 EN D S8 0.8V GND 00468-022 EN VD 00468-027 IS (OFF) 0.8V VS 00468-026 S8 VS *SIMILAR CONNECTION FOR ADG439F. Figure 18. IS (Off) Figure 22. Input Leakage Current (with Power Supplies Off) VDD VDD VSS A2 S1 VDD S1 A1 VSS S8 A0 D S2 ID (OFF) A S8 D VD GND 0.8V 00468-023 EN VIN ADG438F* VS RL 50 VSS VOUT 00468-034 VDD VSS *SIMILAR CONNECTION FOR ADG439F. Figure 19. ID (Off) Figure 23. Off Isolation VDD VSS 0.1F 0.1F NETWORK ANALYZER VOUT RL 50 VDD VSS S1 D S2 R 50 VS GND ID (ON) D NC = NO CONNECT A VD CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 20. ID (On) VOUT VS Figure 24. Channel-to-Channel Crosstalk Rev. E | Page 9 of 16 00468-200 S 00468-025 NC ADG438F/ADG439F VDD VSS VDD VSS A2 VIN S1 A1 50 3V A0 S8 ADG438F* 2.4V VS1 ADDRESS DRIVE (VIN) S2 TO S7 EN VS8 D VOUT CL 35pF RL 1M GND 50% 50% 90% VOUT 90% tTRANSITION 00468-024 *SIMILAR CONNECTION FOR ADG439F. tTRANSITION Figure 25. Switching Time of Multiplexer, tTRANSITION VDD VDD VSS 3V VSS ADDRESS DRIVE (VIN) A2 A1 50 VIN A0 ADG438F* S8 D EN 2.4V VS S1 S2 TO S7 VOUT RL 1k GND CL 35pF VOUT 80% 80% 00468-029 tOPEN **SIMILAR CONNECTION FOR ADG439F. Figure 26. Break-Before-Make Delay, tOPEN VDD A2 A1 VSS 3V VSS ENABLE DRIVE (VIN) VS S1 ADG438F* EN VIN 50 VOUT D GND VOUT RL 1k 50% 0V S2 TO S8 A0 50% CL 35pF 0.9VOUT OUTPUT 0.1VOUT 0V tON (EN) *SIMILAR CONNECTION FOR ADG439F. Figure 27. Enable Delay, tON (EN), tOFF (EN) Rev. E | Page 10 of 16 tOFF (EN) 00468-030 VDD ADG438F/ADG439F VDD VSS VDD A2 VSS A1 A0 RS ADG438F* EN VIN 0V D S VS 3V LOGIC INPUT (VIN) GND VOUT CL 1nF VOUT VOUT 00468-033 QINJ = CL x V OUT *SIMILAR CONNECTION FOR ADG439F. Figure 28. Charge Injection Rev. E | Page 11 of 16 ADG438F/ADG439F TERMINOLOGY VDD Most positive power supply potential. CS (Off) Channel input capacitance for off condition. VSS Most negative power supply potential. CD (Off) Channel output capacitance for off condition. GND Ground (0 V) reference. CD, CS (On) On switch capacitance. RON Ohmic resistance between D and S. CIN Digital input capacitance. RON RON represents the difference between the RON of any two channels as a percentage of the maximum RON of those two channels. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of the on resistance measured over the specified analog signal range and is represented by RFLAT (ON). Flatness is calculated by ((RMAX - RMIN) / RMAX x 100) tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. RON Drift Change in RON when temperature changes by one degree Celsius. tOPEN Off time measured between 80% points of both switches when switching from one address state to another. IS (Off) Source leakage current when the switch is off. VINL Maximum input voltage for Logic 0. ID (Off) Drain leakage current when the switch is off. VINH Minimum input voltage for Logic 1. ID, IS (On) Channel leakage current when the switch is on. IINL (IINH) Input current of the digital input. VD (VS) Analog voltage on Terminal D and Terminal S. Off Isolation A measure of unwanted signal coupling through an off channel. IS (Fault--Power Supplies On) Source leakage current when exposed to an overvoltage condition. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. ID (Fault--Power Supplies On) Drain leakage current when exposed to an overvoltage condition. IDD Positive supply current. IS (Fault--Power Supplies Off) Source leakage current with power supplies off. ISS Negative supply current. Rev. E | Page 12 of 16 ADG438F/ADG439F THEORY OF OPERATION Q1 n-CHANNEL MOSFET SATURATES VDD Q2 Q3 VSS Figure 29. +55 V Overvoltage Input to the On Channel Q1 n-CHANNEL MOSFET IS ON VSS Q2 VDD Q3 p-CHANNEL MOSFET SATURATES 00468-018 -40V OVERVOLTAGE Figure 30. -40 V Overvoltage on an Off Channel with Multiplexer Power On When the power supplies are present but the channel is off, again either the p-channel MOSFET or one of the n-channel MOSFETs remains off when an overvoltage occurs. Finally, when the power supplies are off, the gate of each MOSFET is at ground. A negative overvoltage switches on the first n-channel MOSFET, but the bias produced by the overvoltage causes the p-channel MOSFET to remain turned off. With a positive overvoltage, the first MOSFET in the series remains off because the gate to source voltage applied to this MOSFET is negative. During fault conditions (power supplies off), the leakage current into and out of the ADG438F/ADG439F is limited to a few microamps. This limit protects the multiplexer and succeeding circuitry from over stresses as well as protects the signal sources that drive the multiplexer. Also, the other channels of the multiplexer are undisturbed by the overvoltage and continue to operate normally. Rev. E | Page 13 of 16 Q1 Q2 Q3 n-CHANNEL MOSFET IS OFF 00468-019 Figure 29 to Figure 32 show the conditions of the three MOSFETs for the various overvoltage situations. When the analog input applied to an on channel approaches the positive power supply line, the n-channel MOSFET saturates because the voltage on the analog input exceeds the difference between VDD and the n-channel threshold voltage (VTN). When a voltage more negative than VSS is applied to the multiplexer, the p-channel MOSFET saturates because the analog input is more negative than the difference between VSS and the p-channel threshold voltage (VTP). Because VTN is nominally 1.4 V and VTP - 1.4 V, the analog input range to the multiplexer is limited to VSS + 1.4 V to VDD - 1.4 V (output open circuit) when a 15 V power supply is used. +55V OVERVOLTAGE Figure 31. +55 V Overvoltage with Power Off -40V OVERVOLTAGE n-CHANNEL MOSFET IS ON Q1 Q2 Q3 p-CHANNEL MOSFET IS OFF Figure 32. -40 V Overvoltage with Power Off 00468-020 When an analog input of VSS + 2.2 V to VDD - 2.2 V (output loaded, 1 mA) is applied to the ADG438F/ADG439F, the multiplexer behaves as a standard multiplexer, with specifications similar to a standard multiplexer, for example, the on-resistance is 270 typically. However, when an overvoltage is applied to the device, one of the three MOSFETs saturates. +55V OVERVOLTAGE 00468-017 The ADG438F/ADG439F multiplexers are capable of withstanding overvoltages from -40 V to +55 V, irrespective of whether the power supplies are present or not. Each channel of the multiplexer consists of an n-channel MOSFET, a p-channel MOSFET, and an n-channel MOSFET, connected in series. When the analog input exceeds the power supplies, one of the MOSFETs saturates, limiting the current. The current during a fault condition is determined by the load on the output. Figure 31 illustrates the channel architecture that enables these multiplexers to withstand continuous overvoltages. ADG438F/ADG439F OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16 9 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 8 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 073106-B COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches and (millimeters) 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) Figure 34. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. E | Page 14 of 16 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. ADG438F/ADG439F 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8 0 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 03-27-2007-B 1 Figure 35. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 ADG438FBN ADG438FBNZ ADG438FBR ADG438FBR-REEL ADG438FBRZ ADG438FBRZ-REEL ADG439FBN ADG439FBNZ ADG439FBR ADG439FBR-REEL ADG439FBRW ADG439FBRWZ ADG439FBRWZ-REEL ADG439FBRZ ADG439FBRZ-REEL 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. Rev. E | Page 15 of 16 Package Option N-16 N-16 R-16 R-16 R-16 R-16 N-16 N-16 R-16 R-16 RW-16 RW-16 RW-16 R-16 R-16 ADG438F/ADG439F NOTES (c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00468-0-7/11(E) Rev. E | Page 16 of 16