1
LTC2604/LTC2614/LTC2624
2604fb
CODE
0 16384 32768 49152 65535
ERROR (LSB)
2604 TA01
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
CC
= 5V
V
REF
= 4.096V
215
1
GND
REF LO
REF A
V
OUTA
V
OUTB
REF B
CS/LD
SCK
V
CC
REF D
V
OUT D
V
OUT C
REF C
SDO
SDI
2604 BD
16
3
4
14
DAC A
DAC D
5
7
6
8
10
12
9
13
DAC B
DAC C
DECODE
CONTROL
LOGIC
32-BIT SHIFT REGISTER
CLR
11
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
Quad 16-Bit Rail-to-Rail DACs
in 16-Lead SSOP
The LTC
®
2604/LTC2614/LTC2624 are quad 16-,14- and
12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in
16-lead narrow SSOP packages. These parts have sepa-
rate reference inputs for each DAC. They have built-in
high performance output buffers and are guaranteed
monotonic.
These parts establish advanced performance standards
for output drive, crosstalk and load regulation in single-
supply, voltage output multiples.
The parts use a simple SPI/MICROWIRE
TM
compatible
3-wire serial interface which can be operated at clock
rates up to 50MHz. Daisy-chain capability and a hardware
CLR function are included.
The LTC2604/LTC2614/LTC2624 incorporate a power-
on reset circuit. During power-up, the voltage outputs
rise less than 10mV above zero scale; and after power-up,
they stay at zero scale until a valid write and update take
place. The power-on reset circuit resets the LTC2604-1/
LTC2614-1/LTC2624-1 to midscale. The voltage outputs
stay at midscale until a valid write and update take place.
■
Smallest Pin Compatible Quad 16-Bit DAC:
LTC2604: 16-Bits
LTC2614: 14-Bits
LTC2624: 12-Bits
■
Guaranteed 16-Bit Monotonic Over Temperature
■
Separate Reference Inputs for each DAC
■
Wide 2.5V to 5.5V Supply Range
■
Low Power Operation: 250μA per DAC at 3V
■
Individual DAC Power-Down to 1μA, Max
■
Ultralow Crosstalk Between DACs (<5μV)
■
High Rail-to-Rail Output Drive (±15mA)
■
Double Buffered Digital Inputs
■
LTC2604-1/LTC2614-1/LTC2624-1: Power-On Reset
to Midscale
■
16-Lead Narrow SSOP Package
■
Mobile Communications
■
Process Control and Industrial Automation
■
Instrumentation
■
Automatic Test Equipment
Differential Nonlinearity (LTC2604)
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2
LTC2604/LTC2614/LTC2624
2604fb
PSR Power Supply Rejection V
CC
= 5V ±10% –80 dB
V
CC
= 3V ±10% –80 dB
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
ORDER PART NUMBER
WU
U
PACKAGE/ORDER I FOR ATIO
(Note 1)
Any Pin to GND........................................... – 0.3V to 6V
Any Pin to V
CC
............................................ – 6V to 0.3V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC2604C/LTC2614C/LTC2624C .......... 0°C to 70°C
LTC2604C-1/LTC2614C-1/
LTC2624C-1 .......................................... 0°C to 70°C
LTC2604I/LTC2614I/LTC2624I .......... – 40°C to 85°C
LTC2604I-1/LTC2614I-1/
LTC2624I-1 ....................................... – 40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
GN PART MARKING
ELECTRICAL C CHARA TERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B =
REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution ●12 14 16 Bits
Monotonicity (Note 2) ●12 14 16 Bits
DNL Differential Nonlinearity (Note 2) ●±0.5 ±1±1 LSB
INL Integral Nonlinearity (Note 2) ●±0.9 ±4±4±16 ±14 ±64 LSB
Load Regulation V
REF
= V
CC
= 5V, Midscale
I
OUT
= 0mA to 15mA Sourcing ●0.025 0.125 0.1 0.5 0.3 2 LSB/mA
I
OUT
= 0mA to 15mA Sinking ●0.025 0.125 0.1 0.5 0.3 2 LSB/mA
V
REF
= V
CC
= 2.5V, Midscale
I
OUT
= 0mA to 7.5mA Sourcing ●0.05 0.25 0.2 1 0.7 4 LSB/mA
I
OUT
= 0mA to 7.5mA Sinking ●0.05 0.25 0.2 1 0.7 4 LSB/mA
ZSE Zero-Scale Error ●1.5 9 1.5 9 1.5 9 mV
V
OS
Offset Error (Note 7) ●±1.5 ±9±1.5 ±9±1.5 ±9mV
V
OS
Temperature ±5±5±5μV/°C
Coefficient
GE Gain Error ●±0.1 ±0.7 ±0.1 ±0.7 ±0.1 ±0.7 %FSR
Gain Temperature ±5±5±5 ppm/°C
Coefficient
1
2
3
4
5
6
7
8
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
16
15
14
13
12
11
10
9
GND
REF LO
REF A
V
OUT A
V
OUT B
REF B
CS/LD
SCK
V
CC
REF D
V
OUT D
V
OUT C
REF C
CLR
SDO
SDI
T
JMAX
= 125°C, θ
JA
= 150°C/W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC2624/LTC2624-1 LTC2614/LTC2614-1 LTC2604/LTC2604-1
LTC2604CGN
LTC2604CGN-1
LTC2604IGN
LTC2604IGN-1
LTC2614CGN
LTC2614CGN-1
2604
26041
2604I
2604I1
2614
26141
2614I
2614I1
2624
26241
2624I
2624I1
LTC2614IGN
LTC2614IGN-1
LTC2624CGN
LTC2624CGN-1
LTC2624IGN
LTC2624IGN-1
3
LTC2604/LTC2614/LTC2624
2604fb
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B =
REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
ELECTRICAL C CHARA TERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
t
s
Settling Time (Note 8) ±0.024% (±1LSB at 12 Bits) 7 7 7 μs
±0.006% (±1LSB at 14 Bits) 9 9 μs
±0.0015% (±1LSB at 16 Bits) 10 μs
Settling Time for ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 μs
1LSB Step (Note 9) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 μs
±0.0015% (±1LSB at 16 Bits) 5.2 μs
Voltage Output Slew Rate 0.80 0.80 0.80 V/μs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Midscale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
e
n
Output Voltage Noise At f = 1kHz 120 120 120 nV/√Hz
Density At f = 10kHz 100 100 100 nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 μV
P-P
LTC2624/LTC2624-1 LTC2614/LTC2614-1 LTC2604/LTC2604-1
R
OUT
DC Output Impedance V
REF
= V
CC
= 5V, Midscale; –15mA ≤ I
OUT
≤ 15mA ●0.025 0.15 Ω
V
REF
= V
CC
= 2.5V, Midscale; –7.5mA ≤ I
OUT
≤ 7.5mA ●0.030 0.15 Ω
DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5) ±5μV
Due to Load Current Change ±1μV/mA
Due to Powering Down (per Channel) ±3.5 μV
I
SC
Short-Circuit Output Current V
CC
= 5.5V, V
REF
= 5.5V
Code: Zero Scale; Forcing Output to V
CC
●15 34 60 mA
Code: Full Scale; Forcing Output to GND ●15 36 60 mA
V
CC
= 2.5V, V
REF
= 2.5V
Code: Zero Scale; Forcing Output to V
CC
●7.5 18 50 mA
Code: Full Scale; Forcing Output to GND ●7.5 24 50 mA
Reference Input
Input Voltage Range ●0V
CC
V
Resistance Normal Mode ●88 128 160 kΩ
Capacitance 14 pF
I
REF
Reference Current, Power Down Mode All DACs Powered Down ●0.001 1 μA
Power Supply
V
CC
Positive Supply Voltage For Specified Performance ●2.5 5.5 V
I
CC
Supply Current V
CC
= 5V (Note 3) ●1.3 2 mA
V
CC
= 3V (Note 3) ●1 1.6 mA
All DACs Powered Down (Note 3) V
CC
= 5V ●0.35 1 μA
All DACs Powered Down (Note 3) V
CC
= 3V ●0.10 1 μA
Digital I/O
V
IH
Digital Input High Voltage V
CC
= 2.5V to 5.5V ●2.4 V
V
CC
= 2.5V to 3.6V ●2.0 V
V
IL
Digital Input Low Voltage V
CC
= 4.5V to 5.5V ●0.8 V
V
CC
= 2.5V to 5.5V ●0.6 V
V
OH
Digital Output High Voltage Load Current = –100μA●V
CC
– 0.4 V
V
OL
Digital Output Low Voltage Load Current = +100μA●0.4 V
I
LK
Digital Input Leakage V
IN
= GND to V
CC
●±1μA
C
IN
Digital Input Capacitance (Note 6) ●8pF
4
LTC2604/LTC2614/LTC2624
2604fb
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
OFFSET ERROR (mV)
2604 G03
3
2
1
0
–1
–2
–3
I
OUT
(mA)
–35 –25 –15 –5 5 15 25 35
ΔV
OUT
(mV)
2604 G02
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
REF
= V
CC
= 5V
CODE = MIDSCALE
V
REF
= V
CC
= 3V
I
OUT
(mA)
–40 –30 –20 –10 0 10 20 30 40
ΔV
OUT
(V)
2604 G01
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
V
REF
= V
CC
= 5V
V
REF
= V
CC
= 3V
V
REF
= V
CC
= 5V
V
REF
= V
CC
= 3V
CODE = MIDSCALE
TI I G CHARACTERISTICS
UW
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code k
L
to code
2
N
– 1, where N is the resolution and k
L
is given by k
L
= 0.016(2
N
/V
REF
),
rounded to the nearest whole code. For V
REF
= 4.096V and N = 16,
k
L
= 256, linearity is defined from code 256 to code 65,535.
Note 3: Digital inputs at 0V or V
CC
.
Note 4: DC crosstalk is measured with V
CC
= 5V and V
REF
= 4.096V, with
the measured DAC at midscale, unless otherwise noted.
Note 5: R
L
= 2kΩ to GND or V
CC
.
Note 6: Guaranteed by design and not production tested.
Note 7: Inferred from measurement at code 256 (LTC2604), code 64
(LTC2614) or code 16 (LTC2624), and at full scale.
Note 8: V
CC
= 5V, V
REF
= 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 9: V
CC
= 5V, V
REF
= 4.096V. DAC is stepped 1LSB between half scale
and half scale –1. Load is 2k in parallel with 200pF to GND.
Note 10: These specifications apply to LTC2604/LTC2604-1, LTC2614/
LTC2614-1, LTC2624/LTC2624-1.
Current Limiting Load Regulation Offset Error vs Temperature
(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C =
REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
= 2.5V to 5.5V
t
1
SDI Valid to SCK Setup ●4ns
t
2
SDI Valid to SCK Hold ●4ns
t
3
SCK High Time ●9ns
t
4
SCK Low Time ●9ns
t
5
CS/LD Pulse Width ●10 ns
t
6
LSB SCK High to CS/LD High ●7ns
t
7
CS/LD Low to SCK High ●7ns
t8SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF
VCC = 4.5V to 5.5V ●20 ns
VCC = 2.5V to 5.5V ●45 ns
t9CLR Pulse Width ●20 ns
t
10
CS/LD High to SCK Positive Edge ●7ns
SCK Frequency 50% Duty Cycle ●50 MHz
5
LTC2604/LTC2614/LTC2624
2604fb
V
OUT
10mV/DIV
250μs/DIV
2604 G11
V
CC
1V/DIV
4mV PEAK
4mV PEAK
2.5μs/DIV
V
OUT
0.5V/DIV
2604 G09
V
REF
= V
CC
= 5V
1/4-SCALE TO 3/4-SCALE
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
ICC (nA)
2604 G08
450
400
350
300
250
200
150
100
50
0
V
CC
(V)
2.5 3 3.5 4 4.5 5 5.5
GAIN ERROR (%FSR)
2604 G07
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
OFFSET ERROR (mV)
2604 G06
3
2
1
0
–1
–2
–3
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
GAIN ERROR (%FSR)
2604 G05
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
ZERO-SCALE ERROR (mV)
2604 G04
3
2.5
2.0
1.5
1.0
0.5
0
Gain Error vs Temperature Offset Error vs VCC
Zero-Scale Error vs Temperature
ICC Shutdown vs VCC Large-Signal Settling
Gain Error vs VCC
Midscale Glitch Impulse Power-On Reset Glitch Power-On Reset to Midscale
V
OUT
10mV/DIV
CS/LD
5V/DIV
2.5μs/DIV
2604 G10
12nV-s TYP
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)
V
REF
= V
CC
V
CC
1V/DIV
V
OUT
1V/DIV
500μs/DIV
2604 G34
6
LTC2604/LTC2614/LTC2624
2604fb
V
OUT
1V/DIV
1μs/DIV
2604 G15
CLR
5V/DIV
1V/DIV
0
–50
10mA/DIV
–40
–30
–20
–10
0
1234
2604 G19
56
V
CC
= 5.5V
V
REF
= 5.6V
CODE = FULL SCALE
V
OUT
SWEPT V
CC
TO 0V
1V/DIV
0
0
10mA/DIV
10
20
30
40
50
1234
2604 G18
56
V
CC
= 5.5V
V
REF
= 5.6V
CODE = 0
V
OUT
SWEPT 0V TO V
CC
LOGIC VOLTAGE (V)
00.5 1 1.5 2 2.5 3 3.5 4 4.5 5
ICC (mA)
2604 G13
2.0
1.8
1.6
1.4
1.2
1.0
0.8
VCC = 5V
SWEEP SCK, SDI
AND CS/LD
0V TO VCC
V
OUT
10μV/DIV
SECONDS
012345678910
2604 G17
FREQUENCY (Hz)
1k
dB
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36 1M
2604 G16
10k 100k
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
2.5μs/DIV
V
OUT
0.5V/DIV
CS/LD
5V/DIV
2604 G14
V
CC
= 5V
V
REF
= 2V
DACs A-C IN
POWER-DOWN MODE
Supply Current vs Logic Voltage Exiting Power-Down to Midscale
Hardware CLR Multiplying Frequency Response
Output Voltage Noise,
0.1Hz to 10Hz
Short-Circuit Output Current vs
VOUT (Sinking)
Short-Circuit Output Current vs
VOUT (Sourcing)
IOUT (mA)
012345678910
VOUT (V)
2604 G12
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
3V SOURCING
3V SINKING
5V SINKING
Headroom at Rails
vs Output Current
Hardware CLR to Midscale
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)
V
OUT
1V/DIV
1μs/DIV
2604 G35
CLR
5V/DIV
V
CC
= 5V
V
REF
= 4.096V
CODE = FULL SCALE
7
LTC2604/LTC2614/LTC2624
2604fb
5μs/DIV
2604 G27
V
OUT
100μV/DIV
CS/LD
2V/DIV
V
CC
= 5V, V
REF
= 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
SETTLING TO ±1LSB
12.3μs
2μs/DIV
2604 G26
VOUT
100μV/DIV
CS/LD
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
9.7μs
VREF (V)
012345
DNL (LSB)
2604 G25
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5.5V
DNL (POS)
DNL (NEG)
VREF (V)
012345
INL (LSB)
2604 G24
32
24
16
8
0
–8
–16
–24
–32
VCC = 5.5V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
DNL (LSB)
2604 G23
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
DNL (POS)
DNL (NEG)
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
INL (LSB)
2604 G22
32
24
16
8
0
–8
–16
–24
–32
VCC = 5V
VREF = 4.096V
INL (POS)
INL (NEG)
CODE
0 16384 32768 49152 65535
DNL (LSB)
2604 G21
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
CODE
016384 32768 49152 65535
INL (LSB)
2604 G20
32
24
16
8
0
–8
–16
–24
–32
VCC = 5V
VREF = 4.096V
(LTC2604/LTC2604-1)
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
DNL vs Temperature INL vs VREF DNL vs VREF
Settling to ±1LSB Settling of Full-Scale Step
TYPICAL PERFOR A CE CHARACTERISTICS
UW
8
LTC2604/LTC2614/LTC2624
2604fb
2μs/DIV
2604 G33
VOUT
1mV/DIV
CS/LD
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
6.8μs
CODE
0 1024 2048 3072 4095
DNL (LSB)
2604 G32
VCC = 5V
VREF = 4.096V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
CODE
01024 2048 3072 4095
INL (LSB)
2604 G31
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
VCC = 5V
VREF = 4.096V
CODE
0 4096 8192 12288 16383
DNL (LSB)
2604 G29
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
2μs/DIV
2604 G30
V
OUT
100μV/DIV
CS/LD
2V/DIV
V
CC
= 5V, V
REF
= 4.096V
1/4-SCALE TO 3/4-SCALE STEP
R
L
= 2k, C
L
= 200pF
AVERAGE OF 2048 EVENTS
8.9μs
CODE
04096 8192 12288 16383
INL (LSB)
2604 G28
8
6
4
2
0
–2
–4
–6
–8
VCC = 5V
VREF = 4.096V
(LTC2614/LTC2614-1)
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
Differential Nonlinearity (DNL) Settling to ±1LSB
(LTC2624/LTC2624-1)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Integral Nonlinearity (INL)
PIN FUNCTIONS
UUU
GND (Pin 1): Analog Ground.
REF LO (Pin 2): Reference Low. The voltage at this pin sets
the zero scale (ZS) voltage of all DACs. This pin can be
raised up to 1V above ground at V
CC
= 5V or 100mV above
ground at V
CC
= 3V.
REF A, REF B, REF C, REF D (Pins 3, 6, 12, 15): Reference
Voltage Inputs for each DAC. REF x sets the full scale
voltage of the DACs. 0V ≤ REF x ≤ V
CC
.
V
OUT A
to V
OUT D
(Pins 4, 5, 13, 14): DAC Analog Voltage
Outputs. The output range is from REF LO to REF x.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on SDI
into the register. When CS/LD is taken high, SCK is disabled
and the specified command (see Table 1) is executed.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 9): Serial Interface Data Input. Data is applied to
SDI for transfer to the device at the rising edge of SCK. The
LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/
LTC2624-1 accept input word lengths of either 24 or
32 bits.
9
LTC2604/LTC2614/LTC2624
2604fb
SDI
SDO
CS/LD
SCK
2604 F01
t
2
t
8
t
10
t
5
t
7
t
6
t
1
t
3
t
4
1232324
215
1
GND
REF LO
REF A
V
OUTA
V
OUTB
REF B
CS/LD
SCK
V
CC
REF D
V
OUT D
V
OUT C
REF C
SDO
SDI
2604 BD
16
3
4
14
DAC A
DAC D
5
7
6
8
10
12
9
13
DAC B
DAC C
DECODE
CONTROL
LOGIC
32-BIT SHIFT REGISTER
CLR
11
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
PIN FUNCTIONS
UUU
BLOCK DIAGRA
W
SDO (Pin 10): Serial Interface Data Output. The serial
output of the shift register appears at the SDO pin. The data
transferred to the device via the SDI pin is delayed 32 SCK
rising edges before being output at the next falling edge.
This pin is used for daisy-chain operation.
CLR (Pin 11): Asynchronous Clear Input. A logic low at
this level-triggered input clears all registers and causes
TI I G DIAGRA
UWW
Figure 1
the DAC voltage outputs to drop to 0V for the LTC2604/
LTC2614/LTC2624. A logic low at this input sets all regis-
ters to midscale code and causes the DAC voltage outputs
to go to midscale for the LTC2604-1/LTC2614-1/
LTC2624-1. CMOS and TTL compatible.
V
CC
(Pin 16): Supply Voltage Input. 2.5V ≤ V
CC
≤ 5.5V.
10
LTC2604/LTC2614/LTC2624
2604fb
Table 1.
COMMAND*
C3 C2 C1 C0
0000 Write to Input Register n
0001 Update (Power Up) DAC Register n
0010 Write to Input Register n, Update (Power Up) All n
0011 Write to and Update (Power Up) n
0100 Power Down n
1111 No Operation
ADDRESS (n)*
A3 A2 A1 A0
0000 DAC A
0001 DAC B
0010 DAC C
0011 DAC D
1111 All DACs
OPERATIO
U
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
(LTC2604, LTC2614 and LTC2624 respectively). Data can
only be transferred to the device when the CS/LD signal is
low. The rising edge of CS/LD ends the data transfer and
causes the device to carry out the action specified in the
24-bit input word. The complete sequence is shown in
Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the block diagram.
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width, 8
don’t-care bits are transferred to the device first, followed
by the 24-bit word as just described. Figure 2b shows the
32-bit sequence. The 32-bit word is required for daisy-
chain operation, and is also available to accommodate
Power-On Reset
The LTC2604/LTC2614/LTC2624 clear the outputs to zero
scale when power is first applied, making system initializa-
tion consistent and repeatable. The LTC2604-1/
LTC2614-1/LTC2624-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2604/
LTC2614/LTC2624 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V ≤ REF x ≤ V
CC
+ 0.3V (see Absolute
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V
CC
(Pin 16) is in
transition.
Transfer Function
The digital-to-analog transfer function is
VkREF x REFLO REFLO
OUT IDEAL N
()
[– ]=⎛
⎝
⎜⎞
⎠
⎟+
2
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REF x is the voltage at REF A,
REF B, REF C and REF D (Pins 3, 6, 12 and 15).
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
*Command and address codes not shown are reserved and should not be used.
11
LTC2604/LTC2614/LTC2624
2604fb
C3
COMMAND ADDRESS DATA (12 BITS + 4 DON’T-CARE BITS)
C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XXX
2604 TBL03
MSB LSB
C3
COMMAND ADDRESS DATA (14 BITS + 2 DON’T-CARE BITS)
C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
2604 TBL02
MSB LSB
C3
COMMAND ADDRESS DATA (16 BITS)
C2 C1 C0 A3 A2 A1 A0 D13D14D15 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2604 TBL01
MSB LSB
OPERATIO
U
INPUT WORD (LTC2604)
INPUT WORD (LTC2614)
INPUT WORD (LTC2624)
microprocessors which have a minimum word width of 16
bits (2 bytes).
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy-chain” series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire chain.
Because of this, the devices can be addressed and con-
trolled individually by simply concatenating their input
words; the first instruction addresses the last device in the
chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the first
device as the data input. When the data transfer is com-
plete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four outputs are needed. When in power-down, the
buffer amplifiers, bias circuits and reference inputs are
disabled, and draw essentially zero current. The DAC
outputs are put into a high-impedance state, and the
output pins are passively pulled to ground through indi-
vidual 90k resistors. Input- and DAC-register contents are
not disturbed during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100
b
in combina-
tion with the appropriate DAC address, (n). The 16-bit data
word is ignored. The supply current is reduced by approxi-
mately 1/4 for each DAC powered down. The effective
resistance at REF x (pins 3, 6, 12 and 15) are at high-
impedance input (typically > 1GΩ) when the correspond-
ing DACs are powered down.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state is
12
LTC2604/LTC2614/LTC2624
2604fb
OPERATIO
U
powered up and updated, normal settling is delayed. If less
than four DACs are in a powered-down state prior to the
update command, the power-up delay time is 5μs. If on the
other hand, all four DACs are powered down, then the main
bias generation circuit block has been automatically shut
down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power up delay time is
12μs (for V
CC
= 5V) or 30μs (for V
CC
= 3V).
Voltage Outputs
Each of the four rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex-
pressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.025Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
30Ω typical channel resistance of the output devices; e.g.,
when sinking 1mA, the minimum output voltage = 30Ω •
1mA = 25mV. See the graph Headroom at Rails vs Output
Current in the Typical Performance Characteristics
section.
The amplifiers are stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation and DC crosstalk perfor-
mance of these devices is achieved in part by keeping
“signal” and “power” grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu-
ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. When a zero scale
DAC output voltage of zero is desired, the REFLO pin
(pin 2) should be connected to system star ground.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur near full scale
when the REF pins are tied to V
CC
. If REF x = V
CC
and the
DAC full-scale error (FSE) is positive, the output for the
highest codes limits at V
CC
as shown in Figure 3c. No full-
scale limiting can occur if REF x is less than V
CC
– FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
13
LTC2604/LTC2614/LTC2624
2604fb
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
CS/LD
SCK
SDI
COMMAND WORD ADDRESS WORD DATA WORD
24-BIT INPUT WORD
2604 F02a
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX
CS/LD
SCK
SDI
COMMAND WORD ADDRESS WORD DATA WORD
DON’T CARE
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX
SDO
CURRENT
32-BIT
INPUT WORD
2604 F02b
PREVIOUS 32-BIT INPUT WORD
t
2
t
3
t
4
t
1
t
8
D15
17
SCK
SDI
SDO PREVIOUS D14PREVIOUS D15
18
D14
Figure 2a. LTC2604 24-Bit Load Sequence (Minimum Input Word)
LTC2614 SDI Data Word: 14-Bit Input Code + 2 Don’t Care Bits
LTC2624 SDI Data Word: 12-Bit Input Code + 4 Don’t Care Bits
OPERATIO
U
Figure 2b. LTC2604 32-Bit Load Sequence
LTC2614 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t Care Bits
LTC2624 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t Care Bits
14
LTC2604/LTC2614/LTC2624
2604fb
2600 F03
INPUT CODE
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32,768
065,535
INPUT CODE
OUTPUT
VOLTAGE
VREF = VCC
VREF = VCC
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
OPERATIO
U
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
(b)
(a)
(c)
15
LTC2604/LTC2614/LTC2624
2604fb
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16
LTC2604/LTC2614/LTC2624
2604fb
0°
90°
I + Q
MODULATOR
RF
LO
Q INPUT I INPUT
5V
5V
5V 5V
70MHz IN OUT
1k
10k
10k
1k
10k
10k
20k
0.1μF
0.01μF0.01μF
20Ω49.9Ω
49.9Ω
49.9Ω
ZC830
ZC830
47pF 10pF
20pF
*ZETEX (516) 543-7100
OPTIONAL
5V
5V
LTC2604
CS/LD
SCK
SDI
DAC D
DAC B
OPTIONAL
DAC C
DAC A
0.1μF
0.1μF
20k
100k
2.74k
1%
2.74k
1%
2.74k
1%
2.74k
1%
100k
2.74k
1%
2.74k
1%
2.74k
1%
2.74k
1%
0.1μF
2604 F04
PART NUMBER DESCRIPTION COMMENTS
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.096V
LTC1458L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1654 Dual 14-Bit Rail-to-Rail V
OUT
DAC Programmable Speed/Power
LTC1655/LTC1655L Single 16-Bit V
OUT
DAC with Serial Interface in SO-8 V
CC
= 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L Parallel 5V/3V 16-Bit V
OUT
DAC Low Power, Deglitched, Rail-to-Rail V
OUT
LTC1660/LTC1665 Octal 8/10-Bit V
OUT
DAC in 16-Pin Narrow SSOP V
CC
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2μs for 10V Step
LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range
LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP 300μA per DAC, 2.5V to 5.5V Supply Range
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0407 REV B • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
RELATED PARTS
U
TYPICAL APPLICATIO
Figure 4. Using DAC A and DAC B for Nearly Continuous Attenuation Control and DAC C and
DAC D to Trim for Minimum LO Feedthrough in a Mixer.
