p> PRELIMINARY PRODUCT SPECIFICATION e Z86E04/E08 CMOS Z8 OTP MICROCONTROLLERS PRODUCT DEVICES Part Oscillator Operating Operating ROM Number Type Vee Temperature (KB) Package Z86E0412PEC Crystal 4.5V-5.5V 40C/1 05C 1 18-Pin DIP Z86E0412PSC1866 Crystal 4.5V-5.5V 0C/70C 1 18-Pin DIP Z286E0412PSC1903 RC 4.5V-6.5V oc/70C 1 18-Pin DIP Z86E0412PEC1903 RC 4.5V-5.5V 40C/105C 1 18-Pin DIP Z286E0412SEC Crystal 4.5V-5,5V 40C/105C 1 18-Pin SOIC 286E0412SSC1866 Crystal 4.5V-5.5V oc/70C 1 18-Pin SOIC 786E041288C1903 RC 4.5V-5.5V oc/70C 1 18-Pin SOIC Z286E0412SEC1903 RG 4.5V-5.5V ~40C/105C 1 18-Pin SOIC Z86E0812PEC Crystal 4.5V-5.5V 40C/105C 2 18-Pin DIP Z86E0812PSC1 866 Crystal 4.5V-5.5V 0c/70C 2 18-Pin DIP Z86E0812PSC1903 RC 4.5V-5.5V ac/70C 2 18-Pin DIP Z86E0812PEC1903 RC 4.5V-6.5V 40C/105C 2 18-Pin DIP Z86E0812SEC Crystal 4.5V-5.5V 40C/105C 2 18-Pin SOIC 286E0812SSC1 866 Crystal 4,5V-5.5V 0C/70C 2 18-Pin SOIC Z86E0812SSC1903 RC 4.5V-5.5V OC/70C 2 18-Pin SOIC Z86E0812SEC1903 RC 4.5V-5.5V 40C/105C 2 18-Pin SOIC Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the us- ers application requirements. DS97Z8X1 104 PRELIMINARY 1Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FEATURES @ 14 Input/Output Lines w Six Vectored, Prioritized Interrupts (3 falling edge, 1 rising edge, 2 timers) @ Two Analog Comparators m Program Options: - Low Noise ROM Protect Auto Latch - Watch-Dog Timer (WDT) - EPROMTest Mode Disable Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler mw WDT/ Power-On Reset (POR} On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LC, RC, or External Clock Clock-Free WDT Reset Low-Power Consumption (50 mw typical) Fast Instruction Pointer (1s @ 12 MHz) RAM Bytes (125) GENERAL DESCRIPTION Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time Programmable (OTP) members of Zitogs single-chip Z8 MCU family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions. For applications demanding powerful I/O capabilities, the Z86E04/E08's dedicated input and output lines are grouped into three ports, and are configurable under soft- ware control to provide timing, status signals, or parallel VO. Two on-chip counter/timers, with a larga number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data com- munications. Note: All Signats with an overline, ", are active Low, for example: B/W (WORD is active Low); B/W (BYTE is active Low, only). Power connections follow conventional descriptions be- low: Connection Clreult Device Power Voc Vop Ground GND Vss 2 PRELIMINARY DS97Z8X1104Z86E04/E08 Zilog CMOS Z8 OTP Microcontrollers Input XTAL | | | Vcc GND | A AW. Machine Port3 A, Vj] Timing & Inst. db Control Counter) [A 4 Timers (2) _K ALU OTP Interrupt [A FLAG Control Aye Register Two Analog \ Pointer Program Comparators Counter General-Purpose Register File Port 2 Port 0 \ 0 VO (Bit Programmable) Figure 1. Functional Block Diagram DS9728X1104 PRELIMINARY 3Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog GENERAL DESCRIPTION (Continued) D7-0 i AD 10-0 28 MCU }__ AD 10-0 Address MUX D740 Data AD 10-0 EPROM we Address }_______h| b7-0 counter -__ i z8 Port 2 } 1 bits A ROM PROT v Low Noise Clear Clock PGM , POO P01 Mode Logic . { } VPP EPM | PGM P3s P32 xe P30 OE XT1 P31 Figure 2, EPROM Programming Mode Block Diagram 4 PRELIMINARY DS9728X1104Zilog PIN DESCRIPTION ar D401 18 D3 DS & o D2 D o Mm D1 D7 Gg BO Voc G GND Nc G o PGM CE c mr CLOCK OE > CLEAR EPM a9 10 Vpp Figure 3. 18-Pin EPROM Mode Configuration Table 1. 18-Pin DIP Pin Identification CMOS Z8 OTP Z86E04/E08 Microcontrollers P24 1 P25 o P26 P27 Veco O XTAL2 XTAL1 & P31 0 p32 49 VA 18 10 m P23 m P22 D P21 o P20 GND m Poe P01 I POO I P33 Figure 4, 18-Pin DIP/SOIC Mode Configuration Table 2. 18-Pin DIP/SOIC Pin Identification EPROM Programming Mode Standard Mode Pin # Symbol Function Direction Pin# Symbol Function Direction 1-4 D4-D? Data4, 5,67 In/Output 1-4 P24-P27_ Port 2, Pins 4,5,6,7 _In/Output 5 Voc Power Supply 5 Veo Power Supply 6 NC No Connection 6 XTAL2__Crystal Osc. Clock Output 7 CE Chip Enable Input 7 XTAL1 Crystal Osc. Clock Input 8 OE Output Enable Input 8 Pat Port 3, Pin 1, ANT input 9 EPM EPROM Prog Mode Input 9 P32 Port 3, Pin 2, AN2 input 10 Vee Prog Voltage Input 10 P33 Port 3, Pin 3, REF Input 11 Clear Clear Clock Input 11-13 POO-PO2 Port 0, Pins 0,1,2 In/Output 12 Clock Address Input 14 GND Ground 13 PGM Prog Mode Input 15-18 P20-P23 Port2,Pins0,1,2,3 _In/Output 14 GND Ground 15-18 DO-D3 Data 0,1, 2,3 In/Output DS97Z8X1104 PRELIMINARY 5Z86E04/E08 CMOS 28 OTP Microcontrollers ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This is a stress rating only; functional operation of the device at any condition above those indicated in the oper- ational sections of these specifications is not implied. Ex- posure to absolute maximum rating conditions for an ex- tended period may affect device reliability. Total power Zilog dissipation should not exceed 462 mW for the package. Power dissipatian is calculated as follows: Total Power Dissipation = Vpp x [Ipp>-(sum of I5,,)] +sum of [(Von7VYou) x lou] + Sum Of (Voz X Ip.) Parameter Min Max Units Note Ambient Temperature under Bias 40 +105 Cc Storage Temperature -65 +150 Cc Voltage on any Pin with Respect to Vss -0.7 +12 Vv 1 Voltage on Vpp Pin with Respect to Vss 0.3 +7 V Voltage on Pins 7, 8, 9, 10 with Respect to Veg 0.6 Vopt1 V 2 Total Power Dissipation 1,65 W Maximum Allowable Current out of Vs 300 mA Maximum Allowable Current into Vpp 220 mA Maximum Allowable Current into an input Pin -600 +600 pA 3 Maximum Allowable Current into an Open-Drain Pin -600 +600 pA 4 Maximum Allowable Output Current Sinked by Any I/O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Total Maximum Output Current Sinked by a Port 60 mA Total Maximum Output Current Sourced by a Port 45 mA Notes: 1. This applies to all pins except where otherwise noted. Maximum current into pin must be + 600 LA. There is no input protection diode from pin to Vpp (not applicable to EPROM Made). 2. 3. This excludes Pin 6 and Pin 7. 4. Device pin is not at an output Low state. 6 PRELIMINARY DS97Z8X1104Zilog STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Fig- ure 5). Z86E 04/E08 CMOS Z8 OTP Microcontrollers From Output Under Test Tt 150 pF Figure 5. Test Load Diagram CAPACITANCE Ty = 25C, Vog = GND = OV, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Min Max Input capacitance 0 10 pF Output capacitance 0 20 pF I/O capacitance 0 25 pF DS97Z8X1104 PRELIMINARY 7Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS Standard Temperature Ty = OC to+70C = Typical Sym _ Parameter Vec [4] Min Max @25C Units Conditions Notes Vinmax Max Input Voltage 4.5V 12 Vo lin<250 pA 1 5.5V 12 Vo ,ye250 pA 1 Vex Clock Input High 45V 0.8Vog Vee +0.3 2.8 VY Driven by External Voitage Clock Generator 5.5V 0.8Vog Voc+0.3 2.8 V__ Driven by External Clock Generator Vet Clock Input Low 4.5V Vs5-0.3 0.2 Von 1.7 V__ Driven by External Voltage Clock Generator 5.5V Vsg-0.3 0.2 Veg 1.7 V__ Driven by External Clock Generator Vin Input High Voltage 45V 0.7 Veg Vog+0.3 2.8 V 5.5V 0.7 Voc Voot0.3 92.8 V Vit Input Low Voitage 45V Vgg-0.3 0.2 Veg 1.6 V 5.5V Vg5-0.3 0.2 Voce 1.5 V Vou Output High Voltage 45V Voco-0.4 4.8 Vlog =-2.0 mA 5 5.5V Voo-0.4 4.8 Vo log =-2.0 mA 5 4.5V Voo-0.4 4.8 V Low Noise @ Ip, = -0.5 mA 5.5 Ve--0.4 4.8 VV Low Noise @ Il, =-0.5 mA Vou Output Low Voltage 4.5V 0.8 0.1 Vlg. = +4.0 mA 5 5.5V 0.4 0.1 Vo Io. = +4.0 mA 5 4.5V 0.4 0.1 V_ Low Noise @ Ip, = 1.0 mA 5.5V 0.4 0.1 V Low Noise @ Ip, = 1.0 mA Vor. Output Low Voltage 4.5V 0.8 0.8 Vo Ig, = +12 mA, 5 5.5V 0.8 0.8 Vig. = +12 mA, 5 Vorrser Comparator Input 4.5V 25.0 10.0 mV Offset Voltage 5.5V 25.0 10.0 = mV Viv Voc Low Voltage 2.2 3.0 2.8 Vo @6 MHz Max. Auto Reset Int. GLK Freq. hie Input Leakage 4,.5V -1.0 1.0 HA Vin =OV, Voc Comparate yen of 56V 1.0 1.0 WA Viy = OV, Veg log Output Leakage 4.5V -1.0 1.0 WA Vin = OV, Voc 5.5V ~1.0 1.0 BA Vin = OV, Veg Vicn Comparator Input 0 Veco -1.0 Vv Common Mode Voltage Range 8 PRELIMINARY DS97Z8X1104Zilog Z86E04/E08 CMOS Z8 OTP Microcontrollers Ty = OC to +70C Typical Sym Parameter Voc l4] Min Max @25C Units Conditions Notes leo Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins 5,7 Floating @ 2 MHz 5.5V 11.0 6.8 mA All Output and I/O Pins 5,7 Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins 5,7 Floating @ 8 MHz 5.5V 15.0 8.2 mA All Output and I/O Pins 5? Ficating @ 8 MHz 4.5V 20.0 12.0 mA All Output and |/O Pins 5,7 Floating @ 12 MHz 5.5V 20.0 12.0 mA Atl Output and I/O Pins 5,7 Floating @ 12 MHz lec} Standby Current 4.5V 4.0 2.5 mA HALT Mode Vj, = OV, 5,7 Voc @ 2 MHz 5.5V 4.0 2.5 mA HALT Mode Vy = OV, 5,7 Veco @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode Viy = OV, 5,7 Voc @ 8 MHz 5.5V 5.0 3.0 mA HALT Mode Vy = OV, 5,7 Vec @ 8 MHz 4.5V 7.0 4.0 mA HALT Mode Vy = OV, 5,7 Veco @ 12 MHz 5.5V 7.0 4.0 mA HALT Mode Vy = OV, 5,7 Veg @ 12 MHz leg Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins 7 (Low Noise Mode) Floating @ 1 MHz 5.5V 11.0 6.8 mA All Output and I/O Pins 7 Floating @ 1 MHz 4.5V 13.0 7.5 mA All Output and 1/O Pins 7 Floating @ 2 MHz 5.5V 13.0 7.5 mA All Output and I/O Pins 7 Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins 7 Floating @ 4 MHz 5.5V 15.0 8.2 mA All Output and I/O Pins 7 Floating @ 4 MHz DS97Z8X1104 PRELIMINARY 9Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) T, = 0C to +70C Typical Sym Parameter Vec [4] = Min Max @25C Units Conditions Notes lec, Standby Current 4.5V 4.0 2.5 mA HALT Mode Vy = OV, 7 (Low Noise Mode) Vee @ 1 MHz 5.5V 4.0 2.5 mA HALT Mode Vj, = OV, 7 Veco @ 1 MHz 4.5V 45 2.8 mA HALT Mode Vj, = OV, 7 Voc @ 2 MHz 5.5V 45 2.8 mA HALT Mode V,, = OV, 7 Voc @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode V,, = OV, 7 Voc @ 4 MHz 5.5V 5.0 3.0 mA HALT Mode Vy = OV, 7 Voc @ 4 MHz leco Standby Current 4.5V 10.0 1.0 pA STOP Mode Vy = OV, Veg 7.8 WDT is not Running 5.5V 10.0 1.0 wA STOP Mode Vy = OV,Vog 7,8 WDT is not Running la, Auto Latch Low 4.5V 32.0 16 WA OV<Vin<Voo Current 5.5V 32.0 16 pA OV<Viy<Voo laun Auto Latch High 4.5V -16.0 8.0 vA OV<Viy <Voo Current 5.5V -16.0 80 WA OV<Vy<Voo Notes: 1. 2. 3. DNAH Port 2 and Port 0 only Vsg = OV = GND The device operates down to Vy of the specified frequency for V.,_The minimum operational Veg is determined on the value of the voltage V,y at the ambient temperature. The V,, increases as the temperature decreases. Voc = 4.5 to 5.5V, typical values measured at Voc = 5.0V. The Vg voltage specification of 5.6 V guarantees 5.0 V + 0.5V with typical values measured at Voc = .0V. Standard Mode (not Low EMI Mode) Z86E08 only All outputs unloaded and all inputs are at Vog or Vgg level. If analog comparator is selected, then the comparator inputs must be at Vog level. 10 PRELIMINARY DS972Z8X1104Z86E04/E08 Zilog CMOS Z8 OTP Microcontrollers DC ELECTRICAL CHARACTERISTICS Extended Temperature T, = 40C to +#105C Typical Sym Parameter Vec [4] = Min Max @25C Units Conditions Notes Vinmax Max Input Voltage 4.5V 12.0 Vo ly < 250 pA 1 5.5V 12.0 Vo odin < 250 WA 1 Von Clock Input High 4.5V O0.8Voc Voo+0.3 2.8 V Driven by External Voltage Ciock Generator 5.5V O0.8Vog Voot0.3 2.8 V____ Driven by External Clock Generator Vor Clock Input Low 4.5V Vgg-0.3 0.2 Voge 1.7 V Driven by External Voltage Clock Generator 5.5V Vgg-0.3 0.2 Voc 1.7 V___ Driven by Externai Clock Generator Vin Input High Voltage 4.5V 0.7 Veg Voot0.3 2.8 Vv 5.5V 0.7 Veg Vec+0.3 2.8 V Vit Input Low Voltage 4.5V Vg5-0.39 0.2 Veg 1.6 V 5.5V 0 Vg5-0.3 0.2 Veg 1.5 V Vou Output High Voltage 4.5V V0.4 4.8 Volo =-2.0 mA 5 5.5V Vo_-0.4 4.8 Vo ology = 2.0 MA 5 4.5V = Vo--0.4 V Low Noise @ Ip, = -0.5 mA 5.5V Voc -0.4 V Low Noise @ Igy =-0.5 mA Vou Output Low Voltage 4.5V 0.4 0.1 Vo Ig. = +40 mA 5 5.5V 0.4 0.1 Vo Ig. =+4.0 mA 5 4.5V 0.4 0.1 V Low Noise @ Ig, = 1.0 mA 5.5V 0.4 0.1 Vs Low Noise @ Ip, = 1.0 mA Vor. Output Low Voitage 4.5V 1.0 0.3 Vlg, = +12 mA, 5 5.5V 1.0 0.3 Vo lop = +12 mA, Vorrset Comparator Input 4.5V 25.0 10.0 mV Offset Voltage 5.5V 25.0 10.0 mV Viv Voc Low Voltage 1.8 3.8 2.8 Vo @6 MHz Max. Int. 3 Auto Reset CLK Freq. he Input Leakage 4.5V -1.0 1.0 HA Vin = OV, Vee of Comparator) 5.5V 1.0 1.0 WA Vin = OV, Veg lot Output Leakage 4.5V -1.0 1.0 PA Vin = OV, Voc 5.5V -1.0 1.0 WA Vin = OV, Voc Vicr Comparator Input 0 Veg -1.5 Vv Common Mode Voltage Range DS97Z8X1 104 PRELIMINARY 11Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) T, = 40C to +105C Typical Sym _ Parameter Veco [4] = Min Max @25C Units Conditions Notes loo Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins 5,7 Floating @ 2 MHz 5.5V 11.0 6.8 mA All Output and I/O Pins 5,7 Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins 5,7 Floating @ 8 MHz 5.5V 16.0 8.2 mA All Output and I/O Pins 5,7 Floating @ 8 MHz 4.5V 20.0 12.0 mA All Output and i/O Pins 5,7 Floating @ 12 MHz 5.5V 20.0 12.0 mA All Output and I/O Pins 5,7 Floating @ 12 MHz lees Standby Current 4.5V 5.0 2.5 mA HALT Mode V,, = OV, 5,7 Veco @ 2 MHz 5.5V 5.0 2.6 mA HALT Mode Vj, = OV, 5,7 Vee @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode V,, = OV, 5,7 Veco @ 8 MHz 5.5V 5.0 3.0 mA HALT Mode Vy = OV, 5,7 Voc @ 8 MHz 4.5V 7.0 4.0 mA HALT Mode Vj, = OV, 5,7 Voc @ 12 MHz 5.5V 7.0 40 mA HALT Mode Vy = OV, 5,7 Voo @ 12 MHz loc Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins 7 (Low Noise Mode) Floating @ 1 MHz 5.5V 11.0 6.8 mA All Output and I/O Pins 7 Floating @ 1 MHz 4.5V 13.0 7.5 mA All Output and I/O Pins 7 Floating @ 2 MHz 5.5V 13.0 7.5 mA All Output and I/O Pins 7 Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins 7 Floating @ 4 MHz 5.5V 15.0 8.2 mA All Output and I/O Pins 7 Floating @ 4 MHz 12 PRELIMINARY DS97Z8X1104Z86E04/E08 Zilog CMOS 28 OTP Microcontrollers T, = 40C to +105C Typical Sym Parameter Voc [4] Min Max @25C Units Conditions Notes lect Standby Current 4.5V 4.0 2.5 mA HALT Mode Vy = OV, 7 {Low Noise Mode) Voc @ 1 MHz 5.5V 4.0 2.5 mA HALT Mode Vy = OV, 7 Veco @ 1 MHz 4.5V 4.5 2.8 mA HALT Mode V,, = OV, 7 Voc @ 2 MHz 5.5V 45 2.8 mA HALT Mode V,,, = OV, 7 Veco @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode Vy = OV, 7 Voc @ 4 MHz 5.5V 5.0 3.0 mA HALT Mode Vy = OV, 7 Voc @ 4 MHz lees Standby Current 4.5V 20 1.0 HA STOP Mode Vy=O0V,Ve_ 7,8 WDT is not Running 5.5V 20 1.0 pA STOP Mode Vy =OV.Veg 7,8 WOT is not Running laLL Auto Latch Low 4.5V 40 16 WA OV<ViNn<Veo Current 5.5V 40 16 WA OV <Viy <Voo lacy Auto Latch High 4.5V -20.0 -8.0 WA OV<Vin<Voo Current 5.5V 20.0 8.0 WA OV<Vin<Voo Notes: 1. Port 2 and Port 0 only 2. Vgg = OV = GND 3. The device operates down to V_, of the specified frequency for V_y The minimum operational Voc is determined on the value of PNOas the voltage Vy, at the ambient temperature. The V\, increases as the temperature decreases. Voc = 4.5V to 5.5V, typical values measured at Voc = 5.0V Standard Mode (not Low EMI Mode) Z86E08 only All outputs unloaded and all inputs are at Vog oF Vgg level. lf analog comparator is selected, then the comparator inputs must be at Voc level. D39728xX1104 PRELIMINARY 13Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS Figure 6. AC Electrical Timing Diagram 14 PRELIMINARY DS97Z8X1104Zilog AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Standard Temperature Z86E04/E08 CMOS Z8 OTP Microcontrollers 15 Taz 0 C to +70 C 8 MHz 12 MHz No Symbol Parameter Vec Min Max Min Max Units Notes 1 Tpc Input Clock Period 4.5V 125 DC 83 DC ns 1 5.5V 125 DC 83 DC ns 1 2 TrC, TFC Clock input Rise 4.5V 25 15 ns 1 and Fall Times 5.5V 25 15 ns 1 3 Tw Input Clock Width 4.5V 62 41 ns 1 5.5V 62 41 ns 1 4 TwTinl Timer Input Low Width 4.5V 100 100 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4,5V 5TpC 5TpC 1 5.5V 5TpC 5Tpc 1 6 TpTin Timer Input Period 4.5V 8TpC 8Tpc 1 5.5V 8TpC 8Tpc 1 7 TrTin, Timer Input Rise 4.5V 100 100 ns 1 TtTin and Fall Time 5.5V 100 100 ns 1 8 TwiL Int. Request Input 4.5V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 1,2 9 TwlH Int. Request Input 4.5V 5TpC STpc 1,2 High Time 5.5V 5TpC 5Tpc 1,2 10 Twat Watch-Dog Timer 4.5V 12 12 ms 1 Delay Time for Timeout 5.5V 12 12 ms 1 11 Tpor Power-On Reset Time 4.5V 20 80 20 80 ms 1 .5V 20 80 20 80 ms 1 Notes: 1. Timing Reference uses 0.7 Veg for a logic 1 and 0.2 Veg for a logic 0. 2. Interrupt request through Port 3 (P33-P31). DS97Z8X1104 PRELIMINARY 16Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Extended Temperature T,= 40 C to +105 C 8 MHz 12 MHz No Symbol Parameter Voc Min Max Min Max Units Notes 1 Tpc Input Clock Period 4.5V 125 DC 83 DC ns 1 5.5V 125 DC 83 DG ns 1 2 TrC,TfC = Clock Input Rise 4,.5V 25 15 ns 1 and Fall Times 5.5V 25 15 ns 1 3 Tw Input Clock Width 4.5V 62 41 ns 1 5.5V 62 41 ns 1 4 TwTinL = Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 1 5.5V 5TpC 5Tpc 1 6 TpTin Timer Input Period 4.5V 8Tpc 8Tpc 1 5.5V 8TpC 8Tpc 1 7 TrTin, Timer input Rise 4,.5V 100 100 ns 1 TtTin and Fall Time 5.5V 100 100 ns 1 8 TwIL Int. Request Input 4.5V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 1,2 9 TwlH Int. Request Input 4.5V 5Tpc 5TpC 1,2 High Time 5.5V 5TpC 5Tpc 1,2 10 Twat Watch-Dog Timer 4,5V 10 10 ms 1 Delay Time for Timeout 5.5V 10 10 ms { 11 Tpor Power-On Reset Time 4.5V 12 100 12 100 ms 1 5.5V 12 100 12 100 ms 1 Notes: 1. Timing Reference uses 0.7 Veg for a logic 1 and 0.2 Vgg for a logic 0. 2. Interrupt request mace through Port 3 (P33P31). 16 PRELIMINARY DS97Z8X1104Zilog AC ELECTRICAL CHARACTERISTICS Low Noise Mode, Standard Temperature Z86E04/E08 CMOS Z8 OTP Microcontrollers T,= 0 C to +70C 1 MHz 4 MHz No Symbol Parameter Voe Min Max Min Max Units Notes 1 TPC Input Clock Period 4.5V 1000 DC 250 DC ns 1 5.5V 1000 DC 250 DC ns 1 2 TrG Clock Input Rise 4.5V 25 25 ns 1 TC and Fall Times 5.5V D5 25 ns f 3 Two Input Clock Width 4.5V 500 126 ns 1 5.5V 500 125 ns 1 4, TwTink, Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 2.5TpG 2.5TpG 1 5.5V 2.5TpC 2.5TpG 1 6 TpTin Timer Input Period 4.5V 4TpC 4Tpc 1 5.5V 4TpC 4Tpc 1 7 TrTin, Timer Input Rise 4.5V 100 100 ns 1 TtTin and Fall Time 5.5V 100 100 ns 1 8 TwIL Int. Request Input 4.5V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 1,2 9 TwlH Int. Request Input 4.5V 2.5TpC 2.5TpC 1,2 High Time 5.5V _2.5TpC 2.5TpC 1,2 10 Twat Watch-Dog Timer 4.5V 12 12 ms 1 Delay Time for Timeout 5.5V 12 12 ms 1 Notes: 1. Timing Reference uses 0.7 Vog for a logic 1 and 0.2 Voc for a logic 0. 2. interrupt request through Port 3 (P33-P31). DS97Z8X1 104 PRELIMINARY 17Z86E04/E08 CMOS 28 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS (Continued) Low Noise Mode, Extended Temperature Ta= 40 C to +105 C 1 MHz 4 MHz No Symbol Parameter Veo Min Max Min Max Units Notes 1 TPG Input Ctock Period 4.5V 1000 DC 250 DG ns 1 5.5V 1000 DC 250 DC ns 1 2 TrC Clock Input Rise 4.5V 25 25 ns 1 TIC and Fall Times 5.5V 25 25 ns 1 3 TwC Input Clock Width 4.5V 500 125 ns 1 5.5V 500 125 ns 1 4, TwTink Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4,5V 2.5TpC 2.5TpC 1 5.5V 2.5Tpc 2.5TpC 1 6 TpTin Timer Input Period 4.5V 4TpC 4Tpc 1 5.5V 4TpG 4Tpc 1 7 TrTin, Timer Input Rise 4.5V 100 100 ns 1 TtTin and Fall Time 5.5V 100 160 ns 1 8 TwiL Int. Request Input 4,6V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 1,2 9 TwlH Int. Request Input 4.5V 2.5Tpc 2.5TpC 1,2 High Time 55V -2.5TpC 2.5TpC 1,2 10 Twat Watch-Dog Timer 4.5V 10 10 ms 1 Delay Time for Timeout 5.5V 10 10 ms 1 Notes: 1. Timing Reference uses 0.7 Vog for a logic 1 and 0.2 Vag for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 18 PRELIMINARY DS972Z8X1104Zilog Z86E04/E08 CMOS Z8 OTP Microcontrollers LOW NOISE VERSION Low EMI Emission The Z86E04/E08 can be programmed to operate in a Low EMI Emission Mode by means of a mask ROM bit option. Use of this feature results in: m@ All pre-driver slew rates reduced to 10 ns typical. @ = Internal SCLK/TCLK operation limited to a maximum of 4 MHz-250 ns cycle time. m@ Output drivers have resistances of 500 Ohms (typical). mB Oscillator divide-by-two circuitry eliminated. The Low EMi Mode is mask-programmable to be selected by the customer at the time the ROM code is submitted. PIN FUNCTIONS OTP Programming Mode D7D0 Data Bus. Data can be read from, or written to, the EPROM through this data bus. Voc Power Supply. It is typically 5V during EPROM Read Mode and 6.4V during the other modes (Program, Pro- gram Verify, and so on). CE Chip Enable {active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. OE Output Enable (active Low). This pin drives the Data Bus direction. When this pin is Low, the Data Bus is output. When High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the differ- ent EPROM Program Modes by applying different voltages. Vpp Program Voltage. This pin supplies the program volt- age. Clear Clear (active High). This pin resets the internal ad- dress counter at the High Level. Clock Address Clock. This pin is a clock input. The internal address counter increases by one with one clock cycle. PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above Vo, occur on the XTAL1 pin. In addition, processor operation of Z8 OTP devices may be affected by excessive nolse surges on the Vpp, CE, EPM, OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP Mode include the following: m Using a clamping diode to Voc. @ Adding a capacitor to the affected pin. Note: Programming the EPROM/Test Mode Disable option will prevent accidental entry into EPROM Mode or Test Mode. DS97Z8X1104 PRELIMINARY 19Z86E04/E08 CMOS Z8 OTP Microcontrollers PIN FUNCTIONS (Continued) XTAL1, XTAL2 Crystal in, Crystal Out (time-based input and output, respectively). These pins connect a parallel- resonant crystal, LC, or an external single-phase clock (8 MHz or 12 MHz max) to the on-chip clock oscillator and buffer. Port 0, PO2-P00. Port 0 is a 3-bit bidirectional, Schmitt- triggered CMOS-compatible I/O port. These three I/O lines can be globally configured under software control to be in- puts or outputs (Figure 7). Zilog Auto Latch. The Auto Latch puts valid CMOS levels on ail CMOS inputs (except P33, P32, P31) that are not external- ly driven. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. On Power-up and Reset, the Auto Latch will set the ports to an undetermined state of O or 1. Default condition is Auto Latches enabled. 78 tl $$. Port 0 (I/O) pe Out 1.5 2.3 Hysteresis Vcec@ 5.0V In 4 PAD Auto Latch Option R = 500 kQ Figure 7. Port 0 Configuration 20 PRELIMINARY DS97Z8X1104Z86E04/E08 Zilog CMOS 28 OTP Microcontrollers Port 2, P27-P20. Port 2 is an 8-bit, bit programmable, bi- control to be inputs or outputs, independently. Bits pro- directional, Schmitt-triggered CMOS-compatible I/O port. grammed as outputs can be globally programmed as ei- These eight i/O lines can be configured under software ther push-pull or open-drain (Figure 8). Z8 Port 2 (I/Q) 1.5 2.3 Hysteresis VCC @5.0V =r Auto Latch Option Figure 8 Port 2 Configuration DS97Z8X1 104 PRELIMINARY 21Z86E04/E08 CMOS 28 OTP Microcontrollers PIN FUNCTIONS (Continued) Zilog Port 3, P33-P31. Port 3 is a 3-bit, CMOS-compatible port These three input lines are also used as the interrupt with three fixed input (P33-P31) lines. These three input sources IRQO-IRQ3, and as the timer input signal Tw (Fig- lines can be configured under software control as digital __ure 9). Schmitt-trigger inputs or analog inputs. 28 et] Port 3 0 = Digital R247 =P3M ~ 1 =Analog D1 PAD DIG. l = i t P31 (AN1) AN. ! I PAD P32 (AN2) + I ! { [ I I P33 (REF} Veo IRQ 0,1,2 = Falling Edge Detection IRQ3 = Rising Edge Detection Figure 9. Port 3 Configuration PAD ans pa = TIN P31 Data Latch IRQ2 IRQ3 P32 Data Latch IRQO P33 Data Latch IRQ1 22 PRELIMINARY DS97Z8X1104Zilog Comparator Inputs. Two analog comparators are added to input of Port 3, P31, and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In Analog Mode, P33 input functions serve as a reference voltage to the comparators. The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP ZS6E04/E08 GMOS Z8 OTP Microcontrollers Mode. The common voltage range is 0-4 V when the Vo, is 5.0V; the power supply and common mode rejection ra- tios are 90 dB and 60 dB, respectively. Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's output. The comparator output is used for interrupt generation, Port 3 data inputs, or T), through P31. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ1 and/or P33 input. FUNCTIONAL DESCRIPTION The following special functions have been incorporated into the 28 devices to enhance the standard Z8 core archi- tecture to provide the user with increased design flexibility. RESET. This function is accomplished by means of a Pow- er-On Reset or a Watch-Dog Timer Reset. Upon power- up, the Power-On Reset circuit waits for Tpog ms, plus 18 clock cycles, then starts program execution at address 000C (Hex) (Figure 10). The Z8 control registers' reset val- ue is shown in Table 3. INT OSC XTAL OSG POR | (Cold Start) . Chip Reset Delay Line Pu} 18CLK Ls TPOR msec Reset Fititer P27 (Stop Mode) Figure 10. Internal Reset Configuration Power-On Reset (POR). A timer circuit clocked by a ded- icated on-board RC oscillator is used for a POR timer func- tion. The POR time allows Vc, and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the four following conditions: mw Power-bad to power-good status m Stop-Mode Recovery m@ WOT time-out a WDH time-out Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the 28 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an on- board RC oscillator. DS97Z8X1104 PRELIMINARY 23Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Table 3. Control Registers Reset Condition Addr. Reg. D7 D6 D5 D4 D3 D2 D1 BO Comments FF SPL a) 0 0 0 0 0 0 0 FD RP 0 0 0 0 0 0 0 0 FC FLAGS U U U U U U U U FB IMR 0 U U U U U U U FA IRQ U U 0 0 0 0 0 0 IRQ is used for positive edge detection FQ IPR U U U U U U U U F8* POiM U U U 0 U U 0 1 F7* P3M U U U U U U 0 0 F6* P2M 1 1 1 1 1 1 1 1 Inputs after reset F5 PREO U U U U U U U 0) F4 TO U U U U U U U U F3 PRE1 U U U U i) U 0 0 F2 T1 U U U U U U U U Fi TMR 0 0 0 0 0 0 0 0 Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability. 24 PRELIMINARY DS97Z8X1104Zilog Program Memory. The Z86E04/E08 addresses up to 1K/2KB of Internal Program Memory (Figure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that cor- respond to the six available interrupts. Bytes 0-1024/2048 are on-chip one-time programmable ROM. 1023/2047 Identifiers 3FFH/7FFH Location of OnChip First Byte of ROM Instruction Executed WfP -------------+ After RESET 45 OCH i" IRQS OBH 10 IRQS OAH 9 IRQ4 OSH a lAQ4 08H IRQ3 07H Interrupt Vector 06H (Lower Byte) ~~ IRQS 5 fos IRQ2 05H 4 |. IR 04H Interrupt ~ | Qe Vector (Upper Byte) > IRQ1 03H 2 IRQ) 02H 1 IRQO 01H 0 IRQG OCH Figure 11. Program Memory Map Z86E04/E08 CMOS 28 OTP Microcontrollers Register File. The Register File consists of three I/O port registers, 124 general-purpose registers, and 14 control and status registers RO-R3, R4-R127 and R241-R255, respectively (Figure 12). General-purpose registers occu- py the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS 28. Location Identifiers 255 (FFH) Stack Pointer (Bits 7-0) SPL 254 (FE) General-Purpose Register GPR 253 (FD) Register Pointer RP 252 (FC) Program Control Flags FLAGS 251 (FB) Interrupt Mask Register IMR 250 (FA) Interrupt Request Register IRQ 249 (F9) Interrupt Priority Register IPR 248 (F8) Ports 0-1 Mode POIM 247 (F7) Port 3 Mode P3M 246 (F6) Port 2 Mode P2M 245 (F5) TO Prescaler PREO 244 (F4) Timer/Counter 0 TO 243 (F3) T1 Prescaler PRE1 242 (F2} Timer/Gounter 1 T1 241 (F1H) Timer Mode TMR Not Implemented 128 127 (7FH) General-Purpose Registers 4 3 Port 3 P3 2 Port 2 P2 1 Reserved Pi 0 (00H) Port 0 PO Figure 12. Register File DS97Z8X1 104 PRELIMINARY 25Z86E04/E08 CMOS Z8 OTP Microcontrollers FUNCTIONAL DESCRIPTION (Continued) The 28 instructions can access registers directly or indi- rectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file is divided into eight work- ing register groups, each occupying 16 continuous loca- tions. The Register Pointer (Figure 13) addresses the starting location of the active working-register group. Pd | 76 5 4 | rm 2 ri R253 {Register Pointer) The upper nibble of the register file address provided by the register palnter specifies the active working-+egister group. } Ri& to RO ( FF FO 7F 70 oF 60 SF 50 4F = The lower nibble a of the register file address Specified Workin re Register Group wi provided by the 30 instruction points 2F to the specified = register. 20 1F a Register Group 1 R15 to RO 10 OF Register Group 0 Ri5 to R4* VO Ports R3 to RO 00 Expanded Ragister Group {0) is selected in this figure by handing bits D3 to D0 as "0" in Register R253(RP). Figure 13. Register Polnter Zilog Stack Pointer. The 28 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 124 gen- eral-purpose registers. General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the Vog voltage-specified operating range. Note: Register R254 has been designated as a general-purpose register and is set to 00 Hex after any reset or Stop-Mode Recovery. Counter/Timer. There are two 8-bit programmable counter/timers (TO and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by in- ternal or external clock sources; however, the TO can be driven by the internal clock source only (Figure 14}. The 6-bit prescalers divide the input frequency of the clock source by any integer number from 1 to 64. Each prescater drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt re- quest IRQ4 (TO) or IR@5 (T1} is generated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (Single-Pass Mode) or to automatically reload the initial value and con- tinue counting (Modulo-N Continuous Mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal mi- croprocessor clock divided by four, or an external signal in- put through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger in- put that is retriggerable or non-retriggerable, or used as a gate input for the internal clock. 26 PRELIMINARY DS97Z8X1104Z86E04/E08 Zilog CMOS Z8 OTP Microcontrollers latamal Data Bus we | u wie | J Read | if Osc PREQ Initial Value Initial Value Current Value { Register Register Register aK 2 uy u} 1 6-Bit &-bit _ i] dol Down Down Counter Counter -_$ e- rXHH p_ Internal Clock J Extemal Clock Clock Logic Bit 8-Ba pe 1S +4 Down Down h Counter Counter | Internal Clock | fi | Gated Clock PRE1 11 11 Triggered Clock Initial Value Initial Value Current Value Register Register Register TIN P31 wie? Jf wits Jf east Jb * Note: By passed, if Low EMI Made is selected. Figure 14. Counter/Timers Biock Diagram Internal Data Bus DS97Z8X1 104 PRELIMINARY 27Z86E04/E08 GMOS 28 OTP Microcontrollers FUNCTIONAL DESCRIPTION (Continued) Interrupts. The Z8 has six interrupts from six different sources. These interrupts are maskable and prioritized (Figure 15). The sources are divided as follows: the falling edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge of P32 (AN2), and two counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 4). When more than one interrupt is pending, priorities are re- solved by a programmabie priority encoder that is con- trolled by the Interrupt Priority register. All 28 interrupts are Zilog To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service. Note: User must select any Z8GE08 mode in Zilog's C12 ICEBOX emulator. The rising edge interrupt is not sup- ported on the CCP emulator {a hardware/software workaround must be employed). Table 4. Interrupt Types, Sources, and Vectors Vector vectored through iocations in program memory. When an Name Source Location Comments Interrupt machine cycle is activated. an Interrupt Request TRQQ _AN2(P32) 0,1 External (FyEdge is granted. This disables all subsequent interrupts, saves IRQ REF(P33) 2,3 External (F)Edge the Program Counter and Status Flags, and then branches : , IRQ2. AN1{(P31) 45 External (F)Edge to the program memory vector location reserved for that in- IRQ3 AN2(P32 67 Ext I (R)Ed terrupt. This memory location and the next byte contain the (P32) ' xternal (R)Edge 16-bit starting address of the interrupt service routine for !RQ4 TO 8,9 Internal that particular interrupt request. IRQS 10,11 Internal Notes: F = Falling edge triggered R = Rising edge triggered IRQO - (ROS IRQ PITY TT, Litt IMR Global X6 interrupt Enable IPR Interrupt ( A Request LOGIC Vector Select Figure 15. interrupt Block Dlagram 28 PRELIMINARY DS97Z8X1 104Zilog Clock. The Z8 on-chip oscillator has a high-gain, parallel- resonant amplifier for connection to a crystal, LC, RC, ce- ramic resonator, or any suitable external clock source (XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, up to 12 MHz max., with a series resistance (RS) of less than or equal to 100 Ohms. XTAL1 XTAL1 C1 -L ak XTAL2 C2 Lh Ceramic Resonator or LG Crystal C1, C2 = 47 pF TYP* F = 8 MHz * Typical value including pin parasitics Z86E04/E08 CMOS Z8 OTP Microcontrollers The crystal should be connected across XTAL1 and XTAL2 using the vendors crystal recommended capacitors from each pin directly to device ground pin 14 (Figure 16). Note that the crystal capacitor loads should be connected to Vgs, Pin 14 to reduce Ground noise injection. XTAL1 XTAL1 Tr = R XTAL2 XTAL2 External Clock RC @ 5V Vee (TYP) Ci = 100 pF R=2K F =6 MHz Figure 16. Osciliator Configuration DS97Z8X1 104 PRELIMINARY 29Z86E04/E08 CMOS 28 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Table 5. Typical Frequency vs. RC Values Veo 2 5.0V @ 25C Load Capacitor 33 pFd 56 pFd 100 pFd 0.00 1p:Fd Resistor (R) A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz) 1.0M 33K 31K 20K 20K 12K 11K 1.4K 1.4K 560K 56K 52K 34K 32K 20K 19K 2.5K 2.4K 220K 144K 130K 84K 78K 48K 45K 6K 6K 100K 315K 270K 182K 164K 100K O5K 12K 12K 56K 552K 480K 330K 300K 185K 170K 23K 22K 20K 1.4M 1M 884K 740K 500K 450K 65K 61K 10K 2.6M 2M 1.6M 1.3M 980K 820K 130K 123K 5K 4.4M 3M 2.8M 2M 1.7K 1.3M 245K 225K 2K 8M 5M 6M 4M 3.8K 2.7M 600K 536K 1K 12M 7M 8.8M 6M 6.3K 4,.2M 1.0M 950K Notes: A = STD Mode Frequency. B = Low EMI Mode Frequency. Table 6. Typical Frequency vs. RC Values Veg = 3.3V @ 25C Load Capacitor Resistor (R) 33 pFd 58 pFd 100 pFd 0.00 1nFd A{Hz) B(Hz) A(Hz} B(Hz) A(Hz) B(Hz) A(Hz) B(Hz) 1.0M 18K 18K 12K 12K 7.4K 7.7K 1K 1K 560K 30K 30K 20K 20K 12K 12K 1.6K 1.6K 220K 70K 70K 47K 47K 30K 30K 4K 4K 100K 150K 148K 97K 96K 60K 60K 8K 8K 56K 268K 250K 176K 170K 100K 100K 15K 15K 20K 690M 600K 463K 416K 286K 266K 40K 40K 10K 1.2M 1M 860K 730K 540K 480K 80K 76K 5K 2M 1.7M 1.5M 1.2M 950K 820K 151K 138K 2K 4.6M 3M 3.3M 2.4M 2.2M 1.6M 360K 316K 1K 7M 4,.6M 5M 3.6M 3.6K 2.6M 660K 565K Notes: A = STD Made Frequency. B = Low EMI Mode Frequency. PRELIMINARY DS97Z8X1104 30Zilog Z86E04/E08 CMOS Z8 OTP Microcontrollers HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timers and external interrupts IRQO, IRG1, IRQ2 and IRQ3 remain ac- tive. The device is recovered by interrupts, either external- ly or internally generated. An interrupt request must be ex- ecuted (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. Note: On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT Mode. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 yA. The STOP Mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP Mode. Program exe- cution begins at location O00C(Hex). However, when P27 is used to release the STOP Mode, the I/O port Mode reg- isters are not reconfigured to their default power-on condi- tions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an un- known state. To use the P27 release approach with STOP Mode, use the following instruction: LD P2M, #1XXX XXXXB NOP STOP X = Dependent on user's application. Note: A low level detected on P27 pin will take the device out of STOP Mode even if configured as an output. In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, such as: Watch-Dog Timer (WDT). The Watch-Dog Timer is en- abled by instruction WDT. When the WDT is enabied, it cannot be stopped by the instruction. With the WDT in- struction, the WDT is refreshed when it is enabled within every 1 Twat period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, $=0, V=0. WDT = 5F (Hex) Opcode WDT (5FH). The first time Opcode 5FH is execut- ed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every Twor! otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of Tpor, plus 18 XTAL clock cycles. The software enabled WDT does not run in STOP Mode. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT Mode. A WDH instruction executed without executing WDT (5FH) has no effect. Permanent WDT. Selecting the hardware enabled Perma- nent WDT option, will automatically enable the WDT upon exiting reset. The permanent WDT will always run in HALT Mode and STOP Mode, and it cannot be disabled. Auto Reset Voltage (V,,,). The Z8 has an auto-reset built- in. The auto-reset circuit resets the Z8 when it detects the Vee below Vive Figure 17 shows the Auto Reset Voltage versus tempera- ture. If the Veg drops below the VCC operating voltage range, the 28 will function down to the Vy unless the inter- nal clock frequency is higher than the specified maximum Viy frequency. FF NOP ; Clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; Clear the pipeline TF HALT ; enter HALT Mode DS972Z8xX1 104 PRELIMINARY 31Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Vec (Volts) 2.9 2.8 2.7 Pan | pe 2.6 ae P| 2.5 P| 2.4 2.3 Temp 40C -20C =s_OS 20C 40C 60C 380C 100C Figure 17. Typical Auto Reset Voltage (V_y) vs. Temperature 32 PRELIMINARY DS97Z8X1104Zilog Low EMI Emission The 28 can be programmed to operate in a low EMI Emis- sion (Low Noise) Mode by means of an EPROM program- mable bit option. Use of this feature results in: m Less than 1 mA consumed during HALT Mode. Ail drivers slew rates reduced to 10 ns (typical). m@ Internal SCLK/TCLK = XTAL operation limited to a maximum of 4 MHz250 ns cycle time. m Output drivers have resistances of 500 ohms (typical). @ Oscillator divide-by-two circuitry eliminated. In addition to Vop and GND (Vgs), the Z8 changes all its pin functions in the EPROM Mode. XTAL2 has no function, XTAL1 functions as CE, P31 functions as OE, P32 func- tions as EPM, P33 functions as Vpp, and P02 functions as PGM. Z86E04/E08 CMOS Z8 OTP Microcontrollers ROM Protect. ROM Protect fully protects the Z8 ROM code from being read externally. When ROM Protect is se- lected, the instructions LDC and LDCi are supported (Z86E04/E08 and Z86C04/C08 do not support the instruc- tions of LDE and LDEI). When the device is programmed for ROM Protect, the Low Noise feature will not automati- cally be enabled. Please note that when using the device in a noisy environ- ment, itis suggested that the voltages on the EPM and CE pins be clamped to Veg through a diode to Ve, to prevent accidentally entering the OTP Mode. The Vpp requires both a diode and a 100 pF capacitor. Auto Latch Disable. Auto Latch Disable option bit when programmed will globally disable all Auto Latches. WDT Enable. The WDT Enable option bit, when pro- grammed, will have the hardware enabled Permanent WDT enabled after exiting reset and can not be stopped in Halt or Stop Made. EPROM/Test Mode Disable. The EPROM/Test Mode Disable option bit, when programmed, will disable the EPROM Mode and the Factory Test Mode. Reading, veri- fying, and programming the Z8 will be disabled. To fully verify that this mode is disabled, the device must be power cycled, User Modes. Table 7 shows the programming voltage of each mode. Table 7. OTP Programming Table Programming Modes Vp EPM cE OE PGM ADDR DATA V,," EPROM READ NU Vu Vie Vi Vin ADDR Out 5.0V PROGRAM Vu Vin Vit Vin Vi ADDR In 6.4V PROGRAM VERIFY Vu Vin Vie Vit Vin ADDR Out 6.4V EPROM PROTECT Vu Vu Vu Vin Vib NU NU 6.4V LOW NOISE SELECT Vu Vin Vu Vie Vi NU NU 6.4V AUTO LATCH DISABLE Vu Vin Vu Vie Vib NU NU 6.4V WDT ENABLE Vu Vit Vu Vin Vib NU NU 6.4V EPROM/TEST MODE Vu Vit Vu Vir Vit NU NU 6.4V Notes: 1. Vy=12.75V + 0.25 Voge. 2. Viy= As per specific 78 BC specification. 3. V)= As per specific Z8 DC specification. 4. X = Not used, but must be set to V,, or Vj, level. 5. NU = Not used, but must be set to either V,, or V,, level. 6. Ipp during programming = 40 mA maximum, 7. log during programming, verify, or read = 40 mA maximum. 8. * Voc has a tolerance of +0.25V. DS97Z8X1 104 PRELIMINARY 33Z86E04/E08 CMOS 28 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) Internal Address Counter. The address of Z8 is generat- ed internally with a counter clocked through pin P01 (Clock). Each clock signal increases the address by one and the high level of pin POO (Clear) will reset the ad- dress to zero. Figure 18 shows the setup time of the serial address input. Programming Waveform. Figures 19, 20, 21 and 22 show the programming waveforms of each mode. Table 8 shows the timing of programming waveforms. Programming Algorithm. Figure 23 shows the flow chart of the Z8 programming algorithm. Table 8. Timing of Programming Waveforms Parameters Name Min Max Units 1 Address Setup Time 2 ps Data Setup Time 2 us 3 V,p Setup 2 LS 4 Veg Setup Time 2 ys 5 Chip Enable Setup Time 2 us 6 Program Pulse Width 0.95 ms 7 Data Hold Time 2 us 8 OE Setup Time 2 us 9 Data Access Time 188 ns 10 Data Output Float Time 100 ns 11 Overprogram Pulse Width 2.85 ms 12 EPM Setup Time 2 us 13 PGM Setup Time 2 us 14 Address to OE Setup Time 2 us 15 Option Program Pulse Width 78 ms 16 OE Width 250 ns 17 Address Valid to OE Low 425 ns 34 PRELIMINARY DS97Z8X1104Z86E04/E08 Zilog ; CMOS Z8 OTP Microcontroilers are fo & P00 = Clear ) L Vpp/EPM (78) POQ1 = Clock P\ S\N SNS NSN internal Address Vih iP OMin Data yj Invalid x Valid x invaid Valid x Legend: T1 Reset Clock Width 30 ns Min T2 Input Clock High 100 ns Min T3 Input Clock Period 200 ns Min T4 Input Clock Low 100 ns Min TS Clock to Address Counter Out Delay 15 ns Max T6 Epnv/Vpp Set up Time 40 us Min Figure 18. Z28GE04/E08 Address Counter Waveform DS97Z8X1104 PRELIMINARY 35Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) VIH Address IL & Address Stable x Address Stable x VIH , 4 @ Data VIEL Invalid OX, vat OX vai x vad XK +> VIH Ole * L \ Vit. ve S$ EPM i VIL | 02 i Voc 5.0V 6 VJH CE / VIL fa a? VIH ) aa ( OE \/f \ Sf OE VIL a 1G AO ff PGM \ VIL G3) ke Figure 19. Z86E04/E08 Programming Waveform (EPROM Read) 36 PRELIMINARY DS97Z8X1104Z86E04/E08 Zilog CMOS Z8 OTP Microcontrollers VIH Address Address VIL i Stable ) 4 Vi ct Data Data Out Data ViL MX Stable Valid { VH sf VPP / i Vi ; 5 EPM / 6V Vee fy VIH ke) > + _ NY CE VIL \ i 4_(5)_ VIH OE VIL +(1> Vid }(.__- PGM 3 VIL 6 (8) 1 Program wie Verif > Gyole Cyale Figure 20. Z86E04/E08 Programming Waveform (Program and Verify) DS97Z8X1104 PRELIMINARY 37ZB6E04/E08 CMOS Z8 OTP Microcontrollers FUNCTIONAL DESCRIPTION (Continued) Vin Address Vi Vin Zilog Data Vit Vin 6V Vec 5.0V Via Vin Vit -y EPROM Protect Figure 21. Z86E04/E08 Programming Options Waveform (EPROM Protect and Low Noise Program) Low Noise Program 38 PRELIMINARY DS97Z8X1104Z86E04/E08 Zilog ; CMOS Z8 OTP Microcontrollers Vin Address Vy IL Vig may OX Vu VPp Vin 6V Veo soy VH L CE Mi v BE Vit Vin / ERM T 1 | @ Vi L Auto Latch WDT EPROM/Test Mode Disable Figure 22. Z86E04/E08 Programming Options Waveform (Auto Latch Disable, Permanent WDT Enable and EPROM/Test Mcde Disable) DS97Z8X1104 PRELIMINARY 39Z86E04/E08 CMOS 28 OTP Microcontrollers FUNCTIONAL DESCRIPTION (Continued) Addr = First Location Y Yoo = 6.4V Vpp= 13.0V Program 1ms Pulse y Increment N incrament Address Figure 23. Z86E04/E08 Programming Algorithm Zilog 40 PRELIMINARY DS97Z8X1 104Zilog Z8 CONTROL REGISTERS R241 TMR | D7] 06 ps| pa| 03] D2} Di} 00} | No Function Load TG Disable TO Count Enable TO Count No Function Load T1 Disable T1 Count Enable T1 Count TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) =o =a OO +O Reserved (Must be 0) Figure 24. Timer Mode Register (F1,,: Read/Write) A242 T1 [27] pe] 0s] 04} 08 [p2 | p+ | 00] T, Initial Value {When Written) (Range 1-256 Decimal 01-06 HEX) Ty Current Value (When READ) Figure 25. Counter Timer 1 Register (F2,,; Read/Write) R243 PRE1 [07 | 98] ps] 04] 3 [02 [01 [oo L_ Count Mode O=T, Single Pass 1=7{ Modulo N Ctock Source 1=T, Imemal 0 = T, External Timing Input (Ty) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 26. Prescaler 1 Register (F3,,: Write Only) Z86E04/E08 CMOS 28 OTP Microcontrollers R244 TO [07] D] 05] D4] O3} D2] 01 | oo} DL Ty Initial Value hen Written) (Range: 1-256 Decimal 01-00 HEX) Tg Current Value (When READ) Figure 27. Counter/Timer 0 Register (F4,,: Read/Write) R245 PREO | 07] D6] 05] Ds] 03] 02 ps} Do L_ Count Mode 0 TO Single Pass 1 TO ModuloN Reserved (Must ba 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 28. Prescaler 0 Register (F5,,: Write Only) R246 P2M [bos Pos Tosfos [oe] or Jo] i ae 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT Figure 29. Port 2 Mode Register (F6,,: Write Only) R247 P3M ]07} 06| 05} 04] 3] b2| D1 | Do | L_ C Port 2 Opan-Drain 1 Port 2 Push-pull Port 3 Inputs 0 Digital Mode 1 Analog Moda Reserved (Must be 0) Figure 30. Port 3 Mode Register (F7,,: Write Only) DS97Z8X1104 PRELIMINARY AlZ86E04/E08 CMOS Z8 OTP Microcontrollers Zilog Z8 CONTROL REGISTERS (Continued) R248 PO1M R251 IMR D7] D6] DS] D4] D3] D2] D1] DO p7 | 06 [os | 04 [os [oz [or [po | PO2-P0g Made a 00 = Output (0g ~ IRGO) 01 = Input Reserved (Must ba 0.) Reserved (Must be 1.) 1 Enables Interrupts Reserved (Must be 0,) Figure 34. Interrupt Mask Register (FB,,: Read/Write) Figure 31. Port 0 and 1 Mode Reglster (F&,: Write Only) R252 Flags D7] D6 | DS] D4) D3] D2] D1 | DO [Eres] o>] eos] ce]: [oo] loz] os} oso] os |p2| 0x00 J | | User Flag F1 a | User Flag F2 . Interrupt Group Priority Half Carry FI. Reserved = 000 any reg G>A>B=001 Decimal Adjust Flag A>B>C=2010 A>C>B=01 Overflow Flag B>C>A= t00 Sign Flag C>B>Az=101 BeA>C=110 Zero Flag Reserved = 111 Carry Flag IRQ1, [ROQ4 Priority (Group C) 0 = !RQ1 > IRQS ees Figure 35. Flag Regist cart ur 55. Flag Register IRQO, IRQ2 Priority (Group 8} g 0 = IRQ2>IRQO (FC,,: Read/Write) 1 = IRQO > IRQ2 IRQ3, IRQS Priority (Group A) 0 = IRQS > IRQS 1 = IRQS > IRO5 R253 RP Reserved (Must be 0.} Figure 32. Interrupt Priority Register (F9,,: Write Only) R250 IRQ 07] D6} DS] D4] 03] 02] B14 DO Le IRQO = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P32 Input IRQ4 = TO IRQ5 = T1 Reserved (Must be 0) Figure 33. Interrupt Request Register (FA,,: Read/Write) |07| 06} 0s] 04] o3| b2] 01 | bo | 7 Expanded Register File Working Register Pointer Default After Reset = 00H Figure 36. Register Pointer (FD,: Read/Write) R255 SPL J 07| vs | ps] pa] 03} b2| 01] bof re Stack Pointer Lower Byte (SP 7- SP o) Figure 37. Stack Pointer (FF,,: Read/Write) 42 PRELIMINARY DS97Z8X1104Zilog PACKAGE INFORMATION Z86E04/E08 CMOS Z8 OTP Microcontrollers , sympo. MILLIMETER INCH Jf) ot ed) MIN MAX MIN MAX { Al 051 } om | .o20 032 q El a2 325 | 343 | 128 135 rere | B a3 | 053 | os | oat 10 is Bl 14] 165 fF o4s | 06s c 023 | o38 [ooo | coms > D 22.35 [2337 | seo | 920 E 7.62 | 613 | 300 320 El 622 | 648 | 245 | 255 zB 254 TYP 100 TYP eA 787 | 889 | 310 350 L ais [| 3et | a5 150 a1 use | 165 | 060 065 S aao | tes | 035 | .o65 r al r Az wt CONTROLLING DIMENSIONS + INCH | L Al _~ $s z 18-Pin DIP Package Diagram D T srueot MILLIMETER INCH a 1 MIN MAX KIN MAX H A H H H 4 H H 4 FE A 2.40 2.68 | 0.094 | 0.104 : a 0.10 0.30 | 0,004 | o.0r2 a2 224 2.44 | 0.088 | 0.098 8 0.56 046 | 0.014 | o.o18 ! 0.23 0.30 | 0.009 | 0.012 D 140 | 11.75 | o449 | Oa8s E 7.40 7.60 | 0.291 | 0.289 1.27 TP 0.050 TYP x 10.00 | 1065 | o.s94 | oat9 H H H H H H K H H h 0,30 050 | 0.012 | 0.020 10 t8 L 0.80 1.00 0.024 0.039 a 0.97 1.07 | 0.038 | 0.042 re u t AZ A i of _ft TL lb @ a SEATING PLANE 0-6. DETAIL A 18-Pin SOIC Package Diagram CONTROLLING DIMENSIONS ; Wd LEADS ARE COPLANAR WITHIN .004 INCh. DS97Z8X1104 PRELIMINARY 43Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog ORDERING INFORMATION Z86E04 Z86E08 Standard Temperature Standard Temperature 18-Pin DIP 18-Pin SOIC 18-Pin DIP 18-Pin SOIC Z86E0412PSC Z86E0412SSC Z86E0812PSC Z86E0812SSC Z86E0412PEC Z86E0412SEC Z86E0812PEC Z86E0812SEC For fast results, contact your locai Zilog sales office for assistance in ordering the part(s) desired. Codes Preferred Package P = Plastic DIP Longer Lead Time $= SOIC Preferred Temperature S = 0C to +70C E =-40C to +106C Example: Z 86E04 12 PS C LL Speeds 12 =12 MHz Environmental C = Plastic Standard is a Z86E04, 12 MHz, DIP, 0C to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix 44 PRELIMINARY DS97Z8X1 104Zilog Preliminary Product Specification DS97Z8X1104 Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. 1998 by Zilog, Inc. All rights reserved. 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