CD74HC154EN - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS152D

Features

• Two Enable Inputs to Facilitate Demultiplexing and

Cascading Functions

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at

VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC154 and ’HCT154 are 4- to 16-line

decoders/demultiplexers with two enable inputs, E1 and E2.

A High on either enable input forces the output into the High

state. The demultiplexing function is performed by using the

four input lines, A0 to A3, to select the output lines Y0 to

Y15, and using one enable as the data input while holding

the other enable low.

Pinout CD54HC154, CD54HCT154

(CERDIP)

CD74HC154, CD74HCT154

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC154F3A -55 to 125 24 Ld CERDIP

CD54HCT154F3A -55 to 125 24 Ld CERDIP

CD74HC154E -55 to 125 24 Ld PDIP

CD74HC154EN -55 to 125 24 Ld PDIP

CD74HC154M -55 to 125 24 Ld SOIC

CD74HC154M96 -55 to 125 24 Ld SOIC

CD74HCT154E -55 to 125 24 Ld PDIP

CD74HCT154EN -55 to 125 24 Ld PDIP

CD74HCT154M -55 to 125 24 Ld SOIC

CD74HCT154M96 -55 to 125 24 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

Y10

GND

VCC

Y15

Y13

Y12

Y11

Y14

September 1997 - Revised June 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC154, CD74HC154,

CD54HCT154, CD74HCT154

High-Speed CMOS Logic

4- to 16-Line Decoder/Demultiplexer

[

/Title

(

CD74

C154

D74

CT15

)

Sub-

ect

(

High

peed

MOS

ogic

-to-16

ine

ecod

r/Dem

Functional Diagram

TRUTH TABLE

INPUTS OUTPUTS

E1 E2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

LLLLLLLHHHHHHHHHHHHHHH

LLLLLHHLHHHHHHHHHHHHHH

LLLLHLHHLHHHHHHHHHHHHH

LLLLHHHHHLHHHHHHHHHHHH

LLLHLLHHHHLHHHHHHHHHHH

LLLHLHHHHHHLHHHHHHHHHH

LLLHHLHHHHHHLHHHHHHHHH

LLLHHHHHHHHHHLHHHHHHHH

LLHLLLHHHHHHHHLHHHHHHH

LLHLLHHHHHHHHHHLHHHHHH

LLHLHLHHHHHHHHHHLHHHHH

LLHLHHHHHHHHHHHHHLHHHH

LLHHLLHHHHHHHHHHHHLHHH

LLHHLHHHHHHHHHHHHHHLHH

LLHHHLHHHHHHHHHHHHHHLH

LLHHHHHHHHHHHHHHHHHHHL

LHXXXXHHHHHHHHHHHHHHHH

HLXXXXHHHHHHHHHHHHHHHH

HHXXXXHHHHHHHHHHHHHHHH

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

9Y8

10 Y9

11 Y10

GND = 12

VCC = 24

Y11

Y12

Y13

Y14

Y15

CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical) θJA (oC/W)

E (PDIP) Package (.600) (Note 1) . . . . . . . . . . . . . . 67

EN (PDIP) Package (.300) (Note 1). . . . . . . . . . . . . 67

M (SOIC) Package (Note 2). . . . . . . . . . . . . . . . . . . 46

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

1. The package thermal impedance is calculated in accordance with JESD 51-3.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC

(Note 3) VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE:

3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

A0 - A3 1.4

E1, E2 1.3

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.,

360µA max at 25oC.

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC -55oC T O 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay (Figure 1) tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

Address to Output 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

E1 to Output tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

E2 to Output tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

Output Transition Time

(Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD -5-88-----pF

HCT TYPES

Propagation Delay (Figure 2) tPLH, tPHL

Address to Output CL= 50pF 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - ns

E1 to Output tPLH, tPHL CL= 50pF 4.5 - - 34 - 43 - 51 ns

CL=15pF 5 - 14 - - - - - ns

E2 to Output tPLH, tPHL CL= 50pF 4.5 - 34 - 43 - 51 ns

CL=15pF 5 - 14 - - - - - ns

Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD - 5 84 - - - - - pF

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate.

5. PD = VCC2 fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC -55oC T O 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

PACKAGE OPTION ADDENDUM

www.ti.com 14-Feb-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

5962-8670101JA ACTIVE CDIP J 24 1 TBD Call TI Call TI

5962-8682201JA ACTIVE CDIP J 24 1 TBD Call TI Call TI

CD54HC154F3A ACTIVE CDIP J 24 1 TBD Call TI N / A for Pkg Type

CD54HCT154F3A ACTIVE CDIP J 24 1 TBD Call TI N / A for Pkg Type

CD74HC154E ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC154EE4 ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC154EN ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC154ENE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC154M ACTIVE SOIC DW 24 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC154M96 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC154M96E4 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC154M96G4 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC154ME4 ACTIVE SOIC DW 24 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC154MG4 ACTIVE SOIC DW 24 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT154E ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT154EE4 ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT154EN ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT154ENE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT154M ACTIVE SOIC DW 24 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT154M96 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT154M96E4 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT154M96G4 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 14-Feb-2012

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

CD74HCT154ME4 ACTIVE SOIC DW 24 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT154MG4 ACTIVE SOIC DW 24 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC154, CD54HCT154, CD74HC154, CD74HCT154 :

•Catalog: CD74HC154, CD74HCT154

•Military: CD54HC154, CD54HCT154

NOTE: Qualified Version Definitions:

PACKAGE OPTION ADDENDUM

www.ti.com 14-Feb-2012

Addendum-Page 3

•Catalog - TI's standard catalog product

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC154M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

CD74HCT154M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC154M96 SOIC DW 24 2000 367.0 367.0 45.0

CD74HCT154M96 SOIC DW 24 2000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE

24 PINS SHOWN

0.018 (0,46) MIN

Seating Plane

0.010 (0.25) MAX

Lens Protrusion (Lens Optional)

WIDENARRWIDE

NARRWIDE

0.125 (3,18) MIN

0.514(13,06) 0.571(14,50)

0.541(13,74) 0.598(15,19)

1.668(42,37) 1.668(42,37)

1.632(41,45) 1.632(41,45)

0.590(14,99) 0.590(14,99)

0.624(15,85) 0.624(15,85)

4040084/C 10/97

0.012 (0,30)

0.008 (0,20)

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

2.032(51,61) 2.032(51,61)

2.068(52,53) 2.068(52,53)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

0.090 (2,29)

0.060 (1,53)

0.045 (1,14)

0.065 (1,65)

0.022 (0,56)

0.014 (0,36)

NARR

NARR WIDE

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.235(31,37) 1.235(31,37)

1.265(32,13) 1.265(32,13)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

”A”

DIM

”B”

”C”

PINS **

MAX

MIN

MAX

MIN 0.514(13,06) 0.571(14,50)

0.541(13,74) 0.598(15,19)

1.465(37,21) 1.465(37,21)

1.435(36,45) 1.435(36,45)

0.590(14,99) 0.590(14,99)

0.624(15,85) 0.624(15,85)

0.175 (4,45)

0.140 (3,56)

0.100 (2,54)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).

D. This package can be hermetically sealed with a ceramic lid using glass frit.

E. Index point is provided on cap for terminal identification.

MECHANICAL DATA

MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

N (R–PDIP–T24) PLASTIC DUAL–IN–LINE

0.020 (0,51) MIN

0.021 (0,53)

0.015 (0,38)

0.100 (2,54)

0.070 (1,78) MAX 12

1.222 (31,04) MAX

0.125 (3,18) MIN

0’–15’

0.010 (0,25) NOM

0.425 (10,80) MAX

Seating Plane

0.200 (5,08) MAX

0.360 (9,14) MAX

0.010 (0,25)

4040051–3/D 09/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS–010

MECHANICAL DATA

MPDI008 – OCTOBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

Seating Plane

0.560 (14,22)

0.520 (13,21)

0.610 (15,49)

0.590 (14,99)

524840

0.125 (3,18) MIN

2.390

(60,71)

(62,23)(53,09)

(51,82)

2.040

2.090 2.450 2.650

(67,31)

(65,79)

2.590

0.010 (0,25) NOM

4040053/B 04/95

0.060 (1,52) TYP

322824

1.230

(31,24)

(32,26) (36,83)

(35,81)

1.410

1.450

1.270

PINS **

DIM

0.015 (0,38)

0.021 (0,53)

A MIN

A MAX 1.650

(41,91)

(40,89)

1.610

0.020 (0,51) MIN

0.200 (5,08) MAX

0.100 (2,54)

0.010 (0,25) 0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-011

D. Falls within JEDEC MS-015 (32 pin only)

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

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TI is not responsible or liable for any such statements.

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concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

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anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

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No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

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TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

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Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

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Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

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Wireless Connectivity www.ti.com/wirelessconnectivity

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