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EFM32G232 DATASHEET
F128/F64/F32
•ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 32 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
•Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 45 µA/MHz @ 3 V Sleep Mode
• 180 µA/MHz @ 3 V Run Mode, with code executed from flash
•128/64/32 KB Flash
•16/16/8 KB RAM
•53 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
•8 Channel DMA Controller
•8 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
•Hardware AES with 128/256-bit keys in 54/75 cycles
•Timers/Counters
• 3× 16-bit Timer/Counter
• 3×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter
• 3× 8-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA
• Triple buffered full/half-duplex operation
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
• I2C Interface with SMBus support
• Address recognition in Stop Mode
•Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/2 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
• Supply Voltage Comparator
•Ultra efficient Power-on Reset and Brown-Out Detec-
tor
•2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
•Pre-Programmed UART Bootloader
•Temperature range -40 to 85 ºC
•Single power supply 1.98 to 3.8 V
•TQFP64 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32G232 devices.
Table 1.1. Ordering Information
Ordering Code Flash (kB) RAM (kB) Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC) Package
EFM32G232F32-QFP64 32 8 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G232F64-QFP64 64 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G232F128-QFP64 128 16 32 1.98 - 3.8 -40 - 85 TQFP64
Adding the suffix 'T' to the part number (e.g. EFM32G232F32-QFP64T) denotes tray.
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy
saving modes, and a wide selection of peripherals, the EFM32G microcontroller is well suited for any
battery operated application as well as other systems requiring high performance and low-energy con-
sumption. This section gives a short introduction to each of the modules in general terms and also shows
a summary of the configuration for the EFM32G232 devices. For a complete feature set and in-depth
information on the modules, the reader is referred to the EFM32G Reference Manual.
A block diagram of the EFM32G232 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
Clock Management Energy Management
Serial Interfaces
I/O Ports
Core and Memory
Timers and Triggers Analog Interfaces Security
32-bit bus
Peripheral Reflex System
ARM Cortex™- M3 processor
Flash
Memory
[KB]
Peripheral
Reflex
System
Timer/
Counter
Low Energy
Timer™
Pulse
Counter
3x
Real Time
Counter
Voltage
Regulator
Watchdog
Timer
RAM
Memory
[KB]
Voltage
Comparator
Power-on
Reset Brown-out
Detector
Analog
Comparator
General
Purpose
I/ O
Low
Energy
UART™
Memory
Protection
Unit
ADC DAC
DMA
Controller
Debug
Interface
External
Interrupts Pin
Reset
USART
2
32/64/128
8/16/16
3x
2x
53 pins
3x
2x
G232F32/64/128
Aux High Freq
RC
Oscillator
High Frequency
RC
Oscillator
High Frequency
Crystal
Oscillator
Low Frequency
Crystal
Oscillator
Low Frequency
RC
Oscillator
Watchdog
Oscillator
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well
as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32
implementation of the Cortex-M3 is described in detail in EFM32G Cortex-M3 Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface . In addition
there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace
and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The
flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided
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into two blocks; the main block and the information block. Program code is normally written to the main
block. Additionally, the information block is available for special user data and flash lock bits. There is
also a read-only page in the information block containing system and device calibration data. Read and
write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32G.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32G microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board
the EFM32G. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
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2.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, and IrDA devices.
2.1.12 Pre-Programmed UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Auto-
baud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.13 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.14 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.15 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.16 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
2.1.17 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 - EM3.
2.1.18 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
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2.1.19 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.20 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 8 external
pins and 6 internal signals.
2.1.21 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has one single ended output buffer connected to
channel 0. The DAC may be used for a number of different applications such as sensor interfaces or
sound output.
2.1.22 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.23 General Purpose Input/Output (GPIO)
In the EFM32G232, there are 53 General Purpose Input/Output (GPIO) pins, which are divided into ports
with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32G232 is a subset of the feature set described in the EFM32G Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
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Module Configuration Pin Connections
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[15:8], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[0]
AES Full configuration NA
GPIO 53 pins Available pins are shown in
Table 4.3 (p. 53)
2.3 Memory Map
The EFM32G232 memory map is shown in Figure 2.2 (p. 8) , with RAM and Flash sizes for the
largest memory configuration.
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Figure 2.2. EFM32G232 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 9) , by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 9) , by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 9) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
9) .
Table 3.1. Absolute Maximum Ratings
Symbol Parameter Condition Min Typ Max Unit
TSTG Storage tempera-
ture range -40 1501°C
TSMaximum soldering
temperature Latest IPC/JEDEC J-STD-020
Standard 260 °C
VDDMAX External main sup-
ply voltage 0 3.8 V
VIOPIN Voltage on any I/O
pin -0.3 VDD+0.3 V
Current per I/O pin
(sink) 100 mA
IIOMAX Current per I/O pin
(source) -100 mA
1Based on programmed devices tested for 10000 hours at 150°C. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol Parameter Min Typ Max Unit
TAMB Ambient temperature range -40 85 °C
VDDOP Operating supply voltage 1.98 3.8 V
fAPB Internal APB clock frequency 32 MHz
fAHB Internal AHB clock frequency 32 MHz
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3.4 Current Consumption
Table 3.3. Current Consumption
Symbol Parameter Condition Min Typ Max Unit
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V 180 µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 181 206 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 183 207 µA/
MHz
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 185 211 µA/
MHz
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 186 215 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 191 218 µA/
MHz
IEM0
EM0 current. No
prescaling. Running
prime number cal-
culation code from
Flash. (Production
test condition = 14
MHz)
1.2 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 220 µA/
MHz
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V 45 µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 47 62 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 48 64 µA/
MHz
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 50 69 µA/
MHz
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 51 72 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V 56 83 µA/
MHz
IEM1
EM1 current (Pro-
duction test condi-
tion = 14 MHz)
1.2 MHz HFRCO. all peripheral
clocks disabled, VDD= 3.0 V 103 µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
0.9 1.5 µA
IEM2 EM2 current EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
3.0 6.0 µA
VDD= 3.0 V, TAMB=25°C 0.59 1.0 µA
IEM3 EM3 current VDD= 3.0 V, TAMB=85°C 2.75 5.8 µA
VDD= 3.0 V, TAMB=25°C 0.02 0.045 µA
IEM4 EM4 current VDD= 3.0 V, TAMB=85°C 0.25 0.7 µA
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3.4.1 EM0 Current Consumption
Figure 3.1. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 28 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Idd [mA]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
Figure 3.2. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 21 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
3.5
3.6
3.7
3.8
3.9
4.0
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
3.5
3.6
3.7
3.8
3.9
4.0
Idd [mA]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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Figure 3.3. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 14 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
Idd [mA]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
Figure 3.4. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 11 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
Idd [mA]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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Figure 3.5. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 7 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.20
1.25
1.30
1.35
1.40
1.45
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
1.20
1.25
1.30
1.35
1.40
1.45
Idd [mA]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
3.4.2 EM1 Current Consumption
Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 28 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.15
1.20
1.25
1.30
1.35
1.40
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
1.15
1.20
1.25
1.30
1.35
1.40
Idd [mA]
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
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Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 21 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
Idd [mA]
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
Figure 3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 14 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.64
0.66
0.68
0.70
0.72
0.74
0.76
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.64
0.66
0.68
0.70
0.72
0.74
0.76
Idd [mA]
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
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Figure 3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 11 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.52
0.54
0.56
0.58
0.60
0.62
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.52
0.54
0.56
0.58
0.60
0.62
Idd [mA]
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
Figure 3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 7 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.36
0.37
0.38
0.39
0.40
0.41
0.42
0.43
0.44
Idd [mA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.36
0.37
0.38
0.39
0.40
0.41
0.42
0.43
0.44
Idd [mA]
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
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3.4.3 EM2 Current Consumption
Figure 3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO.
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Idd [uA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Idd [uA]
Vdd= 1.8V
Vdd= 2.2V
Vdd= 2.6V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
3.4.4 EM3 Current Consumption
Figure 3.12. EM3 current consumption.
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Idd [uA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Idd [uA]
Vdd= 1.8V
Vdd= 2.2V
Vdd= 2.6V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
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3.4.5 EM4 Current Consumption
Figure 3.13. EM4 current consumption.
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
Idd [uA]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
Idd [uA]
Vdd= 1.8V
Vdd= 2.2V
Vdd= 2.6V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol Parameter Min Typ Max Unit
tEM10 Transition time from EM1 to EM0 0 HF-
CORE-
CLK
cycles
tEM20 Transition time from EM2 to EM0 2 µs
tEM30 Transition time from EM3 to EM0 2 µs
tEM40 Transition time from EM4 to EM0 163 µs
3.6 Power Management
The EFM32G requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
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Table 3.5. Power Management
Symbol Parameter Condition Min Typ Max Unit
VBODextthr- BOD threshold on
falling external sup-
ply voltage
1.74 1.96 V
VBODextthr+ BOD threshold on
rising external sup-
ply voltage
1.85 V
VPORthr+ Power-on Reset
(POR) threshold on
rising external sup-
ply voltage
1.98 V
tRESETdly Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset. 163 µs
tRESET negative pulse
length to ensure
complete reset of
device
50 ns
CDECOUPLE Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
1 µF
3.7 Flash
Table 3.6. Flash
Symbol Parameter Condition Min Typ Max Unit
ECFLASH Flash erase cycles
before failure 20000 cycles
TAMB<150°C 10000 h
TAMB<85°C 10 yearsRETFLASH Flash data retention
TAMB<70°C 20 years
tW_PROG Word (32-bit) pro-
gramming time 20 µs
tP_ERASE Page erase time 20 20.4 20.8 ms
tD_ERASE Device erase time 40 40.8 41.6 ms
IERASE Erase current 71mA
IWRITE Write current 71mA
VFLASH Supply voltage dur-
ing flash erase and
write
1.98 3.8 V
1Measured at 25°C
3.8 General Purpose Input Output
Table 3.7. GPIO
Symbol Parameter Condition Min Typ Max Unit
VIOIL Input low voltage 0.30VDD1V
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Symbol Parameter Condition Min Typ Max Unit
VIOIH Input high voltage 0.70VDD1 V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.90VDD V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.85VDD V
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.90VDD V
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD V
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.85VDD V
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.60VDD V
VIOOH
Output high volt-
age (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.80VDD V
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD V
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.10VDD V
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.10VDD V
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.05VDD V
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD V
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD V
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.35VDD V
VIOOL
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.25VDD V
IIOLEAK Input leakage cur-
rent High Impedance IO connected
to GROUND or VDD
±0.1 ±40 nA
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Symbol Parameter Condition Min Typ Max Unit
RPU I/O pin pull-up resis-
tor 40 kOhm
RPD I/O pin pull-down re-
sistor 40 kOhm
RIOESD Internal ESD series
resistor 200 Ohm
tIOGLITCH Pulse width of puls-
es to be removed
by the glitch sup-
pression filter
10 50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL 250 ns
tIOOF Output fall time GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
20+0.1CL 250 ns
VIOHYST I/O pin hysteresis
(VIOTHR+ - VIOTHR-)VDD = 1.98 - 3.8 V 0.1VDD V
1If the GPIO input voltage is between 0.3VDD and 0.7VDD, the current consumption will increase.
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Figure 3.14. Typical Low-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0.00
0.05
0.10
0.15
0.20
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0
1
2
3
4
5
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0
5
10
15
20
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0
Low- Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
45
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.15. Typical High-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–0.20
–0.15
–0.10
–0.05
0.00
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–20
–15
–10
–5
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.16. Typical Low-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0
2
4
6
8
10
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low- Level Output Voltage [V]
0
10
20
30
40
50
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.17. Typical High-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–6
–5
–4
–3
–2
–1
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.18. Typical Low-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0
2
4
6
8
10
12
14
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0
10
20
30
40
50
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low- Level Output Voltage [V]
0
10
20
30
40
50
Low- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.19. Typical High-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High- Level Output Current [mA]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.8. LFXO
Symbol Parameter Condition Min Typ Max Unit
fLFXO Supported nominal
crystal frequency 32.768 kHz
ESRLFXO Supported crystal
equivalent series re-
sistance (ESR)
30 120 kOhm
CLFXOL Supported crystal
external load range X1 25 pF
ILFXO Current consump-
tion for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190 nA
tLFXO Start- up time. ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
400 ms
1See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio
For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
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3.9.2 HFXO
Table 3.9. HFXO
Symbol Parameter Condition Min Typ Max Unit
fHFXO Supported nominal
crystal Frequency 4 32 MHz
Crystal frequency 32 MHz 30 60 Ohm
ESRHFXO
Supported crystal
equivalent series re-
sistance (ESR) Crystal frequency 4 MHz 400 1500 Ohm
gmHFXO The transconduc-
tance of the HFXO
input transistor at
crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11 20 mS
CHFXOL Supported crystal
external load range 5 25 pF
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85 µA
IHFXO
Current consump-
tion for HFXO after
startup 32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165 µA
Startup time 32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
400 µs
tHFXO Pulse width re-
moved by glitch de-
tector
1 4 ns
3.9.3 LFRCO
Table 3.10. LFRCO
Symbol Parameter Condition Min Typ Max Unit
fLFRCO Oscillation frequen-
cy , VDD= 3.0 V,
TAMB=25°C
31.29 32.768 34.24 kHz
tLFRCO Startup time not in-
cluding software
calibration
150 µs
ILFRCO Current consump-
tion 190 nA
TCLFRCO Temperature coeffi-
cient ±0.02 %/°C
VCLFRCO Supply voltage co-
efficient ±15 %/V
TUNESTEPL-
FRCO
Frequency step
for LSB change in
TUNING value
1.5 %
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Figure 3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
30
32
34
36
38
40
42
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
30
32
34
36
38
40
42
Frequency [MHz]
2.0 V
3.0 V
3.8 V
3.9.4 HFRCO
Table 3.11. HFRCO
Symbol Parameter Condition Min Typ Max Unit
28 MHz frequency band 27.16 28 28.84 MHz
21 MHz frequency band 20.37 21 21.63 MHz
14 MHz frequency band 13.58 14 14.42 MHz
11 MHz frequency band 10.67 11 11.33 MHz
7 MHz frequency band 6.402 6.616.798 MHz
fHFRCO
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
1 MHz frequency band 1.164 1.221.236 MHz
Settling time after
start-up fHFRCO = 14 MHz 0.6 Cycles
tHFRCO_settling Settling time after
band switch 25 Cycles
fHFRCO = 28 MHz 106 190 µA
fHFRCO = 21 MHz 93 155 µA
fHFRCO = 14 MHz 77 120 µA
fHFRCO = 11 MHz 72 110 µA
fHFRCO = 6.6 MHz 63 90 µA
IHFRCO
Current consump-
tion (Production test
condition = 14 MHz)
fHFRCO = 1.2 MHz 22 32 µA
DCHFRCO Duty cycle fHFRCO = 14 MHz 48.5 50 51 %
TUNESTEPH-
FRCO
Frequency step
for LSB change in
TUNING value
0.33 %
1For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
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Figure 3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
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Figure 3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
20.2
20.4
20.6
20.8
21.0
21.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
20.2
20.4
20.6
20.8
21.0
21.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.26. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
26.8
27.0
27.2
27.4
27.6
27.8
28.0
28.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
525 45 65 85
Temperature [°C]
26.8
27.0
27.2
27.4
27.6
27.8
28.0
28.2
28.4
Frequency [MHz]
2.0 V
3.0 V
3.8 V
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3.9.5 AUXHFRCO
Table 3.12. AUXHFRCO
Symbol Parameter Condition Min Typ Max Unit
fAUXHFRCO Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
14 MHz frequency band 13.580 14.0 14.420 MHz
tAUXHFRCO_settlingSettling time after
start-up fAUXHFRCO = 14 MHz 0.6 Cycles
DCAUXHFRCO Duty cycle fAUXHFRCO = 14 MHz 48.5 50 51 %
TUNESTEPAUX-
HFRCO
Frequency step
for LSB change in
TUNING value
0.31 %
1The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. By using a stable
frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band
to maintain the AUXHFRCO frequency at any arbitrary value in the 14 MHz range across operating conditions.
3.9.6 ULFRCO
Table 3.13. ULFRCO
Symbol Parameter Condition Min Typ Max Unit
fULFRCO Oscillation frequen-
cy 25°C, 3V 0.70 1.75 kHz
TCULFRCO Temperature coeffi-
cient 0.05 %/°C
VCULFRCO Supply voltage co-
efficient -18.2 %/V
3.10 Analog Digital Converter (ADC)
Table 3.14. ADC
Symbol Parameter Condition Min Typ Max Unit
Single ended 0 VREF V
VADCIN Input voltage range Differential -VREF/2 VREF/2 V
VADCREFIN Input range of exter-
nal reference volt-
age, single ended
and differential
1.25 VDD V
VADCREFIN_CH7 Input range of ex-
ternal negative ref-
erence voltage on
channel 7
See VADCREFIN 0 VDD - 1.1 V
VADCREFIN_CH6 Input range of ex-
ternal positive ref-
erence voltage on
channel 6
See VADCREFIN 0.625 VDD V
VADCCMIN Common mode in-
put range 0 VDD V
IADCIN Input current 2pF sampling capacitors <100 nA
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Symbol Parameter Condition Min Typ Max Unit
CMRRADC Analog input com-
mon mode rejection
ratio
65 dB
1 MSamples/s, 12 bit, external
reference 351 µA
1 MSamples/s, 12 bit, internal
reference 411 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00, ADC_CLK running at
13MHz
67 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01, ADC_CLK running at
13MHz
63 µA
IADC Average active cur-
rent
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10, ADC_CLK running at
13MHz
64 µA
CADCIN Input capacitance 2 pF
RADCIN Input ON resistance 1 MOhm
RADCFILT Input RC filter resis-
tance 10 kOhm
CADCFILT Input RC filter/de-
coupling capaci-
tance
250 fF
fADCCLK ADC Clock Fre-
quency 13 MHz
6 bit 7 ADC-
CLK
Cycles
8 bit 11 ADC-
CLK
Cycles
tADCCONV Conversion time
12 bit 13 ADC-
CLK
Cycles
tADCACQ Acquisition time Programmable 1 256 ADC-
CLK
Cycles
tADCACQVDD3 Required acquisi-
tion time for VDD/3
reference
2 µs
Startup time of ref-
erence generator
and ADC core in
NORMAL mode
5 µs
tADCSTART Startup time of ref-
erence generator
and ADC core in
1 µs
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Symbol Parameter Condition Min Typ Max Unit
KEEPADCWARM
mode
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59 dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference 63 dB
1 MSamples/s, 12 bit, single
ended, VDD reference 65 dB
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference 60 dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference 65 dB
1 MSamples/s, 12 bit, differen-
tial, 5V reference 54 dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference 67 dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference 69 dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
62 dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference 63 dB
200 kSamples/s, 12 bit, single
ended, VDD reference 67 dB
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 63 dB
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference 63 69 dB
SNRADC Signal to Noise Ra-
tio (SNR)
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference 70 dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
58 dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference 62 dB
1 MSamples/s, 12 bit, single
ended, VDD reference 64 dB
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference 60 dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference 64 dB
SINADADC
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
1 MSamples/s, 12 bit, differen-
tial, 5V reference 54 dB
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Symbol Parameter Condition Min Typ Max Unit
1 MSamples/s, 12 bit, differen-
tial, VDD reference 66 dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference 68 dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
61 dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference 65 dB
200 kSamples/s, 12 bit, single
ended, VDD reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 63 dB
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference 66 dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference 62 68 dB
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference 69 dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
64 dBc
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference 76 dBc
1 MSamples/s, 12 bit, single
ended, VDD reference 73 dBc
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference 66 dBc
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference 77 dBc
1 MSamples/s, 12 bit, differen-
tial, VDD reference 76 dBc
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference 75 dBc
1 MSamples/s, 12 bit, differen-
tial, 5V reference 69 dBc
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
75 dBc
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference 75 dBc
200 kSamples/s, 12 bit, single
ended, VDD reference 76 dBc
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference 79 dBc
SFDRADC
Spurious-Free Dy-
namic Range (SF-
DR)
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference 79 dBc
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Symbol Parameter Condition Min Typ Max Unit
200 kSamples/s, 12 bit, differ-
ential, 5V reference 78 dBc
200 kSamples/s, 12 bit, differ-
ential, VDD reference 68 79 dBc
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference 79 dBc
After calibration, single ended -4 0.3 4 mV
VADCOFFSET Offset voltage After calibration, differential 0.3 mV
-1.92 mV/°C
TGRADADCTH Thermometer out-
put gradient -6.3 ADC
Codes/
°C
DNLADC Differential non-lin-
earity (DNL) VDD = 3.0 V, external 2.5V ref-
erence -1 ±0.7 4 LSB
INLADC Integral non-linear-
ity (INL), End point
method
VDD = 3.0 V, external 2.5V ref-
erence ±1.2 ±3 LSB
MCADC No missing codes 11.999112 bits
1On the average every ADC will have one missing code, most likely to appear around 2048 ± n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.27 (p.
36) and Figure 3.28 (p. 37) , respectively.
Figure 3.27. Integral Non-Linearity (INL)
Ideal transfer
curve
Digital ouput code
Analog Input
INL=|[(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2N - 1
0
1
2
3
4092
4093
4094
4095
VOFFSET
Actual ADC
tranfer function
before offset and
gain correction Actual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
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Figure 3.28. Differential Non-Linearity (DNL)
Ideal transfer
curve
Digital
ouput
code
Analog Input
DNL=|[(VD+1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2N - 2
0
1
2
3
4092
4093
4094
4095
Actual transfer
function with one
missing code.
4
5
Full Scale Range
0.5
LSB
Ideal Code Center
Ideal 50%
Transition Point
Ideal spacing
between two
adjacent codes
VLSBIDEAL=1 LSB
Code width = 2 LSB
DNL=1 LSB
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
Example: Input value
VD corrresponds to
digital output code D
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3.10.1 Typical performance
Figure 3.29. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.30. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.31. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.32. ADC Absolute Offset, Common Mode = Vdd /2
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd (V)
–4
–3
–2
–1
0
1
2
3
4
5
Actual Offset [LSB]
Vref= 1V25
Vref= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
Offset vs Supply Voltage, Temp = 25°C
–40 –15 5 25 45 65 85
Temp (C)
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
Actual Offset [LSB]
VRef= 1V25
VRef= 2V5
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
Offset vs Temperature, Vdd = 3V
Figure 3.33. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
–40 –15 5 25 45 65 85
Temperature [°C]
63
64
65
66
67
68
69
70
71
SNR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Signal to Noise Ratio (SNR)
–40 –15 5 25 45 65 85
Temperature [°C]
78.0
78.2
78.4
78.6
78.8
79.0
79.2
79.4
SFDR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Spurious-Free Dynamic Range (SFDR)
3.11 Digital Analog Converter (DAC)
Table 3.15. DAC
Symbol Parameter Condition Min Typ Max Unit
VDACOUT Output voltage
range VDD voltage reference, single
ended 0 VDD V
VDACCM Output common
mode voltage range 0 VDD V
500 kSamples/s, 12bit 4001650 µA
100 kSamples/s, 12 bit 2001250 µA
IDAC
Active current in-
cluding references
for 2 channels 1 kSamples/s 12 bit 17125 µA
SRDAC Sample rate 500 ksam-
ples/s
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Symbol Parameter Condition Min Typ Max Unit
Continuous Mode 1000 kHz
Sample/Hold Mode 250 kHzfDAC DAC clock frequen-
cy Sample/Off Mode 250 kHz
CYCDACCONV Clock cyckles per
conversion 2
tDACCONV Conversion time 2 µs
tDACSETTLE Settling time 5 µs
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
58 dB
SNRDAC Signal to Noise Ra-
tio (SNR) 500 kSamples/s, 12 bit, single
ended, internal 2.5V reference 59 dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
57 dB
SNDRDAC
Signal to Noise-
pulse Distortion Ra-
tio (SNDR) 500 kSamples/s, 12 bit, single
ended, internal 2.5V reference 54 dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
62 dBc
SFDRDAC
Spurious-Free
Dynamic
Range(SFDR) 500 kSamples/s, 12 bit, single
ended, internal 2.5V reference 56 dBc
VDACOFFSET Offset voltage After calibration, single ended 2 mV
VDACSHMDRIFT Sample-hold mode
voltage drift 540 µV/ms
DNLDAC Differential non-lin-
earity ±1 LSB
INLDAC Integral non-lineari-
ty ±5 LSB
MCDAC No missing codes 12 bits
1Measured with a static input code and no loading on the output.
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3.12 Analog Comparator (ACMP)
Table 3.16. ACMP
Symbol Parameter Condition Min Typ Max Unit
VACMPIN Input voltage range 0 VDD V
VACMPCM ACMP Common
Mode voltage range 0 VDD V
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
55 600 nA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
2.82 12 µA
IACMP Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
195 520 µA
Internal voltage reference off.
Using external voltage refer-
ence
0 0.5 µA
Internal voltage reference,
LPREF=1 0.050 3 µAIACMPREF
Current consump-
tion of internal volt-
age reference
Internal voltage reference,
LPREF=0 6 µA
VACMPOFFSET Offset voltage BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12 0 12 mV
VACMPHYST ACMP hysteresis Programmable 17 mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL 39 kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL 71 kOhm
CSRESSEL=0b10 in
ACMPn_INPUTSEL 104 kOhm
RCSRES Capacitive Sense
Internal Resistance
CSRESSEL=0b11 in
ACMPn_INPUTSEL 136 kOhm
tACMPSTART Startup time 10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 43) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF (3.1)
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Figure 3.34. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
048 12
ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
Current [uA]
Current consumption, HYSTSEL = 4
0 2 46 8 10 12 14
ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Response Time [us]
HYSTSEL=0.0
HYSTSEL=2.0
HYSTSEL=4.0
HYSTSEL=6.0
Response time
012 3 4 5 67
ACMP_CTRL_HYSTSEL
0
20
40
60
80
100
Hysteresis [mV]
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
Hysteresis
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3.13 Voltage Comparator (VCMP)
Table 3.17. VCMP
Symbol Parameter Condition Min Typ Max Unit
VVCMPIN Input voltage range VDD V
VVCMPCM VCMP Common
Mode voltage range VDD V
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.3 1 µA
IVCMP Active current BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
22 30 µA
tVCMPREF Startup time refer-
ence generator NORMAL 10 µs
Single ended 10 mV
VVCMPOFFSET Offset voltage Differential 10 mV
VVCMPHYST VCMP hysteresis 17 mV
tVCMPSTART Startup time 10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL (3.2)
3.14 I2C
Table 3.18. I2C Standard-mode (Sm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 1001kHz
tLOW SCL clock low time 4.7 µs
tHIGH SCL clock high time 4.0 µs
tSU,DAT SDA set-up time 250 ns
tHD,DAT SDA hold time 8 34502,3 ns
tSU,STA Repeated START condition set-up time 4.7 µs
tHD,STA (Repeated) START condition hold time 4.0 µs
tSU,STO STOP condition set-up time 4.0 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32G Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
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Table 3.19. I2C Fast-mode (Fm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 4001kHz
tLOW SCL clock low time 1.3 µs
tHIGH SCL clock high time 0.6 µs
tSU,DAT SDA set-up time 100 ns
tHD,DAT SDA hold time 8 9002,3 ns
tSU,STA Repeated START condition set-up time 0.6 µs
tHD,STA (Repeated) START condition hold time 0.6 µs
tSU,STO STOP condition set-up time 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32G Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 3.20. I2C Fast-mode Plus (Fm+)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 10001kHz
tLOW SCL clock low time 0.5 µs
tHIGH SCL clock high time 0.26 µs
tSU,DAT SDA set-up time 50 ns
tHD,DAT SDA hold time 8 ns
tSU,STA Repeated START condition set-up time 0.26 µs
tHD,STA (Repeated) START condition hold time 0.26 µs
tSU,STO STOP condition set-up time 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs
1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32G Reference Manual.
3.15 Digital Peripherals
Table 3.21. Digital Peripherals
Symbol Parameter Condition Min Typ Max Unit
IUSART USART current USART idle current, clock en-
abled 7.5 µA/
MHz
IUART UART current UART idle current, clock en-
abled 5.63 µA/
MHz
ILEUART LEUART current LEUART idle current, clock en-
abled 150 nA
II2C I2C current I2C idle current, clock enabled 6.25 µA/
MHz
ITIMER TIMER current TIMER_0 idle current, clock
enabled 8.75 µA/
MHz
ILETIMER LETIMER current LETIMER idle current, clock
enabled 150 nA
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Symbol Parameter Condition Min Typ Max Unit
IPCNT PCNT current PCNT idle current, clock en-
abled 100 nA
IRTC RTC current RTC idle current, clock enabled 100 nA
IAES AES current AES idle current, clock enabled 2.5 µA/
MHz
IGPIO GPIO current GPIO idle current, clock en-
abled 5.31 µA/
MHz
IPRS PRS current PRS idle current 2,81 µA/
MHz
IDMA DMA current Clock enable 8.12 µA/
MHz
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4 Pinout and Package
Note Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32G232.
4.1 Pinout
The EFM32G232 pinout is shown in Figure 4.1 (p. 48) and Table 4.1 (p. 48) . Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32G232 Pinout (top view, not to scale)
Table 4.1. Device Pinout
QFP64 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog Timers Communication Other
1 PA0 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0
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QFP64 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog Timers Communication Other
4 PA3 TIM0_CDTI0 #0
5 PA4 TIM0_CDTI1 #0
6 PA5 TIM0_CDTI2 #0 LEU1_TX #1
7 IOVDD_0 Digital IO power supply 0.
8 VSS Ground.
9 PC0 ACMP0_CH0 PCNT0_S0IN #2 US1_TX #0
10 PC1 ACMP0_CH1 PCNT0_S1IN #2 US1_RX #0
11 PC2 ACMP0_CH2 US2_TX #0
12 PC3 ACMP0_CH3 US2_RX #0
13 PC4 ACMP0_CH4 LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
14 PC5 ACMP0_CH5 LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
15 PB7 LFXTAL_P US1_CLK #0
16 PB8 LFXTAL_N US1_CS #0
17 PA8 TIM2_CC0 #0
18 PA9 TIM2_CC1 #0
19 PA10 TIM2_CC2 #0
20 RESETn Reset input, active low.
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up
ensure that reset is released.
21 PB11 DAC0_OUT0 LETIM0_OUT0 #1
22 VSS Ground.
23 AVDD_1 Analog power supply 1.
24 PB13 HFXTAL_P LEU0_TX #1
25 PB14 HFXTAL_N LEU0_RX #1
26 IOVDD_3 Digital IO power supply 3.
27 AVDD_0 Analog power supply 0.
28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1
29 PD1 ADC0_CH1 TIM0_CC0 #3
PCNT2_S1IN #0 US1_RX #1
30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1
31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1
32 PD4 ADC0_CH4 LEU0_TX #0
33 PD5 ADC0_CH5 LEU0_RX #0
34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1
35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1
36 PD8 CMU_CLK1 #1
37 PC6 ACMP0_CH6 LEU1_TX #0
I2C0_SDA #2
38 PC7 ACMP0_CH7 LEU1_RX #0
I2C0_SCL #2
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QFP64 Pin#
and Name Pin Alternate Functionality / Description
Pin #
Pin Name Analog Timers Communication Other
39 VDD_DREG Power supply for on-chip voltage regulator.
40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2
42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2
44 PC11 ACMP1_CH3 US0_TX #2
45 PC12 ACMP1_CH4 CMU_CLK0 #1
46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3
TIM1_CC0 #0
PCNT0_S0IN #0
47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3
TIM1_CC2 #0 DBG_SWO #1
49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
51 PF2 ACMP1_O #0
DBG_SWO #0
52 PF3 TIM0_CDTI0 #2
53 PF4 TIM0_CDTI1 #2
54 PF5 TIM0_CDTI2 #2
55 IOVDD_5 Digital IO power supply 5.
56 VSS Ground.
57 PE8 PCNT2_S0IN #1
58 PE9 PCNT2_S1IN #1
59 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX
60 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX
61 PE12 TIM1_CC2 #1 US0_CLK #0
62 PE13 US0_CS #0 ACMP0_O #0
63 PE14 LEU0_TX #2
64 PE15 LEU0_RX #2
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 51) . The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
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Table 4.2. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull
down.
DBG_SWDIO PF1 PF1 Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by
software to be used.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock in-
put pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
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Alternate LOCATION
Functionality 0 1 2 3 Description
I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex commu-
nication.
LEU1_RX PC7 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex commu-
nication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an
optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PC9 USART0 clock input / output.
US0_CS PE13 PC8 USART0 chip select input / output.
US0_RX PE11 PC10 USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
US0_TX PE10 PC11
USART0 Asynchronous Transmit.Also used as receive input in half duplex
communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PC1 PD1 USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
US1_TX PC0 PD0 USART1 Asynchronous Transmit.Also used as receive input in half duplex
communication.
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Alternate LOCATION
Functionality 0 1 2 3 Description
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK PC4 USART2 clock input / output.
US2_CS PC5 USART2 chip select input / output.
US2_RX PC3 USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX PC2
USART2 Asynchronous Transmit.Also used as receive input in half duplex
communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G232 is shown in Table 4.3 (p. 53) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port Pin
15 Pin
14 Pin
13 Pin
12 Pin
11 Pin
10 Pin
9Pin
8Pin
7Pin
6Pin
5Pin
4Pin
3Pin
2Pin
1Pin
0
Port A - - - - - PA10 PA9 PA8 - - PA5 PA4 PA3 PA2 PA1 PA0
Port B - PB14 PB13 - PB11 - - PB8 PB7 - - - - - - -
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D - - - - - - - PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 - - - - - - - -
Port F - - - - - - - - - - PF5 PF4 PF3 PF2 PF1 PF0
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4.4 TQFP64 Package
Figure 4.2. TQFP64
Note:
1. All dimensions & tolerancing confirm to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package body size.
3. Datum 'A,B', and 'B' to be determined at datum plane 'H'.
4. To be determined at seating place 'C'.
5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side.
'D1' and 'E1' are maximum plastic body size dimension including mold mismatch. Dimension 'D1' and
'E1' shall be determined at datum plane 'H'.
6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated.
7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the
lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located
on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm
8. Exact shape of each corner is optional.
9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
10.All dimensions are in millimeters.
Table 4.4. QFP64 (Dimensions in mm)
DIM MIN NOM MAX DIM MIN NOM MAX
A - 1.10 1.20 L1 -
A1 0.05 - 0.15 R1 0.08 - -
A2 0.95 1.00 1.05 R2 0.08 - 0.20
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DIM MIN NOM MAX DIM MIN NOM MAX
b 0.17 0.22 0.27 S 0.20 - -
b1 0.17 0.20 0.23 θ0° 3.5° 7°
c 0.09 - 0.20 θ10° - -
C1 0.09 - 0.16 θ211° 12° 13°
D 12.0 BSC θ311° 12° 13°
D1 10.0 BSC
e 0.50 BSC
E 12.0 BSC
E1 10.0 BSC
L 0.45 0.60 0.75
The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch.
The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. TQFP64 PCB Land Pattern
e
a
d
c
b
p1
p2
p3 p4
p5
p6
p7p8
Table 5.1. QFP64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin number Symbol Pin number
a 1.60 P1 1 P6 48
b 0.30 P2 16 P7 49
c 0.50 P3 17 P8 64
d 11.50 P4 32 - -
e 11.50 P5 33 - -
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Figure 5.2. TQFP64 PCB Solder Mask
e
a
d
c
b
Table 5.2. QFP64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.72
b 0.42
c 0.50
d 11.50
e 11.50
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Figure 5.3. TQFP64 PCB Stencil Design
e
a
d
c
b
Table 5.3. QFP64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.50
b 0.20
c 0.50
d 11.50
e 11.50
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.2 (p. 54) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 59) .
6.3 Errata
Please see the errata document for EFM32G232 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.90
May 22nd, 2015
Added clarification on conditions for INLADC and DNLADC parameters.
Corrected EM2 current consumption condition in Electrical Characteristics section.
Added AUXHFRCO to block diagram and Electrical Characteristics.
Updated HFRCO table in the Electrical Characteristics section.
Updated EM0, EM2, EM3, and EM4 maximum current specifications in the Electrical Characteristics
section.
Updated the Output Low Voltage maximum for sinking 20 mA with VDD = 3.0 V in the Electrical Char-
acteristics section.
Updated the Input Leakage Current maximum in the Electrical Characteristics section.
Updated the minimum and maximum frequency specifications for the LFRCO, HFRCO, and AUXHFRCO
in the Electrical Characteristics section.
Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section.
Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section.
Added some minimum ADC SNR, SNDR, and SFDR specifications in the Electrical Characteristics sec-
tion.
Added some minimum and maximum ADC offset voltage, DNL, and INL specifications in the Electrical
Characteristics section.
Added maximum DAC current specifications in the Electrical Characteristics section.
Added maximum ACMP current and maximum and minimum offset voltage specifications in the Electrical
Characteristics section.
Added maximum VCMP current and updated typical VCMP current specifications in the Electrical Char-
acteristics section.
Updated references to energyAware Designer to Configurator.
7.2 Revision 1.80
July 2nd, 2014
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Updated current consumption.
Updated transition between energy modes.
Updated power management data.
Updated GPIO data.
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Updated LFXO, HFXO, HFRCO and ULFRCO data.
Updated LFRCO and HFRCO plots.
Updated ACMP data.
7.3 Revision 1.71
November 21st, 2013
Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
Re-added missing DAC-data.
7.4 Revision 1.70
September 30th, 2013
Added I2C characterization data.
Corrected GPIO operating voltage from 1.8 V to 1.85 V.
Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
Updated Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
7.5 Revision 1.60
June 28th, 2013
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
7.6 Revision 1.50
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.7 Revision 1.40
February 27th, 2012
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Updated Power Management section.
Corrected operating voltage from 1.8 V to 1.85 V.
Corrected TGRADADCTH parameter.
Corrected TQFP64 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.8 Revision 0.90
Initial preliminary revision, June 30th, 2011
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 6
2.3. Memory Map ................................................................................................................................. 7
3. Electrical Characteristics ............................................................................................................................. 9
3.1. Test Conditions .............................................................................................................................. 9
3.2. Absolute Maximum Ratings .............................................................................................................. 9
3.3. General Operating Conditions ........................................................................................................... 9
3.4. Current Consumption ..................................................................................................................... 10
3.5. Transition between Energy Modes .................................................................................................... 17
3.6. Power Management ....................................................................................................................... 17
3.7. Flash .......................................................................................................................................... 18
3.8. General Purpose Input Output ......................................................................................................... 18
3.9. Oscillators .................................................................................................................................... 27
3.10. Analog Digital Converter (ADC) ...................................................................................................... 32
3.11. Digital Analog Converter (DAC) ...................................................................................................... 41
3.12. Analog Comparator (ACMP) .......................................................................................................... 43
3.13. Voltage Comparator (VCMP) ......................................................................................................... 45
3.14. I2C ........................................................................................................................................... 45
3.15. Digital Peripherals ....................................................................................................................... 46
4. Pinout and Package ................................................................................................................................. 48
4.1. Pinout ......................................................................................................................................... 48
4.2. Alternate Functionality Pinout .......................................................................................................... 50
4.3. GPIO Pinout Overview ................................................................................................................... 53
4.4. TQFP64 Package .......................................................................................................................... 54
5. PCB Layout and Soldering ........................................................................................................................ 56
5.1. Recommended PCB Layout ............................................................................................................ 56
5.2. Soldering Information ..................................................................................................................... 58
6. Chip Marking, Revision and Errata .............................................................................................................. 59
6.1. Chip Marking ................................................................................................................................ 59
6.2. Revision ...................................................................................................................................... 59
6.3. Errata ......................................................................................................................................... 59
7. Revision History ...................................................................................................................................... 60
7.1. Revision 1.90 ............................................................................................................................... 60
7.2. Revision 1.80 ............................................................................................................................... 60
7.3. Revision 1.71 ............................................................................................................................... 61
7.4. Revision 1.70 ............................................................................................................................... 61
7.5. Revision 1.60 ............................................................................................................................... 61
7.6. Revision 1.50 ............................................................................................................................... 61
7.7. Revision 1.40 ............................................................................................................................... 61
7.8. Revision 0.90 ............................................................................................................................... 62
A. Disclaimer and Trademarks ....................................................................................................................... 63
A.1. Disclaimer ................................................................................................................................... 63
A.2. Trademark Information ................................................................................................................... 63
B. Contact Information ................................................................................................................................. 64
B.1. ................................................................................................................................................. 64
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32G232 Memory Map with largest RAM and Flash sizes .......................................................................... 8
3.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 28
MHz ........................................................................................................................................................ 11
3.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21
MHz ........................................................................................................................................................ 11
3.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14
MHz ........................................................................................................................................................ 12
3.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11
MHz ........................................................................................................................................................ 12
3.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 7
MHz ........................................................................................................................................................ 13
3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28 MHz .............................. 13
3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz .............................. 14
3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz .............................. 14
3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz .............................. 15
3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 7 MHz .............................. 15
3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ....................................................... 16
3.12. EM3 current consumption. ................................................................................................................... 16
3.13. EM4 current consumption. ................................................................................................................... 17
3.14. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 21
3.15. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 22
3.16. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 23
3.17. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 24
3.18. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 25
3.19. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 26
3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 29
3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.26. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.27. Integral Non-Linearity (INL) ................................................................................................................... 36
3.28. Differential Non-Linearity (DNL) .............................................................................................................. 37
3.29. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 38
3.30. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 39
3.31. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 40
3.32. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 41
3.33. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 41
3.34. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 44
4.1. EFM32G232 Pinout (top view, not to scale) ............................................................................................... 48
4.2. TQFP64 .............................................................................................................................................. 54
5.1. TQFP64 PCB Land Pattern ..................................................................................................................... 56
5.2. TQFP64 PCB Solder Mask ..................................................................................................................... 57
5.3. TQFP64 PCB Stencil Design ................................................................................................................... 58
6.1. Example Chip Marking (top view) ............................................................................................................. 59
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 6
3.1. Absolute Maximum Ratings ...................................................................................................................... 9
3.2. General Operating Conditions ................................................................................................................... 9
3.3. Current Consumption ............................................................................................................................. 10
3.4. Energy Modes Transitions ...................................................................................................................... 17
3.5. Power Management ............................................................................................................................... 18
3.6. Flash .................................................................................................................................................. 18
3.7. GPIO .................................................................................................................................................. 18
3.8. LFXO .................................................................................................................................................. 27
3.9. HFXO ................................................................................................................................................. 28
3.10. LFRCO .............................................................................................................................................. 28
3.11. HFRCO ............................................................................................................................................. 29
3.12. AUXHFRCO ....................................................................................................................................... 32
3.13. ULFRCO ............................................................................................................................................ 32
3.14. ADC .................................................................................................................................................. 32
3.15. DAC .................................................................................................................................................. 41
3.16. ACMP ............................................................................................................................................... 43
3.17. VCMP ............................................................................................................................................... 45
3.18. I2C Standard-mode (Sm) ...................................................................................................................... 45
3.19. I2C Fast-mode (Fm) ............................................................................................................................ 46
3.20. I2C Fast-mode Plus (Fm+) .................................................................................................................... 46
3.21. Digital Peripherals ............................................................................................................................... 46
4.1. Device Pinout ....................................................................................................................................... 48
4.2. Alternate functionality overview ................................................................................................................ 51
4.3. GPIO Pinout ........................................................................................................................................ 53
4.4. QFP64 (Dimensions in mm) .................................................................................................................... 54
5.1. QFP64 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 56
5.2. QFP64 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 57
5.3. QFP64 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 58
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 43
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 45