Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 LM7301 Low Power, 4-MHz GBW, Rail-to-Rail Input-Output Operational Amplifier in SOT-23 Package 1 Features 3 Description * * * The LM7301 provides high performance in a wide range of applications. The LM7301 offers greater than rail-to-rail input range, full rail-to-rail output swing, large capacitive load driving ability, and low distortion. 1 * * * * * * * At VS = 5 V (Typical Unless Otherwise Noted) Tiny, Space-Saving, 5-Pin SOT-23 Package Greater than Rail-to-Rail Input CMVR: -0.25 V to 5.2 V Rail-to-Rail Output Swing: 007 V to 4.93 V Wide Gain-Bandwidth: 4 MHz Low Supply Current: 0.6 mA Wide Supply Range: 1.8 V to 32 V High PSRR: 104 dB High CMRR: 93 dB Excellent Gain: 97 dB 2 Applications * * * * * Portable Instrumentation Signal Conditioning Amplifiers/ADC Buffers Active Filters Modems PCMCIA Cards With only 0.6-mA supply current, the 4-MHz gainbandwidth of this device supports new portable applications where higher power devices unacceptably drain battery life. The LM7301 can be driven by voltages that exceed both power supply rails, thus eliminating concerns over exceeding the common-mode voltage range. The rail-to-rail output swing capability provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages. Operating on supplies of 1.8 V to 32 V, the LM7301 is excellent for a very wide range of applications in low power systems. Placing the amplifier right at the signal source reduces board size and simplifies signal routing. The LM7301 fits easily on low profile PCMCIA cards. Device Information(1) PART NUMBER LM7301 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm SOT-23 (5) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Gain and Phase Gain and Phase, 2.7-V Supply 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 4 5 6 6 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: 5-V DC............................. Electrical Characteristics: AC.................................... Electrical Characteristics: 2.2-V DC.......................... Electrical Characteristics: 30-V DC........................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Feature Description................................................. 12 7.3 Device Functional Modes........................................ 14 8 Applications and Implementation ...................... 16 8.1 Application Information............................................ 16 8.2 Typical Applications ................................................ 16 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................. 19 10.2 Layout Example .................................................... 19 11 Device and Documentation Support ................. 20 11.1 11.2 11.3 11.4 Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (March 2013) to Revision I Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 * Changed 58C to 42C in Power Dissipation ....................................................................................................................... 15 * Changed 113C to 59C in Power Dissipation ..................................................................................................................... 15 * Changed 29C to 21C in Power Dissipation ....................................................................................................................... 15 * Changed 57C to 30C in Power Dissipation ....................................................................................................................... 15 Changes from Revision G (March 2013) to Revision H * 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 16 Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View DBV Package 5-Pin SOT-23 Top View Pin Functions PIN NAME I/O DESCRIPTION SOIC SOT-23 -IN 2 4 I Inverting input voltage +IN 3 3 I Noninverting input voltage N/C 1, 5, 8 -- -- No connection OUT 6 1 O Output V- 4 2 I Negative supply V+ 7 5 I Positive supply Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 3 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT 15 V (V ) - 0.3 V Differential input voltage + Voltage at input and output pin - (V ) + 0.3 Supply voltage (V+ - V-) 35 V Current at input pin 10 mA Current at output pin (3) 20 mA Current at power supply pin 25 mA Junction temperature, TJ (4) 150 C 150 C Storage temperature, Tstg (1) (2) (3) (4) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/RJA. All numbers apply for packages soldered directly into a PC board. 6.2 ESD Ratings V(ESD) (1) VALUE UNIT 2500 V Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Electrostatic discharge JEDEC document JEP155 states that 2500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage Operating temperature (1) (2) MAX UNIT 32 V -40 85 C 5-pin SOT-23 325 325 C/W 8-pin SOIC 165 165 C/W (2) Package thermal resistance (RJA) (2) NOM 1.8 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/RJA. All numbers apply for packages soldered directly into a PC board. 6.4 Thermal Information LM7301 THERMAL METRIC (1) DBV (SOT-23) D (SOIC) 5 PINS 8 PINS UNIT RJA Junction-to-ambient thermal resistance 169 120 C/W RJC(top) Junction-to-case (top) thermal resistance 122 65 C/W RJB Junction-to-board thermal resistance 30 61 C/W JT Junction-to-top characterization parameter 17 16 C/W JB Junction-to-board characterization parameter 29 60 C/W RJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 6.5 Electrical Characteristics: 5-V DC Unless otherwise specified, all limits ensured for TA = 25C, V+ = 5V, V- = 0V, VCM = VO = V+/2 and RL > 1M to V+/2 unless noted that limits apply at the temperature extremes. (1) (2) (3) PARAMETER VOS Input offset voltage TCVOS Input offset voltage average drift TEST CONDITIONS TA = TJ TA = 25C 0.7 0.7 TA = TJ Power supply rejection ratio 2.2 V V+ 30 V VCM Input common-mode voltage range CMRR 65 dB AV Large signal voltage gain RL = 10 k VO = 4 VPP 39 TA = 25C 70 TA = TJ 67 TA = 25C 87 TA = TJ 84 TA = 25C 14 TA = TJ 10 Output swing TA = TJ IS (1) (2) (3) Supply current 104 dB V TA = 25C TA = TJ 4.88 0.12 0.15 4.85 0.14 0.2 V 0.22 4.80 4.87 4.78 8 11 5.5 6 TA = TJ 5 mA 9.5 0.6 TA = TJ V/mV 4.93 TA = 25C TA = 25C 71 0.07 TA = 25C RL = 2 k Sinking dB 5.1 TA = TJ Output short-circuit current M 88 -0.1 RL = 10 k ISC nA 93 TA = 25C Sourcing 55 65 0 V VCM 5 V PSRR nA 70 80 TA = 25C 0 V VCM 3.5 V VO -75 TA = TJ 0 V VCM 5 V mV -85 TA = 25C VCM = 5 V Common mode rejection ratio -40 TA = TJ Input offset current CMRR 200 250 TA = 25C UNIT V/C 90 TA = TJ VCM = 0 V Input resistance, CM 6 2 VCM = 5 V RIN MAX 0.03 8 Input bias current IOS TYP TA = TJ VCM = 0 V IB MIN TA = 25C 1.1 1.24 mA All limits are ensured by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the devices such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 5 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com 6.6 Electrical Characteristics: AC TA = 25C, V+ = 2.2 V to 30 V, V- = 0 V, VCM = VO = V+/2 and RL > 1 M to V+/2 (1) PARAMETER TEST CONDITIONS SR Slew rate 4-V Step at VS 6 V GBW Gain-bandwidth product f = 100 kHz, RL = 10 k en Input-referred voltage noise in Input-referred current noise T.H.D. Total harmonic distortion f = 10 kHz (1) (2) TYP (2) UNIT 1.25 V/s 4 MHz f = 1 kHz 36 nV/Hz f = 1 kHz 0.24 pA/Hz 0.006% Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the devices such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. 6.7 Electrical Characteristics: 2.2-V DC Unless otherwise specified, all limits ensured for TA = 25C, V+ = 2.2 V, V- = 0 V, VCM = VO = V+/2 and RL > 1 M to V+/2 unless noted that limits apply at the temperature. (1) (2) PARAMETER VOS Input offset voltage TCVOS Input offset voltage average drift TEST CONDITIONS TA = TJ TA = 25C -75 TA = TJ -85 0.8 Input offset current 0.4 TA = TJ CMRR Common-mode rejection ratio 0 V VCM 2.2 V PSRR Power supply rejection ratio 2.2 V V+ 30 V VCM Input common-mode voltage range CMRR > 60 dB AV Large signal voltage gain RL = 10 k VO = 1.6 VPP RL = 10 k Output swing 18 TA = 25C 60 TA = TJ 56 TA = 25C 87 TA = TJ 84 dB 104 dB 2.3 V -0.1 TA = 25C 6.5 TA = TJ 5.4 TA = 25C TA = 25C TA = TJ nA M 82 46 0.05 V/mV 0.08 2.15 TA = TJ RL = 2 k 55 65 0 V VCM 2.2 V Input resistance nA 70 80 TA = 25C mV 200 -35 TA = TJ RIN 6 TA = 25C UNIT V/C 250 TA = 25C VCM = 2.2 V (2) 89 TA = TJ VCM = 0 V (1) 6 2 VCM = 2.2 V VO MAX 0.04 8 Input bias current IOS TYP TA = TJ VCM = 0 V IB MIN TA = 25C 0.1 0.09 V 0.13 0.14 Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. All limits are ensured by testing or statistical analysis. Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 Electrical Characteristics: 2.2-V DC (continued) Unless otherwise specified, all limits ensured for TA = 25C, V+ = 2.2 V, V- = 0 V, VCM = VO = V+/2 and RL > 1 M to V+/2 unless noted that limits apply at the temperature. (1)(2) PARAMETER TEST CONDITIONS TA = 25C Sourcing ISC TA = TJ Output short-circuit current Sinking IS Supply current MIN TYP 8 10.9 MAX 5.5 TA = 25C 6 TA = TJ 5 TA = 25C mA 7.7 0.57 TA = TJ UNIT 0.97 1.24 mA 6.8 Electrical Characteristics: 30-V DC Unless otherwise specified, all limits ensured for TA = 25C, V+ = 30 V, V- = 0 V, VCM = VO = V+/2 and RL > 1 M to V+/2 unless noted that limits apply at the temperature (1) PARAMETER VOS Input offset voltage TCVOS Input offset voltage average drift TEST CONDITIONS TA = TJ TA = 25C -100 TA = TJ -200 0.5 TA = TJ 0 V VCM 30 V 0 V VCM 27 V PSRR Power supply rejection ratio 2.2 V V+ 30 V VCM Input common-mode voltage range CMRR > 80 dB AV Large signal voltage gain RL = 10 k VO = 28 VPP 200 TA = 25C 80 TA = TJ 78 TA = 25C 90 TA = TJ 88 TA = 25C 87 TA = TJ 84 Output swing RL = 10 k Sourcing ISC Output short-circuit current (2) Sinking (2) (1) (2) M dB 115 104 dB 30.1 TA = 25C 30 TA = TJ 20 V 105 0.16 TA = TJ V/mV 0.275 0.375 TA = 25C 29.75 TA = TJ 28.65 TA = 25C 8.8 TA = TJ 6.5 TA = 25C 8.2 TA = TJ nA 104 -0.1 TA = 25C VO 65 135 0 V VCM 30 V Common mode rejection ratio nA 90 190 TA = 25C VCM = 30 V mV 300 -50 1.2 UNIT V/C 500 TA = 25C TA = TJ Input offset current CMRR 103 TA = 25C VCM = 0 V Input resistance 6 TA = TJ VCM = 30 V RIN MAX 0.04 2 Input bias current IOS TYP 8 VCM = 0 V IB MIN 29.8 V 11.7 11.5 mA 6 Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the devices such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/RJA. All numbers apply for packages soldered directly into a PC board. Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 7 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com Electrical Characteristics: 30-V DC (continued) Unless otherwise specified, all limits ensured for TA = 25C, V+ = 30 V, V- = 0 V, VCM = VO = V+/2 and RL > 1 M to V+/2 unless noted that limits apply at the temperature(1) PARAMETER IS 8 Supply current TEST CONDITIONS TA = 25C TA = TJ MIN TYP MAX 0.72 1.3 1.35 Submit Documentation Feedback UNIT mA Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 6.9 Typical Characteristics TA = 25C, RL = 1 M unless otherwise specified Figure 1. Supply Current vs Supply Voltage Figure 2. VOS vs Supply Voltage Figure 3. VOS vs VCM VS = 1.1 V Figure 4. VOS vs VCM VS = 2.5 V Figure 5. VOS vs VCM VS = 15 V Figure 6. Inverting Input Bias Current vs Common Mode Voltage VS = 1.1 V Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 9 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com Typical Characteristics (continued) TA = 25C, RL = 1 M unless otherwise specified 10 Figure 7. Noninverting Input Bias Current vs Common Mode Voltage VS = 1.1 V Figure 8. Inverting Input Bias Current vs Common Mode Voltage VS = 2.5 V Figure 9. Noninverting Input Bias Current vs Common Mode Voltage VS = 2.5 V Figure 10. Noninverting Input Bias Current vs Common Mode Voltage VS = 15 V Figure 11. Inverting Input Bias Current vs Common Mode Voltage VS = 15 V Figure 12. VO vs IO VS = 1.1 V Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 Typical Characteristics (continued) TA = 25C, RL = 1 M unless otherwise specified Figure 13. VO vs IO VS = 2.5 V Figure 14. Short-Circuit Current vs Supply Voltage Figure 15. Voltage Noise vs Frequency Figure 16. Current Noise vs Frequency Figure 17. Gain and Phase Figure 18. Gain and Phase, 2.7-V Supply Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 11 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com 7 Detailed Description 7.1 Overview Low supply current, wide bandwidth, input common mode voltage range that includes both rails, rail-to-rail output, good capacitive load driving ability, wide supply voltage (1.8 V to 32 V), and low distortion all make the LM7301 ideal for many diverse applications. The high common-mode rejection ratio and full rail-to-rail input range provides precision performance when operated in noninverting applications where the common-mode error is added directly to the other system errors. 7.2 Feature Description 7.2.1 Capacitive Load Driving The LM7301 has the ability to drive large capacitive loads. For example, 1000 pF only reduces the phase margin to about 25. 7.2.2 Transient Response The LM7301 offers a very clean, well-behaved transient response. Figure 19, Figure 20, Figure 22, and Figure 23 show the response when operated at gains of +1 and -1 when handling both small and large signals. The large phase margin, typically 70 to 80, assures clean and symmetrical response. In the large signal scope photos, Figure 19 and Figure 22, the input signal is set to 4.8 V. The output goes to within 100 mV of the supplies cleanly and without overshoot. In the small signal samples, the response is clean, with only slight overshoot when used as a follower. Figure 21 and Figure 24 are the circuits used to make these photos. Figure 20. AV = -1 V/V, Small Signal Behavior (0.2 V/div, 100 s/div) Figure 19. AV = -1 V/V, Large Signal Behavior (1 V/div, 2 s/div) 10 NY +2.5 V 10 NY + -2.5 V Copyright (c) 2016, Texas Instruments Incorporated Figure 21. AV = -1 V/V Schematic 12 Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 Feature Description (continued) Figure 22. AV = 1 V/V, Large Signal Behavior (1 V/div, 2 us/div) Figure 23. AV = 1 V/V, Small Signal Behavior (0.2 V/div, 200 s/div) +2.5 V + -2.5 V Copyright (c) 2016, Texas Instruments Incorporated Figure 24. AV = 1-V/V Schematic 7.2.3 Wide Supply Range The high power-supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) provide precision performance when operated on battery or other unregulated supplies. This advantage is further enhanced by the very wide supply range (2.2 V to 30 V, ensured) offered by the LM7301. In situations where highly variable or unregulated supplies are present, the excellent PSRR and wide supply range of the LM7301 benefit the system designer with continued precision performance, even in such adverse supply conditions. 7.2.4 Specific Advantages of 5-Pin SOT-23 (TinyPak) The obvious advantage of the 5-pin SOT-23, TinyPak, is that it can save board space, a critical aspect of any portable or miniaturized system design. The need to decrease overall system size is inherent in any handheld, portable, or lightweight system application. Furthermore, the low profile can help in height limited designs, such as consumer hand-held remote controls, sub-notebook computers, and PCMCIA cards. An additional advantage of the tiny package is that it allows better system performance due to ease of package placement. Because the tiny package is so small, it can fit on the board right where the operational amplifier must be placed for optimal performance, unconstrained by the usual space limitations. This optimal placement of the tiny package allows for many system enhancements that are not easily achieved with the constraints of a larger package. For example, problems such as system noise due to undesired pickup of digital signals can be easily reduced or mitigated. This pickup problem is often caused by long wires in the board layout going to or from an operational amplifier. By placing the tiny package closer to the signal source and allowing the LM7301 output to drive the long wire, the signal becomes less sensitive to such pickup. An overall reduction of system noise results. Often times system designers try to save space by using dual or quad op amps in their board layouts. This causes a complicated board layout due to the requirement of routing several signals to and from the same place on the board. Using the tiny operational amplifier eliminates this problem. Additional space savings parts are available in tiny packages from Texas Instruments, including low-power amplifiers, precision-voltage references, and voltage regulators. Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 13 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com Feature Description (continued) 7.2.5 Low-Distortion, High-Output Drive Capability The LM7301 offers superior low-distortion performance, with a total-harmonic-distortion-plus-noise of 0.06% at f = 10 kHz. The advantage offered by the LM7301 is its low distortion levels, even at high output current and low load resistance. See Stability Considerations for methods used to ensure stability under all load conditions. 7.3 Device Functional Modes 7.3.1 Stability Considerations Rail-to-rail output amplifiers like the LM7301 use the collector of the drive transistor(s) at the output pin, as shown in Figure 25. This allows the load to be driven as close as possible towards either supply rail. V+ + VHZ OUT Ccomp + VCopyright (c) 2016, Texas Instruments Incorporated Figure 25. Simplified Output Stage Block Diagram While this architecture maximizes the load voltage swing range, it increases the dependence of loop gain and subsequently stability, on load impedance and DC load current, compared to a non-rail-to-rail architecture. Thus, with this type of output stage, it is even more crucial to ensure stability by meticulous bench verification under all load conditions, and to apply the necessary compensation or circuit modifications to overcome any instability, if necessary. Any such bench verification should also include temperature, supply voltage, input common mode and output bias point variations as well as capacitive loading. For example, one set of conditions for which stability of the LM7301 amplifier may be compromised is when the DC output load is larger than 0.5 mA, with input and output biased to mid-rail. Under such conditions, it may be possible to observe open-loop gain response peaking at a high frequency (for example, 200 MHz), which is beyond the expected frequency range of the LM7301 (4 MHz GBW). Without taking any precautions against gain peaking, it is possible to see increased settling time or even oscillations, especially with low closed loop gain and / or light AC loading. It is possible to reduce or eliminate this gain peaking by using external compensation components. One possible scheme that can be applied to reduce or eliminate this gain peaking is shown in Figure 26. LM7301 + RC 100 Y Output Snubber Network CC 100 pF Copyright (c) 2016, Texas Instruments Incorporated Figure 26. Non-Dissipating Snubber Network to Reduce Gain Peaking 14 Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 Device Functional Modes (continued) The non-dissipating snubber, consisting of Rc and Cc, acts as AC load to reduce high-frequency gain peaking with no DC loading so that total power dissipation is not increased. The increased AC load effectively reduces loop gain at higher frequencies thereby reducing gain peaking due to the possible causes stated in the previous sentence. For the particular set of Rc and Cc values shown in Figure 26, loop gain peaking is reduced by about 25 dB under worst case peaking conditions (I_source= 2mA DC at around 180 MHz) thus confining loop gain to less than 0 dB and eliminating any possible instability. For best results, it may be necessary to tune the values of Rc and Cc in a particular application to consider other subtleties and tolerances. 7.3.2 Power Dissipation Although the LM7301 has internal output current limiting, shorting the output to ground when operating on a 30-V power supply will cause the operational amplifier to dissipate about 350 mW. This is a worst-case example. In the 8-pin SOIC package, this will cause a temperature rise of 42C. In the 5-pin SOT-23 package, the higher thermal resistance will cause a calculated rise of 59C. This can raise the junction temperature to greater than the absolute maximum temperature of 150C. Operating from split supplies greatly reduces the power dissipated when the output is shorted. Operating on 15-V supplies can only cause a temperature rise of 21C in the 8-pin SOIC and 30C in the 5-pin SOT-23 package, assuming the short is to ground. Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 15 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Handheld Remote Controls The LM7301 offers outstanding specifications for applications requiring good speed/power trade-off. In applications such as remote control operation, where high bandwidth and low power consumption are needed, the LM7301 performance can easily meet these requirements. 8.1.2 Remote Microphone in Personal Computers Remote microphones in Personal Computers often use a microphone at the top of the monitor which must drive a long cable in a high noise environment. One method often used to reduce the nose is to lower the signal impedance, which reduces the noise pickup. In this configuration, the amplifier usually requires 30 db to 40 db of gain, at bandwidths higher than most low-power CMOS parts can achieve. The LM7301 offers the tiny package, higher bandwidths, and greater output drive capability than other rail-to-rail input/output parts can provide for this application. 8.1.3 Optical Line Isolation for Modems The combination of the low distortion and good load driving capabilities of the LM7301 make it an excellent choice for driving opto-coupler circuits to achieve line isolation for modems. This technique prevents telephone line noise from coupling onto the modem signal. Superior isolation is achieved by coupling the signal optically from the computer modem to the telephone lines; however, this also requires a low distortion at relatively high currents. Due to its low distortion at high-output drive currents, the LM7301 fulfills this need, in this and in other telecom applications. See Stability Considerations for methods used to ensure stability under all load conditions. 8.2 Typical Applications The circuit shown in Figure 27 uses the wide supply voltage range (1.8 V to 32 V), rail-to-rail input and output voltage capability, and the unity gain stability of the LM7301 to sense the current flow from the power supply to a load, such as a battery being charged, or any other load. The circuit creates a ground-referenced output voltage, which varies linearly with the load current, for easy interface to the rest of the circuitry to create fault-protection, current and power metering, or current regulation functions. V+ + R1 2k R2 2k RSENSE 0.2 Y + Q1 2N3906 VOUT C1 Optional Load R3 10 k ICHARGE VO U T R SENSE u R 3 R1 u IC H A R G E 1 : u IC H A R G E Copyright (c) 2016, Texas Instruments Incorporated Figure 27. High Side Current Sensing 16 Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 Typical Applications (continued) 8.2.1 Design Requirements The output port is designed for easy interface; it is ground-referenced and it produces 0 V with 0 A of load current. A typical stage that follows this stage, an ADC which samples the load current for example, is easily connected to the Q1 collector with no level shifting or additional biasing required. Apart from a wide supply voltage capability, the operational amplifier used in Figure 27 must have an input voltage range that includes the V+ rail voltage to allow high side current sensing. Furthermore, it should be unity gain stable and have an output voltage range which is less than one Vbe from V+. The LM7301 has all these requirements. 8.2.2 Detailed Design Procedure 8.2.2.1 Selecting RSENSE Pick the value of RSENSE low enough to minimize its heat / voltage loss while observing Equation 1 for minimum detectable load current, ICHARGE_MIN , and device offset voltage, VOS: VOS RSENSE > ICHARGE_MIN (1) With the schematic values shown and LM7301's VOS limit of 6 mV: ICHARGE _ MIN > 30 mA (2) If the system has the ability to be initialized and corrected for initial readings, it may be possible to lower the value of RSENSE. 8.2.2.2 Selecting R1, and R3 Values Pick the R3 / R1 ratio to get the proper full-scale VOUT when the maximum load current, ICHARGE_MAX, flows: VOUT R3 = R1 RSENSE ICHARGE _ MAX (3) For example, to get 3-V output with 3 A of load current when RSENSE = 0.2 results in: R3 =5 R1 (4) Ensure that the resulting transfer function also satisfies the application's need when the minimum load current, ICHARGE_MIN is being sensed. In this example, the minimum output voltage will be 30 mV (when ICHARGE_MIN = 30 mA). With the R3/R1 ratio determined, pick the value of R3 for Q1 collector current less than 1 mA at the maximum VOUT, and determine R1 from that. 8.2.2.3 R1, R2 Selection Normally, R2 is set equal to R1 to cancel out the error term due to the input bias current, IB (approximately 200 nA for the LM7301). 8.2.2.4 Error Terms Expressions Here are the expressions for the output change caused by various parameter shifts, evaluated for Figure 27 values with ICHARGE_MAX= 3 A: Offset Voltage, VOS: DVOS R3 DVOUT = = 5DVOS R1 (5) Offset current, IOS: DI R2 R3 DVOUT = OS = IOS 10 k R1 (6) Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 17 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com Typical Applications (continued) Self-heating of RSENSE causing RSENSE with ICHARGE_MAX flowing: R3 DVOUT = DRSENSE ICHARGE _ MAX = DRSENSE 15 R1 (7) 8.2.2.5 Frequency Response Depending on the application, it may be useful to have the means to control the upper end of the circuit's frequency response. An example is limiting the circuit's response to high-frequency load current spikes or switching frequencies so that the circuit only reacts to DC or lower frequencies. Capacitor C1 in Figure 27 can be used to accomplish just that. The original circuit has a -3-dB bandwidth close to 4.5 MHz which can be reduced by increasing the value of C1, as shown in Figure 28. 0 -2 -4 Response (dB) -6 -8 -10 -12 -14 -16 -18 0 10 pF 100 pF 1 nF 10 nF -20 100 1000 10000 100000 Frequency (Hz) 1000000 1E+7 D001 Figure 28. Current Sense Frequency Response vs C1 Value 8.2.3 Application Curves Figure 29 shows the transfer function of the circuit for several values of RSENSE. Notice that with 1 , the output is limited to approximately 16 V because of the additional drop across the sense resistor at higher load currents. Figure 30 shows the low-end of the load current is more non-linear for low RSENSE values, as noted in Selecting RSENSE due to VOS. Higher RSENSE values help with this at the expense of a higher loss and voltage drop. 0.1 18 0.1 : 0.2 : 0.5 : 1: 15 0.1 : 0.2 : 0.5 : 1: 0.08 VOUT (V) VOUT (V) 12 9 0.06 0.04 6 0.02 3 0 0 0 18 1 2 3 I_CHARGE (Amp) 4 5 0 D002 0.02 0.04 0.06 I_CHARGE (A) 0.08 0.1 D003 Use lower sense resistor value to avoid voltage limitation! Line showing linearity degradation at the lower end. Figure 29. Current Sense Transfer Function for Various RSENSE Values Figure 30. Low-End Transfer Function for Various RSENSE Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 LM7301 www.ti.com SNOS879I - AUGUST 1999 - REVISED MAY 2016 9 Power Supply Recommendations The LM7301 is specified for operation from 1.8 V to 32 V (0.9 V to 16 V). Being a rail-to-rail input and output device, any operating voltage conditions within the supply voltage range can be accommodated. Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, TI recommends good printed-circuit board (PCB) layout practices. Low-loss, 0.1-F bypass capacitors should be connected between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single supply applications. 10.2 Layout Example RIN VIN + VOUT RG RF Copyright (c) 2016, Texas Instruments Incorporated Figure 31. Schematic Representation Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines as possible RF NC NC IN V+ +IN OUT VS+ RG GND GND RIN VIN Use low-ESR, ceramic Bypass capacitor V Only needed for dual-supply operation GND VS (or GND for single supply) NC VOUT Copyright (c) 2016, Texas Instruments Incorporated Figure 32. Operational Amplifier Board Layout for Noninverting Configuration Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 19 LM7301 SNOS879I - AUGUST 1999 - REVISED MAY 2016 www.ti.com 11 Device and Documentation Support 11.1 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright (c) 1999-2016, Texas Instruments Incorporated Product Folder Links: LM7301 PACKAGE OPTION ADDENDUM www.ti.com 22-Feb-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM7301IM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM73 01IM LM7301IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM73 01IM LM7301IM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A04A LM7301IM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A04A LM7301IM5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A04A LM7301IM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A04A LM7301IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM73 01IM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Feb-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM7301IM5 SOT-23 DBV 5 1000 178.0 8.4 LM7301IM5/NOPB SOT-23 DBV 5 1000 178.0 LM7301IM5X SOT-23 DBV 5 3000 178.0 LM7301IM5X/NOPB SOT-23 DBV 5 3000 LM7301IMX/NOPB SOIC D 8 2500 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM7301IM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM7301IM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM7301IM5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LM7301IM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM7301IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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