ANALOG Microprocessor-Compatible DEVICES 12-Bit D/A Converter AD667 1.1 Scope. This specification covers the detail requirements for a complete 12-bit digital-to-analog converter with microprocessor interface, buried Zener reference and output amplifier. 1.2 Part Number. The complete part number per Table | of this specification is as follows: Device Part Number! =] AD667S(X)/883B NOTE See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description D D-28 28-Pin DIP E E-28A 28-Pin LCC 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) Vec to Power Ground 2... 1. ns 0 to +18V Veg to Power Ground... 2... 0to 18V Digital Inputs (Pins 11-15, 17-28) to Power Ground .......-....5-.-200- 1.0V to +7.0V Ref In to Reference Ground... 0. 0 oe es +12V Bipolar Offset to Reference Ground... 0... 2 ee +12V 10V Span R to Reference Ground... 2... 2. te ee es +12V 20V Span R to Reference Ground... 6 1 ee ee ee +24V Ref Out, Vour (Pins 6,9) 2. 0 ee ee Indefinite Short to Power Ground Momentary Short to Vec Power Dissipation ......... a ee ee ee ee 1000mW Storage Temperature Range... 1 6. ee te ee ~65C to + 150C Lead Temperature (Soldering 10sec) 2. 2 0 6 ee ae $300C 1.5 Thermal Characteristics. Thermal Resistance 0;- = 25C/W for D-28 . 81a = 60C/W for D-28 8ic =. 42C/W for E-28A | Oya = 125CW for E-28AAD667SPECIFICATIONS Table 1. Design Sub Sub 1 i Limit Group | Group Test Symbol | Device | @+25C | 1 2,3 Test Condition! Units Relative Accuracy RA -) 1/2 V2 3/4 All Bits with Positive + LSB max Errors On. All Bits with Negative Errors On Differential Nonlinearity DNL -1 3/4 3/4 1 Major Carry Errors + LSB max Gain Error? Ag ~1 0.20 0.20 All Bits On + % FSR max -: [cae Temperature TCA, -1 30 30 All Bits On + ppm/C max 1 Coefficient Unipolar Offset Error Vos -1 2 2 All Bits Off + LSB max Temperature Coefficient TCVos | - 1 3 3 All Bits Off + ppm/*C max Unipolar Offset Bipolar Zero Error* Boz -1 0.10 0.10 MSB On, All + % FSR max Other Bits Off Bipolar Mode B/P Zero Temperature TCBpy::} -1 10 10 MSB On, All + ppm/C max 4 Coefficient Other Bits Off Bipolar Mode Input Resistance Rw -1 15 kQmin 25 kf.) max Reference Output Voltage? ; Vari -) 9.9 9.9 9.9 Bipolar Mode, Vs = + 11.4 +V min 10.10 10.10 | 10.10 0.tmA External Load + Vmax Output Current lour -1 5 +mAmin Output Short-Circuit Current Isc. -1 40 + mA max Latch Functionality Agy -1 1 J 1 See Notes 4 & 5 + LSB max Latch Functionality Voss -1 1 ! 1 See Note 4 + LSB max Power Supply Rejection Ratio PSRR -1 10 10 All Bits On ppm of FSR/% +11.4V5Vecs + 16.5V max 10 10 All Bits On -11.4VSVpps -16.5V Power Supply Current lec -1 12 12 Veco = + 16.5V, Vix = 16.5V +mA max lec: AN Bits On lin ~] 25 25 Ing: All Bits On mAmax Digital Input High Voltage Vink -1 2.0 2.0 2.0 +Vmin 5.5 + V max Digital Input Low Voltage Vu. -1 0.8 0.8 0.7 +V max q Digital Input High Current lin -1 10 10 Vin = 5.5V +A max Digital Input Low Current Ii. ~-1 5 5 Viz, = 0.0V +pA max | Data Setup Time toc -1 50 ns min i Data Hold Time toy -1 0 ns min | CS Pulse Width top -1 100 ns min Address Valid End of CS tac -1 100 ns min : Output Voltage Settling Time tsi -1 4 Rep = 10k Ry, = 2k||S00pF ps max 3 Rep = 5k See Figure | : NOTES Voc = +15V, Veg = 15V, 502M resistor Pin 6to Pin 7, Ag, Aj, Az, A;, CS = LOGIC 0, Vig = 2.0V, Viz, = 0.8V, Unipolar configuration unless otherwise specified. Unipolar Configuration ~ Pins | and 2 to Pin 9, Pin 4to PinS. Bipolar Configuration Pin 1 to Pin 9, $02 resistor Pin 4 to Pin 6. * Adjustable to 0. 3In subgroup I, the reference output is loaded with 0.5mA nominal reference current, 1.0mA bipolar offset current and 0.1mA additional current. In subgroups 2 and 3, only the 0.5mA reference input current is applied. The reference must be buffered to supply external loads at elevated temperatures. All bits low, Agy Ay, Az Ay LOGIC 0"; Ap, Aj, Az, Ay initialized to LOGIC 1, each 4-Bit register set to LOGIC 1, and Ao, Ai, Az set sequentially to LOGIC 0 and back to LOGIC 1 to latch data into first rank. 5A, set to LOGIC 0 and back to LOGIC 1 to latch full-scale output into second rank. See Figure | and Table 2.AD667 3.2.1 Functional Block Diagram and Terminal Assignments. ise) (LSB DB1t - 088 OB? -+ OB4 DB3 -- 060 28)\(27)(26 (28 24X23(22K(21 20K(19)(18 (17 cs sors | apts | aaits | a2 (43 , 1) 20V SPAN al (14 3 se 2) 10V SPAN AG (15 5k aa C3 12-B1T PARALLEL LATCH S) sumac woes LiL Lit | Li ji ourrur CG 1ZBIT HIGH SPEED DAC Ss = 9) Your + $) aGNO Mi Low Tc 9.95K our (6 REFERENCE AD667 . 4) ei orF ; Lid WW + Vee POWER -Vee GND E PACKAGE (LCC) a h 2e a4 2 5 8 ff se E28 2 5 a oa 28 6S 8 4 3 2 4 28 27 26 REF GND 5 Vass OUT 6 Vaee IN 7 AD667 +Vee 8 TOP. VIEW Vour 9 =Veg 10 cs 11 12.13 14 18 16 17 18 UD Be 2s 38 8 = = xa rc wn 3 a 3 z 5 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (56) 25 24 23 22 21 20 19 bes DB? O86. oss DB4 083 DB2 Vnee tN ] + Vee QO 22 {7} 085 aif] 08 D PACKAGE (DIP) zov span[_]1 ~ 2a [7] 0811 mse) tov sean (_] 2 em 27 7] 010 sumscr.([} 3 SDENTIFIER 26 [_] 089 Bip OFF Co 4 28) oss acno (js 26 [[} 087 vaer our C] 6 23 [7] oes 7 AD667 8 3 vou Vee Cc 0 eC. aa QO 12 aaj ail] 20 [7] 083 19 [_] 082 46 [7] 081 17 [7} bBo wise) 16 [_] POWER GROUND 16 [_) ao *NOTE DIP PACKAGE PIN NUMBERS AND LCC CONTACT NUMBERS SERVE THE SAME FUNCTION.AD667 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). Sooo dade +15.00V @> ct > a . - 8.00 -__+{10] Te __ ra ta ie 6 GND +5.00V Ears ST 0B11-O0B0 a LX Te. rh " | OUTPUT +1/2LSB Figure 7. Table 2. AD667 Truth Table CS |A3 A2 Al AO | Operation 1 X X X X No Operation X 71 1 1 1 No Operation 0 I 1 1 0 Enable 4 LSBs of First Rank 0 1 1 0 1 Enable 4 Middle Bits of First Rank 0 1 0 1 1 Enable 4 MSBs of First Rank 0 o 1 1 1 Loads Second Rank from First Rank 0 0 0 0 0 All Latches Transparent X" = Dont Care