0.25 dB LSB, 7-Bit, Silicon Digital Attenuator, 0.1 GHz to 6.0 GHz HMC1119 Data Sheet GND 4 ATTNIN 5 GND 6 D3 D4 D5 D6 20 19 SERIAL/ PARALLEL CONTROL 7-BIT DIGITAL ATTENUATOR GND 7 8 9 10 11 18 SERNIN 17 CLK 16 LE 15 GND 14 ATTNOUT 13 GND 12 PACKAGE BASE GND 12962-001 3 21 GND P/S 22 GND 2 23 GND VDD 24 GND 1 GND D0 D2 FUNCTIONAL BLOCK DIAGRAM Attenuation range: 0.25 dB LSB steps to 31.75 dB Low insertion loss: 1.1 dB at 1.0 GHz 1.3 dB at 2.0 GHz Typical step error: less than 0.1 dB Excellent attenuation accuracy: less than 0.2 dB Low phase shift error: 6 phase shift at 1.0 GHz Safe state transitions High linearity 1 dB compression (P1dB): 31 dBm typical Input third-order intercept (IP3): 54 dBm typical RF settling time (0.05 dB final RF output): 250 ns Single supply operation: 3.3 V to 5.0 V ESD rating: Class 2 (2 kV human body model (HBM)) 24-lead, 4 mm x 4 mm LFCSP package: 16 mm2 D1 FEATURES Figure 1. APPLICATIONS Cellular infrastructure Microwave radios and very small aperture terminals (VSATs) Test equipment and sensors IF and RF designs GENERAL DESCRIPTION The HMC1119 is a broadband, highly accurate, 7-bit digital attenuator, operating from 0.1 GHz to 6.0 GHz with 31.5 dB attenuation control range in 0.25 dB steps. The HMC1119 is implemented in a silicon process, offering very fast settling time, low power consumption, and high ESD robustness. The device features safe state transitions and is optimized for excellent step accuracy and high linearity over frequency and temperature range. The RF input and output are internally matched to 50 and do not require any external matching components. The design is bidirectional; therefore, the RF input and output are interchangeable. Rev. C The HMC1119 has an on-chip regulator that can support a wide supply operating range from 3.3 V to 5.0 V with no performance change in electrical characteristics. The HMC1119 incorporates a driver that supports serial (3-wire) and parallel controls of the attenuator. The HMC1119 comes in a RoHS-compliant, compact, 4 mm x 4 mm LFCSP package. A fully populated evaluation board is available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2016-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC1119 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................8 Functional Block Diagram .............................................................. 1 Input Power Compression and Third-Order Intercept ......... 10 General Description ......................................................................... 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Serial Control Interface ............................................................. 11 Specifications..................................................................................... 3 RF Input Output ......................................................................... 11 Electrical Specifications ............................................................... 3 Parallel Control Interface .......................................................... 12 Timing Specifications .................................................................. 4 Power-Up Sequence ................................................................... 12 Absolute Maximum Ratings ....................................................... 5 Applications Information .............................................................. 13 ESD Caution .................................................................................. 5 Evaluation Printed Circuit Board ............................................ 13 Pin Configuration and Function Descriptions ............................. 6 Packaging and Ordering Information ......................................... 15 Interface Schematics..................................................................... 7 Outline Dimensions ................................................................... 15 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 15 REVISION HISTORY 4/2018--Rev. B to Rev C Changes to Figure 23 ...................................................................... 12 Change to PCB Description, Table 7............................................ 13 Updated Outline Dimensions ....................................................... 15 9/2017--Rev. A to Rev. B Changed CP-24-16 to HCP-24-3 ................................. Throughout Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 8/2017--Rev. 0 to Rev. A Added Timing Specifications Section.............................................4 Moved Table 2 ....................................................................................4 Changes to Figure 5 and Figure 6 ....................................................7 Changes to Serial Control Interface Section ............................... 11 Moved Figure 22 and Table 6 ........................................................ 11 Changes to Figure 23...................................................................... 12 Moved Parallel Control Interface Section, Direct Parallel Mode Section, Latched Parallel Mode Section, Power-Up Sequence Section, and Power-Up States Section ......................................... 12 Updated Outline Dimensions ....................................................... 15 9/2016--Revision 0: Initial Version Rev. C | Page 2 of 15 Data Sheet HMC1119 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V to 5.0 V, TA = 25C, 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS ATTENUATION Range Accuracy Step Error Overshoot RETURN LOSS ATTNIN, ATTNOUT RELATIVE PHASE SWITCHING CHARACTERISTICS tRISE, tFALL tON, tOFF Settling Time INPUT LINEARITY 0.1 dB Compression (P0.1dB) 1 dB Compression (P1dB) Input Third-Order Intercept (IP3) SUPPLY CURRENT (IDD) CONTROL VOLTAGE THRESHOLD Low High RECOMMENDED OPERATING CONDITIONS Supply Voltage Range (VDD) Digital Control Voltage Range RF Input Power Case Temperature (TCASE) Test Conditions/Comments 0.1 GHz to 1.0 GHz 0.1 GHz to 2.0 GHz 0.1 GHz to 4.0 GHz 0.1 GHz to 6.0 GHz 0.2 GHz to 6.0 GHz Delta between minimum and maximum attenuation states Referenced to insertion loss; all attenuation states Min 0.1 Typ 1.1 1.3 1.6 2.0 Max 6.0 1.8 2.0 2.3 2.8 31.75 -(0.05 + 4% of attenuation setting) Unit GHz dB dB dB dB dB +(0.05 + 4% of attenuation setting) dB All attenuation states Between all attenuation states All attenuation states 1.0 GHz 2.0 GHz 4.0 GHz 6.0 GHz 1.0 GHz 2.0 GHz 4.0 GHz 6.0 GHz 0.1 0.1 dB dB 23 22 19 17 6 18 38 58 dBm dBm dBm dBm Degrees Degrees Degrees Degrees 10%/90% RF output 50% CTL to 10%/90% RF output 50% CTL to 0.05 dB final RF output 50% CTL to 0.10 dB final RF output All attenuation states, 0.2 GHz to 6 GHz 60 150 250 200 ns ns ns ns 30 31 54 dBm dBm dBm 0.3 0.6 mA mA Two-tone input power = 16 dBm/tone, f = 1 MHz VDD = 3.3 V VDD = 5.0 V <1 A typical VDD = 3.3 V VDD = 5.0 V VDD = 3.3 V VDD = 5.0 V For P/S, CLK, SERNIN, LE, D0 to D6 pins All attenuation states, TCASE = 85C 0 0 2.0 3.5 0.5 0.8 3.3 5.0 V V V V 3.0 0 5.4 VDD 24 +85 V V dBm C -40 Rev. C | Page 3 of 15 HMC1119 Data Sheet TIMING SPECIFICATIONS See Figure 23 and Figure 24 for the timing diagrams. Table 2. Parameter tSCK tCS tCH tLN tLEW tLES tCKN tPH tPS Description Minimum serial period, see Figure 23 Control setup time, see Figure 23 Control hold time, see Figure 23 LE setup time, see Figure 23 Minimum LE pulse width, see Figure 24 Minimum LE pulse spacing, see Figure 23 Serial clock hold time from LE, see Figure 23 Hold time, see Figure 24 Setup time, see Figure 24 Rev. C | Page 4 of 15 Min 70 15 Typ 20 15 10 630 0 10 2 Max Unit ns ns ns ns ns ns ns ns ns Data Sheet HMC1119 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 3. Parameter RF Input Power (TCASE = 85C) Digital Control Inputs (P/S, CLK, SERNIN, LE, D0 to D6) Supply Voltage (VDD) Continuous Power Dissipation (PDISS) Thermal Resistance (at Maximum Power Dissipation) Temperature Channel Temperature Storage Maximum Reflow Temperature ESD Sensitivity (HBM) Rating 25 dBm -0.3 V to VDD + 0.5 V -0.3 V to +5.5 V 0.31 W 156C/W ESD CAUTION 135C -65C to +150C 260C (MSL3 Rating) 2 kV (Class 2) Rev. C | Page 5 of 15 HMC1119 Data Sheet D2 D3 D4 D5 D6 24 23 22 21 20 19 D0 1 18 SERNIN VDD 2 17 CLK P/S 3 16 LE 15 GND HMC1119 TOP VIEW (Not to Scale) 14 ATTNOUT GND 6 13 GND 8 GND GND 7 9 10 11 12 GND 5 GND ATTNIN GND 4 GND GND NOTES 1. THE EXPOSED PAD AND GND PINS MUST BE CONNECTED TO RF DC GROUND. 12962-002 D1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 19 to 24 Mnemonic D0, D6 to D1 2 3 VDD P/S 4, 6 to 13, 15 GND 5 ATTNIN 14 ATTNOUT 16 LE 17 CLK 18 SERNIN EPAD Description Parallel Control Voltage Inputs. These pins attain the required attenuation (see Table 6). There is no internal pull-up or pull-down on these pins; therefore, these pins must always be kept at a valid logic level (VIH or VIL) and must not be left floating. Supply Voltage Pin. Parallel/Serial Control Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. For parallel mode, set Pin 3 to low; for serial mode, set Pin 3 to high. Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF/dc ground. See Figure 4 for the GND interface schematic. Attenuator Input. This pin is dc-coupled and matched to 50 . A blocking capacitor is required. Select the value of the capacitor based on the lowest frequency of operation. See Figure 5. Attenuator Output. This pin is dc-coupled and matched to 50 .A blocking capacitor is required. Select the value of the capacitor based on the lowest frequency of operation. See Figure 5. Serial/Parallel Interface Latch Enable Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section for more information. Serial Interface Clock Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section for more information. Serial interface Data Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section for more information. Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. C | Page 6 of 15 Data Sheet HMC1119 VDD ATTNIN, ATTNOUT 12962-023 INTERFACE SCHEMATICS 12962-021 D0 TO D5 Figure 3. D0 to D6 Interface Figure 5. ATTIN and ATTOUT Interface GND 12962-022 VDD 12962-024 P/S, LE, CLK, SERNIN Figure 4. GND Interface Figure 6. P/S, LE, CLK, and SERNIN Interface Rev. C | Page 7 of 15 HMC1119 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE 0 +85C +25C -40C NORMALIZED ATTENUATION (dB) INSERTION LOSS (dB) 0 -1 -2 -3 -5 -10 -15 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB -20 -25 0 1 2 3 4 5 6 FREQUENCY (GHz) -35 12962-003 -4 0 6 -10 -30 IL 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB -40 1 2 3 4 IL 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB -40 -50 6 5 -30 FREQUENCY (GHz) -60 0 0.8 0.4 STATE ERROR (dB) 0.6 0.4 0 -0.4 -0.8 5 6 1GHz 2GHz 3GHz 4GHz 5GHz 6GHz 0.2 0 -0.2 -0.4 -1.2 -0.6 -1.6 -0.8 8 12 16 20 24 28 32 ATTENUATION STATE (dB) -1 12962-007 4 4 1 0.8 1.2 0 3 Figure 11. Output Return Loss (Major States Only) 100MHz 200MHz 400MHz 500MHz 1.6 2 FREQUENCY (GHz) Figure 8. Input Return Loss (Major States Only) 2.0 1 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) Figure 12. State Error vs. Attentuation State, 1 GHz to 6 GHz Figure 9. State Error vs. Attentuation State, 0.1 GHz to 0.5 GHz Rev. C | Page 8 of 15 12962-009 0 -20 12962-006 OUTPUT RETURN LOSS (dB) -20 12962-004 INPUT RETURN LOSS (dB) 5 0 -10 STATE ERROR (dB) 4 Figure 10. Normalized Attenuation (Major States Only) 0 -2.0 3 FREQUENCY (GHz) Figure 7. Insertion Loss vs. Frequency at Various Temperatures -50 2 1 12962-005 -30 Data Sheet HMC1119 2.0 1.0 1.5 0.8 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB 0.6 STEP ERROR (dB) 0.5 0 -0.5 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB -1.5 1 2 3 4 5 0.2 0 -0.2 -0.4 -0.6 -0.8 -2.0 0 0.4 6 FREQUENCY (GHz) -1.0 0 20 0 -20 -40 -60 0 1 2 3 4 5 FREQUENCY (GHz) 6 12962-011 RELATIVE PHASE (deg) 40 3 4 5 Figure 15. Step Error vs. Frequency, Major States Only 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB 60 2 FREQUENCY (GHz) Figure 13. State Error vs. Frequency, Major States Only 80 1 Figure 14. Relative Phase vs. Frequency, Major States Only Rev. C | Page 9 of 15 6 12962-010 -1.0 12962-008 STATE ERROR (dB) 1.0 HMC1119 Data Sheet INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT 40 40 +85C +25C -40C 35 P1dB (dBm) 30 25 20 25 0.2 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 15 12962-012 0 0 2 4 3 5 6 FREQUENCY (GHz) Figure 16. P1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 1 GHz Figure 19. P1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 6 GHz 40 40 +85C +25C -40C +85C +25C -40C 35 P0.1dB (dBm) 35 30 25 20 30 25 0.2 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 15 12962-013 0 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 17. P0.1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 1 GHz 12962-016 20 15 Figure 20. P0.1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 6 GHz 70 70 +85C +25C -40C +85C +25C -40C 60 IP3 (dBm) 60 50 40 50 40 30 0 0.2 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 12962-014 IP3 (dBm) 1 12962-015 20 15 P0.1dB (dBm) 30 Figure 18. IP3 vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.1 GHz to 1 GHz 30 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 21. IP3 vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.1 GHz to 6 GHz Rev. C | Page 10 of 15 12962-017 P1dB (dBm) 35 +85C +25C -40C Data Sheet HMC1119 THEORY OF OPERATION In serial mode, the 7-bit SERNIN data is clocked MSB first on rising CLK edges into the shift register; then, LE must be toggled high to latch the new attenuation state into the device. The LE must be set low to clock a set of 7-bit data into the shift register because CLK is masked to prevent the attenuator value from changing if LE is kept high. The HMC1119 incorporates a 7-bit fixed attenuator array that offers an attenuation range of 0.25 dB to 31.75 dB, with 0.25 dB steps. An integrated driver provides both serial and parallel mode control of the attenuator array (see Figure 22). The HMC1119 can be in either serial or parallel mode control by setting the P/S pin to high or low, respectively (see Table 5). The 7-bit data, loaded in either serial or parallel mode, then latches with the control signal, LE, to determine the attenuator value. In serial mode operation, both the serial control inputs (LE, CLK, SERNIN) and the parallel control inputs (D0 to D6) must always be kept at a valid logic level (VIH or VIL) and must not be left floating. It is recommended to connect the parallel control inputs to ground and to use pull-down resistors on all serial control input lines if the device driving these input lines goes high impedance during hibernation. Table 5. Mode Selection Table1 P/S Pin State Low High 1 Control Mode Parallel Serial The P/S pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. RF INPUT OUTPUT The attenuator in the HMC1119 is bidirectional; the ATTNIN and ATTNOUT pins are interchangeable as the RF input and output ports. The attenuator is internally matched to 50 at both input and output; therefore, no external matching components are required. The RF pins are dc-coupled; therefore, dc blocking capacitors are required on RF lines. SERIAL CONTROL INTERFACE The HMC1119 utilizes a 3-wire serial to parallel (SPI) configuration, as shown in the serial mode timing diagram (see Figure 23): serial data input (SERNIN), clock (CLK), and latch enable (LE). The serial control interface activates when the P/S pin is set to high. D0 SERNIN D1 DQ DQ DQ D2 D3 D4 DQ DQ DQ D6 D5 DQ P/S P/S SELECT LE 7-BIT LATCH RF INPUT 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB RF OUTPUT Figure 22. Attenuator Array Functional Block Diagram Table 6. Truth Table D6 Low Low Low Low Low Low Low High High 1 D5 Low Low Low Low Low Low High Low High D4 Low Low Low Low Low High Low Low High Digital Control Input 1 D3 D2 Low Low Low Low Low Low Low High High Low Low Low Low Low Low Low High High D1 Low Low High Low Low Low Low Low High D0 Low High Low Low Low Low Low Low High Attenuation State (dB) 0 (reference) 0.25 0.5 1.0 2.0 4.0 8.0 16.0 31.75 Any combination of the control voltage input states shown in Table 6 provides an attenuation equal to the sum of the bits selected. Rev. C | Page 11 of 15 12962-018 CLK HMC1119 P/S SERNIN X Data Sheet MSB [FIRST IN] X D6 tCS LSB [LAST IN] tCH D5 D4 D3 D2 D1 D0 D[6:0] NEXT WORD X tLEW tLN X tCKN tSCK 12962-019 CLK tLES LE Figure 23. Serial Control Timing Diagram PARALLEL CONTROL INTERFACE P/S The parallel control interface has seven digital control input lines (D6 to D0) to set the attenuation value. D6 is the most significant bit (MSB) that selects the 16 dB attenuator stage, and D0 is the least significant bit (LSB) that selects the 0.25 dB attenuator stage (see Figure 22). Setting P/S to low enables parallel mode. There are two modes of parallel operation: direct parallel mode and latched parallel mode. tPS D6 TO D0 X tPH D[6:0] PARALLEL CONTROL X tLEW LE 12962-020 In parallel mode operation, both the serial control inputs (LE, CLK, SERNIN) and the parallel control inputs (D0 to D6) must always be kept at a valid logic level (VIH or VIL) and must not be left floating. It is recommended to connect the serial control inputs to ground and to use pull-down resistors on all parallel control input lines if the device driving these input lines goes high impedance during hibernation. X Figure 24. Latched Parallel Mode Timing Diagram POWER-UP SEQUENCE The ideal power-up sequence is as follows: 1. 2. 3. Power up GND. Power up VDD. Power up the digital control inputs (the relative order of the digital control inputs is not important). Power up the RF input. Direct Parallel Mode 4. For direct parallel mode, the latch enable (LE) pin must be kept high. Change the attenuation state using the control voltage inputs (D0 to D6) directly. This mode is ideal for manual control of the attenuator and using hardware, switches, or a jumper. For latched parallel mode operation, LE must be toggled. The relative order of the digital inputs is not important as long as the inputs are powered up after GND and VDD. Latched Parallel Mode The logic state of the device is at maximum attenuation when, at power up, LE is set to low. The attenuator latches in the desired power-up state approximately 200 ms after power up. The latch enable (LE) pin must be low when changing the control voltage inputs (D0 to D6) to set the attenuation state. When the desired state is set, LE must be toggled high to transfer the 7-bit data to the bypass switches of the attenuator array, then toggled low to latch the change into the device (see Figure 24). Power-Up States Rev. C | Page 12 of 15 Data Sheet HMC1119 APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD 12962-026 The schematic of the evaluation board, EV2HMC1119LP4M, is shown in Figure 25. The PCB is four-layer material with a copper thickness of 0.7 mils on each layer. Each copper layer is separated with a dielectric material. The top dielectric material is 10-mil RO4350 with a typical dielectric constant of 3.48. The middle and bottom dielectric materials are FR-4 material, used for mechanical strength and to meet the overall board thickness of approximately 62 mils, which allows SMA connectors to be slipped in at board edges. All RF and dc traces are routed on the top copper layer. The RF transmission lines are designed using coplanar waveguide model (CPWG) with a width of 18 mils, spacing of 17 mils, and dielectric thickness of 10 mils to maintain 50 characteristic impedance. The inner and bottom layers are solid ground planes. For optimal electrical and thermal performance, an ample number of vias are populated around the transmission lines and under the package exposed pad. The evaluation board layout serves as a recommendation for the optimal performance on both electrical and thermal aspects. Figure 25. EV2HMC1119LP4M Evaluation PCB Table 7. Bill of Materials Item J1, J2 J3 TP1, TP2 C1, C3 C6 C7 R1 to R11 R12 to R25 SW1, SW2 U1 PCB 3 Value 1 100 pF 10 F 1000 pF 0 100 k Description PCB mount SMA connector 18-pin dc connector Through hole mount test point Capacitor, 0402 package Capacitor, 0603 package Capacitor, 0402 package Resistor, 0402 package Resistor, 0402 package SPDT four-position DIP switch HMC1119 digital attenuator 600-01280-00-1 evaluation PCB Manufacturer 2 Analog Devices, Inc. EV2HMC1119LP4M 4 from Analog Devices Blank cells in the Value column indicate that there is no specific value recommendation for the listed component. Blank cells in the Manufacturer column indicate that there is no specific manufacturer recommendation for the listed component. 3 Circuit board material is Arlon 25FR. 4 Reference this number when ordering the full evaluation PCB. See the Ordering Guide section. 1 2 Rev. C | Page 13 of 15 HMC1119 Data Sheet 12962-027 Figure 26. Applications Circuit Rev. C | Page 14 of 15 Data Sheet HMC1119 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 1 18 0.50 BSC 2.85 2.70 SQ 2.55 EXPOSED PAD 13 0.50 0.40 0.30 TOP VIEW 0.95 0.85 0.75 SIDE VIEW 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. PKG-04940 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 12-08-2017-C PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 27. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.85 mm Package Height (HCP-24-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 HMC1119LP4ME HMC1119LP4METR EV2HMC1119LP4M 1 2 Temperature Range -40C to +85C -40C to +85C MSL Rating 2 MSL3 MSL3 Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board All models are RoHS compliant. See the Absolute Maximum Ratings section. (c)2016-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12962-0-4/18(C) Rev. C | Page 15 of 15 Package Option HCP-24-3 HCP-24-3