PIC32MX360F512L-80I/PT - MICROCHIP

PIC32MX3XX/4XX

Data Sheet

High-Performance,

General Purpose and USB,

32-bit Flash Microcontrollers

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

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OTHERWISE, RELATED TO THE INFORMATION,

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suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Te chnology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-149-0

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in Calif ornia

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microper ipher als, nonvol ati le memo ry and

analog product s. In addition, Microchip ’s quality system for th e design

and manufacture of development systems is ISO 9001:2000 certified.

PIC32MX3XX/4XX

High-Performance 32-bit RISC CPU:

•MIPS32

® M4K® 32-bit core w ith 5-st ag e pipeline

• 80 MHz maximum frequency

• 1.56 DMIPS/MHz (Dhrystone 2.1) performance at

0 wait state Flash access

• Single-cycle multiply and high-performance divide

unit

• MIPS16e® mode for up to 40% smaller code size

• T wo sets of 32 core register files (32-bit) to reduce

interrupt latency

• Prefetch Cache module to speed executio n from

Flash

Microcontroller Features:

• Operating temperature range of -40ºC to +105ºC

• Operating voltage range of 2.3V to 3.6V

• 32K to 512K Flash memory (plus an additional

12 KB of boot Flash)

• 8K to 32K SRAM memory

• Pin-compatible with most PIC24/dsPIC® DSC

devices

• Multiple power management mode s

• Multiple interrupt vectors with individually

programmable priority

• Fail-Safe Clock Monitor Mode

• Configurable Watchdog Timer with on-chip

Low-Power RC Oscillator for reliable operation

Peripheral Features:

• Atomic SET, CLEAR and INVERT operation on

select peripheral registers

• Up to 4-channel hardware DMA with automatic

data size detection

• USB 2.0-compliant full-speed device and

On-The-Go (OTG) controller

• USB has a dedicated DMA cha nnel

• 3 MHz to 25 MHz crystal oscillator

• Internal 8 MHz and 32 kHz oscillators

• Separate PLLs for CPU and USB clocks

•Two I

2C™ modules

• Two UART modules with:

- RS-232, RS-485 and LIN support

-IrDA

® with on-chip hardware encoder and

decoder

• Up to two SPI modules

• Parallel Master and Slave Port (PMP/PSP) with

8-bit and 16-bit data and up to 16 address lines

• Hardware Real-Time Clock and Calendar (RTCC)

• Five 16-bit Timers/Counters (two 16-bit pairs

combine to create two 32-bit timers)

• Five capture inputs

• Five compare/PWM outputs

• Five external interrupt pins

• High-Speed I/O pins capable of toggling at up to

80 MHz

• High-current sink/source (18 mA/18 mA) on all I/O

pins

• Configurable open-drain output on digital I/O pins

Debug Features:

• Two programming and debugging Interfaces:

- 2-wire interface wi th un intrusiv e access and

real-time data exchange with application

- 4-wire MIPS® standard enhanced JTAG

interface

• Unintrusive hardware-base d instruction trace

• IEEE Standard 1149.2-compatible (JTAG)

boundary scan

Analog Features:

• Up to 16-channel 10-bit Analog-to-Digital

Converter:

- 1000 ksps conversion rate

- Conversion available during Sleep, Idle

• Two Analog Comparators

High-Performance, General Purpose and USB 32-bit

Flash Microcontrollers

PIC32MX3XX/4XX

TABLE 1: PIC32MX GENERAL PURPOSE – FEATURES

GENERAL PURPOSE

Device

Pins

Packages(2)

MHz

Program Memory (KB)

Data Memory (KB)

Timers/Capture/Compare

Programmable DMA

Channels

VREG

Trace

EUART/SPI/I2C™

10-bit ADC (ch)

Comparators

PMP/PSP

JTAG

PIC32MX320F032H 64 PT, MR 40 32 + 12(1) 8 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes

PIC32MX320F064H 64 PT, MR 80 64 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes

PIC32MX320F128H 64 PT, MR 80 128 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes

PIC32MX340F128H 64 PT, MR 80 128 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes

PIC32MX340F256H 64 PT, MR 80 256 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes

PIC32MX340F512H 64 PT, MR 80 512 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes

PIC32MX320F128L 100 PT 80 128 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes

121 BG

PIC32MX340F128L 100 PT 80 128 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes

121 BG

PIC32MX360F256L 100 PT 80 256 + 12(1) 32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes

121 BG

PIC32MX360F512L 100 PT 80 512 + 12(1) 32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes

121 BG

Legend: PT = TQFP MR = QFN BG = XBGA

Note 1: This device features 12 KB Boot Flash memory.

2: See Legend for an explanation of the acronyms. See Section 30.0 “Packaging Information” for details.

PIC32MX3XX/4XX

TABLE 2: PIC32MX USB – FEATURES

USB

Device

Pins

Packages(2)

MHz

Program Memory (KB)

Data Memory (KB)

Timers/Capture/Compare

Programmable DMA

Channels

Dedicated USB DMA

Channels

VREG

Trace

EUART/SPI/I2C™

10-bit ADC (ch)

Comparators

PMP/PSP

JTAG

PIC32MX420F032H 64 PT, MR 40 32 + 12(1) 8 5/5/5 0 2 Yes No 2/1/2 16 2 Yes Yes

PIC32MX440F128H 64 PT, MR 80 128 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes

PIC32MX440F256H 64 PT, MR 80 256 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes

PIC32MX440F512H 64 PT, MR 80 512 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes

PIC32MX440F128L 100 PT 80 128 + 12(1) 32 5/5/5 4 2 Yes No 2/2/2 16 2 Yes Yes

121 BG

PIC32MX460F256L 100 PT 80 256 + 12(1) 32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes

121 BG

PIC32MX460F512L 100 PT 80 512 + 12(1) 32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes

121 BG

Legend: PT = TQFP MR = QFN BG = XBGA

Note 1: This device features 12 KB Boot Flash memory.

2: See Legend for an explanation of the acronyms. See Section 30.0 “Packaging Information” for details.

PIC32MX3XX/4XX

Pin Diagrams

64-Pin QFN (General Purpo s e)

64 63 62 61 60 59 58 57 56 55

22 23 24 25 26 27 28 29 30 31

17 18 19 20 21

53 52 51 50 49

PIC32MX320F032H

= Pins are up to 5V tol e ran t

Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to

VSS externally.

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

VCAP/VCORE

PMD0/RE0

RF1

CN16/RD7

ENVREG

PMD5/RE5

PMD6/RE6

PMD7/RE7

SCK2/PMA5/CN8/RG6

VDD

AN5/C1IN+/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/SS1/CN4/RB2

SDI2/PMA4/CN9/RG7

SDO2/PMA3/CN10/RG8

PGEC1/AN1/VREF-/CVREF-/CN3/RB1

PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0

SS2/PMA2/CN11/RG9

MCLR

VSS

SOSCI/CN1/RC13

OC1/RD0

IC3/PMCS2/PMA15/INT3/RD10

U1CTS/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

SCL1/RG2

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

SDA1/RG3

SOSCO/T1CK/CN0/RC14

Vss

AVDD

AN8/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CVREFOUT/PMA13/RB10

TDO/AN11/PMA12/RB11

VDD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL2/U2TX/PMA8/CN18/RF5

SDA2/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/U2RTS/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

VSS

AVSS

PIC32MX320F064H

PIC32MX320F128H

PIC32MX340F128H

PIC32MX340F256H

PIC32MX340F512H

PIC32MX3XX/4XX

Pin Diagrams (Continued)

18 64

64-Pin TQFP (General Purpose) = Pins are up to 5V tolerant

PIC32MX320F032H

PIC32MX320F064H

PIC32MX320F128H

PIC32MX340F128H

PIC32MX340F256H

PIC32MX340F512H

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

OC4/RD3

OC3/RD2

OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

VCAP/VCORE

PMD0/RE0

RF1

CN16/RD7

ENVREG

PMD5/RE5

PMD6/RE6

PMD7/RE7

SCK2/PMA5/CN8/RG6

VDD

AN5/C1IN+/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/SS1/CN4/RB2

SDI2/PMA4/CN9/RG7

SDO2/PMA3/CN10/RG8

PGEC1/AN1/VREF-/CVREF-/CN3/RB1

PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0

SS2/PMA2/CN11/RG9

MCLR

VSS

SOSCI/CN1/RC13

OC1/RD0

IC3/PMCS2/PMA15/INT3/RD10

U1CTS/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

SCL1/RG2

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

SDA1/RG3

SOSCO/T1CK/CN0/RC14

Vss

AVDD

AN8/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CVREFOUT/PMA13/RB10

TDO/AN11/PMA12/RB11

VDD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL2/U2TX/PMA8/CN18/RF5

SDA2/U2RX/PMA9/CN17/RF4

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/U2RTS/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

VSS

AVSS

PIC32MX3XX/4XX

Pin Diagrams (Continued)

100

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

PMD13/CN19/RD13

IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

PMD11/RF0

SOSCI/CN1/RC13

OC1/RD0

IC3/PMCS2/PMA15/RD10

IC2/RD9

RTCC/IC1/RD8

IC4/PMCS1/PMA14/RD11

INT4/RA15

INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS

SOSCO/T1CK/CN0/RC14

VREF+/CVREF+/PMA6/RA10

VREF-/CVREF-/PMA7/RA9

AVDD

AVSS

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CVREFOUT/PMA13/RB10

AN11/PMA12/RB11

VDD

U2CTS/RF12

U2RTS/RF13

U1CTS/CN20/RD14

U1RTS/CN21/RD15

VDD

VSS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

U2TX/PMA8/CN18/RF5

U2RX/PMA9/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/RC4

SCK2/PMA5/CN8/RG6

VDD

TMS/RA0

INT1/RE8

INT2/RE9

AN5/C1IN+/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/SS1/CN4/RB2

SDI2/PMA4/CN9/RG7

SDO2/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1

PGED1/AN0/CN2/RB0

VDD

RG15

PMA2/SS2/CN11/RG9

MCLR

AN12/PMA11/RB12

AN13/PMA10/RB13

AN14/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

PMD9/RG1

PMD10/RF1

ENVREG

PMD14/CN15/RD6

TDO/RA5

SDA2/RA3

SCL2/RA2

VSS

VCAP/VCORE

TDI/RA4

TCK/RA1

100-Pin TQFP (General Purpose)

PMD15/CN16/RD7

= Pins are up to 5V tolerant

PIC32MX320F128L

PIC32MX340F128L

PIC32MX360F256L

PIC32MX360F512L

PIC32MX3XX/4XX

Pin Diagrams (Continued)

121-Pin XBGA(1)

1234567891011

ARE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1

BNC RG15 RE2 RE1 RA7 RF0 VCORE/

VCAP RD5 RD3 VSS RC14

CRE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11

DRC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10

ERC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14

FMCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15

GRE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4

HRB5 RB4 VSS VDD NC VDD NC RF7 RF6 RG2 RA2

JRB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3

KRB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2

LRB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5

PIC32MX320F128L

Note 1: Refer to Table 3 for full pin names.

= Pins are up to 5V tolerant

PIC32MX340F128L

PIC32MX360F256L

PIC32MX360F512L

PIC32MX3XX/4XX

TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND

PIC32MX360F512L DEVICES

Number Full Pin Name Pin

Number Full Pin Name

A1 PMD4/RE4 E8 INT4/RA15

A2 PMD3/RE3 E9 RTCC/IC1/RD8

A3 TRD0/RG13 E10 IC2/RD9

A4 PMD0/RE0 E11 INT3/RA14

A5 PMD8/RG0 F1 MCLR

A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8

A7 ENVREG F3 SS2/PMA2/CN11/RG9

A8 VSS F4 SDI2/PMA4/CN9/RG7

A9 IC5/PMD12/RD12 F5 VSS

A10 OC3/RD2 F6 No Connect (NC)

A11 OC2/RD1 F7 No Connect (NC)

B1 No Connect (NC) F8 VDD

B2 RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 INT1/RE8

B6 PMD11/RF0 G2 INT2/RE9

B7 VCAP/VCORE G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 VDD

B10 VSS G6 VSS

B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 TDI/RA4

C5 TRCLK/RA6 H1 AN5/C1IN+/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC)

C10 SOSCI/CN1/RC13 H6 VDD

C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 SDI1/RF7

D2 PMD7/RE7 H9 SCK1/INT0/RF6

D3 PMD5/RE5 H10 SCL1/RG2

D4 VSS H11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/RB3

D6 No Connect (NC) J2 AN2/C2IN-/SS1/CN4/RB2

D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 PMD13/CN19/RD13 J4 AVDD

D9 OC1/RD0 J5 AN11/PMA12/RB11

D10 No Connect (NC) J6 T CK/RA1

D11 IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12

E1 T5CK/RC4 J8 No Connect (NC)

E2 T4CK/RC3 J9 No Connect (NC)

E3 SCK2/PMA5/CN8/RG6 J10 SDO1/RF8

E4 T3CK/RC2 J11 SDA1/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/PMA6/RA10

PIC32MX3XX/4XX

K4 AN8/C1OUT/RB8 L3 AVSS

K5 No Connect (NC) L4 AN9/C2OUT/RB9

K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13

K8 VDD L7 AN13/PMA10/RB13

K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15

K10 U1TX/RF3 L9 CN20/U1CTS/RD14

K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 U2TX/PMA8/CN18/RF5

L2 VREF-/CVREF-/PMA7/RA9

TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND

PIC32MX360F512L DEVICES (CONTINUED)

Number Full Pin Name Pin

Number Full Pin Name

PIC32MX3XX/4XX

Pin Diagrams (Continued)

64-Pin QFN (USB) = Pins are up to 5V tolerant

Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to

VSS externally.

PIC32MX420F032H

646362 61 6059 58 57 56 55

222324 25 26 27 28 29 30 31

171819 20 21

53 52 515049

PIC32MX440F128H

PIC32MX440F256H

PIC32MX440F512H

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

U1TX/OC4/RD3

U1RX/OC3/RD2

U1RTS/OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

VCAP/VCORE

SOSCI/CN1/RC13

OC1/INT0/RD0

SCL1/IC3/PMCS2/PMA15/INT3/RD10

U1CTS/SDA1/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

AVDD

AN8/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CVREFOUT/PMA13/RB10

TDO/AN11/PMA12//RB11

VDD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL2/U2TX/PMA8/CN18/RF5

SDA2/U2RX/PMA9/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

SCK2/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDI2/PMA4/CN9/RG7

SDO2/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/PMA2/CN11/RG9

MCLR

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/U2RTS/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

PMD0/RE0

RF1

CN16/RD7

VSS

Vss

ENVREG

AVSS

PIC32MX3XX/4XX

Pin Diagrams (Continued)

64-Pin TQFP (USB)

CN15/RD6

PMRD/CN14/RD5

OC5/IC5/PMWR/CN13/RD4

U1TX/OC4/RD3

U1RX/OC3/RD2

U1RTS/OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

VCAP/VCORE

SOSCI/CN1/RC13

OC1/INT0/RD0

SCL1/IC3/PMCS2/PMA15/INT3/RD10

U1CTS/SDA1/IC2/INT2/RD9

RTCC/IC1/INT1/RD8

IC4/PMCS1/PMA14/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

D+/RG2

USB

BUS

USBID/RF3

D-/RG3

SOSCO/T1CK/CN0/RC14

AVDD

AN8/U2CTS/C1OUT/RB8

AN9/C2OUT/PMA7/RB9

TMS/AN10/CVREFOUT/PMA13/RB10

TDO/AN11/PMA12//RB11

VDD

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

SCL2/U2TX/PMA8/CN18/RF5

SDA2/U2RX/PMA9/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

SCK2/PMA5/CN8/RG6

AN5/C1IN+/V

BUSON

/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDI2/PMA4/CN9/RG7

SDO2/PMA3/CN10/RG8

PGEC1/AN1/V

REF

-/CV

REF

-/CN3/RB1

PGED1/AN0/V

REF

+/CV

REF

+/PMA6/CN2/RB0

SS2/PMA2/CN11/RG9

MCLR

TCK/AN12/PMA11/RB12

TDI/AN13/PMA10/RB13

AN14/U2RTS/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

PMD0/RE0

RF1

CN16/RD7

VSS

Vss

ENVREG

AVSS

18 64

PIC32MX420F032H

PIC32MX440F128H

PIC32MX440F256H

PIC32MX440F512H

= Pins are up to 5V tolerant

PIC32MX3XX/4XX

Pin Diagrams (Continued)

PMRD/CN14/RD5

OC5/PMWR/CN13/RD4

PMD13/CN19/RD13

IC5/PMD12/RD12

OC4/RD3

OC3/RD2

OC2/RD1

TRD3/RA7

TRCLK/RA6

PMD2/RE2

TRD0/RG13

TRD1/RG12

TRD2/RG14

PMD1/RE1

PMD0/RE0

PMD8/RG0

PMD4/RE4

PMD3/RE3

PMD11/RF0

SOSCI/CN1/RC13

SDO1/OC1/INT0/RD0

SCK1/IC3/PMCS2/PMA15/RD10

SS1/IC2/RD9

RTCC/IC1/RD8

IC4/PMCS1/PMA14/RD11

SDA1/INT4/RA15

SCL1/INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

D+/RG2

VUSB

VBUS

U1TX/RF8

D-/RG3

U1RX/RF2

USBID/RF3

VSS

SOSCO/T1CK/CN0/RC14

VREF+/CVREF+/PMA6/RA10

VREF-/CVREF-/PMA7/RA9

AVDD

AVSS

AN8/C1OUT/RB8

AN9/C2OUT/RB9

AN10/CVREFOUT/PMA13/RB10

AN11/PMA12/RB11

VDD

U2CTS/RF12

U2RTS/RF13

U1CTS/CN20/RD14

U1RTS/CN21/RD15

VDD

VSS

PGEC2/AN6/OCFA/RB6

PGED2/AN7/RB7

U2TX/PMA8/CN18/RF5

U2RX/PMA9/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/SDI1/RC4

SCK2/PMA5/CN8/RG6

VDD

TMS/RA0

INT1/RE8

INT2/RE9

AN5/C1IN+/VBUSON/CN7/RB5

AN4/C1IN-/CN6/RB4

AN3/C2IN+/CN5/RB3

AN2/C2IN-/CN4/RB2

SDI2/PMA4/CN9/RG7

SDO2/PMA3/CN10/RG8

PGEC1/AN1/CN3/RB1

PGED1/AN0/CN2/RB0

VDD

RG15

SS2/PMA2/CN11/RG9

MCLR

AN12/PMA11/RB12

AN13/PMA10/RB13

AN14/PMALH/PMA1/RB14

AN15/OCFB/PMALL/PMA0/CN12/RB15

PMD9/RG1

PMD10/RF1

ENVREG

PMD14/CN15/RD6

TDO/RA5

SDA2/RA3

SCL2/RA2

VSS

VCAP/VCORE

TDI/RA4

TCK/RA1

100-Pin TQFP (USB)

PMD15/CN16/RD7

100

PIC32MX440F128L

PIC32MX460F256L

PIC32MX460F512L

= Pins are up to 5V tol er an t

PIC32MX3XX/4XX

Pin Diagrams (Continued)

121-Pin XBGA(1)

1234567891011

ARE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1

BNC RG15 RE2 RE1 RA7 RF0 VCORE/

VCAP RD5 RD3 VSS RC14

CRE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11

DRC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10

ERC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14

FMCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15

GRE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4

HRB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2

JRB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3

KRB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2

LRB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5

Note 1: Refer to Table 4 for full pin names.

= Pins are up to 5V tolerant

PIC32MX440F128L

PIC32MX460F256L

PIC32MX460F512L

PIC32MX3XX/4XX

TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L

DEVICES

Number Full Pin Name Pin

Number Full Pin Name

A1 PMD4/RE4 E8 SDA1/INT4/RA15

A2 PMD3/RE3 E9 RTCC/IC1/RD8

A3 TRD0/RG13 E10 SS1/IC2/RD9

A4 PMD0/RE0 E11 SCL1/INT3/RA14

A5 PMD8/RG0 F1 MCLR

A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8

A7 ENVREG F3 SS2/PMA2/CN11/RG9

A8 VSS F4 SDI2/PMA4/CN9/RG7

A9 IC5/PMD12/RD12 F5 VSS

A10 OC3/RD2 F6 No Connect (NC)

A11 OC2/RD1 F7 No Connect (NC)

B1 No Connect (NC) F8 Vdd

B2 RG15 F9 OSC1/CLKI/RC12

B3 PMD2/RE2 F10 VSS

B4 PMD1/RE1 F11 OSC2/CLKO/RC15

B5 TRD3/RA7 G1 INT1/RE8

B6 PMD11/RF0 G2 INT2/RE9

B7 VCAP/VCORE G3 TMS/RA0

B8 PMRD/CN14/RD5 G4 No Connect (NC)

B9 OC4/RD3 G5 VDD

B10 VSS G6 VSS

B11 SOSCO/T1CK/CN0/RC14 G7 VSS

C1 PMD6/RE6 G8 No Connect (NC)

C2 VDD G9 TDO/RA5

C3 TRD1/RG12 G10 SDA2/RA3

C4 TRD2/RG14 G11 TDI/RA4

C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5

C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4

C7 PMD15/CN16/RD7 H3 VSS

C8 OC5/PMWR/CN13/RD4 H4 VDD

C9 VDD H5 No Connect (NC)

C10 SOSCI/CN1/RC13 H6 VDD

C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC)

D1 T2CK/RC1 H8 VBUS

D2 PMD7/RE7 H9 VUSB

D3 PMD5/RE5 H10 D+/RG2

D4 VSS H11 SCL2/RA2

D5 VSS J1 AN3/C2IN+/CN5/RB3

D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2

D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7

D8 CN19/PMD13/RD13 J4 AVDD

D9 SDO1/OC1/INT0/RD0 J5 AN11/PMA12/RB11

D10 No Connect (NC) J6 T CK/RA1

D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12

E1 T5CK/SDI1/RC4 J8 No Connect (NC)

E2 T4CK/RC3 J9 No Connect (NC)

E3 SCK2/PMA5/CN8/RG6 J10 U1TX/RF8

E4 T3CK/RC2 J11 D-/RG3

E5 VDD K1 PGEC1/AN1/CN3/RB1

E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0

E7 VSS K3 VREF+/CVREF+/PMA6/RA10

PIC32MX3XX/4XX

K4 AN8/C1OUT/RB8 L3 AVSS

K5 No Connect (NC) L4 AN9/C2OUT/RB9

K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10

K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13

K8 VDD L7 AN13/PMA10/RB13

K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15

K10 USBID/RF3 L9 U1CTS/CN20/RD14

K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4

L1 PGEC2/AN6/OCFA/RB6 L11 U2TX/PMA8/CN18/RF5

L2 VREF-/CVREF-/PMA7/RA9

TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L

DEVICES (CONTINUED)

Number Full Pin Name Pin

Number Full Pin Name

PIC32MX3XX/4XX

Table of Content s

1.0 Device Overview ........................................................................................................................................................................ 21

2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 31

3.0 CPU............................................................................................................................................................................................ 37

4.0 Memory Organization................................................................................................................................................................. 43

5.0 Flash Program Memory.............................................................................................................................................................. 85

6.0 Resets ........................................................................................................................................................................................ 87

7.0 Interrupt Controller ......................................................................... ............................................................................................ 89

8.0 Oscillator Configuration..................................................................................................................................................... ......... 93

9.0 Prefetch Cache........................................................................................................................................................................... 95

10.0 Direct Memory Access (DMA) Controller .................................................................................................................................. 97

11.0 USB On-The-Go (OTG).............................................................................................................................................................. 99

12.0 I/O Ports ................................................................................................................................................................................... 101

13.0 Timer1 ...................................................................................................................................................................................... 103

14.0 Timer2/3 and Timer4/5............................................................................................................................................................ 105

15.0 Input Capture............................................................................................................................................................................ 107

16.0 Output Compare....................................................................................................................................................................... 109

17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 111

18.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 113

19.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 115

20.0 Parallel Master Port (PMP) ...................................................................................................................................................... 119

21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 121

22.0 10-bit Analog-to-Digital Converter (ADC)................................................................................................................................. 123

23.0 Comparator .............................................................................................................................................................................. 125

24.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 127

25.0 Power-Saving Features ...................................................................................... ..................................................................... 129

26.0 Special Features ...................................................................................................................................................................... 131

27.0 Instruction Set ........................................................... ............................................................................................................... 141

28.0 Development Support............................................................................................................................................................... 147

29.0 Electrical Characteristics.......................................................................................................................................................... 151

30.0 Packaging Information.............................................................................................................................................................. 191

Index ................................................................................................................................................................................................. 209

PIC32MX3XX/4XX

TO OUR VALUED CUSTOMERS

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welcome your feedback.

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Customer Notific atio n Syste m

PIC32MX3XX/4XX

NOTES:

PIC32MX3XX/4XX

1.0 DEVICE OVERVIEW This document contains device-specific information for

the PIC32MX3XX/4XX devices.

Figure 1-1 illustrates a general block d iagram of the core

and peripheral modules in the PIC32MX3XX/4XX family

of devices.

Table 1-1 lists the functions of the various pins shown

in the pinout diagrams.

FIGURE 1-1: BLOCK DIAGRAM(1,2)

Note 1: This data sheet summarizes the features

of the PIC32MX3XX/4XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note 1: Some features are not available on all device variants.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

UART1,2

Comparators

PORTA

PORTD

PORTE

PORTF

PORTG

PORTB

CN1-22

JTAG

Priority

DMAC ICD

MIPS32® M4K® CPU Core

IS DS

EJTAG INT

Bus Matrix

Prefetch Data RAM Peripheral Bridge

128

128-bit wide Flash

32 32 32 32

Peripheral Bus Clocked by PBCLK

Program Flash

Memory

Controller

Module

32 32

Interrupt

Controller

BSCAN

PORTC

PMP

I2C1,2

SPI1,2

IC1-5

PWM

OC1-5

OSC1/CLKI

OSC2/CLKO VDD,

Timing

Generation

VSS

MCLR

Power-up

Timer

Oscillator

Star t-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators Regulator

Voltage

VCORE/VCAP

ENVREG

OSC/SOSC

Oscillators

PLL

DIVIDERS

SYSCLK

PBCLK

Peripheral Bus Clocked by SYSCLK

USB

PLL-USB USBCLK

RTCC

10-bit ADC

Timer1-5

PIC32MX3XX/4XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

AN0 16 25 K2 I Analog Analog input channels.

AN1 15 24 K1 I Analog

AN2 14 23 J2 I Analog

AN3 13 22 J1 I Analog

AN4 12 21 H2 I Analog

AN5 11 20 H1 I Analog

AN6 17 26 L1 I Analog

AN7 18 27 J3 I Analog

AN8 21 32 K4 I Analog

AN9 22 33 L4 I Analog

AN10 23 34 L5 I Analog

AN11 24 35 J5 I Analog

AN12 27 41 J7 I Analog

AN13 28 42 L7 I Analog

AN14 29 43 K7 I Analog

AN15 30 44 L8 I Analog

CLKI 39 63 F9 I ST/CMOS External clock source input. Always associated with

OSC1 pin function.

CLKO 40 64 F11 O — Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode. Optionally

functions as CLKO in RC and EC modes. Always

associated with OSC2 pin function.

OSC1 39 63 F9 I ST/CMOS Oscillator crystal input. ST buffer when configured in

RC mode; CMOS otherwise.

OSC2 40 64 F11 I/O — Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode. Optionally

functions as CLKO in RC and EC modes.

SOSCI 47 73 C10 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS

otherwise.

SOSCO 48 74 B11 O — 32.768 kHz low-power oscil lator crystal output.

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt T rigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availab ility.

PIC32MX3XX/4XX

CN0 48 74 B11 I ST Chan ge notification inputs.

Can be software programmed for internal weak

pull-ups on all inputs.

CN1 47 73 C10 I ST

CN2 16 25 K2 I ST

CN3 15 24 K1 I ST

CN4 14 23 J2 I ST

CN5 13 22 J1 I ST

CN6 12 21 H2 I ST

CN7 11 20 H1 I ST

CN8 4 10 E3 I ST

CN9 5 11 F4 I ST

CN10 6 12 F2 I ST

CN11 8 14 F3 I ST

CN12 30 44 L8 I ST

CN13 52 81 C8 I ST

CN14 53 82 B8 I ST

CN15 54 83 D7 I ST

CN16 55 84 C7 I ST

CN17 31 49 L10 I ST

CN18 32 50 L11 I ST

CN19 — 80 D8 I ST

CN20 — 47 L9 I ST

CN21 — 48 K9 I ST

IC1 42 68 E9 I ST Capture inputs 1-5.

IC2 43 69 E10 I ST

IC3 44 70 D11 I ST

IC4 45 71 C11 I ST

IC5 52 79 A9 I ST

OCFA 17 26 L1 I ST Output Compare Fault A Input.

OC1 46 72 D9 O — Outp ut Co mpare ou tp ut 1.

OC2 49 76 A11 O — Output Compare outp u t 2

OC3 50 77 A10 O — Output Comp are output 3.

OC4 51 78 B9 O — Output Comp are output 4.

OC5 52 81 C8 O — Outp ut Co mpare ou tp ut 5.

OCFB 30 44 L8 I ST Output Compare Fault B Input.

INT0 35,46 55,72 H9,D9 I ST External interrupt 0.

INT1 42 18 61 I ST External interrupt 1.

INT2 43 19 62 I ST External interrupt 2.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

PIC32MX3XX/4XX

INT3 44 66 E11 I ST External interrupt 3.

INT4 45 67 E8 I ST External interrupt 4.

RA0 — 17 G3 I/O ST PORTA is a bidirectional I/O port.

RA1 — 38 J6 I/O ST

RA2 — 58 H11 I/O ST

RA3 — 59 G10 I/O ST

RA4 — 60 G11 I/O ST

RA5 — 61 G9 I/O ST

RA6 — 91 C5 I/O ST

RA7 — 92 B5 I/O ST

RA9 — 28 L2 I/O ST

RA10 — 29 K3 I/O ST

RA14 — 66 E11 I/O ST

RA15 — 67 E8 I/O ST

RB0 16 25 K2 I/O ST PORTB is a bidirectional I/O port.

RB1 15 24 K1 I/O ST

RB2 14 23 J2 I/O ST

RB3 13 22 J1 I/O ST

RB4 12 21 H2 I/O ST

RB5 11 20 H1 I/O ST

RB6 17 26 L1 I/O ST

RB7 18 27 J3 I/O ST

RB8 21 32 K4 I/O ST

RB9 22 33 L4 I/O ST

RB10 23 34 L5 I/O ST

RB11 24 35 J5 I/O ST

RB12 27 41 J7 I/O ST

RB13 28 42 L7 I/O ST

RB14 29 43 K7 I/O ST

RB15 30 44 L8 I/O ST

RC1 — 6 D1 I/O ST PORTC is a bidirectional I/O port.

RC2 — 7 E4 I/O ST

RC3 — 8 E2 I/O ST

RC4 — 9 E1 I/O ST

RC12 39 63 F9 I/O ST

RC13 47 73 C10 I/O ST

RC14 48 74 B11 I/O ST

RC15 40 64 F11 I/O ST

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt T rigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availab ility.

PIC32MX3XX/4XX

RD0 46 72 D9 I/O ST PORTD is a bidirectional I/O port.

RD1 49 76 A11 I/O ST

RD2 50 77 A10 I/O ST

RD3 51 78 B9 I/O ST

RD4 52 81 C8 I/O ST

RD5 53 82 B8 I/O ST

RD6 54 83 D7 I/O ST

RD7 55 84 C7 I/O ST

RD8 42 68 E9 I/O ST

RD9 43 69 E10 I/O ST

RD10 44 70 D11 I/O ST

RD11 45 71 C11 I/O ST

RD12 — 79 A9 I/O ST

RD13 — 80 D8 I/O ST

RD14 — 47 L9 I/O ST

RD15 — 48 K9 I/O ST

RE0 60 93 A4 I/O ST PORTE is a bidirectional I/O port.

RE1 61 94 B4 I/O ST

RE2 62 98 B3 I/O ST

RE3 63 99 A2 I/O ST

RE4 64 100 A1 I/O ST

RE5 1 3 D3 I/O ST

RE6 2 4 C1 I/O ST

RE7 3 5 D2 I/O ST

RE8 — 18 G1 I/O ST

RE9 — 19 G2 I/O ST

RF0 58 87 B6 I/O ST PORTF is a bidirectional I/O port.

RF1 59 88 A6 I/O ST

RF2 34 52 K11 I/O ST

RF3 33 51 K10 I/O ST

RF4 31 49 L10 I/O ST

RF5 32 50 L11 I/O ST

RF6 35 55 H9 I/O ST

RF7 — 54 H8 I/O ST

RF8 — 53 J10 I/O ST

RF12 — 40 K6 I/O ST

RF13 — 39 L6 I/O ST

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

PIC32MX3XX/4XX

RG0 — 90 A5 I/O ST PORTG is a bidirectional I/O port.

RG1 — 89 E6 I/O ST

RG6 4 10 E3 I/O ST

RG7 5 11 F4 I/O ST

RG8 6 12 F2 I/O ST

RG9 8 14 F3 I/O ST

RG12 — 96 C3 I/O ST

RG13 — 97 A3 I/O ST

RG14 — 95 C4 I/O ST

RG15 — 1 B2 I/O ST

RG2 37 57 H10 I ST PORTG input pins.

RG3 36 56 J11 I ST

T1CK 48 74 B11 I ST Timer1 external clock input.

T2CK — 6 D1 I ST Timer2 external clock input.

T3CK — 7 E4 I ST Timer3 external clock input.

T4CK — 8 E2 I ST Timer4 external clock input.

T5CK — 9 E1 I ST Timer5 external clock input.

U1CTS 43 47 L9 I ST UART1 clear to send.

U1RTS 35, 49 48 K9 O — UART1 ready to send.

U1RX 34, 50 52 K11 I ST UART1 receive.

U1TX 33, 51 51, 53 J10, K10 O — UART1 transmit.

U2CTS 21 40 K6 I ST UART2 clear to send.

U2RTS 29 39 L6 O — UAR T2 ready to send.

U2RX 31 49 L10 I ST UART2 receive.

U2TX 32 50 L11 O — UART2 trans mit.

SCK1 35 55, 70 D11, H9 I/O ST Synchronous serial clock input/output for SPI1.

SDI1 34 9, 54 E1, H8 I ST SPI1 data in.

SDO1 33 53, 72 D9, J10 O — SPI1 data out.

SS1 14 23, 69 E10, J2 I/O ST SPI1 slave synchronization or frame pulse I/O.

SCK2 4 10 E3 I/O ST Synchronous serial clock input/output for SPI2.

SDI2 5 11 F4 I ST SPI2 data in.

SDO2 6 12 F 2 O — SPI2 data out.

SS2 8 14 F3 I/O ST SPI2 slave synchronization or frame pulse I/O.

SCL1 37, 44 57, 66 E11, H10 I/O ST Synchronous serial clock input/output for I2C1.

SDA1 36, 43 56, 67 E8, J11 I/O ST Synchronous serial data input/output for I2C1.

SCL2 32 58 H11 I/O ST Synchronous serial clock inp ut/output for I2C2.

SDA2 31 59 G10 I/O ST Synchrono us serial data input/output for I2C2.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt T rigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availab ility.

PIC32MX3XX/4XX

TMS 23 17 G3 I ST JTAG Test mode select pin.

TCK 27 38 J6 I ST JTAG test clock input pin.

TDI 28 60 G11 I ST JTAG test data input pin.

TDO 24 61 G9 O — JTAG test data output pin.

RTCC 42 68 E9 O — Real-Time Clock Alarm Output.

CVREF- 15 28 L2 I Analog Comparator Voltage Reference (low).

CVREF+ 16 29 K3 I Analog Comparator Voltage Reference (high).

CVREFOUT 23 34 L5 O Analog Comparator Voltage Reference Output.

C1IN- 12 21 H2 I Analog Comparator 1 Negative Input.

C1IN+ 11 20 H1 I Analog Comparator 1 Positive Input.

C1OUT 21 32 K4 O — Comparator 1 Output.

C2IN- 14 23 J2 I Analog Comparator 2 Negative Input.

C2IN+ 13 22 J1 I Analog Comparator 2 Positive Input.

C2OUT 22 33 L4 O — Comparator 2 Output.

PMA0 30 44 L8 I/O TTL/ST Parallel Master Port Address Bit 0 Input (Buffered

Slave modes) and Output (Master modes).

PMA1 29 43 K7 I/O TTL/ST Parallel Master Port Address Bit 1 Input (Bu ffered

Slave modes) and Output (Master modes).

PMA2 8 14 F3 O — Parallel Master Port Address (De-multiplexed Master

Modes).

PMA3 6 12 F2 O —

PMA4 5 11 F4 O —

PMA5 4 10 E3 O —

PMA6 16 29 K3 O —

PMA7 22 28 L2 O —

PMA8 32 50 L11 O —

PMA9 31 49 L10 O —

PMA10 28 42 L7 O —

PMA11 27 41 J7 O —

PMA12 24 35 J5 O —

PMA13 23 34 L5 O —

PMA14 45 71 C11 O —

PMA15 44 70 D11 O —

PMCS1 45 71 C11 O — Parallel Master Port Chip Select 1 Strobe.

PMCS2 44 70 D11 O — Parallel Master Port Chip Select 2 Strobe.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

PIC32MX3XX/4XX

PMD0 60 93 A4 I/O TTL/ST Parallel Master Port Data (De-multiplexed Ma ster

mode) or Address/Data (Multiplexed Master modes).

PMD1 61 94 B4 I/O TTL/ST

PMD2 62 98 B3 I/O TTL/ST

PMD3 63 99 A2 I/O TTL/ST

PMD4 64 100 A1 I/O TTL/ST

PMD5 1 3 D3 I/O TTL/ST

PMD6 2 4 C1 I/O TTL/ST

PMD7 3 5 D2 I/O TTL/ST

PMD8 — 90 A5 I/O TTL/ST

PMD9 — 89 E6 I/O TTL/ST

PMD10 — 88 A6 I/O TTL/ST

PMD11 — 87 B6 I/O TTL/ST

PMD12 — 79 A9 I/O TTL/ST

PMD13 — 80 D8 I/O TTL/ST

PMD14 — 83 D7 I/O TTL/ST

PMD15 — 84 C7 I/O TTL/ST

PMRD 53 82 B8 O — Parallel Master Port Read Strobe.

PMWR 52 81 C8 O — Parallel Master Port Write Strob e.

PMALL 30 44 L8 O — Parallel Master Port Address Latch Enable low-byte

(Multiplexed Master modes).

PMALH 29 43 K7 O — Parallel Master Port Address Latch Enable high-byte

(Multiplexed Master modes).

VBUS 34 54 H8 I Analog USB Bus Power Monitor.

VUSB 35 55 H9 P — USB Internal Transceiver Supply. If the USB module

is not used, this pin must be connected to VDD.

VBUSON 11 20 H1 O — USB Host and OTG Bus Power Control Output.

D+ 37 57 H10 I/O Analog USB D+.

D- 36 56 J11 I/O Analog USB D-.

USBID 33 51 K10 I ST USB OTG ID Detect.

ENVREG 57 86 A7 I ST Enable for On-Chip Voltage Regulator.

TRCLK — 91 C5 O — Trace Clock.

TRD0 — 97 A3 O — T race Data Bits 0-3.

TRD1 — 96 C3 O —

TRD2 — 95 C4 O —

TRD3 — 92 B5 O —

PGED1 16 25 K2 I/O ST Data I/O pin for programming/debugging

communication channel 1.

PGEC1 15 24 K1 I ST Clock input pin for programmi ng/debugging

communication channel 1.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt T rigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availab ility.

PIC32MX3XX/4XX

PGED2 18 27 J3 I/O ST Data I/O pin for programming/debugging

communication channel 2.

PGEC2 17 26 L1 I ST Clock input pin for programming/debugging

communication channel 2.

MCLR 7 13 F 1 I/P ST Master Clear (Reset) input. This pin is an active-l ow

Reset to the device.

AVDD 19 30 J4 P P Positive supply for analog modules. This pin must be

connected at all times.

AVSS 20 31 L3 P P Ground reference for analog modules.

VDD 10, 26, 38 2, 16, 37,

46, 62 C2, C9,

E5, F8,

G5, H4,

H6, K8

P — Positive supply for peripheral logic and I/O pins.

VCORE/

VCAP 56 85 B7 P — Capacitor for Internal Voltage Regulator.

Vss 9, 25, 41 15, 36,

45, 65,

A8, B10,

D4, D5,

E7, F10,

F5, G6,

G7, H3

P — Ground reference for logic and I/O pins.

VREF+ 16 29 K3 I Analog Analog voltage refe re nce (high) in pu t.

VREF- 15 28 L2 I Analog Analog voltag e refe re nce (low) input .

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1) Pin

Type Buffer

Type Description

64-pin

QFN/TQFP 100-pin

TQFP 121-pin

XBGA

Legend: CMOS = CMOS compatible input or o utput Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

PIC32MX3XX/4XX

NOTES:

PIC32MX3XX/4XX

2.0 GUIDELINES FOR GETTING

STARTED WITH 32-BIT

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC32MX3XX/4XX family of

32-bit Microcontrollers (MCUs) requires attention to a

minimal set of device pin connections before

proceeding with development. Th e following is a list of

pin names, which must always be connected:

• All VDD and VSS pins

(see Section 2.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins (regardless if ADC module

is not used)

(see Section 2.2 “Decoupling Capacitors”)

•V

CAP/VCORE

(see Section 2.3 “Capacitor on Internal Voltage

Regulator (VCAP/VCORE)”)

•MCLR

(see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSC1 and OSC2 pins when external oscillator

source is used

(see Section 2.8 “External Oscillato r Pin s”)

Additionally, the following pins may be required:

•V

REF+/VREF- pins used when external voltage

reference for ADC module is implemented

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required. See Figure 2-1.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: Recommendation

of 0.1 µF (100 nF), 10-20V. This capacitor should

be a low-ESR and have resonance frequency in

the range of 20 MHz and higher. It is

recommended that ceramic capacitors be used.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is within

one-quarter inch (6 mm) in length.

•Handling high freque nc y nois e : If the board is

experiencing high frequency noise, upward of

tens of MHz, add a second ceramic-type capacitor

in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 µF to 0.001 µF. Place this

second capacitor next to the primary decoupling

capacitor. In high-spe ed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible.

For example, 0.1 µF in parallel with 0.001 µF.

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum thereby reducing PCB track inductance.

Note 1: This data sheet summarizes the features

of the PIC32MX3XX/4XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be avail-

able on all devices. Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

Note: The AVDD and AVSS pins must be

connected independent of ADC use and

ADC voltage reference source.

PIC32MX3XX/4XX

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECT I ON

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve

power supply stability . T ypical values range from 4.7 µF

to 47 µF. This capacitor should be located as close to

the device as possible.

2.3 Capacitor on Internal Voltage

Regulator (VCAP/VCORE)

2.3.1 INTERNAL REGULATOR MODE

A low-ESR (< 1 Ohm) capacitor is required on the

VCAP/VCORE pin, which is use d to stabilize the internal

voltage regulator output. The VCAP/VCORE pin must not

be connected to VDD, and must have a CEFC capacitor ,

with at least a 6V rating, connected to ground. The type

can be ceramic or tantalum. Refer to Section 29.0

“Electrical Characteristics” for additional information

on CEFC specifications. This mode is enabled by

connecting the ENVREG pin to VDD.

2.3.2 EXTERNA L REGULA TOR MODE

In this mode the core voltage is supplied externally

through the VCORE/VCAP pin. A low-ESR capacitor of

10 µF is recommended on the VCAP/VCORE pin. This

mode is enabled by grounding the ENVREG pin.

The placement of this capacitor should be close to th e

VCAP/VCORE. It is recommended that the trace length

not exceed one-quarter inch (6 mm). Refer to

Section 26.3 “On-Chip Voltage Regulator” for

details.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device

functions:

• Devic e Re set

• Device Programming and D ebugging

Pulling The MCLR pin low generates a device reset.

Figure 2-2 illustrates a typical MCLR circuit. During

device programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R and C will need to be adjusted based on the

application and PCB requirements.

For example, as illustrated in Figure 2-2, it is

recommended that the capacitor C, be isolated from

the MCLR pin during programming and debugging

operations.

Place the components shown in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

PIC32MX

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

VDD

MCLR

0.1 µF

Ceramic

VCAP/VCORE

10Ω

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

CEFC

Note 1: R≤ 10 kΩ is recommended. A suggested start-

ing value is 10 kΩ. Ensure that the MCLR pin

VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR from the external capacitor C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

3: The capacitor can be sized to prevent uninten-

tional resets from brief glitches or to extend the

device reset period during POR.

VDD

MCLR

PIC32MX

PIC32MX3XX/4XX

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming™ (ICSP™) and debugging pur-

poses. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on the

device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few

tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/d ebugger commu ni-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternately, refe r to the AC/DC charac teri sti cs and tim-

ing requirements information in the respective device

Flash programming specification for information on

capacitive loading limits and pin input voltage high (VIH)

and input low (VIL) requirements.

Ensure that the “Communication Ch annel Sele ct” (i.e .,

PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.

For more information on ICD 2, ICD 3 and REAL ICE

connection requirements, refer to the following

documents that are available on the Microchip web

site.

•“MPLAB® ICD 2 In-Circuit Debugger User’s

Guide” DS51331

•“Using MPLAB® ICD 2” (poster) DS51265

•“MPLAB® ICD 2 Design Advisory” DS51566

•“Using MPLAB® ICD 3” (poster) DS51765

•“MPLAB® ICD 3 Design Advisory” DS51764

•“MPLAB® REAL ICE™ In-Circuit Debugger

User’s Guide” DS51616

•“Using MPLAB® REAL ICE™” (poster) DS51749

2.6 JTAG

The TMS, TDO, TDI and TCK pins are used for testing

and debugging according to the Joint Test Action

Group (JT AG) standard. It is recommended to keep the

trace length between the JTAG connector and the

JTAG pins on the device as short as possible. If the

JTAG connector is expected to experience an ESD

event, a series resistor is recommended, with the value

in the range of a few tens of Ohms, not to exceed 100

Ohms.

Pull-up resistors, series diodes and capacitors on the

TMS, TDO, TDI and TCK pins are not recommended

as they will interfere with the programmer/debugger

communications to the device. If such discrete compo-

nents are an application requirement, they should be

removed from the circuit during programming and

debugging. Alternately , refer to the AC/DC characteris-

tics and timing requirements information in the respec-

tive device Flash programming specification for

information on capacitive loading limits and pin input

voltage high (VIH) and input low (VIL) requirements.

2.7 Trace

The trace pins can be conn ected to a hardware-trace-

enabled programmer to provide a compress real time

instruction trace. When used for trace the TRD3,

TRD2, TRD1, TRD0 and T RCLK pins should be dedi-

cated for this use. The trace hardware requires a 22

Ohm series resistor between the trace pins and the

trace connector.

2.8 External Oscillator Pins

Many MCUs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator (refer to Section 8.0 “Oscillator

Configuration” for details).

The oscillator circuit should be placed on the same

side of the board as the device. Also, place the

oscillator circuit close to the respective oscillato r pins,

not exceeding one-half inch (12 mm) distance

between them. The load capacitors should be placed

next to the oscillator itself, on the same side of the

board. Use a grounded copper pour around the

oscillator circuit to isolate them from surrounding

circuits. The grounded copper pour should be routed

directly to the MCU ground. Do not run any signal

traces or power traces inside the ground pour. Also, if

using a two-sided board, avoid any traces on the

other side of the board where the crystal is placed. A

suggested layout is illustrated in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

PIC32MX3XX/4XX

2.9 Configuration of Analog and

Digital Pins During ICSP

Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is sel ected as a

debugger, it automatically initializes all of the Analog-

to-Digital input pins (ANx) as “digital” pins by setting all

bits in the ADPCFG register.

The bits in this register that correspond to the Analog-

to-Digital pins that are initialized by MPLAB ICD 2, ICD

3 or REAL ICE, must not be cleared by the user

application firmware; o therwise, communication errors

will result between the debugger and the device.

If your application needs to use certain Analog-to-

Digital pins as analog input pins during the debug

session, the user application must clear the

corresponding bits in the ADPCFG register during

initialization of the ADC module.

When MPLAB ICD 2, ICD 3 or REAL ICE is used a s a

programmer, the user application firmware must

correctly configure the ADPCFG register. Automatic

initialization of this register is only done during

debugger operation. Failure to correctly configure the

recognized as analog input pins, resulting in the port

value being read as a logic ‘0’, which may affect user

application functionality.

2.10 Unused I/Os

Unused I/O pins should not be allowed to float as

inputs. They can be configured as outputs and driven

to a logic-low state.

Alternately, inputs can be reserved by connecting the

pin to VSS through a 1k to 10k resistor and configuring

the pin as an input.

PIC32MX3XX/4XX

2.11 Referenced Sources

This device data sheet is based on the following

individual chapters of the “PIC32 Family Reference

Manual”. These documents should be considered as

the general reference for the operation of a particular

module or device feature.

•Section 1. “Introduction” (DS61127)

•Section 2. “CPU” (DS61113)

•Section 3. “Memory Organization ” (DS61115)

•Section 4. “Prefetch Cache” (DS61119)

•Section 5. “Flash Program Memory” (DS61121)

•Section 6. “Oscillator Configuration” (DS61112)

•Section 7. “Resets” (DS61118)

•Section 8. “Interrupt Controller” (DS61108)

•Section 9. “Watchdog Timer and Power-up Timer” (DS61114)

•Section 10. “Power-Saving Features” (DS61130)

•Section 12. “I/O Ports” (DS61120)

•Section 13. “Parallel Master Port (PMP)” (DS61128)

•Section 14. “Timers” (DS61105)

•Section 15. “Input Capture” (DS61122)

•Section 16. “Output Compare” (DS61111)

•Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104)

•Section 19. “Comparator” (DS61110)

•Section 20. “Comparator Voltage Reference (CVREF)” (DS61109)

•Section 21. “Universal Asynchronous Rece iver Transmitter (UART)” (DS61107)

•Section 23. “Serial Peripheral Interface (SPI)” (DS61106)

•Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS61116)

•Section 27. “USB On-The-Go (OTG)” (DS61126)

•Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125)

•Section 31. “Direct Memory Access (DMA) Controller” (DS61117)

•Section 32. “Configuration” (DS61124)

•Section 33. “Programming and Diagnostics” (DS61129)

Note 1: To access the documents listed below,

browse to the documentation section of

the PIC32MX460F512L product page on

the Microchip web site

(www.microchip.com) or select a family

reference manual section from the

following list.

In addition to parameters, features, and

other documentation, the resulting page

provides links to the related family

reference manual sections.

PIC32MX3XX/4XX

NOTES:

PIC32MX3XX/4XX

3.0 CPU

The MIPS32® M4K® Processor Core is the heart of the

PIC32MX3XX/4XX family processor. The CPU fetches

instructions, decodes each instruction, fetches source

operands, executes each instruction and writes the

results of instruction execution to the proper destina-

tions.

3.1 Features

• 5-stage pipeline

• 32-bit Address and Data Paths

• MIPS32 Enhanced Architect u re (R el e a se 2)

- Multiply-Accumul ate and Multiply-Subtract

Instructions

- Targeted Multiply Instruction

- Zero/One Detect Inst ru cti o ns

-WAIT Instruction

- Conditional Move Instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

- Atomic interrupt enable/disable

- GPR shadow registers to minimize latency

for interrupt handlers

- Bit field manipulation instructions

• MIPS16e® Code Compression

- 16-bit encoding of 32-bit instructions to

improve code density

- Special PC-relative instructions for efficient

loading of addresses and constants

- SAVE & RESTORE macro instructions for

setting up and tearing down stack frames

within subroutines

- Improved support for handling 8 and 16-bit

data types

• Simple Fixed Mapping Translation (FMT)

mechanism

• Simple Dual Bus Interface

- Independent 32-bit address and data busses

- Transactions can be aborted to improve

interrupt latency

• Autonomous Multiply/Divide Unit

- Maximum issue rate of one 32x16 multiply

per clock

- Maximum issue rate of one 32x32 multiply

every other clock

- Early-in iterative divide. Minimu m 11 and

maximum 34 clock latency (dividend (rs) sign

extension-dependent)

• Power Control

- Minimum frequency: 0 MHz

- Low-Power mode (tri ggered by WAIT

instruction)

- Extensive use of local gated clocks

• EJTAG Debug and Instruction Trace

- Support for single step ping

- Virtual instruction and data address/value

- breakpoints

- PC traci ng with trace compression

FIGURE 3-1: MIPS® M4K® BLOCK DIAGRA M

Note 1: This data sheet summarizes the features

of the PIC32MX3XX/4XX family of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 2. “CPU” (DS61113) of

the “PIC32 Family Reference Manual”,

which is available from the Microchip web

site (www.microchip.com/PIC32).

Resources for the MIPS32® M4K®

Processor Core are available at:

www.mips.com/products/cores/

32-64-bit-cores/mips32-m4k/.

2: Some registers and associated bits

described in this section may not be avail-

able on all devices. Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

Dual Bus I/F

System

Coprocessor

MDU

FMT

TAP

EJTAG

Power

Mgmt.

Off-Chip

Debug I/F

Execution

Core

(RF/ALU/Shift)

Bus Matrix

Trace

Trace I/F

Bus Interface

CPU

PIC32MX3XX/4XX

3.2 Architecture Overview

The MIPS32® M4K® Processor Core contains several

logic blocks working together in parallel, providing an

efficient high performance computing engine. The

following blocks are included with the core:

• Execution Unit

• Multiply/Divide Un it (MDU)

• System Control Coprocessor (CP0)

• Fixed Mapping Translation (FMT)

• Dual Intern al Bus interfaces

• Power Management

• MIPS16e Support

• Enhanced JTAG (EJTAG) Controll er

3.2.1 EXECUTION UNIT

The MIPS32® M4K® Processor Core execution unit

implements a load/store architecture with single-cycle

ALU operations (logical, shift, add, subtract) and an

autonomous multiply/divide unit. The core contains

thirty-two 32-bit general purpose registers used for

integer operations and address calc ulation. One addi-

tional register file shadow set (containing thirty-two reg-

isters) is added to minimize context switching overhead

during interrupt/exception processi ng. The register file

consists of two read ports and one write port and is fully

bypassed to minimize operation latency in the pipeline.

The execution unit includes:

• 32-bit adder us ed for calculating the data address

• Address unit for calculating the next instruction

address

• Logic for branch determination and branch target

address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when

executing instructions streams where data

producing instructions are followed closely by

consumers of their results

• Leading Zero/One detect unit for implementing the

CLZ and CLO instructions

• Arithmetic Logic Unit (ALU) for performing bitwise

logical operations

• Shifter and Store Aligner

3.2.2 MULTIPLY /DIV IDE UNIT (MDU)

The MIPS32® M4K® Processor Core incl udes a multi-

ply/divide unit (MDU ) that contains a separate pipeline

for multiply and divide operations. This pipeline oper-

ates in parallel with the integer unit (IU) pipeline and

does not stall when the IU pipeline stalls. This allows

MDU operations to be partially masked by system stalls

and/or other integer unit instructions.

The high-performance MDU consists of a 32x16 booth

recoded multiplier, result/accumulation registers (HI

and LO), a divide state machine, and the necessary

multiplexers and control logic. The first number shown

(‘32’ of 32x16) repres ents the rs operand. The second

number (‘16’ of 32x16) represents the rt operan d. The

PIC32MX core only checks the value of the latter (rt)

operand to determine how many times the operation

must pass through the multiplier . The 16x16 and 32x16

operations pass through the multiplier once. A 32x32

operation passes through the multiplier twice.

The MDU supports execution of one 16x16 or 32x16

multiply operation every clock cycle; 32x32 multiply

operations can be issued every other clock cycle.

Appropriate interlocks are implemented to stall the

issuance of back-to-back 32x32 multiply operations.

The multiply operand size is automa tically determined

by logic built into the MDU.

Divide operations are impl emented with a simple 1 bit

per clock iterative algorithm. An early-in detection

checks the sign extension of the dividend (rs) operand.

If rs is 8 bits wide, 23 iterations are skipped. For a 16-

bit-wide rs, 15 iterations are skipped, and for a 24-bit-

wide rs, 7 iterations are skipped. Any attempt to issue

a subsequent MDU instruction while a divide is still

active causes an IU pipeline stall until the divide

operation is completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles

until the operation can be reissu ed) and late ncy (num-

ber of cycles until a result is available) for the PIC32MX

core multiply and divide instructions. The approximate

latency and repeat rates are listed in terms of pipeline

clocks.

PIC32MX3XX/4XX

The MIPS architecture defines that the resu lt of a mul-

tiply or divide operation be placed in the HI and LO reg-

isters. Using the Move-From-HI (MFHI) and Move-

From-LO (MFLO) instructions, these values can be

transferr ed to th e g en e r a l purp ose register fil e.

In addition to the HI/LO targeted operations, the

MIPS32 architecture also defines a multiply instruction,

MUL, which places the least significant results in the

primary register file instead of the HI/LO register pair.

By avoiding the explicit MFLO instruction, required

when using the LO register , and by supporting multiple

destination registers, the throughput of

multiply-intensive operations is increased.

Two other instructions, multiply-add (MADD) and multi-

ply-subtract (MSUB), are used to perform the multiply-

accumulate and multiply-subtract operations. The

MADD instruction multiplies two numbers and then adds

the product to the current contents of the HI and LO

registers. Similarly, the MSUB instruction multiplies two

operands and then subtracts the product from the HI

and LO registers. The MADD and MSUB operations

are commonly used in DSP algorithms.

3.2.3 SYSTEM CONTROL

COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the vir-

tual-to-physical address translation, the exception con-

trol system, the processor ’s diagnostics capability, the

operating modes (kernel, user and debug), and

whether interrupts are enabled or disabled. Config ura-

tion information, such as presence of options like

MIPS16e, is also available by accessing the CP0

registers, listed in Table 3-2.

TABLE 3-1: MIPS® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER

MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode Operand Size (mul rt) (div rs) Latency Repeat Ra te

MULT/MULTU, MADD/MADDU,

MSUB/MSUBU 16 bits 1 1

32 bits 2 2

MUL 16 bits 2 1

32 bits 3 2

DIV/DIVU 8 bits 12 11

16 bits 19 18

24 bits 26 25

32 bits 33 32

TABLE 3-2: COPROCESSOR 0 REGISTERS

Number Register

Name Function

0-6 Reserved Reserved

7 HWREna Enables access via the RDHWR instruction to selected hardware registers

8 BadVAddr(1) Reports the address for the most recent address-related exception

9 Count(1) Processor cycle count

10 Reserved Reserved

11 Compare(1) Timer interrupt control

12 Status(1) Processor status and control

12 IntCtl(1) Interrupt system status and control

12 SRSCtl(1) Shadow register set status and control

12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set

13 Cause(1) Cause of last general exception

14 EPC(1) Program counter at last exception

15 PRId Processor identification and revision

15 EBASE Exception vector base register

16 Config Configuration register

16 Config1 Configuration register 1

16 Config2 Configuration register 2

16 Config3 Configuration register 3

PIC32MX3XX/4XX

Coprocessor 0 also contains the logic for identifying

and managing exceptions. Exceptions can be caused

by a variety of sources, including alignment errors in

data, external events or program errors. Table 3-3

shows the exception types in order of priority.

17-22 Reserved Reserved

23 Debug(2) Debug control and exceptio n status

24 DEPC(2) Program counter at last debug exception

25-29 Reserved Reserved

30 ErrorEPC(1) Program counter at last error

31 DESAVE(2) Debug handler scratchpad register

Note 1: Registers used in exception processing .

2: Registers used during debug.

TABLE 3-2: COPROCESSOR 0 REGISTERS (CONTINUED)

Number Register

Name Function

TABLE 3-3: PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES

Exception Description

Reset Assertion MCLR or a Power-on Reset (POR)

DSS EJTAG Debug Single Step

DINT EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the

EjtagBrk bit in the ECR register

NMI Assertion of NMI signal

Interrupt Assertion of unmasked hardware or software interrupt signal

DIB EJTAG debug hardware instruction break matched

AdEL Fetch address alignment error

Fetch reference to protected address

IBE Instruction fetch bus error

DBp EJTAG Breakpoint (execution of SDBBP instruction )

Sys Execution of SYSCALL instruction

Bp Execution of BREAK instruction

RI Execution of a Reserved Instruction

CpU Execution of a coproces sor instruction for a coprocessor that is not enabled

CEU Execution of a CorExtend instruction when CorExtend is not enabled

Ov Execution of an arithmetic instruction that overflowed

Tr Execution of a trap (when trap condition is tru e)

DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)

AdEL Load address alignment error

Load reference to protected address

AdES Store address alignment error

Store to protected address

DBE Load or store bus error

DDBL EJTAG data hardware breakpoint matched in load data compare

PIC32MX3XX/4XX

3.3 Power Management

The MIPS32® M4K® Processor Core offers a number

of power management features, including low-power

design, active power management and power-down

modes of operation. The core is a static design that

supports slowing or halting the clocks, which reduces

system power consumption during idle periods.

3.3.1 INSTRUCTION-CONTROLLED

POWER MANAGEMENT

The mechanism for invoking power-down mode is

through execution of the WAIT instruction. For more

information on power management, see Section 25.0

“Power-Saving Features”.

3.3.2 LOCAL CLOCK GATING

The majority of the power consumed by the

PIC32MX3XX/4XX family core is in the clock tree and

clocking registers. The PIC32MX family uses extensive

use of local gated-clocks to reduce this dynamic power

consumption.

3.4 EJTAG Debug Support

The MIPS32® M4K® Processor Core provides for an

Enhanced JTAG (EJTAG) interface for use in the

software debug of application and kernel code. In

addition to standard user mode and kernel modes of

operation, the core provides a Debug mode that is

entered after a debug exception (derived from a

hardware breakpoint, single-step exception, etc.) is

taken and continues until a debug exception return

(DERET) instruction is executed. During this time, the

processor executes the debug exception handler

routine.

The EJT AG interface operates through the Test Access

Port (TAP), a serial communication port used for

transferring test data in and out of the core. In addition

to the standard JTAG instructions, special instructions

defined in the EJTAG specification define what

registers are selected and how they are used.

PIC32MX3XX/4XX

NOTES:

PIC32MX3XX/4XX

4.0 MEMORY ORGANIZATION

PIC32MX3XX/4XX microcontrollers provide 4 GB of

unified virtual memory address space. All memory

regions including program, data memory, SFRs and

Configuration registers reside in this addre ss space at

their respective unique addresses. The program and

data memories can be optionally partitioned into user

and kernel memories. In addition, the data memory can

be made executable, allowing PIC32MX3XX/4XX to

execute from data memory.

4.1 Key Features

• 32-bit native data width

• Separate User and Kernel mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and

program space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept

runaway code

• Simple memory mapping with Fixed Mapping

Translation (FMT) unit

• Cacheable and non-cacheable address regions

4.2 PIC32MX3XX/4XX Memory Layout

PIC32MX3XX/4XX microcontrollers implement two

address spaces: Virtual and Physical. All hardware

resources such as program memory, data memory and

peripherals are located at their respective physical

addresses. Virtual addresses are exclusively used by

the CPU to fetch and execute instructions as well as

access peripherals. Physical addresses are used by

peripherals such as DMA and Flash controller that

access memory independently of CPU.

Note 1: This data sheet summarizes the features

of the PIC32MX3XX/4XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 3. “Memory

Organization” (DS61115) of the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

PIC32MX3XX/4XX

FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX320F032H AND PIC32MX420F032H

DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD008000

0xBD007FFF Program Flash(2)

0xBD000000

Reserved

0xA0002000

0xA0001FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FEF

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D008000 0x1F800000

0x9D007FFF Program Flash(2) Reserved

0x9D000000 0x1D008000

Reserved Program Flash(2) 0x1D007FFF

0x80002000

0x80001FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00002000

Reserved RAM(2) 0x00001FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initializa tion code provided by end-user development

tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX3XX/4XX

FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICE(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF Program Flash(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FEF

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF Program Flash(2) Reserved

0x9D000000 0x1D010000

Reserved Program Flash(2) 0x1D00FFFF

0x80004000

0x80003FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM(2) 0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initializa tion code provided by end-user development

tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX3XX/4XX

FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX320F128H AND PIC32MX320F128L

DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF Program Flash(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FEF

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF Program Flash(2) Reserved

0x9D000000 0x1D020000

Reserved Program Flash(2) 0x1D01FFFF

0x80004000

0x80003FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM(2) 0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initializa tion code provided by end-user development

tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX3XX/4XX

FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L,

PIC32MX440F128H AND PIC32MX440F128L DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF Program Flash(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FEF

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF Program Flash(2) Reserved

0x9D000000 0x1D020000

Reserved Program Flash(2) 0x1D01FFFF

0x80008000

0x80007FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM(2) 0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initializa tion code provided by end-user development

tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX3XX/4XX

FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L,

PIC32MX440F256H AND PIC32MX460F256L DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD040000

0xBD03FFFF Program Flash(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FEF

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D040000 0x1F800000

0x9D03FFFF Program Flash(2) Reserved

0x9D000000 0x1D040000

Reserved Program Flash(2) 0x1D03FFFF

0x80008000

0x80007FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM(2) 0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initializa tion code provided by end-user development

tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX3XX/4XX

FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L,

PIC32MX440F512H AND PIC32MX460F512L DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC03000

0xBFC02FFF Device

Configuration

Registers

0xBFC02FF0

0xBFC02FEF Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF SFRs

0xBF800000

Reserved

0xBD080000

0xBD07FFFF Program Flash(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF RAM(2)

0xA0000000 0x1FC03000

Reserved Device

Configuration

Registers

0x1FC02FFF

0x9FC03000

0x9FC02FFF Device

Configuration

Registers

0x1FC02FF0

Boot Flash 0x1FC02FEF

0x9FC02FEF

0x9FC02FEF Boot Flash 0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs 0x1F8FFFFF

0x9D080000 0x1F800000

0x9D07FFFF Program Flash(2) Reserved

0x9D000000 0x1D080000

Reserved Program Flash(2) 0x1D07FFFF

0x80008000

0x80007FFF RAM(2) 0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM(2) 0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115)) and can be changed by initializa tion code provided by end-user development

tools (refer to the specific development tool documentation for information).

KSEG1KSEG0

PIC32MX3XX/4XX

TABLE 4-1: BUS MATRIX REGISTERS MAP

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2000 BMX

CON(1) 31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

15:0 — — — — — — — — —BMXWSDRM— — — BMXARB<2:0> 0042

2010 BMX

DKPBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDKPBA<15:0> 0000

2020 BMX

DUDBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUDBA<15:0> 0000

2030 BMX

DUPBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUPBA<15:0> 0000

2040 BMX

DRMSZ 31:16 BMXDRMSZ<31:0> xxxx

15:0 xxxx

2050 BMX

PUPBA(1) 31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000

15:0 BMXPUPBA<15:0> 0000

2060 BMX

PFMSZ 31:16 BMXPFMSZ<31:0> xxxx

15:0 xxxx

2070 BMX

BOOTSZ 31:16 BMXBOOTSZ<31:0> 0000

15:0 3000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.

PIC32MX3XX/4XX

TABLE 4-2: INTERRUPT REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

1000 INTCON 31:16 ——————————————— SS0 0000

15:0 ———MVEC—TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

1010 INTSTAT(2) 31:16 ————————————————0000

15:0 —————SRIPL<2:0>—— VEC<5:0> 0000

1020 IPTMR 31:16 IPTMR<31:0> 0000

15:0 0000

1030 IFS0 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000

15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000

1040 IFS1 31:16 —————— USBIF FCEIF ———— DMA3IF DMA2IF DMA1IF DMA0IF 0000

15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF

SPI2RXIF SPI2TXIF

SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000

1060 IEC0 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000

15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000

1070 IEC1 31:16 ——————USBIEFCEIE———— DMA3IE DMA2IE DMA1IE DMA0IE 0000

15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE

SPI2RXIE

SPI2TXIE

SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000

1090 IPC0 31:16 ——— INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000

15:0 ——— CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000

10A0 IPC1 31:16 ——— INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000

15:0 ——— IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000

10B0 IPC2 31:16 ——— INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

15:0 ——— IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000

10C0 IPC3 31:16 ——— INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000

15:0 ——— IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000

10D0 IPC4 31:16 ——— INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

15:0 ——— IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000

10E0 IPC5 31:16 ——— SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000

15:0 ——— IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000

10F0 IPC6 31:16 ——— AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000

15:0 ——— I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000

1100 IPC7 31:16 ——— SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000

15:0 ——— CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000

1110 IPC8 31:16 ——— RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000

15:0 ——— I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000

1120 IPC9 31:16 ——— DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000

15:0 ——— DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000

1140 IPC11 31:16 ————————————————0000

15:0 ——— USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Except where noted, all registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV

Registers” for more information.

2: This register does not have associated CLR, SET, and INV registers.

PIC32MX3XX/4XX

TABLE 4-3: INTERRUPT REGISTERS MAP FOR PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L,

PIC32MX360F256L AND PIC32MX3 60F512L DEVICES ONLY(1)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

1000 INTCON 31:16 ——————————————— SS0 0000

15:0 ———MVEC—TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

1010 INTSTAT(2) 31:16 ————————————————0000

15:0 —————SRIPL<2:0>—— VEC<5:0> 0000

1020 IPTMR 31:16 IPTMR<31:0> 0000

15:0 0000

1030 IFS0 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000

15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000

1040 IFS1 31:16 ———————FCEIF———— DMA3IF DMA2IF DMA1IF DMA0IF 0000

15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF

SPI2RXIF SPI2TXIF

SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000

1060 IEC0 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000

15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000

1070 IEC1 31:16 ———————FCEIE———— DMA3IE DMA2IE DMA1IE DMA0IE 0000

15:0 RTCCIE FSCMIE I2C2MIE —————