MAX11626EEE+T - Maxim Integrated

General Description

The MAX11626–MAX11629/MAX11632/MAX11633 are

serial 12-bit analog-to-digital converters (ADCs) with an

internal reference. These devices feature on-chip FIFO,

scan mode, internal clock mode, internal averaging, and

AutoShutdown™. The maximum sampling rate is 300ksps

using an external clock. The MAX11632/MAX11633 have

16 input channels; the MAX11628/MAX11629 have 8

input channels; and the MAX11626/MAX11627 have 4

input channels. These six devices operate from either a

+3V supply or a +5V supply, and contain a 10MHz SPI-/

QSPI™-/MICROWIRE®-compatible serial port.

The MAX11626–MAX11629 are available in 16-pin QSOP

packages. The MAX11632/MAX11633 are available in

24-pin QSOP packages. All six devices are specified over

the extended -40°C to +85°C temperature range.

Applications

●System Supervision

●Data-Acquisition Systems

●Industrial Control Systems

●Patient Monitoring

●Data Logging

●Instrumentation

Features

●Analog Multiplexer with Track/Hold

• 16 Channels (MAX11632/MAX11633)

• 8 Channels (MAX11628/MAX11629)

• 4 Channels (MAX11626/MAX11627)

●Single Supply

• 2.7V to 3.6V (MAX11627/MAX11629/MAX11633)

• 4.75V to 5.25V

(MAX11626/MAX11628/MAX11632)

●Internal Reference

• 2.5V (MAX11627/MAX11629/MAX11633)

• 4.096V (MAX11626/MAX11628/MAX11632)

●External Reference: 1V to VDD

●16-Entry First-In/First-Out (FIFO)

●Scan Mode, Internal Averaging, and Internal Clock

●Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing

Codes Over Temperature

●10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible

Interface

●Small Packages

• 16-Pin QSOP (MAX11626–MAX11629)

• 24-Pin QSOP (MAX11632/MAX11633)

Pin Configurations continued at end of data sheet.

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corp.

19-5323; Rev 5; 9/14

Note: All devices are specified over the -40°C to +85°C operat-

ing temperature range.

+Denotes a lead(Pb)-free/RoHS-compliant package.

PART

NUMBER

INPUTS

SUPPLY

VOLTAGE

RANGE (V)

PACKAGE

MAX11626EEE+ 4 4.75 to 5.25 16 QSOP

MAX11627EEE+ 4 2.7 to 3.6 16 QSOP

MAX11628EEE+ 8 4.75 to 5.25 16 QSOP

MAX11629EEE+ 8 2.7 to 3.6 16 QSOP

MAX11632EEG+ 16 4.75 to 5.25 24 QSOP

MAX11633EEG+ 16 2.7 to 3.6 24 QSOP

AIN0

TOP VIEW

EOC

DOUT

DIN

SCLK

VDD

GND

REF

MAX11626–

MAX11629

QSOP

AIN1

AIN2

AIN5 (N.C.)

AIN3

AIN4 (N.C.)

AIN6 (N.C.)

AIN7/(CNVST)

() MAX11626/MAX11627 ONLY

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

Pin Congurations

Ordering Information

EVALUATION KIT AVAILABLE

VDD to GND ............................................................-0.3V to +6V

CS, SCLK, DIN, EOC, DOUT to GND ..... -0.3V to (VDD + 0.3V)

AIN0–AIN13, AIN_, CNVST/AIN_,

REF to GND ......................................... -0.3V to (VDD + 0.3V)

Maximum Current into Any Pin...........................................50mA

Continuous Power Dissipation (TA = +70°C)

16-Pin QSOP (derate 8.3mW/°C above +70°C)..........667mW

24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW

Operating Temperature Range ........................... -40°C to +85°C

Storage Temperature Range ............................ -60°C to +150°C

Junction Temperature ......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

(VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE

= 300kHz, fSCLK = 4.8MHz external clock (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V

(MAX11626/MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Note 1)

Resolution RES 12 Bits

Integral Nonlinearity INL ±1.0 LSB

Differential Nonlinearity DNL No missing codes over temperature ±1.0 LSB

Offset Error ±0.5 ±4.0 LSB

Gain Error (Note 2) ±0.5 ±4.0 LSB

Offset Error Temperature

Coefcient ±2 ppm/°C

FSR

Gain Temperature Coefcient ±0.8 ppm/°C

Channel-to-Channel Offset

Matching ±0.1 LSB

DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 300ksps, fSCLK = 4.8MHz)

Signal-to-Noise Plus Distortion SINAD MAX11627/MAX11629/MAX11633 71 dB

MAX11626/MAX11628/MAX11632 73

Total Harmonic Distortion THD Up to the 5th

harmonic

MAX11627/MAX11629/

MAX11633 -80

dBc

MAX11626/MAX11628/

MAX11632 -88

Spurious-Free Dynamic Range SFDR MAX11627/MAX11629/MAX11633 81 dBc

MAX11626/MAX11628/MAX11632 89

Intermodulation Distortion IMD fIN1 = 29.9kHz, fIN2 = 30.2kHz 76 dBc

Full-Power Bandwidth -3dB point 1 MHz

Full-Linear Bandwidth S/(N + D) > 68dB 100 kHz

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Electrical Characteristics

(VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE

= 300kHz, fSCLK = 4.8MHz external clock (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V

(MAX11626/MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CONVERSION RATE

Power-Up Time tPU

External reference 0.8 µs

Internal reference (Note 3) 65

Acquisition Time tACQ 0.6 µs

Conversion Time tCONV

Internally clocked 3.5 µs

Externally clocked (Note 4) 2.7

External Clock Frequency fSCLK

Externally clocked conversion 0.1 4.8 MHz

Data I/O 10

Aperture Delay 30 ns

Aperture Jitter < 50 ps

ANALOG INPUT

Input Voltage Range Unipolar 0 VREF V

Input Leakage Current VIN = VDD ±0.01 ±1 µA

Input Capacitance During acquisition time (Note 5) 24 pF

INTERNAL REFERENCE

REF Output Voltage MAX11626/MAX11628/MAX11632 4.024 4.096 4.168 V

MAX11627/MAX11629/MAX11633 2.48 2.50 2.52

REF Temperature Coefcient TCREF

MAX11626/MAX11628/MAX11632 ±20 ppm/°C

MAX11627/MAX11629/MAX11633 ±30

Output Resistance 6.5 kΩ

REF Output Noise 200 µVRMS

REF Power-Supply Rejection PSRR -70 dB

EXTERNAL REFERENCE INPUT

REF Input Voltage Range VREF 1.0 VDD + 50mV V

REF Input Current IREF

VREF = 2.5V (MAX11627/MAX11629/

MAX11633); VREF = 4.096V

(MAX11626/MAX11628/MAX11632),

fSAMPLE = 300ksps

40 100

µA

VREF = 2.5V (MAX11627/MAX11629/

MAX11633); VREF = 4.096V

(MAX11626/MAX11628/MAX11632),

fSAMPLE = 0

±0.1 ±5

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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│

Electrical Characteristics (continued)

(VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE

= 300kHz, fSCLK = 4.8MHz external clock (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V

(MAX11626/MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

Note 1: MAX11627/MAX11629/MAX11633 tested at VDD = +3V. MAX11626/MAX11628/MAX11632 tested at VDD = +5V.

Note 2: Offset nulled.

Note 3: Time for reference to power up and settle to within 1 LSB.

Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 5: See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating

Characteristics section.

Note 6: When CNVST is configured as a digital input, do not apply a voltage between VIL and VIH.

Note 7: Supply current is specified depending on whether an internal or external reference is used for voltage conversions.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (SCLK, DIN, CS, CNVST)(Note 6)

Input Voltage Low VIL

MAX11626/MAX11628/MAX11632 0.8 V

MAX11627/MAX11629/MAX11633 VDD x 0.3

Input Voltage High VIH

MAX11626/MAX11628/MAX11632 2.0 V

MAX11627/MAX11629/MAX11633 VDD x 0.7

Input Hysteresis VHYST 200 mV

Input Leakage Current IIN VIN = 0V or VDD ±0.01 ±1.0 µA

Input Capacitance CIN 15 pF

DIGITAL OUTPUTS (DOUT, EOC)

Output Voltage Low VOL

ISINK = 2mA 0.4 V

ISINK = 4mA 0.8

Output Voltage High VOH ISOURCE = 1.5mA VDD - 0.5 V

Three-State Leakage Current ILCS = VDD ±0.05 ±1 µA

Three-State Output Capacitance COUT CS = VDD 15 pF

POWER REQUIREMENTS

Supply Voltage VDD

MAX11626/MAX11628/MAX11632 4.75 5.25 V

MAX11627/MAX11629/MAX11633 2.7 3.6

MAX11627/MAX11629/MAX11633

Supply Current (Note 7) IDD

Internal

reference

fSAMPLE = 300ksps 1750 2000

µA

fSAMPLE = 0, REF on 1000 1200

Shutdown 0.2 5

External

reference

fSAMPLE = 300ksps 1050 1200

Shutdown 0.2 5

MAX11626/MAX11628/MAX11632

Supply Current (Note 7) IDD

Internal

reference

fSAMPLE = 300ksps 2300 2550

µA

fSAMPLE = 0, REF on 1050 1350

Shutdown 0.2 5

External

reference

fSAMPLE = 300ksps 1550 1700

Shutdown 0.2 5

Power-Supply Rejection PSR VDD = 2.7V to 3.6V; full-scale input ±0.2 ±1 mV

VDD = 4.75V to 5.25V; full-scale input ±0.2 ±1.4

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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Electrical Characteristics (continued)

Note 8: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-

ence needs to be powered up, the total time is additive.

(VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632),

fSAMPLE =300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/

MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted.

VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLK Clock Period tCP

Externally clocked conversion 208 ns

Data I/O 100

SCLK Pulse Width High tCH 40 ns

SCLK Pulse Width Low tCL 40 ns

SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 40 ns

CS Rise to DOUT Disable tDOD CLOAD = 30pF 40 ns

CS Fall to DOUT Enable tDOE CLOAD = 30pF 40 ns

DIN to SCLK Rise Setup tDS 40 ns

SCLK Rise to DIN Hold tDH 0 ns

CS Low to SCLK Setup tCSS0 40 ns

CS High to SCLK Setup tCSS1 40 ns

CS High After SCLK Hold tCSH1 0 ns

CS Low After SCLK Hold tCSH0 0 4 µs

CNVST Pulse Width Low tCSPW CKSEL = 00 40 ns

CKSEL = 01 1.4 µs

CS or CNVST Rise to EOC

Low (Note 8)

Voltage conversion 7 µs

Reference power-up 65

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX11626 toc02

OUTPUT CODE (DECIMAL)

INL (LSB)

307220481024

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

0 4096

MAX11627/MAX11629/MAX11633

fSAMPLE = 300ksps

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX11626 toc03

OUTPUT CODE (DECIMAL)

DNL (LSB)

307220481024

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

0 4096

MAX11626/MAX11628/MAX11632

fSAMPLE = 300ksps

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX11626 toc01

OUTPUT CODE (DECIMAL)

INL (LSB)

307220481024

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

0 4096

MAX11626/MAX11628/MAX11632

fSAMPLE = 300ksps

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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Timing Characteristics (Figure 1)

Typical Operating Characteristics

(VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted.

VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.)

SINAD vs. FREQUENCY

MAX11626 toc05

FREQUENCY (kHz)

SINAD (dB)

10010

1 1000

MAX11627/MAX11629/MAX11633

MAX11626/MAX11628/MAX11632

SFDR vs. FREQUENCY

MAX11626 toc06

FREQUENCY (kHz)

SFDR (dB)

10010

100

1 1000

MAX11627/MAX11629/MAX11633

MAX11626/MAX11628/ MAX11632

THD vs. FREQUENCY

MAX11626 toc07

FREQUENCY (kHz)

THD (dB)

10010

-90

-80

-70

-60

-50

-100

1 1000

MAX11626/MAX11628/MAX11632

MAX11627/MAX11629/MAX11633

SUPPLY CURRENT vs. SAMPLING RATE

MAX11626 toc08

SAMPLING RATE (ksps)

IVDD (µA)

10010

500

1000

1500

2000

2500

3000

1 1000

MAX11626/MAX11628/MAX11632

VDD = 5V

INTERNAL REFERENCE

EXTERNAL REFERENCE

SUPPLY CURRENT vs. SAMPLING RATE

MAX11626 toc09

SAMPLING RATE (ksps)

IVDD (µA)

10010

200

400

600

800

1000

1200

1400

1600

1800

1 1000

MAX11627/MAX11629/MAX11633

VDD = 3V

INTERNAL REFERENCE

EXTERNAL REFERENCE

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX11626 toc04

OUTPUT CODE (DECIMAL)

DNL (LSB)

307220481024

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

0 4096

MAX11627/MAX11629/MAX11633

fSAMPLE = 300ksps

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX11626 toc10

VDD (V)

IDD (µA)

5.154.85 5.054.95

1200

1400

1600

1800

2000

2200

2400

2600

1000

4.75 5.25

MAX11626/MAX11628/MAX11632

fSAMPLE = 300ksps

INTERNAL REFERENCE

EXTERNAL REFERENCE

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

Maxim Integrated

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Typical Operating Characteristics (continued)

(VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted.

VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.)

VDD (V)

IDD (µA)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX11626 toc11

3.5 3.63.3 3.42.9 3.0 3.1 3.22.8

200

400

600

800

1000

1200

1400

1600

1800

2000

2.7

MAX11627/MAX11629/MAX11633

fSAMPLE = 300ksps

INTERNAL REFERENCE

EXTERNAL REFERENCE

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX11626 toc12

VDD (V)

IDD (µA)

5.154.85 5.054.95

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

4.75 5.25

MAX11626/MAX11628/MAX11632

VDD = 5V

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX11626 toc13

VDD (V)

IDD (µA)

3.53.43.33.23.13.02.92.8

0.1

0.2

0.3

0.4

0.5

2.7 3.6

MAX11627/MAX11629/MAX11633

VDD = 3V

SUPPLY CURRENT vs. TEMPERATURE

MAX11626 toc14

TEMPERATURE (°C)

IDD (µA)

603510-15

1300

1600

1900

2200

2500

1000

-40 85

MAX11626/MAX11628/MAX11632

VDD = 5V

fSAMPLE = 300ksps

INTERNAL REFERENCE

EXTERNAL REFERENCE

SUPPLY CURRENT vs. TEMPERATURE

MAX11626 toc15

TEMPERATURE (°C)

IDD (µA)

603510-15

800

1000

1200

1400

1600

1800

600

-40 85

MAX11627/MAX11629/MAX11633

VDD = 3V

fSAMPLE = 300ksps

INTERNAL REFERENCE

EXTERNAL REFERENCE

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

MAX11626 toc16

TEMPERATURE (°C)

IDD (µA)

603510-15

0.5

1.0

1.5

2.0

2.5

-40 85

MAX11626/MAX11628/MAX11632

VDD = 5V

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

Maxim Integrated

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www.maximintegrated.com

Typical Operating Characteristics (continued)

(VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted.

VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.)

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX11626 toc18

VDD (V)

REF

(V)

5.155.054.954.85

4.095

4.096

4.097

4.098

4.099

4.094

4.75 5.25

MAX11626/MAX11628/MAX11632

VDD = 5V

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX11626 toc19

VDD (V)

REF

(V)

3.33.0

2.498

2.499

2.500

2.501

2.502

2.497

2.7 3.6

MAX11627/MAX11629/MAX11633

VDD = 3V

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX11626 toc20

TEMPARATURE (°C)

VREF (V)

603510-15

4.08

4.09

4.10

4.11

4.12

4.07

-40 85

MAX11626/MAX11628/MAX11632

VDD = 5V

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX11626 toc21

TEMPARATURE (°C)

VREF (V)

603510-15

2.48

2.49

2.50

2.51

2.52

2.47

-40 85

MAX11627/MAX11629/MAX11633

VDD = 3V

OFFSET ERROR vs. SUPPLY VOLTAGE

MAX11626 toc22

(V)

OFFSET ERROR (LSB)

5.155.054.954.85

-0.4

-0.2

0.2

0.4

0.6

-0.6

4.75 5.25

MAX11626/MAX11628/MAX11632

fSAMPLE = 300ksps

OFFSET ERROR vs. SUPPLY VOLTAGE

MAX11626 toc23

VDD (V)

OFFSET ERROR (LSB)

3.33.0

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.00

2.7 3.6

MAX11627/MAX11629/MAX11633

fSAMPLE = 300ksps

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

MAX11626 toc17

TEMPERATURE (°C)

IDD (µA)

603510-15

0.2

0.4

0.6

0.8

1.0

-40 85

MAX11627/MAX11629/MAX11633

VDD = 3V

OFFSET ERROR vs. TEMPERATURE

MAX11626 toc24

TEMPERATURE (°C)

OFFSET ERROR (LSB)

603510-15

-0.6

-0.2

0.2

0.6

1.0

-1.0

-40 85

MAX11626/MAX11628/MAX11632

fSAMPLE = 300ksps

OFFSET ERROR vs. TEMPERATURE

MAX11626 toc25

TEMPERATURE (°C)

OFFSET ERROR (LSB)

603510-15

0.7

0.9

1.1

1.3

1.5

0.5

-40 85

MAX11627/MAX11629/MAX11633

fSAMPLE = 300ksps

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

Maxim Integrated

│

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Typical Operating Characteristics (continued)

(VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted.

VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.)

GAIN ERROR vs. SUPPLY VOLTAGE

MAX11626 toc26

VDD (V)

GAIN ERROR (LSB)

5.155.054.954.85

0.1

0.2

0.3

0.4

0.5

0.6

0.7

4.75 5.25

MAX11626/MAX11628/MAX11632

fSAMPLE = 300ksps

GAIN ERROR vs. SUPPLY VOLTAGE

MAX11626 toc27

VDD (V)

GAIN ERROR (LSB)

3.33.0

-0.4

-0.3

-0.2

-0.1

-0.5

2.7 3.6

MAX11627/MAX11629/MAX11633

GAIN ERROR vs. TEMPERATURE

MAX11626 toc28

TEMPERATURE (°C)

GAIN ERROR (LSB)

603510-15

-0.6

-0.2

0.2

0.6

1.0

-1.0

-40 85

MAX11626/MAX11628/MAX11632

fSAMPLE = 300ksps

GAIN ERROR vs. TEMPERATURE

MAX11626 toc29

TEMPERATURE (°C)

GAIN ERROR (LSB)

603510-15

-0.3

-0.1

0.1

0.3

0.5

-0.5

-40 85

MAX11627/MAX11629/MAX11633

fSAMPLE = 300ksps

-10

-6

-8

-2

-4

0 42 6 8 10

SAMPLING ERROR

vs. SOURCE IMPEDANCE

MAX11626 toc30

SOURCE IMPEDANCE (kΩ)

SAMPLING ERROR (LSB)

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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Typical Operating Characteristics (continued)

MAX11626

MAX11627

(4 CHANNELS)

MAX11628

MAX11629

(8 CHANNELS)

MAX11632

MAX11633

(16 CHANNELS)

NAME FUNCTION

5, 6, 7 — — N.C. No Connection. Not internally connected.

— — 1–15 AIN0–AIN14 Analog Inputs

— 1–7 — AIN0–AIN6 Analog Inputs

1–4 — — AIN0–AIN3 Analog Inputs

— — 16 CNVST/AIN15

Active-Low Conversion Start Input/Analog Input 15.

See Table 3 for details on programming the setup

— 8 — CNVST/AIN7

Active-Low Conversion Start Input/Analog Input 7.

See Table 3 for details on programming the setup

8 — — CNVST Active-Low Conversion Start Input. See Table 3 for

details on programming the setup register.

9 9 17 REF Reference Input. Bypass to GND with a 0.1µF

capacitor.

10 10 18 GND Ground

11 11 19 VDD Power Input. Bypass to GND with a 0.1µF capacitor.

12 12 20 CS

Active-Low Chip-Select Input. When CS is low, the

serial interface is enabled. When CS is high, DOUT

is high impedance.

13 13 21 SCLK

Serial Clock Input. Clocks data in and out of the serial

interface. (Duty cycle must be 40% to 60%.) See

Table 3 for details on programming the clock mode.

14 14 22 DIN Serial Data Input. DIN data is latched into the serial

interface on the rising edge of SCLK.

15 15 23 DOUT

Serial Data Output. Data is clocked out on the falling

edge of SCLK. High impedance when CS is connected

to VDD.

16 16 24 EOC End of Conversion Output. Data is valid after EOC

pulls low.

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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Pin Description

Detailed Description

The MAX11626–MAX11629/MAX11632/MAX11633 are

low-power, serial-output, multichannel ADCs with FIFO

capability for system monitoring, process-control, and

instrumentation applications. These 12-bit ADCs have

internal track and hold (T/H) circuitry supporting sin-

gleended inputs. Data is converted from analog voltage

sources in a variety of channel and data-acquisition

configurations. Microprocessor (μP) control is made easy

through a 3-wire SPI-/QSPI-/MICROWIRE-compatible

serial interface.

Figure 2 shows a simplified functional diagram of the

MAX11626–MAX11629/MAX11632/MAX11633 inter-

nal architecture. The MAX11632/MAX11633 have 16

single-ended analog input channels. The MAX11628/

MAX11629 have 8 single-ended analog input channels.

The MAX11626/MAX11627 have 4 single-ended analog

input channels.

Figure 1. Detailed Serial-Interface Timing Diagram

Figure 2. Functional Diagram

SCLK

DIN

DOUT

tDH

tDOE

tDS

tCH

tCL

tCSS0 tCP tCSH1 tCSH0

tCSS1

tDOD

tDOT

12-BIT

SAR

ADC

CONTROL

SERIAL

INTERFACE

OSCILLATOR

FIFO AND

ACCUMULATOR

T/H

CNVST

SCLK

DIN

EOC

DOUT

AIN15

AIN1

AIN2

INTERNAL

REFERENCE

REF

MAX11626–MAX11629/MAX11632/MAX11633

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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Converter Operation

The MAX11626–MAX11629/MAX11632/MAX11633 ADCs

use a successive-approximation register (SAR) conver-

sion technique and an on-chip T/H block to convert volt-

age signals into a 12-bit digital result. This single-ended

configuration supports unipolar signal ranges.

Input Bandwidth

The ADC’s input-tracking circuitry has a 1MHz small-

signal bandwidth, so it is possible to digitize high-speed

transient events and measure periodic signals with

bandwidths exceeding the ADC’s sampling rate by using

undersampling techniques. Anti-alias prefiltering of the

input signals is necessary to avoid high-frequency signals

aliasing into the frequency band of interest.

Analog Input Protection

Internal ESD protection diodes clamp all pins to VDD and

GND, allowing the inputs to swing from (GND - 0.3V) to

(VDD + 0.3V) without damage. However, for accurate con-

versions near full scale, the inputs must not exceed VDD

by more than 50mV or be lower than GND by 50mV. If an

off-channel analog input voltage exceeds the supplies,

limit the input current to 2mA.

3-Wire Serial Interface

The MAX11626–MAX11629/MAX11632/MAX11633 fea-

ture a serial interface compatible with SPI/QSPI and

MICROWIRE devices. For SPI/QSPI, ensure the CPU

serial interface runs in master mode so it generates

the serial clock signal. Select the SCLK frequency of

10MHz or less, and set clock polarity (CPOL) and phase

(CPHA) in the μP control registers to the same value. The

MAX11626–MAX11629/MAX11632/MAX11633 operate

with SCLK idling high or low, and thus operate with CPOL

= CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch

input data at DIN on the rising edge of SCLK. Output data

at DOUT is updated on the falling edge of SCLK. Results

are output in binary format.

Serial communication always begins with an 8-bit input

data byte (MSB first) loaded from DIN. A high-to-low tran-

sition on CS initiates the data input operation. The input

data byte and the subsequent data bytes are clocked

from DIN into the serial interface on the rising edge of

SCLK. Tables 1–5 detail the register descriptions. Bits 5

and 4, CKSEL1 and CKSEL0, respectively, control the

clock modes in the setup register (see Table 3). Choose

between four different clock modes for various ways to

start a conversion and determine whether the acquisi-

tions are internally or externally timed. Select clock mode

00 to configure CNVST/AIN_ to act as a conversion start

and use it to request the programmed, internally timed

conversions without tying up the serial bus. In clock mode

01, use CNVST to request conversions one channel at a

time, controlling the sampling speed without tying up the

serial bus. Request and start internally timed conversions

through the serial interface by writing to the conversion

with SCLK up to 4.8MHz for externally timed acquisitions

to achieve sampling rates up to 300ksps. Clock mode 11

disables scanning and averaging. See Figures 4–7 for

timing specifications and how to begin a conversion.

These devices feature an active-low, end-of-conversion

output. EOC goes low when the ADC completes the last

requested operation and is waiting for the next input data

byte (for clock modes 00 and 10). In clock mode 01, EOC

goes low after the ADC completes each requested opera-

tion. EOC goes high when CS or CNVST goes low. EOC

is always high in clock mode 11.

Single-Ended Inputs

The single-ended analog input conversion modes can be

configured by writing to the setup register (see Table 3).

Single-ended conversions are internally referenced to GND

(see Figure 3).

AIN0–AIN3 are available on the MAX11626–MAX11629/

MAX11632/MAX11633. AIN4–AIN7 are only available on

the MAX11628–MAX11633. AIN8–AIN15 are only avail-

able on the MAX11632/MAX11633. See Tables 2–5 for

more details on configuring the inputs. For the inputs that

can be configured as CNVST or an analog input, only one

can be used at a time.

Unipolar

The MAX11626–MAX11629/MAX11632/MAX11633

always operate in unipolar mode. The analog inputs are

internally referenced to GND with a full-scale input range

from 0 to VREF.

Figure 3. Equivalent Input Circuit

HOLD

CIN+

REF

GND DAC

CIN-

VDD/2

COMPARATOR

AIN0-AIN15

GND

HOLD

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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True Differential Analog Input T/H

The equivalent circuit of Figure 3 shows the MAX11626–

MAX11629/MAX11632/MAX11633’s input architecture.

In track mode, a positive input capacitor is connected

to AIN0–AIN15. A negative input capacitor is connected

to GND. For external T/H timing, use clock mode 01.

After the T/H enters hold mode, the difference between

the sampled positive and negative input voltages is con-

verted. The time required for the T/H to acquire an input

signal is determined by how quickly its input capacitance

is charged. If the input signal’s source impedance is high,

the required acquisition time lengthens. The acquisition

time, tACQ, is the maximum time needed for a signal to

be acquired, plus the power-up time. It is calculated by the

following equation:

tACQ = 9 x (RS + RIN) x 24pF + tPWR

where RIN = 1.5kΩ, RS is the source impedance of the

input signal, and tPWR = 1μs, the power-up time of the

device. The varying power-up times are detailed in the

explanation of the clock mode conversions. When the

conversion is internally timed, tACQ is never less than

1.4μs, and any source impedance below 300Ω does

not significantly affect the ADC’s AC performance. A

high-impedance source can be accommodated either by

lengthening tACQ or by placing a 1μF capacitor between

the positive and negative analog inputs.

Internal FIFO

The MAX11626–MAX11629/MAX11632/MAX11633 con-

tain a FIFO buffer that can hold up to 16 ADC results.

This allows the ADC to handle multiple internally clocked

conversions, without tying up the serial bus. If the FIFO is

filled and further conversions are requested without read-

ing from the FIFO, the oldest ADC results are overwritten

by the new ADC results. Each result contains 2 bytes,

with the MSB preceded by four leading zeros. After each

falling edge of CS, the oldest available byte of data is

available at DOUT, MSB first. When the FIFO is empty,

DOUT is zero.

Internal Clock

The MAX11626–MAX11629/MAX11632/MAX11633 oper-

ate from an internal oscillator, which is accurate within

10% of the 4.4MHz nominal clock rate. The internal oscil-

lator is active in clock modes 00, 01, and 10. Read out the

data at clock speeds up to 10MHz. See Figures 4–7 for

details on timing specifications and starting a conversion.

Applications Information

The MAX11626–MAX11629/MAX11632/MAX11633 com-

municate between the internal registers and the external

circuitry through the SPI-/QSPI-compatible serial interface.

Table 1 details the registers and the bit names. Tables 2–5

show the various functions within the conversion register,

setup register, averaging register, and reset register.

Conversion Time Calculations

The conversion time for each scan is based on a number

of different factors: conversion time per sample, samples

per result, results per scan, and if the external reference

is in use.

Use the following formula to calculate the total conversion

time for an internally timed conversion in clock modes

00 and 10 (see the Electrical Characteristics section as

applicable):

Total Conversion Time = tCNV x nAVG x nRESULT + tRP

where

tCNV = tACQ (max) + tCONV (max).

nAVG = samples per result (amount of averaging).

nRESULT = number of FIFO results requested; deter-

mined by the number of channels being scanned or

by NSCAN1, NSCAN0.

tRP = internal reference wake-up; set to zero if inter-

nal reference is already powered up or external refer-

ence is being used.

In clock mode 01, the total conversion time depends on

how long CNVST is held low or high, including any time

required to turn on the internal reference. Conversion

time in externally clocked mode (CKSEL1, CKSEL0 = 11)

depends on the SCLK period and how long CS is held

high between each set of eight SCLK cycles. In clock

mode 01, the total conversion time does not include the

time required to turn on the internal reference.

Table 1. Input Data Byte (MSB First)

X = Don’t care.

Conversion 1 CHSEL3 CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 X

Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 X X

Averaging 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 NSCAN0

Reset 0 0 0 1 RESET X X X

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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Conversion Register

Select active analog input channels per scan and scan

modes by writing to the conversion register. Table 2

details channel selection and the four scan modes.

Request a scan by writing to the conversion register when

in clock mode 10 or 11, or by applying a low pulse to the

CNVST pin when in clock mode 00 or 01.

A conversion is not performed if it is requested on a chan-

nel that has been configured as CNVST. Do not request

conversions on channels 8–15 on the MAX11626–

MAX11629. Set CHSEL3:CHSEL0 to the lower channel’s

binary values.

Select scan mode 00 or 01 to return one result per single-

ended channel within the requested range. Select scan

mode 10 to scan a single input channel numerous times,

depending on NSCAN1 and NSCAN0 in the averaging

result from a single channel.

Setup Register

Write a byte to the setup register to configure the clock,

reference, and power-down modes. Table 3 details the

bits in the setup register. Bits 5 and 4 (CKSEL1 and

CKSEL0) control the clock mode, acquisition and sam-

pling, and the conversion start. Bits 3 and 2 (REFSEL1

and REFSEL0) control internal or external reference use.

Averaging Register

Write to the averaging register to configure the ADC to

average up to 32 samples for each requested result, and

to independently control the number of results requested

for single-channel scans.

Table 2 details the four scan modes available in the con-

version register. All four scan modes allow averaging as

long as the AVGON bit, bit 4 in the averaging register, is

set to 1. Select scan mode 10 to scan the same channel

multiple times. Clock mode 11 disables averaging.

Reset Register

Write to the reset register (as shown in Table 5) to clear

the FIFO or to reset all registers to their default states.

Set the RESET bit to 1 to reset the FIFO. Set the reset bit

to zero to return the MAX11626–MAX11629/MAX11632/

MAX11633 to the default power-up state.

Table 2. Conversion Register*

*See below for bit details.

BIT

NAME BIT FUNCTION

— 7 (MSB) Set to 1 to select conversion register.

CHSEL3 6 Analog input channel select.

CHSEL2 5 Analog input channel select.

CHSEL1 4 Analog input channel select.

CHSEL0 3 Analog input channel select.

SCAN1 2 Scan mode select.

SCAN0 1 Scan mode select.

— 0 (LSB) Don’t care.

CHSEL3 CHSEL2 CHSEL1 CHSEL0 SELECTED

CHANNEL (N)

0 0 0 0 AIN0

0 0 0 1 AIN1

0 0 1 0 AIN2

0 0 1 1 AIN3

0 1 0 0 AIN4

0 1 0 1 AIN5

0 1 1 0 AIN6

0 1 1 1 AIN7

1 0 0 0 AIN8

1 0 0 1 AIN9

1 0 1 0 AIN10

1 0 1 1 AIN11

1 1 0 0 AIN12

1 1 0 1 AIN13

1 1 1 0 AIN14

1 1 1 1 AIN15

SCAN1 SCAN0 SCAN MODE (CHANNEL N IS

SELECTED BY BITS chsel3–chsel0)

0 0 Scans channels 0 through N.

0 1 Scans channels N through the highest

numbered channel.

1 0 Scans channel N repeatedly. The averaging

1 1 No scan. Converts channel N once only.

MAX11626–MAX11629/

MAX11632/MAX11633

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Table 3. Setup Register*

*See below for bit details.

*For the MAX11626/MAX11627, CNVST has its own dedicated pin.

BIT NAME BIT FUNCTION

— 7 (MSB) Set to 0 to select setup register.

— 6 Set to 1 to select setup register.

CKSEL1 5 Clock mode and CNVST conguration. Resets to 1 at power-up.

CKSEL0 4 Clock mode and CNVST conguration.

REFSEL1 3 Reference mode conguration.

REFSEL0 2 Reference mode conguration.

— 1 Don’t care.

— 0 (LSB) Don’t care.

CKSEL1 CKSEL0 CONVERSION CLOCK ACQUISITION/SAMPLING CNVST CONFIGURATION

0 0 Internal Internally timed CNVST

0 1 Internal Externally timed through CNVST CNVST

1 0 Internal Internally timed AIN15/AIN11/AIN7*

1 1 External (4.8MHz max) Externally timed through SCLK AIN15/AIN11/AIN7*

REFSEL1 REFSEL0 VOLTAGE REFERENCE AutoShutdown

0 0 Internal Reference off after scan; need

wake-up delay.

0 1 External Reference off; no wake-up delay.

1 0 Internal Reference always on; no wake-up

delay.

1 1 Reserved Reserved. Do not use.

MAX11626–MAX11629/

MAX11632/MAX11633

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Table 4. Averaging Register*

Table 5. Reset Register

*See below for bit details.

BIT NAME BIT FUNCTION

— 7 (MSB) Set to 0 to select averaging register.

— 6 Set to 0 to select averaging register.

— 5 Set to 1 to select averaging register.

AVGON 4 Set to 1 to turn averaging on. Set to 0 to turn averaging off.

NAVG1 3 Congures the number of conversions for single-channel scans.

NAVG0 2 Congures the number of conversions for single-channel scans.

NSCAN1 1 Single-channel scan count. (Scan mode 10 only.)

NSCAN0 0 (LSB) Single-channel scan count. (Scan mode 10 only.)

AVGON NAVG1 NAVG0 FUNCTION

0 x x Performs one conversion for each requested result.

1 0 0 Performs four conversions and returns the average for each requested result.

1 0 1 Performs eight conversions and returns the average for each requested result.

1 1 0 Performs 16 conversions and returns the average for each requested result.

1 1 1 Performs 32 conversions and returns the average for each requested result.

NSCAN1 NSCAN0 FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)

0 0 Scans channel N and returns four results.

0 1 Scans channel N and returns eight results.

1 0 Scans channel N and returns 12 results.

1 1 Scans channel N and returns 16 results.

BIT NAME BIT FUNCTION

— 7 (MSB) Set to 0 to select reset register.

— 6 Set to 0 to select reset register.

— 5 Set to 0 to select reset register.

— 4 Set to 1 to select reset register.

RESET 3 Set to 0 to reset all registers. Set to 1 to clear the FIFO only.

x 2 Reserved. Don’t care.

x 1 Reserved. Don’t care.

x 0 (LSB) Reserved. Don’t care.

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

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Power-Up Default State

The MAX11626–MAX11629/MAX11632/MAX11633

power up with all blocks in shutdown, including the refer-

ence. All registers power up in state 00000000, except

for the setup register, which powers up in clock mode 10

(CKSEL1 = 1)

Output Data Format

Figures 4–7 illustrate the conversion timing for the

MAX11626–MAX11629/MAX11632/MAX11633. The

12-bit conversion result is output in MSB-first format with

four leading zeros. DIN data is latched into the serial

interface on the rising edge of SCLK. Data on DOUT tran-

sitions on the falling edge of SCLK. Conversions in clock

modes 00 and 01 are initiated by CNVST. Conversions

in clock modes 10 and 11 are initiated by writing an input

data byte to the conversion register. Data output is binary.

Internally Timed Acquisitions and

Conversions Using CNVST

Performing Conversions in Clock Mode 00

In clock mode 00, the wake-up, acquisition, conversion,

and shutdown sequences are initiated through CNVST

and performed automatically using the internal oscillator.

Results are added to the internal FIFO to be read out

later. See Figure 4 for clock mode 00 timing.

Initiate a scan by setting CNVST low for at least 40ns

before pulling it high again. The MAX11626–MAX11629/

MAX11632/MAX11633 then wake up, scan all requested

channels, store the results in the FIFO, and shut down.

After the scan is complete, EOC is pulled low and the

results are available in the FIFO. Wait until EOC goes low

before pulling CS low to communicate with the serial inter-

face. EOC stays low until CS or CNVST is pulled low again.

Do not initiate a second CNVST before EOC goes low;

otherwise, the FIFO can become corrupted.

Externally Timed Acquisitions and

Internally Timed Conversions with CNVST

Performing Conversions in Clock Mode 01 In clock

mode 01, conversions are requested one at a time using

CNVST and performed automatically using the internal

oscillator. See Figure 5 for clock mode 01 timing.

Setting CNVST low begins an acquisition, wakes up the

ADC, and places it in track mode. Hold CNVST low for at

least 1.4μs to complete the acquisition. If the internal ref-

erence needs to wake up, an additional 65μs is required

for the internal reference to power up.

Set CNVST high to begin a conversion. After the conver-

sion is complete, the ADC shuts down and pulls EOC low.

EOC stays low until CS or CNVST is pulled low again.

Wait until EOC goes low before pulling CS or CNVST low.

If averaging is turned on, multiple CNVST pulses need to

be performed before a result is written to the FIFO. Once

the proper number of conversions has been performed

to generate an averaged FIFO result, as specified by the

averaging register, the scan logic automatically switches

the analog input multiplexer to the next-requested chan-

nel. The result is available on DOUT once EOC has been

pulled low.

Figure 4. Clock Mode 00 Timing

(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)

DOUT

MSB1 LSB1 MSB2

SCLK

CNVST

EOC

SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.

MAX11626–MAX11629/

MAX11632/MAX11633

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Internally Timed Acquisitions and

Conversions Using the Serial Interface

Performing Conversions in Clock Mode 10

In clock mode 10, the wake-up, acquisition, conversion,

and shutdown sequences are initiated by writing an input

data byte to the conversion register, and are performed

automatically using the internal oscillator. This is the

default clock mode upon power-up. See Figure 6 for clock

mode 10 timing.

Initiate a scan by writing a byte to the conversion register.

The MAX11626–MAX11629/MAX11632/MAX11633 then

power up, scan all requested channels, store the results

in the FIFO, and shut down. After the scan is complete,

EOC is pulled low and the results are available in the

FIFO. EOC stays low until CS is pulled low again.

Externally Clocked Acquisitions and

Conversions Using the Serial Interface

Performing Conversions in Clock Mode 11

In clock mode 11, acquisitions and conversions are initiat-

ed by writing to the conversion register and are performed

one at a time using the SCLK as the conversion clock.

Scanning and averaging are disabled, and the conversion

result is available at DOUT during the conversion. See

Figure 7 for clock mode 11 timing.

Figure 5. Clock Mode 01 Timing

Figure 6. Clock Mode 10 Timing

DOUT

SCLK

CNVST

EOC

(CONVERSION2)

MSB1 LSB1 MSB2

(ACQUISITION1) (ACQUISITION2)

(CONVERSION1)

REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION.

(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)

MSB1 LSB1 MSB2

(CONVERSION BYTE)

DOUT

SCLK

DIN

EOC

THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED.

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MAX11632/MAX11633

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Initiate a conversion by writing a byte to the conversion

between the eight and ninth cycles, the pulse width must

be less than 100μs. To continuously convert at 16 cycles

per conversion, alternate 1 byte of zeros between each

conversion byte.

If reference mode 00 is requested, wait 65μs with CS high

after writing the conversion byte to extend the acquisition

and allow the internal reference to power up.

Partial Reads and Partial Writes

If the first byte of an entry in the FIFO is partially read (CS

is pulled high after fewer than eight SCLK cycles), the

second byte of data that is read out contains the next 8

bits (not b7–b0). The remaining bits are lost for that entry.

If the first byte of an entry in the FIFO is read out fully, but

the second byte is read out partially, the rest of the entry

is lost. The remaining data in the FIFO is uncorrupted

and can be read out normally after taking CS low again,

as long as the 4 leading bits (normally zeros) are ignored.

Internal registers that are written partially through the SPI

contain new values, starting at the MSB up to the point

that the partial write is stopped. The part of the register

that is not written contains previously written values. If CS

is pulled low before EOC goes low, a conversion cannot

be completed and the FIFO is corrupted.

Transfer Function

Figure 8 shows the unipolar transfer function. Code tran-

sitions occur halfway between successive-integer LSB

values. Output coding is binary, with 1 LSB = VREF/2.5V

(MAX11627/MAX11629/MAX11633) and 1 LSB =

VREF/4.096V (MAX11626/MAX11628/MAX11632).

Layout, Grounding, and Bypassing

For best performance, use PCBs. Do not use wire wrap

boards. Board layout should ensure that digital and

analog signal lines are separated from each other. Do

not run analog and digital (especially clock) signals par-

allel to one another or run digital lines underneath the

MAX11626–MAX11629/MAX11632/MAX11633 package.

High-frequency noise in the VDD power supply can affect

performance. Bypass the VDD supply with a 0.1μF capac-

itor to GND, close to the VDD pin. Minimize capacitor lead

lengths for best supply-noise rejection. If the power sup-

ply is very noisy, connect a 10Ω resistor in series with the

supply to improve power-supply filtering.

Figure 7. Clock Mode 11 Timing

Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF

DOUT

SCLK

DIN

EOC

MSB1 LSB1 MSB2

(ACQUISITION1) (ACQUISITION2)

(CONVERSION1)

(CONVERSION BYTE)

EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

1 2 3

(COM)

FS - 3/2 LSB

FS = VREF + VCOM

ZS = VCOM

INPUT VOLTAGE (LSB)

1 LSB =

VREF

4096

MAX11626–MAX11629/

MAX11632/MAX11633

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Denitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function,

once offset and gain errors have been nullified. INL for the

MAX11626–MAX11629/MAX11632/MAX11633 is mea-

sured using the end-point method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1 LSB. A DNL

error specification of less than 1 LSB guarantees no miss-

ing codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in

the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time between the rising edge

of the sampling clock and the instant when an actual

sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, signal-to-noise ratio (SNR) is the ratio of the full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The ideal, theoretical minimum ana-

log-to-digital noise is caused by quantization error only

and results directly from the ADC’s resolution (N bits):

SNR = (6.02 x N + 1.76)dB

In reality, there are other noise sources besides quantiza-

tion noise, including thermal noise, reference noise, clock

jitter, etc. Therefore, SNR is calculated by taking the ratio

of the RMS signal to the RMS noise, which includes all

spectral components minus the fundamental, the first five

harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to the

RMS equivalent of all other ADC output signals:

SINAD (dB) = 20 x log (SignalRMS/NoiseRMS)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC error consists of quantiza-

tion noise only. With an input range equal to the fullscale

range of the ADC, calculate the effective number of bits

as follows:

ENOB = (SINAD - 1.76)/6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

()

2222

2 3 4 51

THD 20 x log V V V V /V



= +++





where V1 is the fundamental amplitude, and V2–V5 are

the amplitudes of the first five harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of the

RMS amplitude of the fundamental (maximum signal

component) to the RMS value of the next-largest distor-

tion component.

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

www.maximintegrated.com Maxim Integrated

│

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

16 QSOP E16+5 21-0055 90-0167

24 QSOP E24+1 21-0055 90-0172

EOC

DOUT

DIN

AIN3

AIN2

AIN1

AIN0

TOP VIEW

SCLK

VDD

GND

REFAIN7

AIN6

AIN5

AIN4

AIN14

CNVST/AIN15

AIN13

AIN12AIN11

AIN10

AIN9

AIN8

QSOP

MAX11632

MAX11633

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

www.maximintegrated.com Maxim Integrated

│

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

Chip Information

PROCESS: BiCMOS

Pin Congurations

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 6/10 Initial release —

1 8/10 Initial release of MAX11628/MAX11629 and changed internal reference voltage 1

2 3/11 Added MAX11628 automotive qualied part to data sheet 1

3 10/11 Initial release of MAX11626/MAX11627 1

4 10/11 Updated the Electrical Characteristics, Typical Operating Characteristics global,

and Time Differential Analog Input T/H section. 2–9, 13

5 9/14 Removed automotive designation from Ordering Information 1

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

│

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.