80C186/80C188 CMOS High-Integration 16-Bit Microprocessors al Advanced Micro Devices DISTINCTIVE CHARACTERISTICS H Operation Modes Include Enhanced mode with DRAM Refresh Control Unit Power-save mode Compatible Mode NMOS 80186/80188 pin-for-pin replacement for non-numerics applications @ Integrated Feature Set Enhanced 80C86/C88 CPU Clock generator Two independent DMA channels -Programmable interrupt controller Three programmable 16-bit timers -~Dynamic RAM refresh control unit Programmable memory and peripheral chip select logic Programmable wait-state generator Local bus controller Power-save mode System-level testing support (high-impedance test mode) @ Available in 25-MHz, 20-MHz, 16-MHz, 12.5-MHz, and 10-MHz versions @ Direct addressing capability to 1-Mbyte of memory and 64-Kbyte I/O @ Fully static CMOS design @ Completely object code compatible with all existing 8086/8088 software. Has ten additional instructions over 8086/8088. m Complete system development There are many vendors making support tools for the 80C186/C188. Software tools for the NMOS 80186/80188 can be used for the 80C0186/C188 as can the NMOS emulators @ Available in 68-Pin Plastic Leaded Chip Carrier (PLCC) 80-Pin Thin Quad Flat Pack (TQFP) 80-Pin Plastic Quad Flat Pack (PQFP) |n Trimmed/Formed Configuration GENERAL DESCRIPTION The 80C186/C188 is a CMOS _high-integration microprocessor. It has features that are new to the 80186/80188 Family, which include a DRAM refresh control unit, and power-save mode. When used in compatible mode, the 80C186/C188 is 100% pin-for-pin compatible with the NMOS 80186/80188 (except for 8087 applications). The Enhanced mode of operation allows the full feature set of the 80C 186/C 188 to be used. The 80C186/ 80C188 is upward compatible with 8086 and 8088 software and fully compatible with 80186 and 80188 software. www.DataSheet4U.com Issue Date: June 1994 product without notice. Publication #: 17907 Rey. B Amendment /0 | This document contains information on a product under development at Advanced Micro Devices, Inc. The information 1 is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposedcl AMD PRELIMINARY 800186 BLOCK DIAGRAM INT3/INTATARQ 4 INT2/iNTAO NMI TMR OUTO TMR OUT1 4 (SEL a 4 CLKOUT INTVSELECT | Typ ino | TMR IN1 DRQ0 ~~ DRY doh #4 INTO j q j y Programmable DMA Control Timers Unit Vee X1 X2 c ! 5 , Max Count Y 20-Bit Clock Programmable Register B i, Source Pointers Generator Interrupt Max Count 20-Bit GND Controller Register A Destination Pointers Power Save 16-Bit 16-Bit Count Registers Count Regist Control Control g erres Registers Registers Control Registers Control Registers | 4h Internal Bus ff SRDY Ready Control | Refresh | } Execution Unit | Control PGSE/ Lagic Registers | Control ' ARDY ontro Registers Al Unit 52-0 16-Bit ' General ' DT/R Segment Registers Chip Select PCS6/ . Registers Bus Interface Control Unit I ao EN Unit \ Tock Profetch 16-Bit L < Queue ALU _. __ MCSO HOLD ALE/QSO TEST __ POS4PCS0 v v_ MCS1 v HLDA RES 4 RD/QSMD 1 y ics TD MCS3 aS AD15-ADO RESET WR/QS1 Ucs v v A19/S6-A16/S3 BHE MCS2 www.DataSheet4U.com 80C186/80C188 MicroprocessorsPRELIMINARY amp ot 800188 BLOCK DIAGRAM INTSANTAT/IRQ NMI 4 INT2ANTAO TMR OUTO TMR OUTI d (SELECT 4 4 CLKOUT INTVSELECT foie ino f Tur int DRQ0 RAY ih 4 INTO d q q r Programmable DMA Control Timers Unit Veo x0 0 1 2 0 1 x1 Max Count 7 20-Bit Clock Programmable Register B i) Source Pointers Generator Interrupt Max Count 20-Bit GND Controller Register A Destination Pointers Power Save 16-Bit 16-Bit Count Registers Cc i Control Contral + 3 curt Registers Registers Registers Control Registers Control Registers t fl Internal Bus st ff Uf S2eecoeey 2 SRDY Ready Control | Refresh | * Execution Unit ! a Lagic Registers t Control Lt POSS ARDY 9 9 Control : | Registers A nr ' 55-50 16-Bit S2 soC General DTA + Segment Registers Chip Select PGSa/ ae Registers Bus Interface Control Unit TT ao _ Byte ven 1e-pit | + LOCK Prefetch ALU 1 Queue _.! v v HOLD ALE/QSO TEST MCSO PCS4-PCSO v v_ v v HLDA RES y y RD/IQSMD McST | y lcs AD7-ADO RESET WR/QS1 MCS3 Ucs v v A19/S6-A16/S3, RFSH MCS2 A15-A8 13088B-001 www.DataSheet4U.com 80C186/80C188 Microprocessors 3A amo PRELIMINARY 80C186 CONNECTION DIAGRAMS 68-Pin Plastic Leaded Chip Carrier (PL 068) \ 68 FI A16/S3 67 F2 A17/S4 66 FO Ai8/S5 65 [2 A19/S6 64 F 9 BHE 63 &2 WRaS1 62 [> RD/QSMD 61 F ALE/aso jo 60 FJ Vss 57 [2 RESET 56 - CLKOUT 55 [3 ARDY 59 [7 X1 538 [ X2 54 3 82 53 Fo 57 52 [So AbDi5 Co AD7 CS AD14 Co AD6 [4 AD13 CS AD5 ADi2 Co AD4 Veco AD11 CS AD3 AD10 Co AD2 (> ADS CS AD1 Co AD8 Co ADO cS oP ert on ron se aoa ae oe ee NO OQ & WOW MH + OC co 29 cS 31 CS 32 Pcs4 C4 30 co 24 cc 25 CS 26 co 2 cS 238 a] DRQi Co 19 TMRINO C4 20 TMRIN1 Co 21 DRQo CS 18 TMROUTO Coy 22 LCS UCS PCSO Vss RE PCS1 PCS2 PCS3 PCS5/A1 PCOS5/A2 TMROUT1 C4 23 Note: Pin One marked for orientation purposes only. www.DataSheet4U.com cy 33 co 34 51 50 49 48 47 46 45 44 43 42 At 40 39 38 37 36 35 UUTOODGUYUOUUUUUUo INT1 Vee INT2/INTAO INTS/INTAT 4 80C186/80C188 MicroprocessorsPRELIMINARY AMD &h 800186 CONNECTION DIAGRAMS (continued) 80-Pin Plastic Quad Flat Pack (PQR 80) wt oy N - Q ~ Tr O r HO r- Tt o ox or nw Dr qgqoaqaaqnagag gs spsagaanwanaa <atadtqdatatcdaetorratctaeaetactactc LODE AOA OOO / oOomomoen owt OWN er COC OOhmem oO DH en en a be a a a <9 A) ADIs C4 1e 64 ADO Neo C4 2 63 Fo NC Aie/s3 C4 3 62 [9 NC Ai7/s4 Coy 4 61 Fo DRQo Aies5 Cy 5 60 F= pRat A19/sg Cy & 59 [3 TMRINOo poe CO 7 58 [= TMRIN1 WRasi Cj 8 57 [= TMROUTO Ro/asmp CH 3 56 [3 TMROUTI ALE/Qso [4 10 55 [= AES wo C4 1 54 [2 PGSO Vss CO 12 53 = Vss Vss C=] 13 52 FC] pcsi No Cy 14 51 poss nro F415 50 Fo PCSs3 x; Eq 16 49 [ Pcsa Xo CE 17 48 [> PCSS/AI RESET co 18 47 E23 BCSa/A2 cLKoUT [4 19 46 [4 [cs ARDY C4 20 45 E UGS Se co 21 44 Eo] NS St cy 22 43 E93 NC So Co 23 42 - mGSs3 NC CS 24 41 Ea mcs2 woonr vonoeried otro onrenemwmnoa NNNNN OOOOH OOOH YM OM HM THT td ! to> rFSsPr8 8 eGic 8 : Se Se o 6 = a O77 Aw E b > > <r i Am Wm Oo 22 |i Eek GO 1d TIG6ee bi Z : a 's fs cn qi ie ~ -E 5 Ee Zz g < 5 Zz Notes: 1. Pin 1 is marked for orientation purposes only. 2, NC = Not connected. www.DataSheet4U.com 80C186/80C188 Microprocessors 5Pa AMD PRELIMINARY 800186 CONNECTION DIAGRAMS (continued) 80-Pin Thin Quad Flat Pack Top View EE =a S522 xt < e@+rZZ0900 2 - IW [It 1 1S ge REFS RB eB BE BBB BE s > OorrFrrFFEFMe Zo S>e ee hee ap > IHH ONAN hin ininniiih SeEPRLPKF LNT LSSES RISES ADO Co te 60-3 ADs Cj 2 59 ADI C= 3 5839 Nic CS 4 57 co ADS c= 5 56 AD2 J 6 55 AD1O C7 549 AD3 8 533 ADI co 9 5269 Voo C=] 10 51-3 Veco Co 11 50-3 AD4 Co] 12 4969 ADi2 C4 13 48-5 ADS Co 14 475 AD13 Cj 15 46-5 AD6 Cj 16 453 AD14 Co 17 445 Ab7 Co 18 423 AD15 Go 19 ae Vee E=] 20 415 ANKRARKRKRAABESEHEBSRSESEBBSSY UUUGUUUUUUUU UU UU <<< BB = 3 Notes: 1.Pin 1 is marked for orientation purposes only. 2. N/C = Not connected. me 0257525 0049573 198 N/C DT/R INT3/INTAT/AIRQ INT2/INTAO Vee Vee INT1/SELECT INTO NMI TEST COCK SRDY HOLD HLDA Ves 80C186/80C188 MicroprocessorsPRELIMINARY 80C186 PIN DESIGNATIONS (sorted by Pin Name) AMD al signal recognition by the processor. A(E) = Edge Sensitive A({L) = Level Sensitive Oes75e5 0849574 Och Mi. R(t} = R(0) = ; Pin Number Pin Number Pin Name _[PLcc|PaFP|TGFP Code PinName | picc | PGFP| TQFP Code A19/S6 65 | 6 | 24 MCSO 38 39 57 _|VO, HA(1), R(PU) A18/S5 66 5 23 AI7/S4 67 4 29 O, HA(Z), R(Z) MCS1 37 40 58 |I/O, HA(1), R(PU) A16/S3 68 | 3 | 21 MCS2 36 41 59 10, HA(t b R(PU) ADI5 1 1 19 MCS3 35 42 60 O, HA(1}, R(PU) nots 3 6 i NMI 46 30 47 I, S(E} 5 5 AD12 7175 | 43 PCS5/A1 31 48 65 | 0, HA(X), R(T) AD11 10 | 71 9 PCSE/A2 32 47 64 | O, HA(X), R(1) AD10 12 | 69 7 DOGA PCS4 30 49 66 Ae 3 ee 3 PCS3 29 50 67 VO, S(L), HA(Z), R(Z) ]{PES2 28 51 68 | 0, HA(T), A(t) AD7 2 | 80 |} 18 (1), FAIZ), BIZ) PCS 27 52 69 AD6 4 | 78 | 16 PCSO 25 54 71 AD5 6 76 | 14 BHOSHD ADA 3 | 74 | qe RD/QSMD| 62 9 28 [VO, HA(Z), R(PU) AD3 11170] 8 RES 24 55 73 I, S(L) ADS i" ee : RESET 57 18 34 O, HA(A) ADO 17164) 4 S2-SO6 64, 53, 52 P1, 22, 2388, 39, 40) O, HAZ), R(Z) ALE/QSO 61 | 10 | 29 O, HA(0), FO) SRDY 49 a7 44 1, S(L) ARDY 55 | 20 | 37 LAL) TEST 47 29 46 1, R(PU) = TMRINO 20 59 77 BHE 64 7 26 O, HA(Z), R(Z) TMRIN1 4 58 76 |, S(E) CLKOUT 56 | 19 | 36 O, HA(A), R(A) TMROUTO 2D 57 75 0, HAA}, R(t) DEN 39 | 38 | 56 O, HA(Z), RZ} TMROUT1 23 56 74 , , DRQa, DRQi_ |18, 19161, 60/79, 78 I, S(L) ucs 34 45 62 {/0, HA(1), R(PU) DT/R 40 37 54 O, HA(Z), R(Z} 9 33 61,10 HOLD 50 | 26 | 43 1, SL) Veo 43 | ott | HLDA 51 | 25 | 42 O, HA(A), R(0) - 73 20 INTO 45 | 31 48 |, ACE, L) WR/QS1 63 8 27 0, HA(Z), R(Z) INTI/SELECT | 44 | 32 | 49 |, A(E, L) V 26 12 30, 70 INT2INTAO | 42 | 35 | 52 [/0,A(E,b), HA(X), R@II SS 60 BL ue | INTSANTATARQ 41_{ 36 | 53 |V/O, A(E, L), HAQO, RZ) Ry 59 16 32 LCS 33 4 46 | 63 VO, HA(1), R(PU) X2 58 7 33 0 LOCK 48 | 28 | 45 O, HA(Z), R(PU) On the PQFP package, the following pins are N/C (No Connect): 2, 11, 14, 15, 24, 43, 44, 62, and 63. On the TQFP package, the following pins are N/C (No Connect): 4, 25, 35, 55, and 72. Key to Pin Description Codes Symbol Description Symbol Description I Input Only HA(x) | Hold Acknowledge: Pin state while processor is i" the Hold Acknowledge state. 0 Output Only HA(1) = Internally driven to Veo vO Input or Output (depending on situation) HA(0) = Internally driven to Vgg S(x)__ | Synchronous: Setup and Hold times must HA(Z) = Internally floated be met for praper operation. HA(A) = Remains active S(E) = Edge Sensitive HA(X) = Retains current state S(L) = Level Sensitive R(x) | Reset: Pin state while the processors RES A(x) Asynchronous: Setup and Hold times guarantee line is held Low externally. Internally driven to Voc Internally driven to Vgs R(Z) = Internally floated R(A) = Remains Active R(PU) = R(PD) = Weak internal pull-u Weak internal pull-down Pp 80C186/80C188 Microprocessorsol amo PRELIMINARY 800188 CONNECTION DIAGRAMS 68-Pin Plastic Leaded Chip Carrier (PL 068) SH 68 F A16/S3 67 FO A17/S4 66 F A18/S5 65 [2 A19/S6 63 [1 WR/QS1 62 9 RD/QSMD i ALE/QSO 60 > Vss 57 (3 RESET 56 FO CLKOUT 55 [= ARDY 64 4 59 [3X1 58 Fo X2 54 4 $2 53 Fo 57 52 7 50 61 At5 Co AD? co A14Co AD6 C4 Ai3 Co ADS Co Ai2 Co AD4 co Voc AW co AD3 Co A10 C4 AD2 CJ Ag cI ADI C4 As Co ADO C9 se ern eanRense _ os os oss se N Oo ff O MY + CO CF 29 co 3 cy 32 cy 33 cs Cy 34 PCs4 C4 30 Co 25 Vss Co 26 CS 27 cy 28 Res Co 24 RES DRQi Co 19 PCSO DRQG Co 18 TMRINO Co 20 Pcs2 PCS3 PCSi TMRIN1 Co 21 TMROUTO Lo 22 PCS5/A1 PCS6/A2 TMROUT1 CH 23 Note: Pin One marked for orientation purposes only. mm 0257525 0049575 Tho = 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 UUUTUTODUUUUUUUUY HLDA HOLD SRDY LOCK TEST NMI INTO INT1 Vec INT2/INTAO INT3/NTAT DT/R 8 80C186/80C188 MicroprocessorsPRELIMINARY 800188 CONNECTION DIAGRAMS (continued) 80-Pin Plastic Quad Fiat Pack (PQR 80) UUUUUUUUUUUUUUUUU UU B27 aAa2aX8hzserBs bode eqeqeqcqctctcsrate ecectie Sf oo mor O WO FON N rT oawsmsenrvo wm co nn nmonoeeReeReReoMmeMHe ER O O O Ais Cy te 64 NG Co 2 63 Ai6/S3 Cy 3 62 Ai7/S4 Co 4 61 A1igs/S5 Co 5 60 Aig/s6 Co 6 59 RFSH Co 7 58 WwR/QS1 Co 8 57 RD/ASMD Co Q 56 ALE/QSo =] 10 55 NC co 1 54 Vss Co 12 53 Vss Coy 13 52 N/C Eo 14 51 No coy 15 50 Xi Co 16 49 xX2 cS i7 48 RESET Co 18 47 CLKOUT Co 19 46 ARDY Co 20 45 go Co 241 44 S| Cy 22 43 s Cy 23 42 NiO Cy 24 41 oon onoewrnrent owtwoornr OD Oo NNNNNMON YH YN ON YN OH HM + ~~ UVUUUUUCUTUoUoooo <Orpy E Sere g Poe zh io o-7 alo Z2EoLS & KEE ia 6 oO weer > EEE O e && = z iz cL Zi 2 & Z Notes: 1. Pin 1 is marked for orientation purposes only. 2. N/C = Not connected. ME 0257525 COu3S7& IT? oe AMD a ADO N/C N/C DRQo DRQi TMRINO TMRIN1 TMROUTO TMROUT1 80C186/80C188 MicroprocessorsON amp PRELIMINARY 800188 CONNECTION DIAGRAMS (continued) 80-Pin Thin Quad Flat Pack Top View 2555 << , S822 ffe. 8 RRB BRE we e > aaQgqgrFrF FFA aZ Oo >i fb oO ooo ab > DOONAN AAAI inno ooo i ZBSLLRLKLTLKKLGSSSLBELES ADO Co 1 60-2 MCSs3 ADs CI 2 593 MCS2 AD1 C4 3 58 NCSI nic Co 4 573 MCSO ADg Cy 5 56 DEN AD2 TJ 6 55F3 NC ADi0 C7 54-9 DTA AD3 Co 8 533 INT3ANTAT/IRQ ADI1 Co 9 52 (79 INT2/INTAO Voce Ce] 10 512] Voc Veco Eq 11 50 E> Vec AD4 Ho 12 49 E> INTI/SELECT AD12 Cj 13 48 (2 = INTO AD5 Coy 14 47 E> NMI AD13 Ga 15 4607 TEST AD6 Co 16 45-9 [OCcK AD14 Co 17 445 SRDY AD7 Co 18 43 E23 HOLD AD15 C4 19 42155 HLDA Voc =] 20 41 Vos SNRARKRAAARSHSSBABRKRESRSS VUUUUT UU UCU UU Uo eezz FERS = 30 ic Notes: 1.Pin 1 is marked far orientation purposes only. 2. N/C = Not connected. Me 0257525 0049577 433 10 80C186/80C188 MicroprocessorsPRELIMINARY 800188 PIN DESIGNATIONS (sorted by Pin Name) AMD al M@ 0257525 OO49S74 77T Pin Number Pin Number Pin Name fp_ccParP|TarP Code Pin Name! picc | parp | TOFP Code A19/S6 65 6 24 MCS1 37 40 58 O, HA(1), R(PU) A18/S5 66 5 23 A17/S4 87 4 22 O, HA(Z), R(Z) MCS2 36 41 59 O, HA(1), R(PU) A16/S3 68 3 21 MCS3 35 42 60 O, HA(1), R(PU) Als 1 1 19 A14 4 7a | 47 NMI 46 30 47 |, S(E) A13 5 77 | 15 PCS5/A1 31 48 65 O, HA(X), A(1) Al2 7 75 | 13 PCS6/A2 32 47 64 | O, HAOS, A(t) AN 10 a PCS4 30 49 66 Ato 2 || 7 ress | 20 | so | er AS 16 65 2 PCS2 28 51 68 O, HA(1), R(1) PCS1 27 52 69 AT 2 80 | 18 | W/O, S(L), HA(Z), R(Z) {[ECS 25 54 an AG 4 78 | 16 RD/QSMD| 62 9 28 = 11/0, HA(Z), R(PU AS 6 76 14 Ad 8 va | 42 RES 24 55 73 1, S(L) A3 11 70 8 RESET 57 18 34 O, HA(A) A2 13 | 68 | 6 RESH 64 7 26 HA(Z), R(Z) A2 15 66 3 S550 AG 17 64 4 54, 53, 52/21, 22, 23|38, 39, 40] O, HA(Z), R(Z) ALE/QSO et | 10 | 29 0, HA(O), R(O) SRDY 49 a7 44 1 S(L) ARDY eT 0 | a7 TA) TEST 47 29 46 |, R(PU) TMRIN1 20 59 76 CLKOUT 56 19 | 36 O, HA(A), RA) TMRINO 4 58 77 1, S(E) DEN 39 38 | 56 O, HA(Z), R(Z) TMROUTI 22 57 74 0, HANA), FCI) DRQO, DRQ1_ /18, 1961, 60/79, 78 I, S(L) TMROUTO 23 56 75 , DT/R 40 37 | 54 O, HA(Z), R(Z) UCS 34 45 62 |V/O, HA(1), R(PU HOLD 50 26 | 43 |, S(L) 9 33 61,10 HLDA 51 | 25 | 42 O, HAVA), R(0) Voc 43 5 OL feo INTO 45 31 48 1, ACE, L) - 73 20 INTI/SELECT | 44 32 | 49 i, ACE, L) WR/QS1 63 8 27 O, HA(Z), R(Z) INT2ANTAO 42 35 | 52 | 1/0, A(E, L), HA(X), R(Z) V 26 12 30, 70 INTSINTATIRG] 41 | 36 | 53 |V/0, A(E, L), HA(X), A(Z}|| 8S 60 Bl MP | tcs 33 46 | 63 VO, HA(1)}, R(PU) X 59 16 32 LOCK 48 | 28 | 45 O, HA(Z), R(PU) Xo 58 17 33 0 MCSO 38 39 | 57 O, HA(1), R(PU) On PQFP package the following pins are N/C (No Connect}: 2, 11, 14, 15, 24, 43, 44, 62, and 63. On TQFP package the fallawing pins are N/C (No Connect): 4, 25, 35, 55, 72. Key to Pin Description Codes Symbol! Description Symbol Description | Input Only HA(x) | Hold Acknowledge: Pin state while processor is in the Hold Acknowledge state. Qo Output Only HA(1) = Internally driven to Vee vO Input or Output {depending on situation) HA(O) = Internally driven to Vss S(x) | Synchronous: Setup and Hold times must HA(Z) = Internally floated be met for proper operation. HA(A) = Remains active S(E) = Edge Sensitive HA(X) = Retains current state S(L) = Level Sensitive A(x) Reset: Pin state while the processor's RES : ; line is held Low externally. A(x) Asynchronous: Setup and Hold times guarantee + signal recognition by the processor. R(1) = Internally driven to Voc ~ a: R(0) = Internally driven to Vsg A(E) = Edge Sensitive A(L) = Level Sensiti R({Z) = Internally floated (L) = Level Sensitive R(A) = Remains Active R(PU) = Weak internal pull-up R(PD) = Weak internal pull-down 80C186/80C188 Microprocessors 11cl AMD 800186 ORDERING INFORMATION Commodity Products PRELIMINARY AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. N socias 12 Valid Combinations N80C 186, IN80C186 N80C186-12, IN80C 186-12 PLOC N80C 186-16, IN80C186-16 SPEED OPTION Blank = 10 MHz -12 = 12.5MHz -16 = 16MHz -20 = 20 MHz -25 = 25MHz DEVICE NUMBER/DESCRIPTION 800186 CMOS High-Integration 16-Bit Microprocessor PACKAGE TYPE N =68-Pin Plastic Leaded Chip Carrier S = 80-Pin Plastic Quad Flat Pack SB = 80-Pin Thin Quad Flat Pack TEMPERATURE RANGE Industrial (-40C to +85C) Commercial (0C to +70C} | Blank Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly rel d combinations. N80C 186-20, IN80C 186-20 N80C 186-25 $8001 86 PQFP $80C186-12 Trimmed $80C186-16 and Formed $800186-20 $80C 186-25 SB80C 186 SB80C 186-12 TOFP SB80C186-16 SB80C186~20 SB80C 186-25 we 0257525 0049579 &bOb = 12 80C186/80C188 MicroprocessorsPRELIMINARY amp A 800188 ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. N gocies 12 Valid Combinations N80C 188, IN80C188 N80C 188-12, IN80C-188-12 PLoC N80C 188-16, IN80C 188-16 N80C 188-20, IN80C 188-20 N80C 188-25 $80C188 PQFP $800 188-12 Trimmed $80C188-16 and Formed $80C188-20 $80C1 88-25 SB80C188 $B80C188-12 TQFP SB80C188-16 $B80C188-20 SB80C 188-25 MM! 0257525 0049580 328 oe SPEED OPTION Blank = 10 MHz 12 = 12.5 MHz -16 = 16MHz -20 = 20MHz -25 = 25 MHz DEVICE NUMBER/DESCRIPTION 800188 CMOS High-Integration 16-Bit Microprocessor PACKAGE TYPE N =68-Pin Plastic Leaded Chip Carrier S = 80-Pin Plastic Quad Flat Pack SB = 80-Pin Thin Quad Flat Pack TEMPERATURE RANGE | = Industrial (-40C to +85C) Blank = Commercial (0C to +70C) Valid Combinations Valid Combinations list configurations are planned to be supported in volume for this device. Consult the local AMD sales office to confirm the avail- ability of specific valid combinations and to check on newly released combinations. 80C186/80C188 Microprocessors 13cl AMD PRELIMINARY PIN DESCRIPTIONS A19/S6, A18/S5, A17/S4, A16/S3 Address Bus Outputs (Outputs) Address Bus Outputs (19-16) and Bus Cycle Status (6-3) indicate the four most significant address bits dur- ing T1. These signals are active High. During T2, T3, TW, and T4, the S6 pin is Low to indicate a CPU-initiated bus cycle, or High to indicate a DMA-ini- tiated bus cycle. During the same T states, S3, S4, and S5 are always Low. These outputs are floated during bus HOLD or RESET. A15A8 (80C188 only) Address-Only Bus (Outputs) Address-Only Bus (15-8) contains valid addresses from T1-T4. The bus is active High. These outputs are floated during a bus HOLD or RESET. AD7-ADO (80C188 only) Address/Data Bus (Inputs/Outputs) Address/Data Bus (7-0) signals constitute the time mul- tiplexed memory or I/O address (T1) and data (T2, TS, TW, and T4) bus. The bus is active High. These pins are floated during bus HOLD or RESET. AD15-ADO (80C186 only) Address/Data Bus (Inputs/Outputs) Address/Data Bus (15-0) signals constitute the time multiplexed memory or I/O address (T1) and data (T2, T3, TW, and T4) bus. The bus is active High. AQ is analo- gous to BHE for the lower byte of the data bus, pins D7D0. it is Low during Ti when a byte is to be trans- ferred onto the lower partion of the bus in memory or I/O operations. These pins are floated during a bus HOLD or RESET. ALE/QSO Address Latch Enable/Queue Status (Output) Address Latch Enable/Queue Status 0 is provided by the 80C186/C188 to latch the address. ALE is active High, with addresses guaranteed to be valid on the trail- ing edge. ARDY Asynchronous Ready (input) Asynchronous Ready informs the 800186/C188 that the addressed memory space or I/O device will com- plete a data transfer. The ARDY pin accepts a rising edge that is asynchronous to CLKOUT and is active High. The falling edge of ARDY must be synchronized to the 80C186/C188 clock. Connecting ARDY High always asserts the ready condition to the CPU. If this line is unused, it should be tied Low to yield control to the SRDY pin. BHE (80C186 only) Bus High Enable (Output) The BHE (Bus High Enable) signal is analogous to AO in that it is used to enable data on to the most significant half of the data bus, pins D15D8. BHE is Low during T1 when the upper byte is transferred and remains Low through T3 and TW. BHE does not need to be latched. BHE floats during HOLD or RESET. In Enhanced Mode, BHE is also used to signify DRAM refresh cycles. A refresh cycle is indicated by both BHE and AO being High. BHE and AO Encodings BHE AG Value Function | Value 0 0 Word Transfer 0 1 Byte Transfer on upper half of data bus (D8-D1) 1 0 Byte Transfer on lower half of data bus (D7D0) 1 1 Refresh CLKOUT Clock Output (Output) Clock Output provides the system with a 50% duty cycle waveform. All device pin timings are specified relative to CLKOUT. CLKOUT is active during RESET and bus HOLD. DEN Data Enable (Output) Data Enable is provided as a data bus transceiver output enable. DEN is active Low during each memory and I/O access (including 80C 187 access). DEN is High when- ever DT/R changes state. DEN floats during a bus HOLD or RESET. DRQO-DRQ1 DMA Requests (Inputs) DMA Request is asserted High by an external device when it is ready for DMA Channel 0 or 1 to perform a transfer. These signals are level triggered and internally synchronized. DT/R Data Transmit/Receive (Output) Data Transmit/Receive controls the direction of data flow through an external data bus transceiver. When Low, data is transferred to the 800186/C188. When High, the 80C186/C188 place write data on the data bus. DT/R floats during a bus HOLD or RESET. We 0257525 0049581 eby 14 80C186/80C188 MicroprocessorsMM 0e575e5 00495se To me PRELIMINARY HOLD, HLDA (Input, Output) HOLD indicates that another bus master is requesting the local bus. The HOLD input is active High. The 80C186/C188 generate HLDA (High) in response to a HOLD request. Simultaneous with the issuance of HLDA, the 80C186/C 188 will float the local bus and con- trol lines. After HOLD is detected as being Low, the 80C186/C188 lower HLDA. When the 80C186/ 800188 needs to run another bus cycle, it will again drive the local bus and contro! lines. In Enhanced Mode, HLDA goes Low when a DRAM refresh cycle is pending in the 80C186/C188 and an external bus master has control of the bus. It willbe upto the external master to relinquish the bus by lowering HOLD so that the 80C0186/C188 may execute the refresh cycle. INTO, INT1/SELECT, INT2/INTAO, INT3/INTA1/IRQ Maskable Interrupt Requests (Inputs, Input/Output) Maskable Interrupt Requests can be requested by acti- vating one of these pins. When configured as inputs, these pins are active High. Interrupt Requests are syn- chronized internally. INT2 and INT3 may be configured to provide active-Low interrupt-acknowledge output sig- nals. All interrupt inputs may be configured to be either edge or level triggered. To ensure recognition, all inter- rupt requests must remain active until the interrupt is acknowledged. When Slave Mode is selected, the func- tion of these pins changes (see the Interrupt Controller section of this data sheet). LCS Lower Memory Chip Select (Output/Input) Lower Memory Chip Select is active Low whenever a memory reference is made to the defined lower portion (1K-256K) of memory. LCS does not float during bus HOLD. The address range activating LCS is software programmable. UCS andLCS are sampled upon the rising edge of RES. If both pins are held Low, the 80C186/C 188 enter ONCE mode. In ONCE mode all pins assume a high-imped- ance state and remain so until a subsequent RESET. CCS has a weak internal pul-up that is active only during RESET to ensure that the 80C186/C188 does not enter ONCE mode inadvertently. LOCK Lock (Output) LOCK output indicates that other system bus masters are notto gain control of the system bus. LOCK is active Low. The LOCK signal is requested by the LOCK prefix instruction and is activated at the beginning of the first AMD al data cycle associated with the instruction immediately following the LOCK prefix. It remains active until the completion of that instruction. No instruction prefetching will occur while LOCK is asserted. LOCK has an internal pull-up that is active during bus HOLD or RESET. MCS0, MCS1, MCS2, MCS3 Mid-Range Memory Chip Select (Output/Inputs, Outputs) Mid-Range Memory Chip Select signals are active Low when a memory reference is made to the defined mid- range portion of memory (8K512k). These lines do not float during bus HOLD. The address ranges activating MCS3-MCS0 are software programmable. In Enhanced Mode, MCSO and MCS3 become dummy inputs to maintain compatibility. They should be treated as inputs and tied High/Low when in Enhanced Mode. MCSO and MCS1 have weak internal pull-ups that are active during RESET. NMI Non-Maskable Interrupt (Input) The Non-Maskable interrupt input causes a Type 2 interrupt. An NMI transition from Low to High is latched and synchronized internally, and initiates the interrupt at the next instruction boundary. NMI must be asserted for at least one CLKOUT period. The Non-Maskable tnter- rupt cannot be avoided by programming. PCS5/A1 Peripheral Chip Select 5 or Latched A1 (Output) Peripheral Chip Select 5 or Latched A1 may be pro- grammed to provide a sixth peripheral chip select, or to provide an internally latched A1 signal. The address range activating PCS5 is software programmable. When programmed to provide latched A1 rather than PCS5, this pin will retain the previously latched value of Ai during abus HOLD. A1 is active High. PCS5/A1 does not float during bus HOLD. PCS6/A2 Peripheral Chip Select 6 or Latched A2 (Output) Peripheral Chip Select 6 or Latched A2 may be pro- grammed to provide a seventh peripheral chip select, or to provide an internally latched A2 signal. The address range activating PCS6 is software programmable. When programmed to provide latched A2 rather than PCS6, this pin retains the previously latched value of A2 during a bus HOLD. A2 is active High. PCS6/A2 does not float during bus HOLD. PCS4-PCS0 Peripheral Chip Setect Signals (Outputs) Peripheral Chip Select signals (4-0) are active Low when a reference is made to the defined peripheral area 80C186/80C188 Microprocessors 15cl AMD PRELIMINARY (64-Kbyte I/O or 1-Mbyte memory space). These lines do not float during bus HOLD. The address ranges acti- vating PCS4-PCS0 are software programmable. RD/QSMD Read Strobe (Output/Input) Read Strobe is an active Low signal, which indicates that the 80C186/C188 is performing a memory or I/O read cycle. It is guaranteed not to go Low before the A/D bus is floated. An internal pull-up ensures that RD/QS- MD is High during RESET. Foliowing RESET, the pin is sampled to determine whether the 80C186/C188 is to provide ALE, AD, and WR, or queue status information. To enable Queue Status Mode, RD must be connected to GND. RD floats during bus HOLD. RES RESET (Input) Anactive RES causes the 80C 186/C 188 to immediately terminate its present activity, clear the internal logic, and enter adormantstate. This signal may be asynchronous to the 80C186/C188 clock. The 80C186/C188 begins fetching instructions approximately 61 clock cycles after RES is returned High. For proper initialization, Vec must be within specifications and the clock signal must be stable for more than four clocks with RES held Low. RES is internally synchronized. This input is provided with a Schmitt-trigger to facilitate power-on RES gen- eration via an RC network. RESET System Reset (Output) RESET output indicates that the 80C186/C188 CPU is being reset and can be used as a system reset. It is active High, synchronized with the processor clock, and lasts an integer number of clock periods corresponding to the length of the RES signal. RESET goes inactive two clockout periods after RES goes inactive. When tied to the TEST pin, RESET forces the 80C186/ 800188 into enhanced mode. RESET is not floated during bus HOLD. RFSH (80C188 only) Refresh (Output) In compatible mode, RFSH is High. in enhanced mode, RFSH is asserted Low to signify a refresh bus cycle. The RFSH output pin floats during bus HOLD or RESET, regardless of operating mode. $2-S0 Bus Cycle Status (Outputs) Bus cycle status S2-S0 are encoded to provide bus- transaction information. The status pins float during HOLD/HLDA. S2 may be used as a logical memory or I/O indicator, and S71 as a DT/R indicator. 80C186/C188 Bus Cycle Status Information 52 | ST | SO | Bus Cycle Initiated 0 0 0 | Interrupt Acknowledge 0 0 1 Read 1/0 0 1 0 | Write I/O 0 1 1 | Halt 1 0 0 {Instruction Fetch 1 0 1 | Read Data from Memory 1 1 0 |Write Data to Memory 1 1 1 | Passive (no bus cycle) SRDY Synchronous Ready (Input) Synchronous Ready informs the 80C186/C188 that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active-High input synchronized to CLKOUT. The use of SRDY allows a relaxed system timing over ARDY. This is accomplished by elimination of the one-half clock cycle required to internally synchronize the ARDY input sig- nal. Connecting SRDY High always asserts the ready condition to the CPU. If this fine is unused, it should be tied Low to yield control to the ARDY pin. TEST Test (Input) The TEST pin is sampled during and after reset to deter- mine whether the 80C186/C 188 is to enter Compatible or Enhanced Mode. Enhanced Mode requires TEST to be High on the rising edge of RES and Low four CLKOUT cycles later. Any other combination places the 80C0186/C188 in Compatible Mode. During power-up, active RES is required to configure TEST as an input. A weak internal pull-up ensures a High state when the pin is not driven. This pin is examined by the WAIT instruc- tion. If the TEST input is High when WAIT execution begins, instruction execution will suspend. TEST resampled every five clocks until it goes Low, at which time execution resumes. If interrupts are enabled while the 80C186/C 188 is waiting for TEST, interrupts will be serviced. TMR INO, TMR IN1 Timer Inputs (Inputs) Timer inputs are used either as clock or control signals, depending upon the programmed timer mode. These inputs are active High (or Low-to-High transitions are counted) and internally synchronized. Timer inputs must M@ 0257525 0049563 037 16 80C186/80C188 MicroprocessorsPRELIMINARY be tied High when not being used as clock or retrigger inputs. TMR OUTO, TMR OUT1 Timer Outputs (Outputs) Timer outputs are used to provide single pulse or contin- uous waveform generation, depending upon the timer mode selected. These outputs are not floated during a bus HOLD. ucsS Upper Memory Chip Select (Output/Input) Upper Memory Chip Select is an active Low output whenever a memory reference is made to the defined upper portion (1K-256K block) of memory. UCS does not float during bus HOLD. The address range activat- ing UCS is software programmable. UCS andLCS are sampled upon the rising edge of RES. If both pins are held Low, the 80C186/C188 enters ONCE Mode. In ONCE Mode, all pins assume a high- impedance state and remain so until a subsequent RESET. UCS has a weak internal pull-up that is active during RESET to ensure that the 80C186/C188 does not enter ONCE Mode inadvertently. Vee Power Supply (Inputs) System power: +5-V power supply. Vss Ground (Inputs) System ground. AMD al WR/QS1 Write Strobe/Queue Status 1 (Output) Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a memory or an 1/O device. It is active Low and floats during bus HOLD or RESET. When the 80C186/C 188 is in Queue Status Mode, the ALE/QSO and WA/QS1 pins provide information about processor/instruction queue interaction. QS1 | QSO | Queue Operation 0 QO | No queue operation 0 1 First opcode byte fetched from the queue 1 1 | Subsequent byte fetched fram the queue 1 0 | Empty the queue X1, X2 Crystal Inputs (Input/Output) Crystal inputs X1 and X2 provide external connections for a fundamental mode or third overtone parallel reso- nant crystal for the internal oscillator. X1 can connect to an external clock instead of a crystal. In this case, mini- mize the capacitance on X2. The input or oscillator fre- quency is internally divided by two to generate the clock signal (CLKOUT). MM 0257525 0049584 T73 80C186/80C188 Microprocessors 17al AMD PRELIMINARY FUNCTIONAL DESCRIPTION Introduction The following Functional Description describes the base architecture of the 80C 186/C 188. The 80C186/80C188 is a very high integration 16-bit microprocessor. It com- bines 15-20 of the most common microprocessor sys- tem components onto one chip. The 80C186/80C188 is object code compatible with the 8086/8088 micropro- cessors and adds 10 new instruction types to the 8086/8088 instruction set. The 80C186/C188 has two major modes of operation, Compatible and Enhanced. In Compatible Mode the 80C186/C188 is completely compatible with the NMOS 80186/80188, with the exception of 8087 support. The Enhanced Mode adds two new features to the system design: power-save control, and dynamic RAM refresh. 80C186/C188 Base Architecture The 8086, 8088, 80186, and 80188 Family ali contain the same basic set of registers, instructions, and addressing modes. The 80C 186/C 188 processor is upward compat- ible with the 8086 and 8088 CPUs. Register Set The 80C186/C188 base architecture has fourteen regis- ters, as shown in Figure 1. These registers are grouped into the following categories. General Registers Eight 16-bit general purpose registers may be used for arithmetic and logical operands. Four of these (AX, BX, CX, and DX) can be used as 16-bit registers or split into pairs of separate 8-bit registers. Segment Registers Four 16-bit special-purpose registers select, at any given time, the segments of memory that are immedi- ately addressable for code, stack, and data. (Forusage, refer to Memory Organization.) Base and Index Registers Four of the general-purpose registers may aiso be used to determine offset addresses of operands in memory. These registers may contain base addresses or indexes to particular locations within a segment. The addressing mode selects the specific registers for operand and address calculations. Status and Control Registers Two 16-bit special-purpose registers record or alter certain aspects of the 80C186/C 188 processor state. These are the Instruction Pointer Register, which contains the offset address of the next sequential instruction to be executed, and the Status Word Register, which contains status and control flag bits (see Figures 1 and 2). Status Word Description The Status Word records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the operation of the 80C186/C 188 within a given operating mode (bits 8, 9, and 10). The Status Word Register is 16-bits wide. The function of the Status Word bits is shown in Table 1. cs Code Segment Selector DS Data Segment Selector Stack Segment Selector 16-Bit Special Register Register Name Functions 7 0 7 0 Byte AH Multiply/Divi ply/Divide OD DH VO Instructions Register Loop/Shift/Repeat/Count Names GH Pp Pp ount SS Shown) BH Base Registers index Registers Stack Pointer General Registers ES Extra Segment Selector Segment Registers 15 0 F Status Word Instruction Pointer Status and Control Registers 13087D-002 Figure 1. 80C186/C188 Register Set M@ 0e575e5 0049585 40T 18 80C186/80C188 MicroprocessorsPRELIMINARY AMD al Table 1. Status Word Bit Functions Bit Position| Name | Function 0 CF Carry Flag-Set on high-order bit carry or borrow; cleared otherwise. 2 PF Parity FlagSet if low-order 8 bits of result contain an even number of 1 bits; cleared otherwise. 4 AF Auxiliary CarrySet on carry from or borrow to the fow order four bits of the general purpose register AL; cleared otherwise. ZF Zero FlagSet if result is 0; cleared otherwise. SF Sign FlagSet equal to high-order bit of result (0 if positive, 1 if negative). TF Single-Step FlagOnce set, a single-step interrupt occurs after the next instruction executes. TF is cleared by the single-step interrupt. 9 IF Interrupt-Enable FlagWhen set, maskable interrupts cause the CPU to transfer control to an interrupt vector specified location. 10 DF Direction FlagCauses string instructions to auto decrement the appropriate index register when set. Clearing DF causes auto-increment. on OF Overflow FlagSet if the signed result cannot be expressed within the number of bits in the destination operand; cleared otherwise. Status Flags: Carry Parity Auxiliary Carry Zero Sign Overflow 15 14 #13 #12 11 #10 9 8 Riss oF | oF | iF | TF | vl | z SEG SS AWTS] Control! Flags: Trap Flag Interrupt Enable Do Reserved Direction Flag 13087D-003 Figure 2. Status Word Format Instruction Set The instruction set is divided into seven categories: data transfer, arithmetic, shift/rotate/logical, string manipula- tion, control transfer, high-level instructions, and pro- cessor control. These categories are summarized in 800 186/C188 Instruction Set section. The 80C186/C188 instruction can reference anywhere from zero to several operands. An operand can reside in a register, in the instruction itself, or in memory. Specific Mi 0257525 0049586 846 operand addressing modes are discussed later in this data sheet. Memory Organization Memory is organized in sets of segments. Each seg- ment is a linear contiguous sequence of up to 64K (21) 8-bit bytes. Memory is addressed using a two- component address (a pointer) that consists of a 16-bit base segment and a 16-bit offset. The 16-bit base values are contained in one of four internal seg- ment registers (cade, data, stack, extra). The physical 80C186/80C188 Microprocessors 19cl AMD PRELIMINARY address is calculated by shifting the base value LEFT by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 3). This allows for a 1-Mb physical address size. All instructions that address operands in memory must specity the base segment and the 16-bit offset value. For speed and compact instruction encoding, the seg- ment register used for physical address generation is implied by the addressing mode used (see Table 2). These rules follow the way programs are written (see Figure 4) as independent modules that require areas for code and data, a stack, and access to external data areas. Special segment override instruction prefixes allow the implicit segment register selection rules to be overrid- den for special cases. The stack, data, and extra seg- ments may coincide for simple programs. Shift Left 4 Bits 1 > 3 (C4 Segment 15 0 ase Logical Address 15 0 Physical Address To Memory 13087D-004 Note: To accass operands that do not reside in one of the four immediately available segments, a full 32-bit pointer can be used to reload both the base (segment) and offset values. Figure 3. Two-Component Address og Code Module A Data Module ' B ' CPU Process Stack Code Data Process Data Stack Block 1 Extra Process Segment Data Registers Block 2 weer ead Memary 13087D-005 Figure 4. Segmented Memory Helps Structure Software 80C186/C188 Instruction Set General Purpose MOV Move byte or word PUSH Push word onto stack POP Pop word off stack PUSHA Push all registers on stack POPA Pop all registers from stack SCAS Scan byte or word string LODS Load byte or word string XCHG Exchange byte or word XLAT Translate byte Table 2. Segment Register Selection Rules Memory Reference Segment Register Needed Used implicit Segment Selection Rule Instructions Code (CS) Instruction prefetch and immediate data. Local Data Data (DS) All other data references. Stack Stack (SS) All stack pushes and pops; any memory references that use BP Register as a base register. External Data (Global) Extra (ES) All string instruction references that use the DI register as an index. M@ 0257525 004958? 742 me 20 &0C186/80C188 MicroprocessorsMH 619 PPSbhOd S2oSe0 me Input/Output IN OUT Address Object LEA LDS LES Flag Transfer LAHF SAHF PUSHF POPF Addition ADD ADC INC AAA DAA Subtraction SUB SBB DEC NEG CMP AAS DAS Multiplication MUL IMUL AAM Division DIV IDIV AAD CBW CWD MOVS INS OUTS CMPS STOS REP REPE/REPZ PRELIMINARY REPNE/REPNZ Repeat while not equal/not zero Input byte or word Output byte or word Load effective address Load pointer using DS Load pointer using ES Load AH register from flags Store AH register in flags Push flags onto stack Pop flags off stack Add byte or word Add byte or word with carry Increment byte or word by 1 ASCII adjust for addition Decimal adjust for addition Subtract byte or word Subtract byte or word with borrow Decrement byte or word by 1 Negate byte or word Compare byte or word ASCII adjust for subtraction Decimal adjust for subtraction Multiply byte or word unsigned Integer multiply byte or word ASCII adjust for multiply Divide byte or word unsigned Integer divide byte or word ASCIl adjust for division Convert byte or word Convert word to doubleword Move byte or word string Input bytes or word string Output bytes or word string Compare byte or word string Store byte or word string Repeat Repeat while equal/zero Logicals NOT AND OR XOR TEST Shifts SHL/SAL SHR SAR Rotates ROL ROR RCL RCR AMD al NOT" byte or word AND byte or word Inclusive or byte or word Exclusive or" byte or word Test byte or word Shift logical/arithmetic left byte or word Shift logical right byte or word Shift arithmetic right byte or word Rotate left byte or word Rotate right byte or word Rotate through carry left byte or word Rotate through carry right byte or word Flag Operations STC CLC CMC STD CLD STl CLI Set carry flag Clear carry flag Complement carry flag Set direction flag Clear direction flag Set interrupt-enable flag Clear interrupt-enable flag External Synchronization HLT WAIT ESC LOCK No Operation NOP Halt until interrupt or reset Wait for TEST pin active Escape to extension processor Lock bus during next instruction No operation High Level Instructions ENTER LEAVE BOUND Format stack for procedure entry Restore stack for procedure exit Detects values outside prescribed range Conditional Transfers JA/JNBE JAE/JNB JB/JNAE JBE/JNA Jc Jump if above/not below nor equal Jump if above or equal/not below Jump if below/not above nor equal Jump if below or equal/not above Jump if carry 80C186/80C188 Microprocessors 21cl AMD PRELIMINARY JENZ Jump if equal/zero JG/JNLE Jump if greater/not less nor equal JGE/JNL Jump if greater or equal/not less JLUNGE Jump if less/not greater nor equal JLE/ING Jump if less or equal/not greater JNC Jump if not carry JNE/JNZ Jump if not equal/not zero JNO Jump if not overflow JNP/JPO Jump if not parity/parity odd JNS Jump if not sign JO Jump if overflow JP/JPE Jump if parity/parity even JS Jump if sign Unconditional Transfers CALL Call procedure RET Return from procedure JMP Jump Iteration Controls LOOP Loop LOOPE/ LOOPZ Loop if equal/zero LOOPNE/ LOOPNZ Loop if not equal/not zero JOXZ Jump if register CX = 0 Interrupts INT Interrupt INTO Interrupt if overflow IRET Interrupt return Addressing Modes The 80C186/C 188 provides eight categories of addres- sing modes to specify operands. Two addressing modes are provided for instructions that operate on reg- ister or immediate operands: 1. Register Operand Mode: The operand is located in one of the 8- or 16-bit registers. 2. Immediate Operand Mode: The operand is included in the instruction. Six modes are provided to specify the location of an operand in a memory segment. A memory operand address consists of two 16-bit components: a segment base and an offset. The segment base is supplied by a 16-bit segment register either implicitly chosen by the addressing mode or explicitly chosen by a segment override prefix. The offset, also called the effective address, is calculated by summing any combination of the following three address elements: 1. the displacement (an 8- or 16-bit immediate value contained in the instruction); 2. the base (contents of either the BX or BP base registers); and, 3. the index (contents of either the SI or DI index registers). Any carry out from the 16-bit addition is ignored. Eight- bit displacements are sign-extended to 16-bit values. Combinations of these three address elements define the six memory addressing modes, described below. 1. Direct Mode: The operands offset is contained in the instruction as an 8- or 16-bit displacement element. 2. Register Indirect Mode: The operands offset is in one of the registers S!, DI, BX, or BP. 3. Based Mode: The operands offset is the sum of an 8- or 16-bit displacement and the contents of a base register (BX or BP). 4. Indexed Mode: The operand's offset is the sum of an 8- or 16-bit displacement and the contents of an index register (SI or Dl). 5. Based Indexed Mode: The operancs offset is the sum of the contents of a base register and an index register. 6. Based Index Mode with Displacement: The operands offset is the sum of a base registers contents, an index registers contents, and an 8- or 16-bit displacement. Data Types The 80C186/C188 directly supports the following data types: m Integer: A signed binary numeric value contained in an 8-bit byte or a 16-bit word. All operations assume a two's complement representation. Ordinal: An unsigned binary numeric value contained in an 8-bit byte or a 16-bit word. m Pointer: A 16- or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component in addition to a 16-bit offset component. a String: A contiguous sequence of bytes or words. A string may contain 1 to 64 Kbytes. a ASCII: A byte representation of alphanumeric and control characters using the ASCII standard of character representation. m BCD: A byte (unpacked) representation of the decimal digits 0-9. M 0257525 0049589 555 a 22 80C186/80C188 MicroprocessorsPRELIMINARY m Packed BCD: A byte (packed) representation of two decimal digits (0-9). One digit is stored in each nibble (4 bits) of the byte. In general, individual data elements must fit within defined segment limits. Figure 5 graphically represents the data types supported by the 80C186/C188. lO Space The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. 8-bit port addresses are zero-extended such that A15-A8 are Low. I/O port addresses 00F8(H) through OOFF(H) are reserved, Interrupts An interrupt transfers execution to a new program loca- tion. The old program address (CS:IP) and machine state (Status Word) are saved on the stack to allow resumption of the interrupted program. interrupts fall into three classes: hardware initiated, INT instructions, and instruction exceptions. Hardware-initiated inter- rupts occur in response to an external input and are clas- sified as non-maskable or maskable. Programs may cause an interrupt with an INT instruc- tion. Instruction exceptions occur when an unusual condition that prevents further instruction processing is detected while attempting to execute an instruction. AMD al 7 9 Signed anes TT Sign Bit + Wagnitude 7 0 Unsigned LW Magnitude +1 0 Signed [7+ Word Sign Bit CMSB __ Magnitude Signed, 8 % 15 4 a Double Word* r Sign Bit CMSB Magnitude Signed et? 8 ia ait? 8 is! +9 , Quad TTT TT TIT 4 Word! iC MSB Sign Bit Les Magnitude +1 0 15 CG Unsigned Word TC MSB Magnitude Binary +N +1 0 Coded 7 Qo 7 O7 o imal Lee Pee) BCD BCD BCD Digit N Digit 1 Digit o 7 *N y 7 +1 97 % g ASCII wee ASCII ASCII ASCII Charactery Character, Character, Packed Orme 7 1 97 0 4g eked [TTT] il Most Significant Least Digit Significant Digit 718+N 9 zis tl ; 0 0 String TTT]... ByteWord N- Byte/Ward 1 Byte/Word 0 31 +3 + ts Ot 0 6 Pointer Selector Offset 13087D-006 Figure 5. 80C186/C188 Supported Data Types Mm 0257525 0045590 277 80C186/80C188 Microprocessors 23Me COT ThSbhOO S2o2S5e0 1 ano if the exception was caused by executing an ESC instruction, the return instruction points to the ESC instruction, or to the segment override prefix immedi- ately preceding the ESC instruction if the prefix was present. In all other cases, the return address from an exception points to the instruction immediately following the instruction causing the exception. Atable containing up to 256 pointers defines the proper interrupt service routine for each interrupt. Interrupts 0-31, some of which are used for instruction exceptions, are reserved. Table 3 shows the 80C186/C188 prede- fined types and default priority levels. For each interrupt, an 8-bit vector must be supplied to the 80C186/C188, which identifies the appropriate table entry. Exceptions supply the interrupt vector internally. In addition, intemal peripherals and non-cascaded external interrupts gen- erate their own vectors through the internal interrupt controller. INT instructions contain or imply the vector and allow access to all 256 interrupts. Maskable hard- ware-initiated interrupts supply the 8-bit vector to the CPU during an interrupt acknowledge bus sequence. Non-maskable hardware interrupts use a predefined internally supplied vector. Interrupt Sources The 800186/C188 can service interrupts generated by software or hardware. The software interrupts are gen- erated by specific instructions (INT, ESC, unused OP, etc.) orthe results of conditions specified by instructions (array bounds check, INTO, DIV, IDIV, etc.). Allinterrupt sources are serviced by an indirect call through an ele- ment of a vector table. This vector table is indexed by using the interrupt vector type (Table 3), multiplied by four. All hardware-generated interrupts are sampled at the end of each instruction. Thus, the software interrupts begin service first. Once the service routine is entered and interrupts are enabled, any hardware source of suffi- cient priority can interrupt the service routine in progress. Those pre-defined 80C186/C188 interrupts that cannot be masked by programming are described below. Divide Error Exception (Type 0) Generated when a DIV or IDIV instruction quotient can- not be expressed inthe number of bits in the destination. Single-Step Interrupt (Type 1) Generated after most instructions if the TF (single step) flag in the status word is set. This interrupt allows pro- grams to execute one instruction at a time. Interrupts are not be generated after prefix instructions (e.g., REP), instructions that modify segment registers (e.g., POP DS), or the WAIT instruction. Vectoring to the single- step interrupt service routine clears the TF bit. An IRET instruction in the interrupt service routine restores the TF bit to logic 1 and transfers control to the next instruc- tion to be single-stepped. PRELIMINARY Non-Maskable Interrupt-NMI (Type 2) An external interrupt source that is serviced regardless of the state of the IF (interrupt enable flag) bit. No exter- nal interrupt acknowledge sequence is performed. The \F bit is cleared at the beginning of a NMI interrupt to pre- vent maskable interrupts from being serviced. A typical use of NMI would be to activate a power failure routine. Breakpoint Interrupt (Type 3) A 1-byte version of the INT instructions. It uses 12 (OCH) as an index into the service routine address table (because it is a Type 3 interrupt). INTO Detected Overtlow Exception (Type 4) Generated during an INTO instruction if the OF bit is set. Array BOUNDS Exception (Type 5) Generated during a BOUND instruction if the array index is outside the array bounds. The array bounds are located in memory at a location indicated by one of the instruction operands. The other operand indicates the value of the index to be checked. Unused Opcode Exception (Type 6) Generated if execution is attempted on undefined opcodes. ESCAPE Opcode Exception Generated if execution is attempted of ESC opcodes (D8-DFH). The 80C186/C188 does not check the escape opcode trap bit. ESC traps occur in both compat- ible and enhanced operating modes. The return address of this exception will point to the ESC instruction causing the exception. If a segment override prefix pre- ceded the ESC instruction, the return address will point to the segment override prefix. Note: All numerics coprocessor opcodes cause a trap. The 80C186/C 188 does not support the numerics interface. Hardware Interrupts Hardware-generated interrupts are divided into two groups: maskable interrupts and non-maskable inter- rupts. The 80C186/C 188 provides maskable hardware interrupt request pins INT3-INTO. In addition, maskable interrupts may be generated by the 80C186/C188 inte- grated DMA controller and the integrated timer unit. The vector types for these interrupts is shown in Table 3. Software enables these inputs by setting the interrupt enable flag bit (IF) inthe Status Word. The interrupt con- troller is discussed in the peripheral section of this data sheet. Further maskable interrupts are disabled while servicing an interrupt because the IF bit is reset as part of the response to an interrupt or exception. The saved Status Word will reflect the enable status of the processor prior 24 80C186/80C188 MicroprocessorsPRELIMINARY to the interrupt. The interrupt flag will remain zero unless specifically set. The interrupt return instruction restores the Status Word, thereby restoring the original status of IF (interrupt-enable flag) bit. If the interrupt return re-en- ables interrupts and another interrupt is pending, the 80C 186/188 will immediately services the highest-prior- ity interrupt pending (i.e., no instructions of the main line program are executed). Initialization and Processor Reset Processor initialization or startup is accomplished by driving the RES input pin Low. RES must be Low during AMD at power-up to ensure proper device initialization. RES forces the 80C186/C188 to terminate all execution and local bus activity. No instruction or bus activity occurs as long as RES is active. After RES becomes inactive and an internal processing _ interval elapses, the 80C186/C188 begins execution with the instruction at physical location FFFFO(H). RES also sets some regis- ters to predefined values as shown in Table 4. Table 3. 80C186/C188 Interrupt Vectors Interrupt Name Vector Vector Default Related Applicable Type Address Priority instructions Notes Divide Error Exception 0 00H 1 DIV, IDIV 1 Single-Step Interrupt 1 04H 1A All 2 Non-Maskable Interrupt (NMI) 2 08H 1 All Breakpoint Interrupt 3 OCH 1 INT 1 INTO Detected Overflow Exception 4 10H 1 INTO 1 Array Bounds Exception 5 14H 1 BOUND 1 Unused Opcode Exception 6 18H 1 Undefined 1 Opcodes ESC Opcode Exception 7 1CH 1 ESC Opcodes 1,3 Timer 0 Interrupt 8 20H 2A 4 Timer 1 Interrupt 18 48H 2B 4,5 Timer 2 Interrupt 19 4CH 2c 4,5 Reserved 9 24H 3 DMA 0 Interrupt 10 28H 4 DMA 1 Interrupt 11 2CH 5 INTO Interrupt 12 30H 6 INT1 Interrupt 13 34H 7 INT2 Interrupt 14 38H 8 INT3 Interrupt 15 3CH 9 Reserved 16, 17 40H, 44H Reserved 20~31 50H ...7CH Notes: Default priorities for the interrupt sources are used only if the user does not program each source to a unique priority level. 1. Generated as a result of an instruction execution. Performed in the same manner as 8086/8088. 2. 3. An ESC opcode will cause a trap regardless of the 80C186/C188 operating mode. The 80C186/C188 are not directly compat- ible with the 80188 in this respect. The instruction set of the numerics coprocessor cannot be executed. 4. All three timers constitute one source of request to the interrupt controller. As such, they share the same priority level with respect to other interrupt sources. However, the timers have a defined Priority order among themselves (2A > 2B > 2C). 5. The vector type numbers of these sources are programmable in Slave Mode. Ee ee | 80C186/80C188 Microprocessors 25cl AMD Table 4. 80C186/C188 Initial Register State after RESET Status Word F002(H) Instruction Pointer 0000(H) Code Segment FFFF(H) Data Segment 0000(H) Extra Segment 0000(H) Stack Segment 0000(H}) Relocation Register 20FF(H) UMCS FFFB(H) 80C186/C188 CLOCK GENERATOR The 80C186/C188 provide an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide-by- two counter, synchronous and asynchronous ready inputs, and reset circuitry. Oscillator The oscillator circuit of the 80C186/C188 is designed to be used either with a parallel resonant fundamental or third-overtone mode crystal, depending upon the fre- quency range of the application, as shown in Figure 6(c). This is used as the time base for the 80C186/C 188. The crystal frequency chosen should be twice the required processor frequency. Use of an LC or RC circuit is not recommended. The output of the oscillator is not directly available out- side the 80C186/C188. The two recommended crystal configurations are shown in Figure 6{a and b). When used in third-overtone mode, the tank circuit shown in Figure 6(b) is recommended for stable operation. The sum of the stray capacitances and loading capacitors should equal the values shown. It is advisable to limit stray capacitance between the X1 and X2 pins to less than 10 pF. While a ftundamental-mode circuit requires approximately 1 ms for start-up, the third-overtone arrangement may require 1 ms to 3 ms to stabilize. Alternately, the oscillator may be driven from an external source, as shown in Figure 6(d). The configuration shown in Figure 6(e) is not recommended. The following parameters should be used when choos- ing a crystal: Temperature Range: 0C to 70C ESR (Equivalent Series Resistance): 40 ohms max CO (Shunt Capacitance of Crystal): 7.0 pF max Ci (Load Capacitance): 20 pF +2 pF Drive Level: 1 mW max PRELIMINARY Clock Generator The 80C186/C188 clock generator provides the 50%-duty cycle processor clock for the 80C0186/ 80C188. It does this by dividing the oscillator output by two, forming the symmetrical clock. If an external oscil- lator is used, the state of the clock generator changes on the falling edge of the oscillator signal. The CLKOUT pin provides the processor clock signal for use outside the 80C186/C188. This may be used to drive other sys- tem components. All timings are referenced to the out- put clock. READY Synchronization The 80C186/C188 provide both synchronous and asynchronous ready inputs. Asynchronous ready syn- chronization is accomplished by circuitry that samples ARDY in the middle of T2 and again in the middle of each TW until ARDY is sampled High. One-haif CLKOUT cycle of resolution time is used for full syn- chronization of a rising ARDY signal. A High-to-Low transition on ARDY may be used as an indication of the not-ready condition, but it must be performed synchro- nously to CLKOUT, either in the middle of T2 or TW, or at the falling edge of TW. A second ready input (SRDY) is provided to interface with externally synchronized ready signals. This input is sampled at the end of T2 and again at the end of each TW until it is sampled High. By using this input rather than the asynchronous ready input, the half-clock cycle resolution time penalty is eliminated. This input must satisfy set-up and hold times to guarantee proper opera- tion of the circuit. in addition, the 80C186/C 188, as part of the integrated chip-select logic, have the capability to program wait states for memory and peripheral blocks. This is dis- cussed in the Chip Select/Ready Logic description. RESET Logic The 80C186/C188 provides both a RES input pin and a synchronized RESET output pin for use with other system components. The RES input pin on the 800 186/C188 is provided with hysteresis in order to facilitate power-on Reset generation via an RC network. RESET is guaran- teedto remain active for at least five clocks given a RES input of at least six clocks. RESET may be delayed up to approximately two and one-half clocks behind RES. Mi 0257525 0049593 Th 26 80C186/80C188 MicroprocessorsPRELIMINARY 30 pF I aa X1 & Crystal = 20pF 80C186/ 800188 a. Fundamental Mode Configuration 30 pF x1 ES Crystal i- x2 = 20pF 80C186/ Note 1 800188 Tt 200 pF b. Third-Overtone Configuration Note 1: XTAL Frequency L1 Value (Max) 20 MHz 12.0 WH 420% 25 MHz 8.2 WH 420% 32 MHz 4.7 WH 420% 40 MHz 3.0 WH +20% 50 MHz 2.2 LH +20% Recommended Crystal Mode {q Third-Overtone | le Fundamental | | | ij Desired CPU Frequency 10 MHz 12.5 MHz 25 MHz c. Recommended Crystal Mode External Clock Source x1 (DO NOT USE) LT} *! NC | X2 External Clock Source x2 80C186/ 800 186/ 800188 800188 d. Recommended Externally Generated Clock e. Invalid Alternative for Externally Generated Clock 13087D-007 Figure 6. 80C186/C188.Oscillator Configurations LOCAL BUS CONTROLLER The 800 186/C188 provide a local bus controller to gen- erate the local bus control signals. In addition, they employ a HOLD/HLDA protocol for relinquishing the local bus to other bus masters. It also provides outputs that can be used to enable external buffers and to direct the flow of data on and off the local bus. /M@ 0257525 0049594 912 Memory/Peripheral Control The 80C186/C188 provide ALE, RD, and WR bus con- trol signals. The RD and WR signals are used to strobe data from memory or I/O to the 80C186/C188 or to strobe data from the 80C186/C188 to memory or I/O. The ALE line provides a strobe to latch the address when it is valid. The 80C186/C188 local bus controller does not provide a memory/IO signal. If this is required, use the S2 signal (which will requires external latching, 0=O and 1=memory), make the memory and I/O 80C186/80C188 Microprocessors 27&1 amo spaces non-overlapping, or use only the integrated chip-select circuitry. Transceiver Control The 80C186/C188 generate two control signals for external transceiver chips. This capability allows the addition of transceivers for extra buffering without adding external logic. These control lines, DT/R and DEN, are generated to control the flow of data through the transceivers. The operation of these signals is shown in Table 5. Table 5. Transceiver Control Signals Description Pin Name Function DEN (Data Enable) Enables the output drivers of the transceivers. It is active Low during memory, /O, or INTA cycles. DT/R (Data Transmit/ Receive) Determines the direction of travel through the transceivers. A High level directs data away from the processor during write operations, while a Low level directs data toward the proces- sor during a read operation. Local Bus Arbitration The 80C186/C188 use a HOLD/HLDA system of local bus exchange. This provides an asynchronous bus exchange mechanism. This means multiple masters utilizing the same bus can operate at separate clock frequencies. The 80C186/C188 provide a single HOLD/HLDA pair through which all other bus masters may gain control of the local bus. External circuitry must arbitrate which external device gains control of the bus when there is more than one alternate local bus master. When the 80C186 relinquishes control of the local bus, it floats DEN, RD, WR, S2-S0, LOCK, AD15-ADO, A19-A16, BHE, and DT/R. The 80C188 floats DEN, RD, WR, $2 LOCK, AD7-ADO, A19-A8, RFSH, and DT/R. $2-S0, The 80C186/C188 HOLD latency time, that is, the time between HOLD request and HOLD acknowledge, is a function of the activity occurring in the processor when the HOLD request is received. A HOLD request is second only to DRAM refresh requests in priority of activity requests received by the processor. Any bus cycle in progress completed before the 80C186/C188 relinquish the bus. This implies that if a HOLD request is received just as a DMA transfer begins, the HOLD latency canbe as great as 4-bus cycles. This occurs ifa DMA word transfer operation is taking place from an odd address to an odd address. This is a total of 16 clock- cycles or more if wait states are required. In addition, if locked transfers are performed, the HOLD latency time is increased by the length of the locked transfer. If the 80C186/C188 have relinquished the bus and a refresh request is pending, HLDA is removed (driven PRELIMINARY Low) to signal the remote processor that the 80C186/C188 wish to regain control of the bus. The 80C186/C188 will wait until HOLD is removed before taking contro! of the bus to run the refresh cycle. Local Bus Controller and RESET During RESET, the local bus controler performs the fol- lowing actions: 1. Drive DEN, RD, and WR High for one clock cycle, then float them. 2. Drive S2-S0 to the inactive state (all High) and then float. 3. Float the Address/Data Bus, BHE (RFSH on the 800188), DT/R. 4. Drive ALE Low. 5, Drive HLDA Low. RD/QSMD, UCS, LCS, MCS0, MCS1, LOCK, and TEST pins have internal pull-up devices that are active while RESis applied. Excessive loading or grounding of some of these pins causes the 80C 186/C188 to enter an alter- native mode of operation: mg RD/QSMD Low results in Queue Status Mode. m UCS and LCS Low result in ONCE Mode. m TEST Low (and High later) results in Enhanced Mode. INTERNAL PERIPHERAL INTERFACE All the 80C186/C188 integrated peripherals are con- trolled by 16-bit registers contained within an internal 256-byte control block. The contro! block may be mapped into either memory or I/O space. Internal logic recognizes control block addresses and responds to bus cycles. During bus cycles to internal registers, the bus controller signals the operation externally (i.e., the Rb, WR, status, address, data, etc., lines are driven as in a normal bus cycle), but the data bus, SRDY, and ARDY are ignored. The base address of the control block must be on an even 256-byte boundary (i.e., the lower eight bits of the base address are alf Qs). All of the defined registers within this contra! block may be read or written by the 80C186/C188 CPU at any time. The control block base address is programmed by a 16-bit relocation register contained within the contro! block at offset FEH from the base address of the control block (see Figure 7). It provides the upper 12 bits of the base address of the control block. The control block is effectively an internal chip select range and must abide by ail the rules concerning chip selects (the chip select circuitry is discussed tater in this data sheet). Any access to the 256 bytes of the control biock activates an internal chip select. - mm 0257525 0049595 655 28 80C186/80C188 MicroprocessorsPRELIMINARY 15 14 13. 12 #11 +10 9 8 7 6 5 4 3 2 1 0 Offset: FEH| X | Slave/Master | xX | Mio] Relocation Address Bits R19-R8 | M/O = Register block located in Memory/ I/O Space (1/0) Slave/Master = Configures interrupt controller for Slave/Master Mode (1/0) 13087D-008 Figure 7. Relocation Register Other chip selects may overlap the control block only if they are programmed to zero wait states and ignore external ready. In addition, bit 12 of this register deter- mines whether the control block is mapped into V/O or memory space. If this bit is 1, the control block is located in memory space. If the bit is 0, the control block is located in /O space. If the control register block is Mapped into I/O space, the upper four bits of the base address must be programmed as 0 (since /O addresses are only 16-bits wide). In addition to providing relocation information for the control block, the relocation register contains bits that place the interrupt controller into slave mode. At RESET, the relocation register is set to 20FFH, which maps the control block to start at FFOOH in I/O space. An offset map of the 256-byte control register block is shown in Figure 8. OFFSET Relocation Register FEH DAH DMA Descriptors Channel 1 DOH . CAH DMA Descriptors Channel 0 COH ABH Chip-Select Contro! Registers AOH 66H Time 2 Control Registers 60H 5EH Time 1 Control Registers 58H Time 0 Control Registers 56H 50H . 3EH Interrupt Controller Registers 20H 13087D-009 Figure 8. Internal Register Map CHIP-SELECT/READY GENERATION LOGIC The 80C186/C188 contain logic that provides program- mable chip-select generation for both memories and peripherals. In addition, it can be programmed to pro- vide READY (or wait state) generation. It can also pro- vide latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their pro- grammed areas, whether they be generated by the CPU or by the integrated DMA unit. Memory Chip Selects The 80C186/C 188 provide six memory chip-select out- puts for three address areas: upper memory, lower memory, and mid-range memory. One each is provided for upper memory and lower memory, while four are pro- vided for mid-range memory. The range for each chip select is user-programmabie and can be set to 2K, 4K, 8K, 16K, 32K, 64K, or 128K (plus 1K and 256K for upper and lower chip selects). In addition, the beginning or base address of the mid- range memory chip select may also be selected. Only one chip select may be programmed to be active for any memory location at a time. All chip-select sizes are in bytes, whereas 80C186/C188 memory is arranged in words. For example, this means that if, 16 64K x 4 memories are used, the memory block size is 128K, not 64K. Upper Memory CS The 80C 186/C 188 provide a chip select, called UCS, for the top of memory. The top of memory is usually used as the system memory because, after reset, the 80C186/C188 begin executing at memory location FFFFOH. The upper limit of memory defined by this chip select is always FFFFFH, while the lower limit is programmable. By programming the lower limit, the size of the select block is also defined. Table 6 shows the relationship between the base address selected and the size of the memory block obtained. : M@ 0257525 00495956 795 a 80C186/80C188 Microprocessors 29ME T29 bSbhoo seseseO mm cl AMD PRELIMINARY Table 6. UMCS Programming Values Table 7. LMCS Programming Values Starting Memory Block UMCS Value Upper Memory Biock LMCS Value Address (Base Size (Assuming Address Size (Assuming RO = Ri Address) RO = Rt = R2 = 0) = R2=0) FFCOO 1K FFF8H 003FFH 1K 0038H FF8oo 2K FFB8H 007FFH 2K 0078H FFOOO 4K FF38H OOFFFH 4K OOF8H FE000 8K FE38H 01FFFH 8K 01F8H FCO00 16K FC38H O3FFFH 16K 03F8H F8000 32K F838H 07FFFH 32K 07F8H FO000 64K FO38H OFFFFH 64K OFF8H E0000 128K E038H {FFFFH 128K 1FF8H C0000 256K C038H SFFFFH 256K 3FF8H The lower limit of this memory block is defined in the UMCS register (see Figure 9). This register is at offset AOH in the internal control block. The legal values for bits 13-6 and the resulting starting address and memory block sizes are given in Table 6. Any combination of bits 13-6 not shown in Table 6 result in undefined operation. After reset, the UMCS register is programmed for a 1K area. It must be reprogrammed if a larger upper memory area is desired. The internal generation of any 20-bit address whose upper 16 bits are equal to or greater than the UMCS value (with bits 5-0 as 0) asserts UCS. UMCS bits, R2-RO specify the READY mode forthe area of memory detined by the chip-select register, as explained later. Lower Memory CS The 80C186/C188 provide a chip select for low memory called LCS. The bottom of memory contains the inter- rupt vector table, starting at location 00000H. The lower limit of memory defined by this chip select is always 0H, while the upper limit is programmable. By programming the upper limit, the size of the memory blockis defined. Table 7 shows the relationship between the upper address selected and the size of the memory block obtained. The upper limit of this memory block is defined in the LMCS register (see Figure 10) at offset A2H inthe inter- nal control block. The legal values for bits 15-6 and the resulting upper address and memory block sizes are givenin Table 7. Any combination of bits 1 5-6 not shown in Table 7 result in undefined operation. After reset, the LMCS register value is undefined. However, the LCS chip-select line does not become active until the LMCS register is accessed. Any internally generated 20-bit address whose upper 16 bits are less than or equal to LMCS (with bits 5-0 as 1) will assert LCS. LMCS register bits, R2-RO, specify the READY mode for the area of memory defined by this chip-select register. Mid-Range Memory CS The 80C186/C188 provides four MCS lines that are active within a user-locatable memory block. This block can be located within the 80C186/C188 1-Mb memory address space, exclusive of the areas defined by UCS and LCS. Both the base address and size of this memory block are programmable. The size of the memory block defined by the mid-range select lines, as shown in Table 8, is determined by bits 14-8 of the MPCS register (see Figure 11). This register is at location ASH in the internal control block. One, and only one, of bits 14-8 must be set at a time. Unpredict- able operation of the MCS lines otherwise occurs. Each of the four chip-select lines is active for one of the four equal contiguous divisions of the mid-range block. If the total block size is 32K, each chip select is active for 8K of memory with MCSO being active for the first range, MCGS1 active for the second, MCS2 for the third, and MCS3 being active for the last range. The EX and MS in MPCS relate to peripheral functional- ity, as described in a later section. Table 8. MPCS Programming Values Total Block Individual MPCS Bits Size Select Size 14-8 8K 2k 0000001B 16K 4K 0000010B 32K 8K 00001008 64K 16K 0001000B 128K 32K 0010000B 256K 64K 0100000B 512K 128K 10000008 30 80C186/80C188 MicroprocessorsPRELIMINARY The base address of the mid-range memory block is defined by bits 15-9 of the MMCS register (see Figure 12). This register is at offset A6H in the internal control block (see Figure 8). These bits correspond to bits A19-A13 of the 20-bit memory address. Bits A12A0 of the base address are always 0. The base address may be set at any integer multiple of the size of the total memory block selected. For example, if the mid-range block size is 32K (or the size of the block for which each WCS line is active is 8K), the block could be located at 10000H or 18000H, but not at 14000H, since the first few integer multiples of a 32K memory block are OH, 8000H, 10000H, 18000H, etc. After reset, the contents of both registers are undefined. However, none of the MCS lines are active until both the MMCS and MPCS registers are accessed. MMCS bits R2-R0 specify READY mode of operation for all four mid-range chip selects. The 512K block size for the mid-range memory chip selects is a special case. When using 512K, the base address has to be at either locations 00000H or 80000H. If it is to be programmed at 00000H when the LCS line was programmed, there is an internal conflict between the LCS ready generation logic and the MCS ready AMD cl generation logic. Likewise, if the base address is pro- grammed at 80000H, there would be a conflict with the UCS ready generation logic. Since the LCS chip-select line does not become active until programmed, while the UGS line is active at reset, the memory base canbe set only at OOOOOH. If this base address is selected, how- ever, the LCS range must not be programmed. In Enhanced Mode, three of the four MCS pins become unusable to maintain compatibility. MCS2 is still avail- able as a chip select covering one-fourth the mid-range address block, subject to the usual programming of the MPCS and MMCS registers. Peripheral Chip Selects The 80C186/C188 can generate chip selects for up to seven peripheral devices. These chip selects are active for seven contiguous blocks of 128 bytes above a pro- grammable base address. The base address may be located in either memory or I/O space. Seven CS lines, called PCS6-PCS0, are generated by the 80C186/C188. The base address is user-program- mable; however, it can only be a multiple of 1K byte (i-e., the least significant ten bits of the starting address are always 0). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oftset: AOH| 1 | 1 Ju Tu Aig fu tutu tufuteti did | R2 | Ai | Ao | AN 13087D-010 Figure 9. UMCS Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset: A2ZH} 0 | o Ju fu A19 tu tu juftufu[uf[i fi | | Re | Ai | Ao | = Ait 13087D-011 Figure 10. LMCS Register 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 ) Offset: ASH | 1 [me [ms [ma [us | mo [ui [mo lex tus] i |a | | po | at | po | 13087D-012 Figure 11. MPCS Register M@ 0257525 0049598 Sbo mm 80C186/80C188 Microprocessors 31cl AMD PRELIMINARY 15 9 3 0 oftse:acH|u Tu lu lu lu lu lu[1[1[:1[:11[:1[:1[ elm | wo} A19 A13 13087D-013 Figure 12. MMCS Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a ots: 4H uu lululululululu[lu[ vl i1[i[i][ ml ml pol Aig A10 13087D-014 Figure 13. PACS Register PCS5 and PCS6 can also be programmed to provide latched address bits A1 and A2. If so programmed, they cannot be used as peripheral selects. These outputs can be connected directly to the AO and A1 pins used for selecting internal registers of 8-bit peripheral chips. This scheme simplifies the external hardware because the peripheral registers can be located on even boundaries in /O or memory space. The starting address of the peripheral chip-select block is defined by the PACS register (see Figure 13). The reg- ister is located at offset A4H in the internal control block. Bits 15-6 of this register correspond to bits 19-10 of the 20-bit Programmable Base Address (PBA) of the peripheral chip-select block. Bits 9-0 of the PBA of the peripheral chip-select block are all Os. If the chip-select block is located in /O space, bits 15-12 must be pro- grammed 0, since the l/O address is only 16-bits wide. Table 9 shows the address range of each peripheral chip select with respect to the PBA contained in PACS register. The user should program bits 15-6 to correspond to the desired peripheral base location. PACS bits 2-0 are used to specify READY mode for PCS3-PCS0. MPCS bits 2-0 specify the READY mode for PCS6-PCS4, as outlined below. The operation mode of the peripheral chip selects is defined by the MPCS register (which is also used to set the size of the mid-range memory chip-select block, see Figure 11). The register is located at offset A8H in the internal control block. Bit 7 is used to select the function of PCS5 and PCS6, while bit 6 is used to select whether the peripheral chip selects are mapped into memory or \/O space. Table 10 describes the programming of these bits. After reset, the contents of both the MPCS and the PACS registers are undefined; however, none of the PCS lines are active until both of the MPCS and PACS registers are accessed. Table 9. PCS Address Ranges PCS Line Active between Locations PCSO PBAPBA + 127 PCStT PBA + 128PBA + 255 PCS2 PBA + 256PBA + 383 PCS3 PBA + 384PBA + 511 PCs4 PBA + 512PBA + 639 PCS5S PBA + 640PBA + 767 PCS6 PBA + 768PBA + 895 READY Generation Logic The 80C186/C 188 can generate a READY signal inter- nally for each of the memory or peripheral CS lines. The number of wait states to be inserted for each peripheral or memory is programmable to provide 30 wait states for all accesses to the area for which the chip select is active. In addition, the 80C186/C188 may be pro- grammed to either ignore external READY for each chip-select range individually, or to factor external READY with the integrated ready generator. Table 10. MS, EX Programming Values Bit Description MS 1 = Peripherals mapped into memory space. 0 = Peripherals mapped into I/O space. EX 0 =5 PCS lines. A1, A2 provided. 1 = 7 PCS lines. A1, A2 are not provided. Me 0257525 0049599 4Th mf 32 80C186/80C188 MicroprocessorsPRELIMINARY READY control consists of three bits for each CS line or group of lines generated by the 80C186/C188. The interpretation of the READY bits is shown in Table 11. Table 11. READY Bits Programming R2 | R1 | RO |Number of Wait States Generated 0 | 0 0 |0 wait states, external RDY also used. 0 | 0 1 | 1 wait state inserted, external RDY also used. 2 wait states inserted, external RDY also used. 3 wait states inserted, external RDY also used. 0 wait states, external RDY ignored. 1 wait state inserted, external RDY ignored. 2 wait states inserted, external RDY ignored. 3 wait states inserted, external RDY ignored. The internal ready generator operates in parallel with external READY, not in series if the external READY is used (R2 = 0). For example, if the internal generator is set to insert two wait states but activity on the external READY lines inserts four wait states, the processor only inserts four wait states, not six. This is because the two wait states generated by the internal generator over- lapped the first two wait states generated by the external ready signal. Note that the external ARDY and SRDY lines are always ignored during cycles accessing inter- nal peripherals. R2-RO0 of each contro! word specify the READY mode for the corresponding block, with the exception of the peripheral chip selects: R2-RO of PACS set the PCS3-PCS0 READY mode, R2-R0 of MPCS set the PCS6-PCS4 READY mode. Chip Select/Ready Logic and Reset Upon RESET, the Chip Select/Ready Logic performs the following actions: 1. All chip-select outputs are driven High. 2. Upon leaving RESET, the UCS line is programmed to provide chip selects to a 1K block with the accompanying READY control bits set at 011 to insert three wait states in conjunction with external READY (i.e., UMCS resets to FFBH). 3. No other chip select or READY control registers have any predefined values after RESET. They do not become active until the CPU accesses their control registers. Both the PACS and MPCS registers must be accessed before the PCS lines become active. AMD cl DMA CHANNELS The 80C186/C188 DMA controllers provides two inde- pendent high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., Memory to I/O) or within the same space (e.g., Memory to Memory or I/O to I/O). Data can be transferred either in bytes (8 bits) or in words (16 bits) to or from even or odd addresses. Each DMA channel maintains both a 20-bit source and destination pointer that can be optionally incremented or decremented after each data transfer (by one or two, depending on byte or word transfers). Each data transfer consumes two bus cycles (a minimum of eight clocks), one cycle to fetch data and the other to store data. DMA Operation Each channel has six registers in the control block that define each channel's specific operation. The control registers consist of a 20-bit Source pointer (2 words), a 20-bit Destination Pointer (2 words), a 16-bit Transfer Count Register, and a 16-bit Control Word. The format of the DMA Control Blocks is shown in Table 12. The Transfer Count Register (TC) specifies the number of DMA transfers to be performed. Up to 64K byte or word transfers can be performed with automatic termination. The Control Word defines the channel's operation (see Figure 15a and 15b). Allregisters may be modified or altered during any DMA activity. Any changes made to these registers are reflected immediately in DMA operation. Table 12. DMA Control Block Format Register Address Register Name Cho Ch Control Word CAH DAH Transfer Count C8H D8H Destination Pointer (upper 4 bits) C6H D6H Destination Pointer C4H D4H Source Pointer (upper 4 bits) C2H D2H Source Pointer COH DOH DMA Channel Control Word Register Each DMA Channel Control Word determines the mode of operation for the particular 80C 186/C188 DMA chan- nel. This register specifies m the mode of synchronization m whether bytes or words are transferred (800186 only) m whether interrupts are generated after the last transfer m whether DMA activity ceases after a programmed number of DMA cycles M 0257525 0049600 TH mm 80C186/80C188 Microprocessors 33cl AMD the relative priority of the DMA channel with respect to the other DMA channel m whether the source pointer is incremented, decremented, or maintained constant after each transfer m whether the source pointer addresses memory or VO space m whether the destination pointer is incremented, decremented, or maintained constant after each transfer m whether the destination pointer addresses memory or /O space The DMA channel control registers may be changed while the channel is operating. However, any changes made during operation affect the current DMA transfer. DMA Control Word Bit Descriptions DEST: MAG Destination pointer is in memory (1) or I/O (0) space. DEC Decrement destination pointer by 1 (1 or 2 for the 80C186 depending on B/W). PRELIMINARY INC Increment destination pointer by 1 (1 or 2 for the 80C186 depending on B/W) after each transfer. If both INC and DEC are specified, the pointer remains constant after each cycle. SOURCE: MAG DEC INC TC Source pointer is in M/IO space (1/0). Decrement source pointer by 1 (1 or 2 for the 80C186 depending on B/W) after each transfer. Increment source pointer by 1 (1 or 2 for the 80C186 depending on B/W) after each transfer. If both INC and DEC are specified, the pointer remains constant after each cycle. If set, DMA terminates when the contents of the Transfer Count register reach 0. The ST/STGOP bitis also reset at this point. If this bit is cleared, the DMA unit decrements the transfer count register for each DMA cycle, but the DMA transfer does not stop when the contents of the TC register reach 0. SRC. Adrs. Pointer Ch. 1 0 nter SRC. Adrs. Pointer Ch. 0 Internal Address/Data Bus Adder Control Logic Timer Request DRQ1 Request Selection Logic DRQOo interrupt Request 13087D-015 Figure 14. DMA Unit Block Diagram M@@ 0257525 0049601 4c 34 80C186/80C188 MicroprocessorsMm &T? eO9bhOO SeseSceO PRELIMINARY 15 14 13 12 11 10 9 8 Z 6 5 4 3 2 1 0 Destination Source cHa | sty MIG DEC ING | MAG DEC Inc | Tc | INT SYN P |TDRQ} X |NOcHG STOP! Bw Figure 15a. DMA Control Register for the 80C186 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Destination Source cHa | sty MIG DEC INC | MfO DEC INC | Tc | INT SYN P |TDRQ]| X |NOGHQ stop] xX Figure 15b. DMA Control Register for the 800188 INT Enable Interrupts to CPU upon transfer count ually incremented or decremented after each transfer. If termination. word transfers are performed, the pointer is increm- SYN 00 No synchronization ented or decremented by two. Note: When unsynchronized transfers are specified, the TC Each pointer may point into either memory or I/O space. bit is ignor ed and the STATOP bit is cleared pon the Since the upper four bits of the address are not automat- transfer count reaching zero, stopping the channel. ically programmed to zero, the user must program them 01 Source synchronization in order to address the normal 64K I/O space. Since the 10 Destination synchronization DMA channels can perform transfers to or from odd U addresses, there is no restriction on values for the "1 nused pointer registers. Higher transfer rates can be achieved P Channel priority relative to other if all word transfers are performed to or from even channel during simuitaneous requests addresses so that accesses occur in single bus cycles. 0 Low priority 1 High priority Higher Regist - Channels alternate cycles if both are set at Address XXX XXX XXX AI9A16 same priority level. Lower i A15-A12]A11-A8 | A7-A4 A3-A0 TDRQ Enable/Disable (1/0) DMA requests from hegister Timer 2. 15 0 CHG/NOCHG ; XXX = Dont Care Change/Do not change (1/0) ST/STOP bit. If 13087D-017 this bit is set when writing to the control word, . . the ST/STOP bit is programmed by the write to Figure 16. DMA Pointer Register Format the control word. If this bit is cleared when writing the control word, the ST/STOP bit is : not altered. This bit is not stored; it is always DMA Transfer Count Register read as 0. Each DMA channel maintains a 16-bit transfer count ST/STOP register (TC). This register is decremented after every Start/Stop (4/0) ch | DMA cycle, regardless of the state of the TC bit in the _ art/Stop (1/0) channe DMA Control Register. However, if the TC bit inthe DMA Bw Byte/Word (0/1) transfers (for the 80C186 control word is set or if unsynchronized transfers are only) programmed, DMA activity terminates when the transfer DMA Destination and Source Pointer counter register reaches 0. Registers Each DMA channel maintains a 20-bit source and a 20-bit destination pointer. Each of these pointers takes up two full 16-bit registers inthe peripheral control block. Foreach DMAchannel to be used, all four pointer regis- ters must be initialized. The lower four bits of the upper register contain the upper four bits of the 20-bit physical address (see Figure 16). These pointers may be individ- DMA Requests Data transfers may be either source or destination syn- chronized, that is, either the source of the data or the destination of the data may request the data transfer. In addition, DMA transfers may be unsynchronized:; that is, the transfer takes place continually until the correct number of transfers has occurred. When source or 80C186/80C188 Microprocessors 35cl AMD unsynchronized transfers are performed, the DMA channel may begin another transfer immediately after the end of a previous DMA transfer. This allows a com- plete transfer to take place every two bus cycles or eight clock cycles (assuming no wait states). When destina- tion synchronization is performed, data will not be fetched from the source address until the destination device signals that itis ready to receive it. When destina- tion synchronized transfers are requested, the DMA controller relinquishes control of the bus after every transfer. If no other bus activity is initiated, another DMA cycle begins after two processor clocks. This allows the destination device time to remove its request if another transfer is not desired. Since the DMA controller relin- quishes the bus, the CPU can initiate a bus cycle. As a result, a complete bus cycle is often inserted between destination-synchronized transfers. Table 13 shows the maximum DMA transfer rates. DMA Acknowledge No explicit DMA acknowledge pulse is provided. Since both source and destination pointers are maintained, a read from a requesting source or a write to a requesting destination should be used as the DMA acknowledge sig- nal. Since the chip-select lines can be programmed to be active for a given block of memory or I/O space, and the DMA pointers can be programmed to point to the same given block, a chip-select line could be used to indicate a DMA acknowledge. DMA Priority The DMA channels may be programmed such that one channel is always given priority over the other, or they may be programmed such as to alternate cycles when both have DMA requests pending. DMA cycles always have priority over internal CPU cycles except between lacked memory accesses or word accesses to odd memory locations; however, an external bus hold takes priority over an internal DMA cycle. Because an interrupt request cannot suspend a DMA operation and the CPU PRELIMINARY cannot access memory during a DMA cycle, interrupt latency time suffers during sequences of continuous DMA cycles. An NMI request, however, causes all inter- nal DMA activity to halt. This allows the CPU to quickly respond to the NMI request. DMA Programming DMA cycles occur whenever the ST/STOP bit of the con- trol register is set. If synchronized transfers are pro- grammed, a DRQ must also be generated. Therefore, the source and destination transfer pointers, and the transfer count register (if used) must be programmed before the ST/STOP bit is set. Each DMA register may be modified while the channel is operating. ifthe CHG/NOCHG bitis cleared when the con- trol register is written, the ST/STOP bit of the control regis- teris not modified by the write. If multiple channel! registers are modified, it is recommended that a LOCKED string transfer be used to prevent a DMA transfer from occurring between updates to the channel registers. DMA Channels and Reset Upon RESET, the state of the DMA channels is as follows: mw The ST/STOP bit for each channel is reset to STOP. m Any transfer in progress is aborted. m The values of the transfer count registers, source pointers, and destination pointers are indeterminate. TIMERS The 800 186/C188 provide three internal 16-bit program- mable timers (see Figure 17). Two of these are highly flexible and are connected to four external pins (two per timer). They can be used to count external events, time external events, generate non-repetitive waveforms, etc. The third timer is not connected to any external pins and is useful for real-time coding and time delay applications. In addition, the third timer can be used as a prescaler to the other two, or as a DMA request source. Table 13. Maximum DMA Transfer Rates at 25 MHz for the 80C186/80C188 800186 800188 Type of Synchronization Selected CPU CPU CPU CPU Units Running Halted Running Halted Unsynchronized 6.25 6.25 3.1 3.1 Mbytes/s Source Synch 6.25 6.25 3.4 3.4 Mbytes/s Destination Synch 4.2 5.0 2.1 2.5 Mbytes/s M@ 0257525 OO45EO3 755 36 80C186/80C188 MicroprocessorsPRELIMINARY AMD al TO To T1 T1 In Out In Out [-*_ DMA Req, TO Ti Int. > Int. r> T2 Int. Req. Req. Req. T2 Out r Timer 0 Timer 1 Max Count Value A Max Count Value A Timer 2 #Clock/4 Max Count Value B Clock/4 Max Count Value B Max Count Value Mode/Control Word Mode/Control Word Mode/Control Word \ Internal Address/Data Bus \ All 16-Bit Registers 13088 B002 Figure 17. Timer Block Diagram Timer Operation The timers are controlled by eleven 16-bit registers in the peripheral control block. The configuration of these regis- ters is shown in Table 14. The count register contains the current value of the timer. It can be read or written at any time independent of whether the timer is running or not. The value of this register is incremented for each timer event. Each of the timers is equipped with a MAX COUNT register, which defines the maximum count the timer will reach. After reaching the MAX COUNT register value, the timer count value resets to 0 during that same clock, that is, the maximum count value is never stored in the count register itself. In addition, timers 0 and 1 are equipped with a second MAX COUNT register that enables the timers to alternate their count between two different MAX COUNT values. If a single MAX COUNT register is used, the timer output pin switches Low for a clock, one clock after the maximum count value has been reached. Inthe dual MAX COUNT register mode, the out- put pin indicates which MAX COUNT register is currently in use, thus allowing nearly complete freedom in select- ing waveform duty cycles. For the timers with two MAX COUNT registers, the RIU bit in the control register deter- mines which is used for the comparison. Each timer gets serviced every fourth CPU-clock cycle, and thus, can operate at speeds up to one-quarter the internal clock frequency (one-eighth the crystal rate). External clocking of the timers may be done at up to a rate of one-quarter of the internal CPU-clock rate. Due to internal synchronization and pipelining of the timer cir- cuitry, a timer output may take up to six clocks to respond to any individual clock or gate input. Since the count registers and the maximum count regis- ters are all 16-bits wide, 16 bits of resolution are provided. However, any read or write access to the timers adds one wait state to the minimum four-clock bus cycle. This is needed to synchronize and coordinate the internal data flows between the internal timers and the internal bus. The timers have several programmable options: w All three timers can be set to halt or continue on a terminal count. m Timers 0 and 1 can select between internal and external clocks, alternate between MAX COUNT registers, and be set to retrigger on external events. m The timers may be programmed to cause an interrupt on terminal count. These options are selectable via the timer mode/contro! word. Timer Mode/Control Register The mode/control register (see Figure 18) allows the user to program the specific mode of operation or check the current programmed status for any of the three inte- grated timers. me 0257525 OO49604 691 80C186/80C188 Microprocessors 37Me fes SO%hOO Secseseo my al AMD PRELIMINARY Table 14. Timer Control Block Format Register Offset Register Name Timer 0 | Timer1 | Timer 2 Mode/Control Word 56H 5EH 66H Max Count B 54H 5CH | Not Present Max Count A 52H 5AH 62H Count Register 50H 58H 60H EN The Enable bit provides programmer contro! over the timers RUN/HALT status. When set, the timer is enabled to increment subject to the input pin constraints in the internal clock mode (discussed previously). When cleared, the timer is inhibited from counting. Allinput pin transitions during the time EN is 0 are ignored. If CONT is 0, the EN bit is automatically cleared upon maximum count. INH The Inhibit bit allows the selective updating of the enable (EN) bit. if INH is a 1 during the write to the mode/control word, thenthe state of the EN bit is modified by the write. If INH is a 0 during the write, the EN bit is unaffected by the operation. This bit is not stored; itis always a0 ona read. INT When set, the INT bit enables interrupts from the timer, which are generated on every terminal count. If the timer is configured in dual MAX COUNT register mode, an interrupt is generated each time the value in MAX COUNT register A is reached and each time the value in MAX COUNT register B is reached. If this enable bit is cleared after the interrupt request has been generated, but before a pending interrupt is serviced, the interrupt request is still in force. (The request is latched in the Interrupt Controller.) RIU The Register In Use bit indicates which MAX COUNT register is currently being used for comparison to the timer count value. A 0 value indicates register A. The RIU bit cannot be written (ie., its value is not affected when the control register is written). It is always cleared when the ALT bit is 0. MC The Maximum Count bit is set whenever the timer reaches its final maximum count value. If the timer is configured in dual MAX COUNT register mode, this bit willbe set each time the value in MAX COUNT register A is reached, and each time the value in MAX COUNT reg- ister B is reached. This bit is set regardless of the timer's interrupt-enable bit. The MC bit gives the user the ability to monitor timer status through software instead of through interrupts. Programmers intervention is required to clear this bit. RTG Retrigger bit is only active for internal clocking (EXT = 0). Inthis case, it determines the contro! function provided by the input pin. \f RTG = 0, the input level gates the internal clock on and off. If the input pin is High, the timer counts; if the input pin is Low, the timer holds its value. As indicated pre- viously, the input signal may be asynchronous with respect to the 80C186/C188 clock. When RTG = 1, the input pin detects Low-to-High tran- sitions. The first such transition starts the timer running, clearing the timer value to 0 on the first clock, and then incrementing thereafter. Further transitions on the input pin again reset the timer to 0, from which it starts count- ing up again. If CONT = 0, when the timer has reached maximum count, the EN bit is cleared, inhibiting further timer activity. P The Prescaler bit is ignored unless internal clocking has been selected (EXT = 0). If the P bit is a 0, the timer counts at one-fourth the internal CPU clock rate. If the P bit is a 1, the output of Timer 2 is used as a clock for the timer. Note that the user must initialize and start Timer 2 to obtain the prescaled clock. EXT The External bit selects between internal and external clocking for the timer. The external signal may be asynchronous with respect to the 80C186/C188 clock. If this bit is set, the timer counts Low-to-High transitions on the input pin. If cleared, it counts an internal clock while using the input pin for control. In this mode, the function of the external pin is defined by the RTG bit. The maximum input to output transition latency time may be as much as six clocks. However, clock inputs may be pipelined as closely together as every four clocks with- out losing clock pulses. 15 14 13 12 1 5 4 3 2 1 0 fen Tina Tint [aw [ o |... [wc [are| ep lexriarr [cont | 13087D-019 Figure 18. Timer Mode/Control Register 38 80C186/80C188 MicroprocessorsPRELIMINARY ALT The ALT bit determines which of two MAX COUNT reg- isters is used for count comparison. If ALT = 0, register Aforthat timer is always used, while if ALT = 1, the com- parison alternates between register A and register B when each maximum count is reached. This alternation allows the user to change one MAX COUNT register while the other is being used, and thus provides a method of generating non-repetitive waveforms. Square waves and pulse outputs of any duty cycle are a subset of available signals obtained by not changing the final count registers. The ALT bit also determines the function of the timer output pin. If ALT is 0, the output pin goes Low for one clock, the clock after the maximum count is reached. If ALT is 1, the output pin reflects the current MAX COUNT register being used (0/1 for B/A). CONT Setting the CONT bit causes the associated timer to run continuously, while resetting it causes the timer to halt upon maximum count. If CONT = 0 and ALT = 1, the timer counts to the MAX COUNT register A value, resets, counts to the register B value, resets, and halts. Not all mode bits are provided for Timer 2. Certain bits are hardwired as indicated below: ALT = 0, EXT=0, P=0, RTG=0, RIU=0 Count Registers Each of the three timers has a 16-bit count register. The contents of this register may be read or written by the processor at any time. If the register is written into while the timer is counting, the new value takes effect in the current count cycle. The count registers should be programmed before attempting to use the timers, since they are not automat- ically initialized to zero. Max Count Registers Timers 0 and 1 have two MAX COUNT registers, while Timer 2 has a single MAX COUNT register. These con- tain the number of events the timer counts. In Timers 0 and 1, the MAX COUNT register used can alternate between the two MAX COUNT values whenever the current maximum count is reached. A timer resets when the timer count register equals the MAX COUNT value being used. If the timer count register or the MAX COUNT register is changed so that the MAX COUNT is less than the timer count, the timer does not immediately reset. Instead, the timer counts up to OFFFFH, wraps around to zero, counts up to the MAX COUNT value, and then resets. Timers and Reset Upon RESET, the Timers perform the following actions: me 0257525 OO4Sb0b 4b4 AMD Pa 1. All EN (Enable) bits are reset preventing timer counting. 2. For Timers 0 and 1, the RIU bits are reset to zero and the ALT bits are set to one. This results in the Timer Out pins going High. 3. The contents of the count registers are indeterminate. INTERRUPT CONTROLLER The 80C186/C 188 can receive interrupts from a number of sources, both internal and external. The internal inter- rupt controller serves to merge these requests on a priority basis for individual service by the CPU. Internal interrupt sources (Timers and DMA channels) canbe disabled by their own control registers or by mask bits within the interrupt controller. The 80C186/C188 interrupt controller has its own control register that sets the mode of operation for the controller. The interrupt controller resolves priority among requests that are pending simultaneously. Nesting is provided so interrupt service routines for lower priority interrupts may themselves be interrupted by higher priority interrupts. A block diagram of the interrupt con- troller is shown in Figure 19. The 80C186/C188 have a special slave mode in which the internal interrupt controller acts as a slave to an external master. The controller is programmed into this mode by setting bit 14 in the peripheral control block relocation register (see Slave Mode section). MASTER MODE OPERATION Interrupt Controller External Interface Five pins are provided for external interrupt sources. One of these pins is the non-maskable interrupt, NMI. NM! is generally used for unusual events such as power- fail interrupts. The other four pins may be configured in any of the following ways: m As four interrupt lines with internally generated interrupt vectors; g As an interrupt line and interrupt acknowledge line pair (cascade made) with externally generated interrupt vectors, plus two interrupt input lines with internally generated vectors; and, m As two pairs of interrupt/interrupt acknowledge lines (cascade mode) with externally generated interrupt vectors. External sources in the Cascade Mode use externally generated interrupt vectors. When an interrupt is acknowledged, two INTA cycles are initiated and the vector is read into the 80C186/C188 on the second cycle. The capability to interface to external 82C59A programmable interrupt controllers is provided when the inputs are configured in Cascade Mode. 80C186/80C188 Microprocessors 39al AMD PRELIMINARY Timer Timer Timer DMA OMA 0 1 2 0 1 INTO INTI/SELECT INT2/NTAO INT3/INTAT/IROQ NMI Timer Control Register Interrupt Request Register DMA 0 Control Register Interrupt Mask Register DMA 1 Control Register In-Service Register Interrupt Ext. Input 0 Control Register y Priority Priority Level Mask Register Resolver Ext. Input 1 Control Register Interrupt Status Register Ext. Input 2 Control Register Vector Generation Ext. input 3 Control Register Lagic Interrupt Request to <_ Processor < Internal Address/Data Bus 13088B-003 Figure 19. interrupt Controller Block Diagram Interrupt Controller Modes of Operation The basic modes of operation of the interrupt controller in Master Mode are similar to the 82C59A. The interrupt controller responds identically to internal interrupts in all three modes; the difference is only in the interpretation of function of the four external interrupt pins. The inter- rupt controller is set into one of these three modes by programming the correct bits in the INTO and INT1 con- trol registers. The modes of interrupt controller opera- tion are as follows. Fully Nested Mode When in the Fully Nested Mode, four pins are used as direct interrupt requests as in Figure 20. The vectors for these four inputs are generated internally. An in-service bit is provided for every interrupt source. If a lower-prior- ity device requests an interrupt while the in-service bit (IS) is set, no interrupt is generated by the interrupt con- troller. In addition, if another interrupt request occurs from the same interrupt source while the in-service bit is set, no interrupt is generated by the interrupt controller. This allows interrupt service routines to operate with We 0257525 OO4Ib0? 3TO interrupts enabled, yet be suspended only by interrupts of higher priority than the in-service interrupt. INTO ke-_ Interrupt Source INT1 ke-_ Interrupt Source 80C186/ 80C188 INT2 ke Interrupt Source INT3 }#_ Interrupt Source 13087D-021 Figure 20. Fully Nested (Direct) Mode Interrupt Controller Connections When a service routine is completed, the proper IS bit must be reset by writing the proper pattern to the EO! register. This is required to allow subsequent interrupts from this interrupt source and to allow servicing of lower- 40 80C186/80C188 MicroprocessorsPRELIMINARY priority interrupts. An EOI command is executed at the end of the service routine just before the return from interrupt instruction. If the fully nested structure has been upheld, the next highest-priority source with its |S bit set is then serviced. Cascade Mode The 80C186/C 188 has four interrupt pins andtwo of them have dual functions. In the Fully Nested Mode, the four pins are used as direct interrupt inputs and the corre- sponding vectors are generated intemally. In the Cas- cade Mode, the four pins are configured into interrupt input-dedicated acknowledge signal pairs. The intercon- nection is shown in Figure 21. INTO is an interrupt input interfaced to an 82C59A, while INT2/INTAO serves as the dedicated interrupt acknowledge signal to that periph- eral. The same is true for INT1 and INT3/INTA1. Each pair can selectively be placed in the Cascade or Non-cas- cade Mode by programming the proper value into INTO and INT1 control registers. The use of the dedicated acknowledge signals eliminates the need for the use of external logic to generate INTA and device select signals. The Primary Cascade Mode allows the capability to serve up to 128 external interrupt sources through the use of external master and slave 82C59As. Three levels of priority are created, requiring priority resolu- tion inthe 80C 186/C 188 interrupt controller, the mas- ter 82C59As, and the slave 82C59As. If an external interrupt is serviced, one IS bit is set at each of these AMD cl levels. When the interrupt service routine is completed, up to three end-of-interrupt commands must be issued by the programmer. Special Fully Nested Mode This mode is entered by setting the SFNM bit in INTO or INT1 control register. It enables complete nestability with external 82C59A masters. Normally, an interrupt request from an interrupt source is not recognized unless the in-service bit for that source is reset. If more than one interrupt source is connected to an external interrupt controller, all of the interrupts are funnelled through the same 80C186/C188 interrupt request pin. As a result, if the external interrupt controller receives a higher-priority interrupt, its interrupt is not recognized by the 80C186/C188 controller until the 80C186/C 188 in- service bit is reset. In Special Fully Nested Mode, the 80C186/C188 interrupt controller allows interrupts from an external pin, regardless of the state of the in-service bit for an interrupt source, in order to allow multiple inter- rupts from a single pin. An in-service bit continues to be set, however, to inhibit interrupts from other lower-prior- ity 80C186/C 188 interrupt sources. Special procedures should be followed when resetting IS bits at the end of interrupt service routines. Software polling of the IS register in the external master 82C59A is required to determine if there is more than one bit set. If so, the IS bit in the 80C186/C188 remains active and the next interrupt service routine is entered. 82C59A INTAO 80C186/ 800188 INT1 82C59A Interrupt Sources 82C59A 82C59A oeoe et ee ewe ewe eee eeved Interrupt Sources 13087D-022 Figure 21. Cascade and Special Fully Nested Mode Interrupt Controller Connections MM 0257525 0049608 237 80C186/80C188 Microprocessors 41al AMD Operation in a Polled Environment The controller may be used ina polled mode if interrupts are undesirable. When polling, the processor disables interrupts and then polls the interrupt controller when- ever it is convenient. Polling the interrupt controller is accomplished by reading the Poll Word (Figure 30). Bit 15 in the Poll Word indicates to the processor that an interrupt of high enough priority is requesting service. Bits 40 indicate to the processor the type vector of the highest-priority source requesting service. Reading the Poll Word causes the in-service bit of the highest-priority source to be set. It is desirable to be able to read the Poll Word informa- tion without guaranteeing service of any pending inter- rupt, that is, not set the indicated in-service bit. The 80C186/C188 provides a Poll Status Word, in addition to the conventional Poll Word, to allow this to be done. Poll Word information is duplicated in the Poll Status Word, but reading the Poll Status Word does not set the associated in-service bit. These words are located in two adjacent memory locations in the register file. Master Mode Features Programmable Priority The user can program the interrupt sources into any of eight different priority levels. The programming is done by placing a three-bit priority level (0-7) in the control register of each interrupt source. (A source with a prior- ity level of 4 has higher priority over all priority levels from 5 to 7. Priority registers containing values lower than 4 have greater priority.) All interrupt sources have preprogrammed default priority levels (see Table 3). If two requests with the same programmed priority level are pending at once, the priority ordering scheme shown in Table 3 is used. If the serviced interrupt routine re-en- ables interrupts, it allows other interrupt requests to be serviced. End-of-Interrupt Command The end-of-interrupt (EOI) command is used by the pro- grammer to reset the in-service (IS) bit when an interrupt service routine is completed. The EQI command is issued by writing the proper pattern to the EOI register. There are two types of EOI commands, specific and non-specific. The non-specific command does not spec- ify which IS bit is reset. When issued, the interrupt con- troller automatically resets the 1S bit of the highest priority source with an active service routine. A specific EO! command requires that the programmer send the interrupt vector type to the interrupt controller indicating which source's IS bit is to be reset. This command is used when the fully nested structure has been disturbed or the highest priority 1S bit that was set does not belong to the service routine in progress. PRELIMINARY Trigger Mode The four external interrupt pins can be programmed in either Edge- or Level-trigger Mode. The control register for each external source has a Leveltrigger Mode (LTM) bit. All interrupt inputs are active High. In the Edge-sense Mode or the Level-trigger Mode, the interrupt request must remain active (High) until the interrupt request is acknowl- edged by the 80C186/C188 CPU. In the Edge-sense Mode, if the level remains High after the interrupt is acknowledged, the input is disabled and no further requests are generated. The input level must go Low for at least one clock cycle to re-enable the input. In the Level- trigger Mode, no such provision is made; holding the inter- rupt input High causes continuous interrupt requests. Interrupt Vectoring The 80C186/C188 Interrupt Controller generates interrupt vectors for the integrated DMA channels and the inte- grated timers. In addition, the Interrupt Controller gener- ates interrupt vectors for the external interrupt lines, if they are not configured in Cascade or Special Fully Nested Mode. The interrupt vectors generated are fixed and can- not be changed (see Table 3). Interrupt Controller Registers The Interrupt Controller Register Mode is shown in Figure 22. It contains 15 registers. All registers can either be read or written, unless specified otherwise. Offset INT3 Contro! Register 3EH INT2 Control Register 3CH INT1 Control Register 3AH INTO Control Register 38H BMA 1 Control Register 36H DMA 0 Control Register 34H Timer Control Register 32H Interrupt Status Register 30H Interrupt Request Register 2EH In-Service Register 2CH Priority Mask Register 2AH Mask Register 28H Poll Status Register 26H Poll Register 24H EOI Register 22H 13087D-023 Figure 22. Interrupt Controller Register (Master Mode) MB 0257525 0044609 173 42 80C186/80C188 MicroprocessorsM Sb OTSbhog SeS520 my PRELIMINARY In-Service Register This register can be read from or written into. The for- mat is shown in Figure 23. It contains the in-service bit for each of the interrupt sources. The in-service bit is set to indicate that a sources service routine is in prog- ress. When an in-service bitis set, the interrupt control- ler does not generate interrupts to the CPU when it receives interrupt requests from devices with a lower programmed priority level. The TMR bit is the in-service bit for all three timers; the DO and D1 bits are the in-ser- vice bits for the two DMA channels; the 13-10 are the in- service bits for the external interrupt pins. The IS bit is set when the processor acknowledges an interrupt request either by an interrupt acknowledge or by read- ing the poll register. The IS bit is reset at the end of the interrupt service routine by an end-of-interrupt com- mand. Interrupt Request Register The internal interrupt sources have interrupt request bits inside the interrupt controller, The format of this register is shown in Figure 23. A read from this register yields the status of these bits. The TMR bit is the logical OR of all timer interrupt requests. DO and D1 are the interrupt request bits for the DMA channels. The state of the external interrupt input pins is also indi- cated. The state of the external interrupt pins is not a stored condition inside the interrupt controller; there- fore, the external interrupt bits cannot be written. The external interrupt request bits are set when an interrupt request is given to the interrupt controller, so if Edge- triggered Mode is selected, the bit in the register is High only after an inactive-to-active transition. For internal interrupt sources, the register bits are set when a request arrives and are reset when the processor acknowledges the requests. Writes to the interrupt request register affect the DO and D1 interrupt request bits. Setting either bit causes the corresponding interrupt request, while clearing either bit removes the corresponding interrupt request. All other bits in the register are read-only. Mask Register This is a 16-bit register that contains a mask bit for each interrupt source. The format for this register is shown in Figure 23. A one in abit position corresponding to a par- ticular source serves to mask the source from generat- ing interrupts. These mask bits are the exact same bits AMD at that are used in the individual control registers; pro- gramming a mask bit using the mask register also changes this bit in the individual contro! registers, and vice versa. Priority Mask Register This register is used to mask all interrupts below a partic- ular interrupt priority level. The format of this register is shown in Figure 24. The code in the lower three bits of this register inhibits interrupts of priority lower (a higher priority number) than the code specified. For example, 100 written into this register masks interrupts of level five (101), six (110), and seven (111). The register is reset to seven (111) upon RESET so no interrupts are masked due to priority number. Interrupt Status Register This register contains general interrupt controller status information. The format of this register is shown in Fig- ure 25. The bits in the status register have the following functions: DHLT: DMA Halt Transfer; setting this bit halts all DMA transfers. It is automatically set when- ever anon-maskable interrupt occurs, and it is reset when an IRET instruction is executed. This bit allows prompt service of all non-mask- able interrupts. This bit may also be set by the programmer. IRTx: These three bits represent the individual timer interrupt request bits. These bits differentiate between timer interrupts, since the timer IR bit in the interrupt request register is the OR func- tion of all timer interrupt requests. Note that setting any one of these three bits initiates an interrupt request to the interrupt controller. Control Registers: Timer, DMA 0, 1 These registers are the control words for all the internal interrupt sources. The format for these registers is shown in Figure 26. The three bit pasitions PRO, PR1, and PR2 represent the programmable priority level of the interrupt source. The MSK bit inhibits interrupt requests from the interrupt source. The MSK bits in the individual control registers are the exact same bits as in the Mask Register; modifying them in the individual con- trol registers also modifies them in the Mask Register, and vice versa. 1514 10 9 8 7 6 5 4 3 2 1 0 olol. fof of of 3] ef uf] iw] of bol o [tal 13087D-024 Figure 23. In-Service, Interrupt Request, and Mask Register Formats 80C186/80C188 Microprocessors 431 amo PRELIMINARY 15 14 3 2 1 0 fo Toy... | PRM] PRMt] PRMO | 13087D-025 Figure 24. Priority Mask Register Format 15 14 7 6 5 4 3 2 1 0 font. of... fo J oo | oo [ oo | oo [irra] ints] ito} 13087D-026 Figure 25. Interrupt Status Register Format (Master Mode) 15 14 4 3 2 14 0 folofl.. . 2. | io [sk] pre{ Pri] PRO} 13087D-027 Figure 26. Timer/DMA Control Register Formats 15 14 7 6 5 4 3 2 14 0 fofof. . . . 2. J] 0 [senm] c [tm | Msk] Pre | PRt | PRO | 13087D-028 Figure 27. INTO/INT1 Control Register Formats 15 14 5 4 3 2 1. 0 folTof. . .. 2... Jo [ttm | Msk] pre {| Pri] PRo | 13087D-029 Figure 28. INT2/INT3 Control Register Formats M@@ 0257525 O045b11 421 44 80C186/80C188 MicroprocessorsPRELIMINARY INT3-INTO Control Registers These registers are the control words for the four exter- nal input pins. Figure 27 shows the format of the INTO and INT1 control registers; Figure 28 shows the format of the INT2 and INT3 control registers. In Cascade Mode or Special Fully Nested Mode, the control words for INT2 and INT3 are not used. The bits in the various control registers are encoded as follows: PR2-0: Priority programming information. Highest priority = 000, lowest priority = 111. LTM: Level-trigger Mode bit. 1 = level-triggered; 0 = edge-triggered. Interrupt input levels are active High. In Level-triggered Mode, an interrupt is generated whenever the external line is High. in Edge-triggered Mode, an interrupt is generated only when this level is preceded by an inactive-to-active transition on the line. In both cases, the level must remain active until the interrupt is acknowledged. MSK: Mask bit, 1 = mask; 0 = non-mask. C: Cascade Mode bit, 1 = cascade; 0 = direct. SFNM: Special Fully Nested Mode bit, 1 = SFNM. EOI Register The end of the interrupt register is a command register that can only be written into. The format of this register is shown in Figure 29. It initiates an EO! command when written to by the 80C186/C188 CPU. The bits in the EOI register are encoded as follows: Sx: Encoded information that specifies an interrupt source vector type as shown in Table 3. For example, to reset the in-service bit for DMA channel 0, these bits should be set to 01010, since the vector type for DMA channel 0 is 10. Note: To reset the single in-service bit for any of the three timers, the vector type for Timer 0(8) should be writ- ten in this register. NSPEC/SPEC: A bit that determines the type of EO! command. Non-specific = 1, Specific = 0. Poll and Poll Status Registers These registers contain polling information. The format of these registers is shown in Figure 30. They can only be read. Reading the Poll register constitutes a software poll. This sets the [S bit of the highest priority pending AMD cl interrupt. Reading the poll status register does not set the IS bit of the highest priority pending interrupt; only the status of pending interrupts is provided. Encoding of the Poll and Poll Status register bits are as follows: Sy: Encoded information that indicates the vector type of the highest priority interrupting source. Valid only when INTREQ = 1. INTREQ: This bit determines if an interrupt request is present. Interrupt Request =1; no Interrupt Request = 0. SLAVE MODE OPERATION When Slave Mode is used, the internal 80C186/C188 interrupt controller is used as a slave controller to an external master interrupt controller. The internal 80C186/C188 resources are monitored by the internal interrupt controller, while the external controller func- tions as the system master interrupt controller. Upon reset, the 80C186/C 188 is in the Master Mode. To provide for Slave Mode operation, bit 14 of the reloca- tion register should be set (see Figure 7). Because of pin limitations caused by the need to inter- face to an external 82C59A master, the internal interrupt controller no longer accepts external inputs. There are, however, enough 80C186/C188 interrupt controller inputs (internally) to dedicate one to each timer. In this mode, each timer interrupt source has its own mask bit, 1S bit, and control word. in Slave Mode each peripheral must be assigned a unique priority to ensure proper interrupt controller operation. Theretore, itis the programmer's responsibil- ity to assign correct priorities and initialize interrupt con- trol registers before enabling interrupts. Slave Mode External Interface The configuration of the 80C186/C188 with respect to an external 82C59A master is shown in Figure 31. The INTO input is used as the 80C186/C188 CPU interrupt input. INT3/IRQ functions as an output to send the 800186/C188 slave-interrupt-request to one of the eight master PIC inputs. Correct master-slave interface requires decoding of the slave addresses (CAS2-CAS0). Slave 82C59As do this internally. Because of pin limitations, the 80C186/C188 slave address has to be decoded externally. INT1/SELECT is used as a slave-select input. Note that the slave vector address is transferred internally, but the READY input must be supplied externally. Mi 0257525 OO4Ib12 768 om 80C186/80C188 Microprocessors 45Pa AMD PRELIMINARY 15 14 13 SPEC/ Nspec| 9 | 9 13087D-030 Figure 29. EOI Register Format 15 14 13 4 3 2 1 0 INT REQ! 0 0 $4] S3] S2] S1 So 13087D-031 Figure 30. Poll Register Format | ' Interrupt Sources INTO INT 4 or Other Slaves Voc <<_ 82C59A j+ CPU 4 _ ?_~ INTAO INTA 4 80C186/ 80C188 SELECT Ie Cascade PIC Address Decoder IRQ _ 13087D-030 Figure 31. Slave Mode Interrupt Controller Connections INT2/INTAO is used as an acknowledge output, suitable to drive the INTA input of an 82C59A. Interrupt Nesting Slave Mode operation allows nesting of interrupt requests. When an interrupt is acknowledged, the prior- ity logic masks off all priority levels except those with equal or higher priority. Vector Generation in the Slave Mode Vector generation in Slave Mode is exactly like that of an 8259A or 82C59A slave. The interrupt controller gener- ates an 8-bit vector type number that the CPU multiplies by four and uses as an address into the vectortable. The five most significant bits of this type number are user- programmable, while the three least significant bits are defined according to Figure 32. The significant five bits of the vector are programmed by writing to the Interrupt Vector register at offset 20H. Specific End-of-Interrupt In Slave Mode, the specific EO! command operates to reset an in-service bit of a specific priority. The user sup- plies a three-bit priority-level value that points to an in- service bit to be reset. The command is executed by writing the correct value in the Specific EOI register at offset 22H. Interrupt Controller Registers in the Slave Mode All control and command registers are located inside the internal peripheral control block. Figure 32 shows the Offsets of these registers. WM 0257525 0049613 LTs 46 80C186/80C188 MicroprocessorsPRELIMINARY AMD cl Offset Timer 2 Control Register (Vector Type XXXXX101) 3AH Timer 1 Control Register (Vector Type XXXXX100) 38H DMA 1 Control Register (Vector Type XXXXX011) 36H DMA 0 Control Register (Vector Type XXXXX010) 34H Timer 0 Control Register (Vector Type XXXXX000) 32H Interrupt Status Register 30H Interrupt-Request Register 2EH In-Service Register 2CH Priority-Level Mask Register 2AH Mask Register 28H Specific EOI Register 22H Interrupt Vector Register 20H 13087D-033 Figure 32. Interrupt Controller Registers (Slave Mode) End-of-Interrupt Register The end-of-interrupt register is a command register that can only be written. The format of this register is shown in Figure 33. It initiates an EOI command when written by the 80C186/C 188 CPU. The bits in the EO! register are encoded as follows: Ly: Encoded value indicating the priority of the IS bit to be reset. In-Service Register This register can be read from or written into. It contains the in-service bit for each of the interrupt sources. The format for this register is shown in Figure 34. Bit posi- tions 2 and 3 correspond to the DMA channels; positions 0, 4, and 5 correspond to the integral timers. The source's IS bit is set when the processor acknowledges its interrupt request. Interrupt Request Register This register indicates which internal peripherals have interrupt requests pending. The format of this register is shown in Figure 34. The interrupt request bits are set when a request arrives from an intemal source, and are reset when the processor acknowledges the request. The interrupt as in master mode, DO and D1 are read/ write; all other bits are read only. Mask Register This register contains a mask bit for each interrupt source. The format for this register is shown in Figure 34. If the bit in this register corresponding to a particular interrupt source is set, any interrupts from that source are masked. These mask bits are exactly the same bits that are used in the individual control registers; that is, changing the state of a mask bit in this register also changes the state of the mask bit in the individual inter- rupt control register corresponding to the bit. Control Registers These registers are the control words for all the internal interrupt sources. The format of these registers is shown in Figure 35. Each of the timers and both of the DMA channels have their own Control! Register. The bits of the Control Registers are encoded as follows: PRx: three-bit encoded field indicating a priority level for the source; note that each source must be programmed at specified levels. MSK: mask bit for the priority level indicated by PR bits. Interrupt Vector Register This register provides the upper five bits of the interrupt vector address. The format of this register is shown in Figure 36. The interrupt controller itself provides the lower three bits of the interrupt vector, as determined by the priority level of the interrupt request. The format of the bits in this register is: Tx: five-bit field indicating the upper five bits of the vector address. Priority-Level Mask Register This register indicates the lowest priority-level interrupt to be serviced. The encoding of the bits in this register is: Mx: _ three-bit encoded field indication priority-level value. All levels of lower priority are masked. ME 0257525 oo4sniy 530 @ 80C186/80C188 Microprocessors 47mm 22h STIBHOO SeS245cO PRELIMINARY 15 14 13 8 7 6 5 4 3 2 1 0 fo Jo f of . To Jo fof of ofo fw]u to] 13087D-034 Figure 33. Specific EOI Register Format 15 14 13 8 7 6 5 4 3 2 1 0 [fo [o]o]... .Jo | o [ 0 [tre] tmnr[ ot [do | | TMRO} 13087D-035 Figure 34. In-Service, Interrupt Request, and Mask Register Format 15 14 13 8 7 6 5 4 3 2 1 0 fo Jo] oj . .[o | 0 ] 0 o | o | msk] PRa{ Pri] PRO} 13087D-036 Figure 35. Control Word Format 15 14 13 8 7 6 5 4 3 2 1 0 fo Jol o]. . . .fo [ taf m3] ta] tr] tof of o] o | 13087D-037 Figure 36. Interrupt Vector Register Format 15 14 13 8 7 6 5 4 3 2 1 0 fo | o | of . fo [ofof[ of ofo [me] mi} Mo} 13087D-038 Figure 37. Priority Level Mask Register Interrupt Status Register This register is defined as in Master Mode except that DHLT is not implemented (see Figure 25). Interrupt Controller and Reset Upon RESET, the interrupt controller performs the fol- lowing actions: 1. all Interrupt Service bits reset to 0 all Interrupt Request bits reset to 0 all MSK (Interrupt Mask) bits set to 1 (mask) all C (Cascade) bits reset to 0 (non-cascade) all M (Priority Mask) bits set to 1, implying no levels masked 9. initialized to Master Mode. ONnNon ss all SFNM bits reset to 0, implying Fully Nested Mode Enhanced Mode Operation 2. all PR bits in the various control registers set to 1. In Compatible Mode, the 80C 186/C 188 operates with all This places all sources at lowest priority (level 111) the features of the NMOS 80186/80188, with the excep- . oar 7 tion of 8087 support (i.e., no numeric coprocessing is 3. aa bits reset to 0, resulting in Edge-sense possible). Queue-Status information is still available for design purposes other than 8087 support. 48 80C186/80C188 MicroprocessorsPRELIMINARY Allthe Enhanced Mode features are completely masked when in Compatible Mode. A write to any of the Enhanced Mode registers has no effect, while a read does not return any valid data. In Enhanced Mode, the 80C186/C188 operates with Power-Save, and DRAM refresh in addition to all the Compatible Mode features. Entering Enhanced Mode This mode can he entered by tying the RESET output signal from the 80C186/C188 to the TEST input. Queue-Status Mode The Queue-status Mode is entered by strapping the AD pin Low. RD is sampled at RESET and if Low, the 800 186/C188 reconfigures the ALE and WR pins to be QS0 and QS1, respectively. This mode is available on the 80C186/C188 in both Compatible and Enhanced Modes. DRAM Refresh Control Unit Description The Refresh Control Unit (RCU) automatically gener- ates DRAM refresh bus cycles. The RCU operates only in Enhanced Mode. After a programmable period of time, the RCU generates a memory read request to the BIU. tf the address generated during a refresh bus cycle is within the range of a properly programmed chip select, that chip select is activated when the BIU executes the refresh bus cycle. The ready logic and wait States programmed for that region are also in force. If no chip select is activated, then external ready is automati- cally required to terminate the refresh bus cycle. lf the HLDA pin is active when a DRAM refresh request iS generated (indicating a bus hold condition), then the 80C 186/C188 deactivates the HLDA pin in order to per- form a refresh cycle. The circuit external to the 80C186/C188 must remove the HOLD signal for at least one clock in order to execute the refresh cycle. The sequence of HLDA going inactive while HOLD is being held active can be used to signal a pending refresh request. All registers controlling DRAM refresh may be read and written in Enhanced Mode. When the processor is oper- ating in Compatible Mode, they are deselected and are therefore inaccessible. Some fields of these registers cannot be written and are always read as Os. DRAM Refresh Addresses The address generated during a refresh cycle is deter- mined by the contents of the MDRAM register (see AMD al Figure 38) and the contents of a 9-bit counter. Figure 39 illustrates the origin of each bit. Refresh Control Unit Programming and Operation After programming the MDRAM and the CDRAM regis- ters (see Figures 38 and 40), the RCU is enabled by set- ting the E bit in the EDRAM register (Figure 41). The clock counter (T8-T0 of EDRAM) is loaded from C8-Co of CDRAM during T3 of the instruction cycle that sets the E bit. The clock counter is then decremented at each subsequent CLKOUT. Arefreshis requested when the value of the counter has reached 1 and the counter is reloaded from CDRAM. In order to avoid missing refresh requests, the value in the CDRAM register should always be at least 18 (12H). Clearing the E bit at anytime clears the counter and stop refresh requests, but does not reset the refresh address counter. POWER-SAVE CONTROL Power-Save Operation The 80C186/C188, when in Enhanced Mode, can enter a power saving state by internally dividing the processor clock frequency by a programmable factor. This divided frequency is also available at the CLKOUT pin. The PDCON register contains the three-bit fields for select- ing the clock division factor and the enable bit. All internal logic, including the Refresh Control Unit and the timers, has their clocks slowed down by the division factor. To maintain a real time count or a fixed DRAM refresh rate, these peripherals must be reprogrammed when entering and leaving the Power-Save Mode. The Power-Save Mode is exited whenever an interrupt is processed by automatically resetting the enable bit. If the Power-Save Mode is to be re-entered after serving the interrupt, the enable bit needs to be set in software before returning from the interrupt routine. The internal clocks of the 80C186/C188 begin to be divided during the T3 state of the instruction cycle that sets the enable bit. Clearing the enable bit restores full speed in the T3 state of that instruction. The AMD 80C186/C188 is a static design and as such has no minimum clock frequency. MB 0257525 OO45b1b 303 80C186/80C188 Microprocessors 49oA aun PRELIMINARY MDRAM: 615 14 #13 12 11 ~100 09 068 ~= 670666 h6 64 CU tO ottsetEoH [M6] M5 [M4 | Ma] M2[mi] MoT o[o[ofofofofo|o]o | Bits 15-9: M6MO are address bits A19-A13 of the 20-bit memory refresh address. These bits should correspond to any chip select address to be activated for the DRAM partition. These bits are cleared to 0 at RESET. Bits 8-0: Reserved, read back as 0. 13087D-039 Figure 38. Memory Partition Register AiQ AI8 A17 A16 Ai5 A14 A13 A12 A11 A1O AQ AS AZ AGB AS AS AB AZ AB AQ | M6 | M5 | M4 | m3 | M2|Mt| Mo] o }o] 0 | cas] ca7] cas [ cas] ca4]| CAs] CA2| CAI | CAa| 1 | M6-Mo: Bits defined by MDRAM Register. CA8-CAO: Bits defined by refresh address counter. These bits change according to a linear/feedback shift register; they do not directly follow a binary count, but each value is achieved once. 13087D-040 Figure 39. Addresses Generated by RCU 1s 14 18 12 1110 9 8 7 6 5 4 3 2 4 0 one Ce Tote Telefe] eo {esf cr] oe] os [ c4 [os [ca] ct | oo | Bits 15-9: Reserved, read back as 0. Bits 8-0: C8-CO, clack divisor register, holds the number of CLKOUT cycles between each refresh request. 13087D-041 Figure 40. Clock Pre-Scaler Register 16 14 #18 #12 211 +1029 28 +47 6 & 4 38 2 4 0 aoe. Te. olo]ofo] of ol] tft] te] ts] 4 | 13] 2] 711 | To | Bit 15: Enable RCU, set to 0 on RESET. Bits 14~9: Reserved, read back as 0. Bits 8-0: T8-TO refresh counter outputs. Read only. 13087D-042 Figure 41. Enable RCU Register 15 14 #18 +12 1 10 9 #8 7 +6 & 4 3 2 1 0 PDCON: ometros LEL Te ToTofToTeoytof[o {eto o to] rf | Fo | Bit 15: Enable Power-Save Mode. Set to 0 on RESET. Bits 14-3: Reserved, read back as 0. Bits 2-0: Clock Divisor Select. F2 F1 FO Divider Factor F2 F1 FO Divider Factor 0 0 O _ Divide by 1 1 0 O __ Divide by 32 0 o 1 Divide by 4 1 0 1 Divide by 64 0 1 0 Divide by 8 1 1 0 Divide by 128 0 1 1 Divide by 16 1 1 1 Divide by 256 13087D-043 Figure 42. Power-Save Control Register ONCE Test Mode The ONCE Mode is selected by typing the UCS and the LCS Low during RESET. These pins are sampled on the To facilitate testing and inspection of devices when fixed low-to-high transition of the RES pin. The UCS and LCS into a target system, the 80C186/C188 has a test mode pins have weak internal pull-up resistors, similar to the RD available that allows all pins to be placed in a high-im- and TEST pins, to guarantee normal operation. pedance state. ONCE stands for ON Circuit Emula- tion. When placed in this mode, the 80C186/C188 puts we 0257525 O045b1? cuT all pins in the high-impedance state until RESET. 50 80C186/80C188 MicroprocessorsPRELIMINARY amp oA X1 X2 ucs Address A19-A16, AD15~ADO ALE 74AC373 Latch STB OF STB OF 80C186 Program RAM 74AC245 Transceiver Terminal T OE Disk Disk Interface Hardware 13087D-044 Figure 43a. A Typical 80C186 System M@ 0257525 0045618 166 80C186/80C188 Microprocessors 51il amo PRELIMINARY x1 X2 UCS A15-A8 A19-A16, AD7-ADO ALE Address 74AC373 Latch STB OF STB OE 800188 AD15-ADO RO WR Program RAM 74AC245 Transceiver Terminal T OE Disk Interface Hardware 13087D-044 Figure 43b. A Typical 800188 System @ 0257525 0045619 Ole 52 80C186/80C188 MicroprocessorsPRELIMINARY ABSOLUTE MAXIMUM RATINGS Ambient temperature under bias AMD cl Not to exceed the maximum allowable die temperature based on thermal resistance of the package. Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maxi- Commercial(T,) ...........0..00. 0C to +70C Industrial(Taiwn) .....-.0.20. 000. 40C to +85C Storage temperature ............. 65C to +150C Voltage on any pin with respect to ground ............. -1.0 Vto +7.0V Package power dissipation ................... 1W mum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating ranges Ta= 0C to 470C, Taino = 40C to +85C, Veo = 5 V10% Me KEG OFFeHOR GesdscD we Preliminary Symbol Parameter Description Test Conditions Min Max Unit ViL Input Low Voltage (Except X1) 0.5 0.2 Veo 0.3 Vv Vi Clock Input Low Voltage (X1) 0.5 0.6 Vv Vin Input High Voltage 0.2 Veg + 0.9 Veco+ 0.5 v (Except X1, RES) Vint Input High Voitage (RES) 3.0 Veo+ 0.5 Vino Clock Input High Voltage (X1) 3.9 Voo+ 0.5 Vv Vor Output Low Voltage lo, = 2.5 mA (S2-S0) 0.45 lo, = 2.0 mA (others) Vou Output High Voltage low = mar i @ 2.4 2.4 Voc Vv log = -200 pA @ Voc -0.5 Vec Vv Voc - 0.5 loc Power Supply Current 25 MHz, 0C Voc = 5.5 V@) 125 mA 20 MHz, 0C Voc = 5.5 V@) 100 mA 16 MHz, 0C Voc = 5.5 V@) 80 mA 12 MHz, 0C Voc = 5.5 V@) 65 mA 10 MHz, 0C Veo = 5.5 V@) 50 mA DC, oC Voc = 5.5 V 100 pA lo Input Leakage Current @ 0.5 MHz 0.45 V < Vins Veco +10 pA lLo Output Leakage Current 0.45 V < Vout $ Veo!) +10 LA @ 0.5 MHz Veto Clock Output Low leto = 4.0 mA 0.45 Vv VocHo Clock Output High loo = 500 LA Vee -0.5 Vv Cn Input Capacitance @ 1 MHz@) 10 pF Cio Output or I/O Capacitance @ 1 MHz@) 20 pF Notes: 1. Default priorities for the interrupt sources are used only if the user does not program each source to a unique priority level. Pins being floated during HOLD or by invoking the ONCE Mode. . Characterization conditions are: a) Frequency = 1 MHz; b) Unmeasured pins at GND; C) Vin @ +5.0 Vor0.45 V. This parameter is not tested. AD/ 2 3. Current is measured with the device in RESET with X1 and X2 driven and all other non 4 , UTS, LCS, MCS0, MOST, LOCK, -power pins open. and TEST pins have internal pull-up devices. Loading some of these pins above loy =200 WA can cause the 80C186/C188 to go into alternative modes of operation. 80C186/80C188 Microprocessors 53il amo PRELIMINARY Power Supply Current Current is linearly proportional to clock frequency and is Typical current is given by lcc (typical) = 3.5 mA x freq. measured with the device in RESET with X1 and X2 (MHz). Typicals are based on a limited number of sam- driven and all other non-power pins open. ples taken from early manufacturing lots measured at Veo = 5 V and room temperature. Typicals are not Maximum current is given by lee = 5 MA x freq. (MHz). guaranteed. 126 T 80 Maximum La | lee (mA) A Le 40 Tn ) Typical sar | 4 8 12 16 20 25 Clock Frequency (MHz) Figure 44. |,, versus Frequency 43087D-045 mm 0257525 oO4dbel 770 = 54 80C186/80C188 MicroprocessorsPRELIMINARY Parameter Number with Description AMD al Symbol | Parameter Parameter Description Symboi | Parameter Parameter Description Name # Name # tarnycu 49 ARDY Resolution Trans. tetpox 30 Data Hold Time Setup Time tARYCHL 51 ARDY Inactive Holding Time tetpv Data Valid Delay tARYLCL 52 ARDY Setup Time teLpx Data in Hold (A/D) tavcy 14 Address Valid to Clock High toLHav 62 HLDA Valid Delay tave 12 Address Valid to ALE Low toy 23 LOCK Valid/invalid Delay tazrL 24 Address Float to RD Active toLAaH 27 RD Inactive Delay tonicHe 45 CLKOUT Rise Time toca. 25 RD Active Delay tovek 38 CLKIN High Time tetro 61 Reset Delay tone 44 CLKOUT High Time tous 4 Status Inactive Delay toucsx 18 Chip-Select Inactive Delay toLsry 48 SRDY Transition Hold Time toot 22 Control Active Delay 2 tortuy 55 Timer Output Delay tenev 64 Com. Lines Valid Delay (after tevety 20 Control Active Delay 1 Float) tevez 63 Com. Lines Float Delay tevetx 31 Control Inactive Delay toupx 8 Status Hold Time tovpex 21 DEN Inactive Delay tout 9 ALE Active Delay texcsx 17 Chip-Select Hold from Com. inactive toHLL 11 ALE Inactive Delay tove 1 Data in Setup (A/D) tousy 3 Status Active Delay toxot 19 DEN Inactive to DT/R Low toHasv 56 Queue Status Delay tuveL 58 HOLD Setup teico 41 CLKIN to CLKOUT Skew tinvcH 53 INTx, NMI, TEST, TMR IN Setup Time toKHL 39 CLKIN Fall Time tinvel 54 DRQ0, DRQ1 Setup Time toxin 36 CLKIN Period tau 10 ALE Width tony 40 CLKIN Rise Time tilax 13 Address Hold from ALE Inactive totecti 46 CLKOUT Fall Time {resin 57 RES Setup toLaRx 50 ARDY Active Hold Time taHav 29 RD Inactive to Address Active toLay 5 Address Valid Delay trHtH 28 RD Inactive to ALE High totax 6 Address Hold trLrH 26 RD Pulse Width toLaz 15 Address Fioat Delay tsrycu 47 SRDY Transition Setup Time teLcn 43 CLKOUT Low Time twHDEX 35 WR Inactive to DEN Inactive tore 37 CLKIN Low Time twHpx 34 Data Hold after WR tee 42 GLKOUT Period twaty 33 WR Inactive to ALE High totesv 16 Chip-Select Active Delay twiwH 32 WR Pulse Width M@ 0257525 0045622 07 80C186/80C188 Microprocessors 55cl AMD PRELIMINARY SWITCHING CHARACTERISTICS over COMMERCIAL operating range Major Cycle Timings (Read Cycle) T, = 0C to +70C, Voc = 5 V 410% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min | Max Min | Max Min | Max | Unit General Timing Requirements (listed more than once) 1 | tove.__|Data in Setup (A/D) 15 15 | 15 ns 2 | tovox [Data in Hold (A/D) 3 3 3 ns General Timing Responses (listed more than once) 3 tcusv | Status Active Delay 3 45 3 35 3 31 ns 4 tcis | Status Inactive Delay 3 46 3 35 3 30 | ns 5 tcoay | Address Valid Delay 3 44 3 36 3 33 | ns 6 totax | Address Hold 0 0 9) ns 7 te_py | Data Valid Delay 3 40 3 36 3 33 | ns 8 tcupx | Status Hold Time 10 10 10 ns 9 tout | ALE Active Delay 30 25 20 | ns 10 | tu | ALE Width terci-15 = 85 toroi-15 = 65 terc. 15 = ns 47.5 11 tout. | ALE Inactive Delay 30 25 20 | ns 12 tev. | Address Valid to ALE Low to_cH -18= 26 tercy -15 = tetcH-15 = ns 20 11.25 13 tiax | Address Hold from ALE topo. -15= 29 tener -18 = toHcl-15 = ns Inactive 20 11.25 14] tayoy | Addr Valid to Clock High 0 0 0 ns 15 teraz | Address Float Delay toLax = 0 30 totax = 0 25 totax= 9 20 | ns 16 | toicey |Chip-Select Active Delay 3 42 3 33 3 30 | ns 17 | texcsx | Chip-Select Hold from toicy-10= 34 tetcH-10= 25 totcH-10= ns Command Inactive 16.25 18 | toucsx | Chip-Select Inactive Delay 3 35 3 30 3 25 ns 19) tpxo. | DEN Inactive to DT/R Low* 0 0 0 ns 20 | tevcry | Control Active Delay 1** 3 44 3 37 3 31 ns 21 | tovpex | DEN Inactive Delay 3 44 3 37 3 31 ns 22 | tcc | Control Active Delay 2** 3 44 3 37 3 31 ns 23 | tow LOCK Valid/nvalid Delay 3 40 3 37 3 35 ns Timing Responses (Read Cycle} 24 | taza. | Address Float to AD Active 0 0 0 ns 25 toca. | RD Active Delay 3 44 3 37 3 31 ns 26 taLrH RD Pulse Width 2tcic_-30= 2teic_-25= Pterc.-25= ns 170 135 100 27 | tory | RD Inactive Delay 3 44 3 37 3 31 | ns 28 tRHLH RD Inactive to ALE High* tetcH-1 4= torcH-1 4= 21 tetcH-1 4= ns 30 12.25 29 | tauav | RD Inactive to Addr Active ter. -15= 85 tocr-15= 65 toto. -15= ns 47.50 Notes: *Equal Loading **DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input Vz = 0.45 V and Viy= 2.4 V, except at X1 where Vy = Voc 0.5 V. M@ 0257S2S O049be3 S43 56 80C186/80C188 MicroprocessorsPRELIMINARY SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Read Cycle) Ta = 0C to +70C, Voc = 5 Vt10% Preliminary Parameter 20 MHz 25 MHz # | Sym | Description Min | Max Min |Max | Unit General Timing Requirements (listed more than once) 1 tovc. | Data in Setup (A/D) 10 10 ns 2 tctox | Data in Hold (A/D) 3 3 ns General Timing Responses (listed more than once) 3 tcHsv | Status Active Delay 8 25 3 23 | ns 4 tcLsH _| Status Inactive Delay 3 25 3 23 | ns 5 tetav | Address Valid Delay 3 25 3 20 | ns 6 tctax | Address Hold 0 0 ns 7 te_py | Data Valid Delay 3 25 3 20 | ns 8 tcHpx | Status Hold Time 10 10 ns 9 tcHLH | ALE Active Delay 20 18 | ns 10 tluit | ALE Width toLtcL-15 = 35 teoreL-13 = 27 ns 1 tcut. | ALE Inactive Delay 20 18 | ns 12 tav_L | Address Valid to ALE Low* tetcH-10 = 10 totcH-5 = 10 ns 13 tttax | Address Hold from ALE Inactive | toyo,-10 = tcHcL-10 = 5 ns 10 14 tavcH | Addr Valid to Clock High 0 0 ns 15 | tcLaz | Address Float Delay tcrax = 0 17 tcLax = 0 15 | ns 16 | tetcsy | Chip-Select Active Delay 3 25 3 20 | ns 17 | texcsx | Chip-Select Hold from te_cH -10= totcH-10= 5 ns Command Inactive* 10 18 | tcucsx | Chip-Select Inactive Delay 3 20 3 18 | ns 19 | toxp. | DEN Inactive to DT/R Low* 0 0 ns 20 | tevetv | Control Active Delay 1** 3 22 3 18 j ns 21 | tcvoex | DEN inactive Delay 3 22 3 18 | ns 22 | teyctv_ | Control Active Delay 2** 3 22 3 20 | ns | 23 | tou _ | LOCK Valid/invalid Delay 3 22 3 18 | ns Timing Responses (Read Cycle) 24 tazar |Address Float to RD Active 0 0 ns 25 | tcir. |RD Active Delay 3 27 3 24 | ns 26! triny |RD Pulse Width 2tcic_-20= 2tcicL-15= ns 80 65 27 | tcuRH | RD inactive Delay 3 25 3 18 | ns 28 | trHLH {RO Inactive to ALE High* tcLcH -10= teLcH-5= 10 ns 10 29 | teHay | RD Inactive to Addr Active* tetc_~15= 35 tcic_-10=30 ns Notes: Equal Loading DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CG, = 50-100 pF (10-25 MHz). For AC tests, input Vi. = 0.45 V and Vyy = 2.4 V, except at X1 where Vin = Voc - 0.5 V. MM! 0257525 OO49K2y 4oT my AMD al 80C186/80C188 Microprocessors 57ol amo PRELIMINARY 80C186/80C188 Read-Cycle Waveforms 4 te ts ty tw CLKOUT 4) (Note 1) a Ny | oO Status BHE/RFSH __ A19/S6-A16/S3 A19-A16 BHE/RFSH S6-S3 A15-A8 A15-A8 (800188 only) ALE @ AD7-ADO (80C188 only) AD15-ADO (800186 only) RD , UGS, Note 2) L z gD a Pi QO) Ss | Oo m = DT/A (Note 5) (Note 4) Q oO x Notes: 1. Status inactive in state preceding t. 2. If latched, Al and A2 are selected instead of PUSS and PCS6, only to.osy is applicable. 3. Far write cycle followed by read cycle. 4. t, of next bus cycle. 5. Changes in t-state preceding next bus cycle if followed by write. Mm 0257525 OO4%beS 31b 58 80C186/80C188 MicroprocessorsPRELIMINARY AMD al SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Write Cycle) Ta = 0C to +70C, Veo = 5 V+10% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min | Max Min | Max Min | Max | Unit General Timing Responses (listed more than once) 3 tcusy _| Status Active Delay 3 45 3 35 3 31 ns 4 torsh | Status Inactive Delay 3 46 3 35 3 30 ns 5 tctay | Address Valid Delay 3 44 3 36 3 33 ns 6 totax | Address Hold 0 0 0 ns 7 tc.oy _ | Data Valid Delay 3 40 3 36 3 33 ns 8 tcupx | Status Hold Time 10 10 10 ns 9 teri | ALE Active Delay 30 25 20 ns 10 Ton ALE Width tetcL-15 = tetci-1 5= teteL-1 5 = ns 5 65 47.5 11 teu. | ALE Inactive Delay 30 25 20 ns 12 taviL Address Valid to ALE Low* totcH-18 = tetcH-15 = tetcH-15 = ns 26 20 11 13 titax | Address Hold from ALE Inactive* tencL-15 = tone. -15 = tone. -15 = ns 20 11.25 14 taven | Addr Valid to Clock High 0 0 0 ns 16 teicsy__| Chip-Select Active Delay 3 42 3 33 3 30 ns 17 texesx | Chip-Select Hold from torcH-10= toicy-10= toicH-10= ns Command Inactive* 34 5 16.25 18 tcucsx | Chip-Select Inactive Delay 3 35 3 30 3 25 ns 19 tpxo. | DEN Inactive to DT/R Low* 0 0 0 ns 20 toverv | Contral Active Delay 1** 3 44 3 37 3 31 ns 23 teuy | LOCK Valid/Invalid Delay 3 40 3 37 3 35 ns Timing Responses (Write Cycle) 30 tetpox | Data Hold Time 3 3 3 ns 31 teverx | Control Inactive Delay** 3 44 3 37 3 31 ns 32 twowH WR Pulse Width 2teic_-30 = 2terc_-25 = 2terco_-25 = ns 170 135 100 33 twHtH WR Inactive to ALE High* tetcu-14 = tetct-14 = torcr-T4 = ns 30 21 12.25 34 twupx | Data Hold after WR toici-34 = totcH-20 = teicH-20 = ns 66 60 42.5 35 twupex |WR Inactive to DEN Inactive* tecH-10 = tere-10 = tero_~-10 = ns 34 25 16.25 Notes: *Equal Loading DEN, INTA, WR All timings are measured at 1.5 V and 100 PF loading on CLKOUT unless otherwise noted. All output test conditions ara with CG, = 50-100 pF (10-25 MHz). For AC tests, input Vy = 0.45 Vand Vj, = 2.4 V, except at X1 where Vy = Voc 0.5 V. - MM 0257525 ooygpen eSc mm 80C186/80C188 Microprocessors 59al AMD PRELIMINARY SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Write Cycle) Ta = 0C to +70C, Voc =5Vt10% Preliminary Parameter 20 MHz 25 MHz # | Sym | Description Min LE: Min | Max | Unit General Timing Responses (listed more than once) 3 tousv Status Active Delay 3 25 3 23 ns 4 teLsH Status Inactive Delay 3 25 3 23 ns 5 toLAV Address Valid Delay 3 25 3 20 ns 6 toLax Address Hold 0 0 ns 7 tetov Data Valid Delay 3 25 3 20 ns 8 toupx Status Hold Time 10 10 ns 9 toutH ALE Active Delay 20 18 ns 10 TLHLL ALE Width torcL-15 = 35 toc. -13 = 27 ns 11 toHLL ALE Inactive Delay 20 18 ns 12 taviL Address Valid to ALE Low* teicH-10 = 10 torcH-S = 10 ns 13 TLLAX Address Hold from ALE Inactive* toycL-10 = 10 teHo_-10 = 5 ns 14 tavoH Addr Valid to Clock High 0 0 ns 16 toLesv Chip-Select Active Delay 3 25 3 20 ns 17 texcsx Chip-Select Hold from torcH-10= 10 tetcH -10= 5 ns Command inactive 18 tcHesx Chip-Select Inactive Delay 3 20 3 18 ns 19 toxoL DEN Inactive to DT/R Low* 0 0 ns 20 toverv Control Active Delay 1** 3 22 3 18 ns 23 tou LOCK Valid/Invalid Delay 3 22 3 18 ns Timing Responses (Write Cycle) 30 teLpox Data Hold Time 3 3 ns 31 teverx Control Inactive Delay** 3 22 3 20 ns 32 twiwH WA Pulse Width 2too. -20 = 80 Ptoo.-15 = 65 ns 33 twHLH WR Inactive to ALE High* tec. -14 = 6 toc. - 10 =5 ns 34 twHpx Data Hold after WR* torcH 15 = 35 tercH 10 = 30 ns 35 twHDex WH Inactive to DEN Inactive* foie. 10 = 10 tere. = 10 ns Notes: *Equal Loading **DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input Vy, = 0.45 V and Vy, = 2.4 V, except at X7 where Vin = Voc 0.8 V. - gm o2575e5 goudbe? 195 a 60 80C186/80C188 MicroprocessorsPRELIMINARY 80C186/80C188 Write-Cycle Waveforms t; te ts ty CLKOUT S2-S0 Status @ 6 BHE/RFSH BHE, RFSH A19/S6-A16/S3 A19-A16 A15-A8 5 (80C188 only) A15-AB ALE AD15-AD8 (800186 only) G2) (Note 5) (Note 4 Notes: Status inactive in state preceding t. iflatched, A1 and A2 are selected instead of PCS5 and PUS6, only tercsy is applicable. For write cycle followed by read cycle. t, of next bus cycle. Changes in t-state preceding next bus cycle if followed by read, INTA, or halt. - MM 0257525 OO49be6 O25 mw 80C186/80C188 Microprocessors 61ol amp PRELIMINARY SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Interrupt Acknowledge Cycle) Ty = 40C to +85C, Voc = 5 Vt10% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | sym | Description Min Max Min Max Min Max | Unit 80C186 General Timing Requirements (listed more than once) 1 tove. | Data in Setup (A/D) 15 15 15 ns 2 totox | Data in Hold (A/D) 3 3 3 ns 80C186 General Timing Responses (listed more than once) 3 tcusv | Status Active Delay 3 45 3 35 3 31 ns 4 ters | Status Inactive Delay 3 46 3 35 3 30 | ns 5 tctav | Address Valid Delay 3 44 3 36 3 33 ] ns 6 torax | Address Hold 0 0 QO ns 7 to_py _| Data Valid Delay 3 40 3 36 3 33 | ns 8 tcupx | Status Hold Time 10 10 10 ns 9 tcuty | ALE Active Delay 30 25 20 | ns 10 | tii |ALE Width Teter 18 = 85 toro. -15 = 65 tero.-15 = 47 ns 11 tcut. | ALE Inactive Delay 30 25 20 | ns 12 tavi. | Address Valid to ALE Low* torcH-18 = tetcH715 = toicH-15 = ns 26 20 11 13 tiiax | Address Hold from ALE Inactive | tec.15 = tener -15 = tone -15 = ns 29 20 11 14 tavcy | Addr Valid to Clock High 0 0 0 ns 15 teraz | Address Float Delay toLax = 0 30 torax = 0 25 toLax = 9 20 | ns 19] tpxo. | DEN Inactive to DT/R Low* 0 0 ) ns 20 | tevery | Control Active Delay 1** 3 44 3 37 3 31 ns 21 | toypex | DEN Inactive Delay 3 44 3 37 3 31 ns (Non-Write Cycles) 22 | tcuery |Control Active Delay 2** 3 44 3 37 3 31 ns 23 tery | LOCK Valid/invalid Delay 3 40 3 37 3 35 | ns 31 | tovcrx | Control Inactive Delay** 3 44 3 37 3 31 ns Notes: *Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 80-100 pF (12.5-25 MHz). For AC tests, input V, = 0.45 V and Vy, = 2.4 V, except at X17 where Viq = Voo 0.8 V. . MM 0257525 0045be9 Th) 62 80C186/80C188 MicroprocessorsPRELIMINARY AMD at SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Interrupt Acknowledge Cycle) Ta = 0C to +70C, Voc = 5 V 410% Preliminary Parameter 20 MHz 25 MHz # | Sym | Description Min Max Min Max | Unit 80C186 General Timing Responses (listed more than once) 1 tpve. | Data in Setup (A/D) 10 10 ns 2 tcLpx | Data in Hold (A/D) 3 3 ns 80C186 General Timing Responses (listed more than once) 3 tcHsv | Status Active Delay 3 25 3 23 | ns 4 tetsH | Status Inactive Delay 3 25 3 23 | ns 5 tctav_| Address Valid Delay 3 25 3 20 | ns 6 teLtax | Address Hold 0 0 ns 7 tcLpy | Data Valid Delay 3 25 3 20 | ns 8 | tcHpx | Status Hoid Time 10 10 ns 9 tcHLH | ALE Active Delay 20 18 | ns 10 ttHtL =| ALE Width tere_-15 = 35 teLcL-13 = 27 ns 11 tcHL_L | ALE Inactive Delay 20 18 j ns 12 tavi_L | Address Valid to ALE Low* teicH-10 = 10 tetcH-S = 10 ns 13 | tiLax |Address Hold from ALE Inactive* | toric.-10 = 10 toHcL-10 = ns 14] tavcH | Addr Valid to Clock High 0 0 ns 15 tcLaz_ | Address Float Delay tetax = 0 17 totax = 0 15 | ns 19] tpxpL | DEN Inactive to DT/R Low* 0 0 ns 20 | tevcry | Control Active Delay 1** 3 22 3 18 | ns 21 | tcvoex | DEN Inactive Delay 3 22 3 18 | ns (Non-Write Cycles) 22 | tcucry | Control Active Delay 2** 3 22 3 20 | ns 23 | tctty |LOCK Valid/Invalid Delay 3 22 3 18 | ns 311 tevetx | Control Inactive Delay** 3 22 20 j ns Notes: *Equal Loading DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (12.5-25 MHz). For AC tests, input Vy, = 0.45 V and Viy = 2.4 V, except at X1 where Vy = Veg 0.5 V. - MM 0eS7525 0049630 7535 mm 80C186/80C188 Microprocessors 63Ot amo PRELIMINARY 80C186/80C188 Interrupt Acknowledge Cycle Waveforms | ty | te | ts | ty tw l ln Sy cLKouT / NS NS wads \ @ 4 Status Wr Vy, Y i] \ ~ | O- + @+ BHE (806186) aE A19/S6-A16/S3 A19-A16 BHE, S6-S3 % LY tr [ Om > i (43 ALE A15-A8 (800188) (Note 2) AD15-ADO (800186) AD7ADO (800188) er rm (Note 3) > @9 @" | pn 4 (Note 4) DTA LOCK | (Note 5) Fal e { al Notes: Status inactive in state preceding t, The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to tcp (min). INTA occurs one clock later in Slave Mode. For write cycle followed by interrupt acknowledge cycle. TOCK is active upon t, of the first interrupt acknowledge cycle and inactive upon tb; of the second interrupt acknowledge cycle. Changes in t-state preceding next bus cycle if followed by write. OaAABM> - MM 0257525 0049631 617 64 80C186/80C188 MicroprocessorsPRELIMINARY SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Software Halt Cycle Timings Ta = 0C to 70C, Voc = 5 V+10% AMD cl Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min Max Min Max Min Max | Unit 800186 General Timing Responses (listed more than once) 3 tcusv | Status Active Delay 3 45 3 35 31 ns 4 teisH | Status Inactive Delay 3 46 35 3 30 | ns 5 toLay | Address Valid Delay 3 44 3 36 3 33 | ns 9 tcuty | ALE Active Delay 30 25 20 | ns 10 | tun. [ALE Width toc.-15 = 85 torel-15 = 65 toc--15 = 47 ns 11 tou. | ALE Inactive Delay 30 25 20 ns | 19 | toxo. | DEN Inactive to DT/R Low* 0 0 0 ns 22 | tcucry | Control Active Delay 2** 3 44 3 37 3 31 ns Preliminary Parameter 20 MHz 25 MHz # | Sym | Description Min Max Min Max | Unit 80C186 General Timing Responses (listed more than once) 3 tcusv | Status Active Delay 3 29 25 | ns 4 tetsy | Status Inactive Delay 3 29 3 25 | ns 5 terav | Address Valid Delay 3 25 3 20 | ns 9 tcuitH | ALE Active Delay 20 18 ns 10 tut. | ALE Width tere 15 = 35 tota13 = 27 ns 1 teu. | ALE Inactive Delay 20 18 ns 19 | toxoL | DEN Inactive to DT/A Low* 0 0 0 ns 22 | tcucty | Control Active Delay 2** 3 22 3 20 ns Notes: *Equal Loading DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (12.5-25 MHz). For AC tests, input Vi = 0.45 V and Vj, = 2.4 V, except at X1 where View = Veo 0.5 V. - MM 0257525 o045b32 Ssh me 80C186/80C188 Microprocessors 651 amo PRELIMINARY 80C186/80C188 Software Halt Cycle Waveforms | t | te | fj & cLKouT _SA \ aso @a le le @ \ Status 4 T A19/S6-A16/S3, AD15-ADB8/A15-A8, Invalid Address AD7-ADO 4) 4 ALE @>* > Gd) i; (Note 1) DTA Ter oO m Note: 1. For write cycle followed by halt cycle. Clock Waveforms CLKOUT - Ml 0257525 0049633 4c mf 66 80C186/80C188 MicroprocessorsPRELIMINARY AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Clock Timings Ta = 0C + 70C, Veo = 5 V+10% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min Max Min | Max Min Max | Unit CLKIN Requirements Measurements taken with: external clock input to X1 and X2 not connected (Float). 36 toxin CLKIN Period 50 40 31.25 ns 37 | toick | CLKIN Low Time 1.5 V@) 20 16 13 ns 38 | tcuck | CLKIN High Time 1.5 Vi2} 20 16 13 ns 39 tex, | CLKIN Fall Time 3.5 - 1.0 V 5 5 5 ns 40 toxin | CLKIN Rise Time 1.0- 3.5 V 5 5 5 ns CLKOUT Timing 41 teico = | CLKIN to CLKOUT Skew 25 21 17 | ns 42 tere CLKOUT Period 100 80 62.5 ns 43 tetcH CLKOUT Low Time 0.5 tere 6 0.5 tere. - 5 0.5 tore. - 5 ns C= 50pFS) = 44 =35 = 26.25 C= 100pF@) 0.5 tetc. 8 0.5 tere. - 7 0.5 tere. - 7 = 42 =33 = 24.25 44 toueL CLKOUT High Time 0.5 tere. - 6 0.5 tect -5 0.5 tere. - 5 ns C.= 50 pF) = 44 = 35 = 26.25 C.= 100pF4) 0.5 toto. - 8 0.5 tere. 7 0.5 terc.7 = 42 =33 = 24.25 45 | tcuicue2 | CLKOUT Rise Time 1.0-3.5 V 10 10 10 | ns 46 | tcracr: | CLKOUT Fall Time 3.5-1.0V 10 10 10 | ns Preliminary Parameter 20 MHz 25 MHz # | Sym | Description Min | Max Min | Max } Unit CLKIN Requirements Measurements taken with: external clock input to X1 and X2 not connected (Float). 36 teKin CLKIN Period 25 20 ns 37 tock CLKIN Low Time 1.5 V@) 7 5 ns 38 | toyck | CLKIN High Time 1.5 V@) 8 5 ns 39 torHL CLKIN Fall Time 3.5 -1.0 V 5 5 ns 40 tex.y | CLKIN Rise Time 1.0 ~ 3.5 V 5 5 ns CLKOUT Timing 41 teico | CLKIN to CLKOUT Skew 17 15 | ns 42 tote CLKOUT Period 50 40 ns 4 totcu CLKOUT Low Time 0.5 teic.~ 5= 20 0.5 tere. ~ 5 = 15 ns C,= 50 pF) C.= 100 pF) 0.5 toto. 7= 18 NA 44 teHcL CLKOUT High Time 0.5 tetc_- 5 = 20 0.5 tee. -5 = 15 ns C,= 50 pF) C.= 100 pF) 0.5 tec.7 = 18 NA 45 | tonicHe | CLKOUT Rise Time 1.0-3.5V 8 8 ns 46 | totect1 | CLKOUT Fall Time 3.5-1.0 V 8 8 ns Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted, All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input Vi, = 0.45 Vand V;, = 2.4 V, except at X1 where Vy = Voc 0.5 V. 1. tetex and teyen (CLKIN Low and High times) should not have a duration less than 40% of toxin. 2. Tested under worst case conditions: Vcc = 5.5 V @ 25 MHz, Ta=70C. 3. Not tested. 4. Tested under worst case conditions: Vec = 4.5 V @ 25 MHz, Ta =0C. - MM 0257525 ooyg,3y 3:5 80C186/80C188 Microprocessors 67at AMD PRELIMINARY SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Ready, Peripheral, and Queue Status Timings Ta = OC to +85C, Vog = 5 V 410% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym Description Min Max Min | Max Min Max | Unit Ready and Peripheral Timing Requirements 47 | tsayc. | SRDY Transition Setup Time 15 15 15 ns 48 | torsry | SRDY Transition Hold Time() 15 15 15 ns 49 | tanycH |ARDY Res. Transition Setup 15 15 15 ns Time) 50 | tocarx |ARDY Active Hold Time(!) 15 15 15 ns 51 | tanycut | ARDY Inactive Holding Time 15 15 15 ns 52 | taryict | ARDY Setup Time? 25 25 25 ns 53 | twvcH | Peripheral Setup(): INTx, NMI, 15 15 15 ns TMR IN, TEST/BUSY 54 | tinve. |DRQO, DRQ1 Setup Time@ 15 15 15 ns Peripheral and Queue Status Timing Responses 55 | terry | Timer Output Delay 40 33 27 | ns 56 | tcHasy | Queue Status Delay 37 32 30 | ns Preliminary Parameter 20 MHz 25 MHz # Sym | Description Min Max Min Max | Unit Ready and Peripheral Timing Requirements 47 | tsryc. | SRDY Transition Setup Time) 10 10 ns 48 | torsny | SRDY Transition Hold Time) 10 10 ns 49 | tanycu | ARDY Res. Transition Setup 10 10 ns Time?) 50 | totaax | ARDY Active Hold Time 10 10 ns 51 | tarycu_ | ARDY Inactive Holding Time 10 10 ns 52 | taryvic | ARDY Setup Time") 15 15 ns 53 | tinvcy | Peripheral Setup'2): INTx, NMI, 10 10 ns TMR IN, TEST/BUSY 541 twyct |DRQO, ORQ1 Setup Time) 10 10 ns Peripheral and Queue Status Timing Responses 55 | terrmy | Timer Output Delay 22 18 | ns 56 | tcHasy | Queue Status Delay 23 18 | ns Notes: Alt timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AG tests, input Vy = 0.45 V and Vy, = 2.4 V, except at X1 where Vin = Voc 0.5 V. 1. To guarantee proper operation. 2. To guarantee recognition at clock edge. MB 0257525 0049635 cbs 68 80C186/80C188 MicroprocessorsPRELIMINARY AMD & Synchronous Ready (SRDY) Waveforms | twort,ort, | tw Ort, | tw OF ts | t CLKOUT SRDY Asynchronous Ready (ARDY) Waveforms | twortort, | tw OF te | ty OF te | t. | Sf \ S\N S\N S\N CLKOUT @& i -e ARDY (Normally Not Ready System) _J< ARDY (Normally Ready System) @) tt MB 0257525 0045636 1TL 80C186/80C188 Microprocessors 69ol amo PRELIMINARY Peripheral and Queue Status Waveforms CLKOUT NON ST VE INT3-INTO, NMI, ~ TEST, TMR IN | a \ 5 cc DRQo, DRQ1 7 eC > cc TMR OUT 1 ec _ 1 QSo, QS +) te | RESET Waveforms x1 | a mm a Ne] | A cuxour XX _/ RESET MM 0257525 0049637 038 me 70 80C186/80C188 MicroprocessorsPRELIMINARY AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) RESET and HOLD/HLDA Timings Ta = 0C to +85C, Veo = 5 V+10% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min Max Min Max Min Max | Unit RESET and HOLD/HLDA Timing Requirements 57 | tresin {RES Setup 15 15 15 ns 58 | tuver |HOLD Setup) 15 15 15 ns 15 teLaz | Address Float Delay 0 30 0 25 0 20 | ns 5 terav |Address Valid Delay 3 44 3 36 3 33 | ns RESET and HOLD/HLDA Timing Responses 61 tetro | Reset Delay 40 33 27 | ns 62 | towav |HLDA Valid Delay 3 40 3 33 3 25 | ns 63 | tcuez {Command Lines Float Delay 40 33 28 | ns 64 | tcoycy | Command Lines Valid Delay 44 36 32 | ns (after Float) Preliminary Parameter 20 MHz 25 MHz # | sym | Description Min Max Min Max | Unit RESET and HOLD/HLDA Timing Requirements 57 | tresin | RES Setup 10 10 ns 58 | tuve. |HOLD Setup() 10 10 ns 15 tctaz | Address Float Delay 0 17 0 15 | ns 5 to.ay | Address Valid Delay 3 25 3 20 | as RESET and HOLD/HLDA Timing Responses 61 toro Reset Delay 22 18 ns 62 | teinav |HLDA Valid Delay 3 22 3 20 | ns 63 | tcucz |Command Lines Float Delay 25 18 | ns 64 | tcHcv |Command Lines Valid Delay 25 20 | ns {after Float) Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input Vj. = 0.45 V and Vi, = 2.4 V, except at X1 where Vy = Voc 0.5 V. 1. To guarantee recognition at next clock. Mi 0257525 0049636 Th 80C186/80C188 Microprocessors 71it amp PRELIMINARY 80C186/80C188 HOLD/HLDA Waveforms (Entering HOLD) ts or t, | ti | ti | | wor \_f?\ NS VS \ ce HOLD / 27 HLDA ce ad 6c * @ AD15-AD8/A15-A8, ae AD7-ADO, DEN cc a? oe (ad A19/S6-A16/S3, RD, WR >) \ BHE/RFSH, DT/R, S2S0, cc LOCK as 80C186/80C188 HOLD/HLDA Waveforms (Leaving HOLD) Pop BH CLKOUT \ t , / \ 2 HOLD | Al a? HLDA v tc | as Or AD15-ADB/A15-A8, ee AD7-AD0, DEN 9 h a A19/S6-A16/S3, RD, WR, BHE/RFSH, DT/A, S2-S0, LOC Al wm we MB 0257525 0049639 900 me 72 80C186/80C188 MicroprocessorsPRELIMINARY AMD oN SWITCHING CHARACTERISTICS over INDUSTRIAL operating range Major Cycle Timings (Read Cycle) Taino = 40C to +85C, Voc = 5 Vv +1 0% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min | Max Min | Max Min Max | Unit General Timing Requirements (listed more than once) 1 tove. | Data in Setup (A/D) 15 15 15 ns 2 totox | Data in Hold (A/D) 3 3 3 ns General Timing Responses (listed more than once) 3 tcusv | Status Active Delay 3 45 3 35 3 31 ns 4 tetsH | Status Inactive Delay 3 46 3 35 3 30 ns 5 tctav | Address Valid Delay 3 44 3 36 3 33 | ns 6 totax | Address Hold 0 0 0 ns 7 tetpy _| Data Valid Delay 3 40 3 36 3 33 [ ns 8 tcypx | Status Hold Time 10 10 10 as 9 tcuty | ALE Active Delay 30 25 20 [| ns 10 fiut, | ALE Width tore. -15 = 85 tete_-15 = 65 tort 5= ns 11 tout. | ALE Inactive Delay 30 25 20 } ns 12 | tay. | Address Valid to ALE Low* tercy-18 = tetcH-15 = tetcy-15 = ns 26 20 14.25 13 tuax | Address Hold from ALE tener -15 = toe -15 = tcueL-15 = ns Inactive* 29 20 11.25 14) taycn | Addr Valid to Clock High 0 0 0 ns 15 tctaz | Address Float Delay teLax = 0 30 torax = 0 25 toLax = 0 20 | ns 16 | tcucsy | Chip-Select Active Delay 3 42 3 33 3 30 7 ns 17 | texcsx | Chip-Select Hold from teicy-10= 34 torcH-10= 25 toicy-1 0= ns Command Inactive* 16.25 18 | tcucsx | Chip-Select Inactive Delay 3 35 3 30 3 25 | ns 19 | toxo. | DEN Inactive to DT/R Low 0 0 a ns 20 |! tevety | Control Active Delay 1** 3 44 3 37 3 31 ns 21) tovpex |DEN Inactive Delay 3 44 3 37 3 31 | ns 22 | tcxctv | Control Active Delay 2** 3 44 3 37 3 31 ns 23 tery | COCK Valid/Invalid Delay 3 40 3 37 3 35 | ns Timing Responses (Read Cycle) 24 tazr. | Address Float to RD Active 0 0 0 ns 25 tc_a. | AD Active Delay 3 44 3 37 3 31 ns 26 trirH RD Pulse Width 2terc. JO= 2toiq.-25= 2tcict-25= ns 170 135 100 27 | terry | AD Inactive Delay 3 44 3 37 3 31 | ns 28 | tryin | RD Inactive to ALE High* tetcu-14= 30 torcy-14= 21 tas 4= ns .25 29 | tryay | RD Inactive to Addr Active* too. -15= 85 tere. -15= 65 toot 5= ns 5 Notes: Equal Loading All timings are measured at 1.8 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-16 MHz). For AC tests, input Vi, = 0.45 V and Vy, = 2.4 V, except at X1 where Vij = Voc - 0.5 V. MB 0es?7sSeS CO4db40 b22 80C186/80C188 Microprocessors 73oN amo PRELIMINARY 80C186/80C188 Read-Cycle Waveforms + k@ al le - BHE/RFSH BHE/RFSH Pe toe dt teh S| y\N YN Y V- eLKoUT / NS NS , N_ 55-5 + le G) te(4) (Note 1) \ Status LLL \ - BHE/RFSH S6-S3 A19/S6-A16/S3 A1S-A16 1 1 I l l | AD15-A8 x (800188 only) | 0 )/ ALE @* + +@ < Or > +O On ae @ AD7-ADa (800188 only) A7-A0 Data . @* + |e) | a AD15-AD8 AB_AB Oat (80C186 only) \ Nene RD \ / @ke : we OF LCS, MCS, UCS, > | on PGS (Note 2) \ a x ae) l of (19) Note 3) DR TY je @ ( o| i+ @2) (Note 5) > at le @ | oD m Zz (Note 4) ><he LOCK | Notes: 1. Status inactive in state preceding t,. 2. if latched, Al and A2 are selected instead of PCS5 and PCS6, only tcsy is applicable. 3. For write cycle followed by read cycle. 4. t, of next bus cycle. 5. Changes in t-state preceding next bus cycle if followed by write. Mi 0257525 0049641 SLo 74 80C186/80C188 MicroprocessorsSWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) PRELIMINARY Major Cycle Timings (Write Cycle) Taino = 40C to + 85C, Veg = 5 V 410% AMD at Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min Max Min | Max Min Max | Unit General Timing Responses (listed more than once) 3 tcusy | Status Active Delay 3 45 3 35 3 31 ns 4 teisH | Status Inactive Delay 3 46 3 35 3 30 ns 5 tc.av | Address Valid Delay 3 44 3 36 3 33 ns 6 tetax | Address Hold 0 0 0 ns 7 te.ov | Data Valid Delay 3 40 3 36 3 33 ns 8 tcHpx | Status Hold Time 10 10 10 ns 9 tent | ALE Active Delay 30 25 20 ns 10 TLL ALE Width terct-15 = tetc_-15 = tetc_-15 = ns 85 65 47 11 tcut. | ALE Inactive Delay 30 25 20 ns 12 tavi. | Address Valid to ALE Low* fotcH-18 = torcy-15 = torcu-15 = ns 26 20 11 13 tttax | Address Hold from ALE Inactive teue_-15 = teet~15 = tcHcL-15 = ns 29 20 11 14 tavcy | Addr Valid to Clock High 0 0 0 ns 16 teicsy | Chip-Select Active Delay 3 42 3 33 3 30 ns 17 toxcsx | Chip-Select Hold from tetcH-10= tetcH-10= toLcy-T0= ns Command Inactive* 34 25 16 18 touicsx | Chip-Select Inactive Delay 3 35 3 30 3 25 ns 19 toxo. | DEN Inactive to DT/R Low ) 0 0 ns 20 tevety | Control Active Delay 1** 3 44 3 37 3 31 ns 23 tory LOCK Valid/invalid Delay 3 40 3 37 3 35 ns Timing Responses (Write Cycle) 30 tctpox | Data Hold Time 3 3 3 ns 31 teverx | Control Inactive Delay** 3 44 3 37 3 31 ns 32 twowy WR Pulse Width 2terc. 30 = 2tercL-25 = 2terei-25 = ns 170 135 100 33 twety | WR Inactive to ALE High* totcH-14 = toto -14 = totcH-14 = ns 30 i 12.25 34 twupx Data Hold after WR* tet. -34 = torcH-20 = tetcH-20 = ns 66 60 42.5 35 twHpex WR Inactive to DEN Inactive* teicH-10 = teteL-10 = terol 10 = ns 34 16.25 Notes: *Equal Loading DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-16 MHz). For AC tests, input V, = 0.45 Vand Vi, = 2.4 V, except at X1 where Vy, = Veg 0.5 V. Me 0257525 OO45b4e 475 80C186/80C188 Microprocessors 7521 amp PRELIMINARY 80C186/80C188 Write-Cycle Waveforms ty te ty ty CLKOUT $2-SO Status 8 BHE/AFSH SHEESH A19/S6-A16/S3 A19-A16 BHE/RFSH S6-S3 A15-AB (806188 only) A15-A8 ALE AD15-AD8 (800186 only) AD7-ADO WR LCS, MCS, UGS, c PCS (Note 2) oO m z DT/A @) (note 5) (Note 4 Notes: 1. Status inactive in state preceding t,. 2. If latched, A1 and A2 are selected instead of PCS5 and PCS6, only tercsy is applicable. 3. For write cycle followed by read cycle. 4. t, of next bus cycle. 5. Changes in t-state preceding next bus cycle if followed by read, INTA, or halt. MB 0257525 0044643 331 a 76 80C186/80C188 MicroprocessorsMajor Cycle Timings (Interrupt Acknowledge Cycle) Ta = 40C to +85C, Veg = 5 VH10% PRELIMINARY SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (continued) AMD il Preliminary Parameter 10 MHz 12 MHz 16 MHz # | sym | Description Min Max Min Max Min Max | Unit 800186 General Timing Requirements (listed more than once) 1 tove. {Data in Setup (A/D) 15 15 15 ns 2 tetpx | Data in Hold (A/D) 3 3 3 ns 800186 General Timing Responses (listed more than once) 3 tcusv | Status Active Delay 3 45 3 35 3 31 ns 4 | tos | Status Inactive Delay 3 46 3 35 3 30 | ns 5 | tciay |Address Valid Delay 3 44 3 36 3 33 | ns 6 tctax | Address Hold 0 0 0 ns 7 teipy _| Data Valid Delay 3 40 3 36 3 33 ns 8 tcupx | Status Hold Time 10 10 10 ns 9 tcuty | ALE Active Delay 30 25 20 | ns 10 |} tun. {ALE Width tore. -15 = 85 tetc.-15 = 65 terc.-15 = 47 ns 11 tou. | ALE Inactive Delay 30 25 20 | ns 12) ta | Address Valid to ALE Low* tecow_18 = toon-15 = toccun15 = ns 26 20 11 13 tiiax | Address Hold from ALE Inactive* | tou. -15 = tency -15 = tone. -15 = ns 29 20 11 14 tavcH | Addr Valid to Clock High 0 0 0 ns 15 tclaz | Address Float Delay totax = 0 30 torax = 0 26 totax = 0 20 | ns 19 | toxo. | DEN Inactive to DT/R Low* 0 0 0 ns 20 | tevery | Control Active Delay 1** 3 44 3 37 3 31 ns 21; tevoex | DEN Inactive Delay 3 44 3 37 3 31 | ns (Non-Write Cycles) 22 | tcucry | Control Active Delay 2** 3 44 3 37 3 31 ns 23 feu |LOCK Valid/Invalid Delay 3 40 3 37 3 35 { ns 31.{ teverx | Control Inactive Delay** 3 44 37 5 31 ns Notes: *Equal Loading DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-200 pF (10 MHz) and C, = 50-100 pF (12.5-20 MHz). For AC tests, input Vz = 0.45 V and Vy, = 2.4 V, except at X1 where Vy, = Voc - 0.5 V. MP 0257525 0049K44y 278 me 80C186/80C188 Microprocessors 774 amo PRELIMINARY 80C186/80C188 Interrupt Acknowledge Cycle Waveforms ty te ty | | t CLKOUT S/ / ae, \_ . (Note 1) oa | Yi UL + le @ G)- a kee BHE (800186) BHE, BHE, S6-S3 A19/S6-A16/S3 A19-A16 ' L_ (10 T -@ tT Le L OT re ALE (e001) C @ my 4 (Note 2) AD15-ADO (800186) OTR AD?7ADO (806188) MY XN > he 65) > 6) (Note 3} > @ | a 4 (Note 4) oA | | @ G2) (Note 6) j>| A (Note 5) Ke =] Notes: Status inactive in state preceding t, The data hald time lasts only until INTA goes inactive, even if the INTA transition occurs prior to torpx (min). INTA occurs one clock later in Slave Mode. For write cycle followed by interrupt acknowledge cycle. LOCK is active upon t, of the first interrupt acknowledge cycle and inactive upon & of the second interrupt acknowledge cycle. Changes in t-state preceding next bus cycle if followed by write. WH 0257525 OO4cbYsS 104 BaAAwWNY > 78 80C186/80C188 MicroprocessorsPRELIMINARY AMD tA SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (continued) Software Halt Cycle Timings Ts = 40C to 85C, Voc = 5 V 410% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | sym | Description Min Max Min Max Min Max | Unit 80C186 General Timing Responses (listed more than once) 3 tcusv | Status Active Delay 3 45 3 35 3 31 ns 4 teisy | Status Inactive Delay 3 46 3 35 3 30 | ns 5 tcrav |Address Valid Delay 3 44 3 36 3 33 | ns 9 tcuun | ALE Active Delay 30 25 20 | ns 10 | tu |ALE Width teic_-15 = 85 totcL-15 = 65 toicL-15 = 47 ns 11 tent. | ALE Inactive Delay 30 25 20 | ns 19! toxp. | BEN Inactive to DT/R Low* 0 0 0 ns 22 | tcucty | Control Active Delay 2** 3 44 3 37 3 31 ns Notes: Equal Loading DEN, INTA, WR All timings are measured at 1.8 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-200 pF (10 MHz) and C, = 50-100 pF (12.5-20 MHz). For AC tests, input Vj, = 0.45 V and Vy, = 2.4 V, except at X1 where Vj, = Voc 0.5 V. M@! 0257525 DOYSbYb CUO 80C186/80C188 Microprocessors 79ot amo PRELIMINARY 80C186/80C188 Software Halt Cycle Waveforms | i | te | ti t yN Ly le le @ \ Status f A19/S6-A16/S3, AD15-AD8/A15A8, Invalid Address AD7-ADO Ms ott +ko (Note 1) DUR T@r x m 2 Note: 1. For write cycle followed by halt cycle. Clock Waveforms CLKOUT mM 0257525 OO4F9b4? Th? 80 80C186/80C188 MicroprocessorsPRELIMINARY AMD al SWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) Clock Timings Taano = ~40C to +85C, Veo = 5 V+10% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym Description Min Max Min Max Min Max | Unit CLKIN Requirements Measurements taken with: external clock input to X1 and X2 not connected (Float). 36 toxin CLKIN Period 50 40 31.25 ns 37 | terck | CLKIN Low Time 1.5 V2} 20 16 13 ns 38 | touck |CLKIN High Time 1.5 V@) 20 16 13 ns 39 toKHL CLKIN Fall Time 3.5 - 1.0 V 5 5 5 ns 40 toxiy CLKIN Rise Time 1.0-3.5 V 5 5 5 ns CLKOUT Timing 41 teica = | CLKIN to CLKOUT Skew 25 21 17 | ns 42 tete. | CLKOUT Period 100 80 62.5 ns 4 totcH CLKOUT Low Time 0.5 tere - 6 0.5 tere. - 5 0.5 tere. - 5 ns C.= 50 pF) = 44 = 35 = 26.25 C= 100 pF) 0.5 totic. - 8 0.5 tere. ~ 7 0.5 tere. 7 = 42 =33 = 24,25 44 toner CLKOUT High Time 0.5 tercL- 6 0.5 tetcL- 5 0.5 Tete 5 ns C,= 50 pF@) = 44 = 35 = 26.25 C= 100 pF(4) 0.5 tote. 8 0.5 tecL-7 0.5 tetcL 7 = 42 = 33 = 24.25 45 | tcuicue | CLKOUT Rise Time 10 10 10 j ns 1.0-3.5V 46 tevecti CLKOUT Fall Time 10 10 10 ns 3.5-1.0V Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-16 MHz). For AC tests, input V, = 0.45 V and Vy, = 2.4 V, except at X1 where Viy = Voc 0.5 V. 1. teuck and Ioucx (CLKIN Low and High times) should not have a duration less than 40% of toy. 2. Tested under worst case conditions: Voo=5.5 V @ 16 MHz, Ta=70C. 3. Not tested. 4. Tested under worst case conditions: Voc=4.6 V@ 16 MHz, Ty =OC. 5. To guarantee proper operation. 6. To guarantee recognition at clock edge. 7. To guarantee recognition at next clock. Me 0257525 0049648 413 80C186/80C188 Microprocessors 81oA amo PRELIMINARY SWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) Ready, Peripheral, and Queue Status Timings Tawa = 40C to +85C, Voc = 5 V 10% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min Max Min Max Min Max | Unit Ready and Peripheral Timing Requirements 47 | tsryo. | SRDY Transition Setup Time) 15 15 15 ns 48 | tasay |SRDY Transition Hold Time) 15 15 15 ns 49 | tapycy | ARDY Res. Transition Setup 15 15 45 ns Time() 50 | tcanx | ARDY Active Hold Time) 15 15 15 ns 51 | tanycu. {ARDY Inactive Holding Time 15 15 15 ns 52 | taryec. |ARDY Setup Time) 25 25 25 ns 53 | twvcn | Peripheral Setup): INTx, NMI, 15 15 15 ns TMR IN, TEST/BUSY 54 | tno, |ORQ0, DRA1 Setup Time) 15 15 15 ns Peripheral and Queue Status Timing Responses 55 | tomy | Timer Output Delay 40 33 27 | ns 56 | tonasy | Queue Status Delay 37 32 30 | ns All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-16 MHz). For AC tests, input Vy, = 0.45 V and Vj, = 2.4 V, except at X1 where Vy, = Voc 0.5 V. Notes: NOOAwNY lorcx and toucKn (CLKIN Low and High times) should not have a duration less than 40% of tony. Tested under worst case conditions: Voc=5.5 V @ 16 MHz, T,=70C. Not tested. Tested under worst case conditions: Voeo=4.5 V@ 16 MHz, Ts =0C. To guarantee proper operation. To guarantee recognition at clock edge. To guarantee recognition at next clock. we 0257525 CO4db4s &ST 82 80C186/80C188 MicroprocessorsPRELIMINARY Amp Synchronous Ready (SRDY) Waveforms | tw ort, ort, | tw ort. | tw or ts | t CLKOUT SRDY Asynchronous Ready (ARDY) Waveforms | tw Ort, ort, | tw ort. | tw ort, | t | SJ \S\f SNS \ CLKOUT +T- ARDY (Normally Not Ready System) @O> ARDY (Normally Ready System) @ _* M@! 0257525 GO45b50 571 me 80C186/80C188 Microprocessors 83&\ amp PRELIMINARY Peripheral and Queue Status Waveforms CLKOUT NOV ST Ve 6) INT3-INTO, NMi, TEST, TMR IN 2 149 | S.. ri | we DRGs, DRQ1 ). [<q TMR QUT + cc __ 6) eC X QSo0, ast 1 ] RESET Waveforms x1 a i o % CLKOUT RESET MH 0257525 OO45651, 4OS 84 80C186/80C188 MicroprocessorsPRELIMINARY AMD ie SWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) RESET and HOLD/HLDA Timings Taino = 40C to +85C, Veco = 5 V+10% Preliminary Parameter 10 MHz 12 MHz 16 MHz # | Sym | Description Min Max Min Max Min Max | Unit RESET and HOLD/HLDA Timing Requirements 57 | tees |RES Setup 15 15 15 ns 58 | tuye. {HOLD Setup!) 15 15 15 ns 15 te_az | Address Float Delay 0 30 0 25 0 20 ns 5 tcray | Address Valid Delay 3 44 3 36 3 33 | ns RESET and HOLD/HLDA Timing Requirements 61 tctro | Reset Delay 40 33 27 | ns 62 toinav |HLDA Valid Delay 3 40 3 33 3 25 | ns 63 | tcHez | Command Lines Float Delay 40 33 28 | ns 64 | tcuey | Command Lines Valid Delay 44 36 32 j ns (after Float) Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 80-100 pF (10-16 MHz). For AC tests, input Vy = 0.45 V and Vy, = 2.4 V, except at X1 where Vy, = Veco 0.5 V. NOOR WN > lorcx and Icuck (CLKIN Low and High times) should not have a duration less than 40% of tray. Tested under worst case conditions: Vac = 5.5 V@ 16 MHz, T4=70 C. Not tested. Tested under worst case conditions: Voc = 4.5 V @ 16 MHz, Ta =0C. To guarantee proper operation. To guarantee recognition at clock edge. To guarantee recognition at next clock. WM 0257525 0049652 344 mm 80C186/80C188 Microprocessors 85ol amo PRELIMINARY 80C186/80C188 HOLD/HLDA Waveforms (Entering HOLD) { tg ort { ti | ti | exon J \_f?\ LVS VS XN & HOLD a *@2 HLDA cc PP RR J @ AD15-AD8/A15-A8, 7 AD7-ADO, DEN c 4 ad a < A19/S6-A16/S3, RD, WR, as BHE/RESH, DT/R, S2-S0, _ LOC + = CLKOUT } ~\ VN / \ @ HOLD ica | A > am HLDA v ee | 23 > Or- AD15-AD8/A15-A8, ce AD7-ADo0, DEN 23 i a ~-________ A19/S6-A16/S3, RD, NR, BHE/RFSH, DT/R, S2-SO, LOG ml A Me 0257525 0049653 230 86 80C186/80C188 MicroprocessorsPRELIMINARY EXPLANATION OF THE SWITCHING SYMBOLS Each timing symbol has from five to seven characters. The first character is always a t (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of ail the characters and what they stand for. A Address ARY Asynchronous Ready Input Cc Clock Output CK Clock Input cs Chip Select CT Control (DT/R, DEN...) D Data Input DE DEN H Logic Level High IN Input (DRQO, TIMO... } L Logic Level Low or ALE 0 Output Qs Queue Status (QS1, QS2) R RD Signal, RESET Signal S Status (S2, $1, $6) SRY Synchronous Ready Input Vv Valid Ww WR Signal Xx No Longer a Valid Logic Level Z Float Examples: totayTime from Clock Low to Address Valid touu-Time from Clock High to ALE High tercsyTime from Clock Low to Chip Select Valid AMD at 80C186/C188 EXECUTION TIMINGS A determination of 80C186/C188 program execution timing must consider bus cycles necessary to prefetch instructions, as well as the number of execution unit cycles necessary to execute instructions. The following instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following assumptions: The opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. @ No wait states or bus HOLDs occur. @ All word-data is located an even-address boundaries (80C 186 only). Alljumps and calls include the time required to fetch the opcode of the next instruction at the destination address. All instructions that involve memory access can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit. With a 16-bit BIU, the 80C 186 has sufficient bus pertor- mance to ensure that an adequate number of pre- fetched bytes reside in the queue most of the time. Therefore, actual program execution time is not sub- stantially greater than that derived from adding the instruction timings shown. The 80C 188 8-bit BIU is noticeably limited in its perfor- mance relative to the execution unit. A sufficient number of prefetched bytes may not reside in the prefetch queue much of the time. Therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown. me 0257525 OO49bS4 117 a 80C186/80C188 Microprocessors 87oN amo PRELIMINARY Waveforms (continued) x = High-to-Low @ = Low-to-High 50 75 100 125 150 175 Capacitive Load (pF) 13087D-046 Figure 45. Capacitive Derating Curve for Typical Output Delay x =2Vt00.8V @=08Vto2V 50 75 100 125 150 175 Capacitive Load (pF) 13087D-047 Figure 46. TTL Voltage Level Rise and Fall Times for Output Buffers =3.5Vto0.4V e=04Vt03.5V t (ns) 8 50 75 100 125 150 175 Capacitive Load (pF) 13087D-048 Figure 47. CMOS Voltage Level Rise and Fall Times for Output Buffers we 0257525 OO49bS5 053 a 88 80C186/80C188 MicroprocessorsPRELIMINARY 80C186 INSTRUCTION SET SUMMARY AMD cl . Clock Function Format Cycles Comment DATA TRANSFER MOV = Move: Register ta register/memory 1000100w mod reg r/m a2 Register/memory to register 1o001DIW mod reg r/m Ag Immediate to register/memory 1100011W mod 000 r/m data data if w= 1 12-13 8/16 bit Immediate to register 1011wreg data data if w=1 3-4 8/16 bit Memary to accumulator 1010000w addr-low addr-high 8 Accumulator to memory 1010001W addr-low addr-high 9g Register/memory to segment register | 10001110 mod 0 reg rm aa Segment register to register/memary 10001100 mod 0 reg /m ati PUSH = Push: Memory 17111111 mod 11Orm 16 Register 0101 Oreg 10 Segment register O00regii0 9 immediate* 01101081 data | data ifs =0 | 10 PUSHA = Push All* 01100000 36 POP = Pop: Memory 20 Register 10 Segment register 000 111 (reg 01) 8 POPA = Pop All* 01100001 51 XCHG = Exchange: Register/memary with register 1000011WwW mod reg r/m | ANT Register with accumulator 1001 O0reg 3 IN = Input from: Fixed port 1110010wW port | 10 Variable port 1110110wW 8 OUT = Output to: Fixed port 1110011W port | 9g Variable port 1110111W 7 XLAT = Translate byte to AL 171010111 11 LEA = Load EA to register 10001101 mod reg r/m 6 LDS = Load painter to DS 11000701 mod reg r/m (mod # 41) 18 LES = Load pointer to ES 11000100 mad reg F/m (mod # 11) 18 LAHF = Load AH with flags 10011111 2 SAHF = Store AH into flags 10011110 3 PUSHF = Push flags 10011100 9 POPF = Pop flags 10011101 8 Note: Indicates instructions not available in 8086 or 8088 microsystems. M@ 0257525 OOudbSb TUT 80C186/80C188 Microprocessors 89cl AMD PRELIMINARY 800186 INSTRUCTION SET SUMMARY (continued) . Clock Function Format Cycles Comment DATA TRANSFER (continued) SEGMENT = Segment Override: cs 00101110 2 Ss 00110110 2 DS 00111110 2 ES 00100110 2 ARITHMETIC: ADD = Add: Reg/memory with register to either oo00000dw mod reg r/m 3/10 Immediate to register/memory 100000sw mod 000 rm data data ifs w = ov | 46 Immediate to accumulator oo00010W data data if w =1 3/4 8/16 bit ADC = Add with carry: Reg/memory with register to either o000100dw mod reg r/m 3/10 Immediate to register/memory 100000swW mod 0 1 Or/m data data ifs w= 01 | 416 Immediate to accumulator go001010w data data if w = 1 3/4 8/16 bit INC =Increment: Register/memory 417111110 mod 000rm 3/15 Register 01000reg 3 SUB =Subtract: Reg/memory and register to either 001010dw mod reg r/m 3/10 Immediate from register/memory 100000sw mod 1014 /m data data ifs w= 1 | 4/16 Immediate from accumulator 00010110W data data ifw=1 3/4 8/16 bit SBB = Subtract with borrow: Reg/memory and register to either o0qg0110dw mod reg r/m 3/10 immediate from register/memory 100000sWw mod 01 1 1/m data data ifs w = 01 | 4/16 Immediate from accumulator 0001110w data data it w= 1 3/4 8/16 bit DEC = Decrement: Register/memory 11111114 mod 001 um | 35 Register a1ad01reg 3 CMP = Compare: Register/memory with register 0011101W Mod reg r/m 30 Register with register/memary ooti1100Ww mod reg r/m 3/10 Immediate with register/memory 100000sWw mod 11 14 /m data dataifsw=01 3/10 Immediate with accumulator 0011110W data data if w= 1 3/4 8/16 bit NEG = Change sign registermemory |} 1111011W mod 01 1 /m 3/10 AAA = ASCII adjust for add 00110111 8 DAA = Decimal adjust for add 00100111 4 AAS = ASCII adjust for subtract 00111111 7 DAS = Decimal adjust for subtract 001011114 4 MUL = Multiply (unsigned) 1111011W mod 100 am | Register-Byte 26-28 Register-Word 35-37 Mermory-Byte 32-34 Memory-Word 41-43 90 80C186/80C188 MicroprocessorsM299 8S96h00 S2s520 my PRELIMINARY amp 80C186 INSTRUCTION SET SUMMARY (continued) : Clock Function Format Cycles Comment ARITHMETIC (continued) IMUL = Integer multiply (signed) 1111011w Register-Byte 25-28 Register. Word 34-37 Memory-Byte 31-34 Memory-Word 40-49 IMUL = Integer Immediate multiply | 011010s1 | mod reg t/m | data | data ifs =0 22-25/ (signed)* 29-32 Register-Byte 29 Register-Word 38 Memory-Byte a5 Memory-Word 44 IDIV = Integer divide (signed) 111101141w Register-Byte 44-52 Register-Word 53-61 Memory-Byte 50-58 Memory-Word 59-67 AAM = ASCII adjust for multiply 11010100 00001010 19 AAD = ASCIli adjust for divide 11010104 00001010 15 CBW = Convert byte to word 10011000 2 CWD = Convert word to double word | 10011001 4 LOGIC Shift/Rotate Instr 2 Register/Memory by 1 1101000w mod TTT r/m ats Register/Memory by CL 1101001w mod TTT r/m S4#i7en Register /Memary by Count* 1100000wW mod TTT rm count | 54+M17+n TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 100 SHLU/SAL 101 SHR 111 SAR AND = And: Reg/memory and register to either 001000dw mod reg r/m 3/10 Immediate to register/memory 1000005w mod 100 rm data data if w= 1 | 46 Immediate to accumulator 0010010w data data if w = 1 a4 8/16 bit TEST = And function to flags, no result: Register/memory and register 1000010w mod reg r/m 3/10 immediate data and registerfmemory f1111014+w mod 000 1r/m data data if w= 1 4/10 Immediate data and accumulator 1010100w data data it w = 1 3/4 8/16 bit OR = Or: Reg/memory and register to either a00010dw mod reg r/m 3/10 Immediate to register/memory 1000005w mod 00 + rm data data if w =1 | 4/16 Immediate to accumulator o000T10W data data if w = 1 3/4 8/76 bit XOR = Exclusive or: Reg/memory and register to either 001100dw mod reg r/m 3/10 Immediate to register/memory 1000005wW mod 11Orm data data if w= 1 | 4/16 Immediate to accumulator 0011010w data data if w= 1 3/4 8/16 bit NOT = Invert register/memory: 1411011 mod 01 0t/m 3/10 Indicates instructions not available in 8086 or 8088 microsystems. 80C186/80C188 Microprocessors 91cl AMD PRELIMINARY 80C186 INSTRUCTION SET SUMMARY (continued) . Clock Function Format Cycles Comment STRING MANIPULATION: MOVS = Mave byte/word 1010010wW 14 CMPS = Compare byte/word 1010011w 22 SCAS = Scan byte/word 1010111W 15 LODS = Load byte/wd to AVAX 1010110wW 12 STOS = Store byte/wd from ALVA 1010101w 10 INS = Input byte/wd from DX port* 0110110W 14 OUTS = Output byte/wd to DX port* O110111W 14 Repeated by count in CX (REP/REPE/REPZ/PEPNE/PEPNZ) MOVS = Move string 11110010 1010010w 8+8n CMPS = Compare string 11110012 1010011W 5 + 22n SCAS = Scan string 11110012 1010111W 5+ 15n LODS = Load string 41110010 1010110w 64+tin STOS = Store string 11110010 1010101w 6+9n INS = Input string* 11110010 0110110W 8+8n OUTS = Output string* 11110010 0110111 8+8n CONTROL TRANSFER CALL = Call: Direct within segment 11101000 disp-low disp-high 15 Register memory indirect 44941111 mod 01 Or/m 13/19 within segment Direct intersegment |" 0011010 segment offset 23 segment selector Indirect intersegment 441111411 mod 01 1 1/m | (mod = 11) 38 JMP = Unconditional jump: Shortiong 11101011 disp-low 14 Direct within segment 1411101001 disp-low disp-high | 414 Register/mem indirect within segment |} 11111111 mod 100 1/m WAT Direct intersegment 11101010 segment offset 14 segment selector Indirect intersegment | 41111111 mod 101 t/m | (mod 11) 26 RET = Return from CALL: Within segment 41000011 16 Within seg adding immed to SP 41000010 data-low data-high | 18 Intersegment 110010114 22 Intersegment adding immediate toSP | 11001010 data-low | data-high 25 Indicates instructions not available in 8086 or 8088 microsystems. M8 0257525 OO45L55 779 92 80C186/80C188 MicroprocessorsPRELIMINARY 80C186 INSTRUCTION SET SUMMARY (continued) AMD al . Clock Function Format Cycles Comment CONTROL TRANSFER (continued) JE/JZ = Jump on equal zero 01110100 | disp 4/13 JL/JNGE = Jump on less/ not greater or equal 01111100 4/13 JLE/ING = Jump on less/ JB/JNAE = Jump on below/ not above or equal a1110010 | disp 413 JBE/JNA = Jump on below or equal/nal above 01110110 4/13 JP/JPE = Jump on parity/ parity even 01117010 disp 43 JMP not JO = Jump on overtiow 01110000 disp 4/13 taken/JMP JS = Jump on sign 01111000 disp 4/13 taken JNE/INZ = Jump on not equal not zero 01110104 | _diso 4/3 JNL/JGE = Jump on notless greater or equal 011114107 | disp | 4/13 UNLEAG = Jump on not less/ or equal/greater orisitit | disp | 43 JNB/JAE = Jump on not below above or equal 01110011 | _ disp | 43 JNBENA = Jump on not below or equavabove 01110111 | disp 4/13 JNP/JPO = Jump on not Par/par odd O1141011 413 JNO = Jump on not overflow 01110001 4/13 UNS = Jump on not sign 01111001 41g JCXZ = Jump on CX zera 41100011 5/15 LOOP = Loop CX Times 11100010 6/16 Loop not fakery LOOPZ/LOOPE = Loop while zero/equal 11100001 | disp 6/16 LOOP taken LOOPNZ/LOOPNE = Loop while not zero/equat | 11100000 | dso 6/16 ENTER = Enter Procedure* | 11001000 | data-low | data-high | L = 15 Let 25 L>1 22 + 16(n-1) LEAVE = Leave Procedure 11001001 8 INT = Interrupt: Type specified 141001101 47 Type 3 411001100 45 if INT, takery INTO = Interrupt an overflow 11001110 48/4 if INT. not taken IRET = Interrupt return 110011141 28 BOUND = Detect value out of ranget | 01100010 mod reg r/m 33-35 Indicates instructions not available in 8086 or 8088 microsystems. Mi 0257525 coyqgeg 410 = 80C186/80C188 Microprocessors 93cl AMD PRELIMINARY 800186 INSTRUCTION SET SUMMARY (continued) i Clock Comment Function Format Cycles PROCESSOR CONTROL CLC = Clear carry 11111000 2 CMC = Complement carry 4 2 STC = Set carry 2 CLD = Clear direction 4441 0 2 STD = Set direction 11411101 2 CLI = Clear interrupt 111110190 2 STI = Set interrupt 11141011 2 HLT = Halt 11110100 2 WAIT = Wait 10011011 6 if TEST = 0 ESC = Processor Extension Escape 1O0T1TTT 6 LOCK = Bus lock prefix 11110000 2 NOP = No Operation 4 0 3 (T T T LLL are opcade to processor extension) Footnotes The Effective Address (EA) of the memory operand is com- puted according to the mod and r/m fields: if mod = 11 then r/m is treated as a REG field * if mod =00 then DISP = 0*, disp-low and disp-high are absent if mod = 01 then DISP = disp-low sign-extended to 16-bits, disp-high is absent if mod = 10 then DISP = disp-high: disp-low e if rm = 000 then EA = (BX) + (SI) + DISP if m = 001 then EA = (BX) + (Dl) + DISP if /m = 010 then EA = (BP) + (Si) + DISP if /m = 011 then EA = (BP) + (Dl) + DISP e if r/m = 100 then EA = (SI) + DISP e if rm = 101 then EA = (DI) + DISP if rm = 110 then EA = (BP) + DISP* o if rm = 111 then EA = (BX) + DISP DISP follows second byte of instruction (before data if required) *except if mod = 00 and r/m = 110 then EA = disp-high: disp-tow. EA calculation time is four-clock cycles for all modes, and is included in the execution times given whenever appropriate. Segment Override Prefix Lofo[s [rs] +f] 0] Reg is assigned according to the following: Segment Reg Register 00 ES 01 cs 10 ss 11 DS REG is assigned according to the following table: 16 Bit (w= 1) 8 Bit (w = 0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL O11 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 141 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment reg- ister. The physical addresses of the destination oper- ands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden. we 0257525 O045bb1 357 @ 94 80C186/80C188 MicroprocessorsPRELIMINARY 800188 INSTRUCTION SET SUMMARY AMD al Function Format Gyeies Comment nenTaaere Register to register/memory 1000100w mad reg r/m 212" Register/memory to register 1000101WwW mod reg r/m 2/g* Immediate ta register/memory 1100011WwW mod 0 0 0 t/m data data if w = 4 12-13 8/16 bit Immediate ta register 1011wreg data data if w= 1 34 8/16 bit Memory to accumulator 1010000w addr-low addr-high a" Accumulator to memory 1010001W addr-low addr-high gt Register/memory to segment register | 10001110 mod 0 reg fm 213 Segment register to register/memory 10001100 mod 0 reg rm 2/15 PUSH = Push: Memory 111414141441 mod 1 101/m 20 Register 01010reg 14 Segment register 000reg110 13 Immediate** 011010s1 data | data ifs =0 14 PUSHA = Push All** 01100000 68 POP = Pop: Memory 40001111 | modooorm 24 Register 0101 1reg 14 Segment register 000regi11 (reg 04) 12 POPA = Pop All** 01100001 33 XCHG = Exchange: Register/memory with register 100001iw mod reg r/m | 4ii7* Register with accumulator 10010reg 3 IN = Input from: Fixed port 1110010W port 10 Variable port 1110110W 8* OUT = Output to: Fixed port 1110011Ww port | 9* Variable port 1410111W 7 XLAT = Translate byte to AL 11010111 15 LEA = Load EA to register 10001101 mod reg r/m 6 LDS = Load pointer to DS 11000101 mod reg r/m {mod # 11} 26 LES = Load pointer to ES 11000100 mod reg r/m {mod # 11) 26 LAHF = Load AH with flags 10017111 2 SAHF = Store AH into flags 10014110 3 PUSHF = Push flags 10011100 13 POPF = Pop flags 10011701 12 Notes: *Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. Indicates instructions not available in 8086 or 8088 microsystems. M@ 0257525 OO45bbe 293 80C186/80C188 Microprocessors 95me let 996h00 sesesce0 ON amp PRELIMINARY 800188 INSTRUCTION SET SUMMARY (continued) . Clock Function Format Cycles | Comment DATA TRANSFER (Continued) SEGMENT = Segment Override: cs 00101110 2 ss 00110110 2 DS 00111110 2 ES 00100110 2 ARITHMETIC: ADD = Add: Reg/memory with register to either aoaqo0dddw mod reg r/m 3/10* Immediate to register/memory 100000sWw mod 000rm data data ifs w = 01 4/16" Immediate to accumulator o000010w data data ifw=1 3/4 8/16 bit ADC = Add with carry: Reg/memory with register to either 000100dw mod reg r/m 3/10* Immediate to register/memory 100000sw mad 0 1 0 r/m data data ifs w = 01 4/16" Immediate to accumulator 0001010wW data dataifw=1 3/4 8/16 bit INC =Increment: Register/memory 1114111w mod 0 0 0 r/m | 3/15" Register 01000reg 3 SUB =Subtract: Reg/memory and register to either 001010dw mod reg r/m 3/10 Immediate from register/memory 100000sw mod 101 1/m data data ifs w= 1 | 4ne Immediate from accumulator 00010110w data data ifw=1 4 8/16 bit SBB = Subtract with borrow: Reg/memory and register to either 000110dw mod reg r/m asia" Immediate from register/memory 100000sw mod 0 14 /m data data ifs w = 01 4/16* Immediate from accumulator 0001110wW data data ifw=1 3/4 8/16 bit DEC = Decrement: Register/memory 1111111W mod 00 1 1/m a/15* Register 01001 rag 3 CMP = Compare: Register/memory with register 0011101W mod reg fm 3/10 Register with register/memory 0011100w mod reg rm 3/10* Immediate with register/memory 100000swW mod 1114 t/m data data ifs w = 01 3/10* Immediate with accumulator 0011110W data data ifw=1 3/4 8/16 bit NEG = Change sign register/memory | 1111011w mod 011 t/m 3/10* AAA = ASCIl adjust tor add 00110111 8 DAA = Decimal adjust for add 00100111 4 AAS = ASCII adjust for subtract go111111 7 DAS = Decimal adjust for subtract 00101111 4 MUL = Multiply (unsigned) 11417011wW mod 100 1r/m Register-Byte 26-28 Register-Word 35-37 Mermory-Byte 32-34 Memory-Word 41-43* Note: *Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. 96 80C186/80C188 Microprocessorswo990 499bhOO SseseScO PRELIMINARY 800188 INSTRUCTION SET SUMMARY (continued) AMD al . Clock Function Format Cycles Comment ARITHMETIC (Continued) Register-Byte 25-28 Register-Word 34-37 Memory-Byte 31-34 Memory-Word 40-43 IMUL = Integer Immediate multiply** | 01101081 | mod reg t/m | data dataifs=0 22-25/ (signed) 29-32 Register-Byte 29 Register-Word 38 Memory-Byte 35 Memory-Word 44* Ragister-Byte 44-59 Register-Word 53-61 Memory-Bye 50-58 Memory-Word 59-67* AAM = ASCIi adjust for multiply 41010100 00001010 19 AAD = ASCII agjust for divide 11010101 00001010 15 CBW = Convert byte to word 10011000 2 CWD = Convert word to double word 710011001 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000WwW mod TTT r/m 2/15 Register/Memory by CL 4101001W mod TTT r/m S4+ni7en Register /Memory by Count** 1100000wW mod TTT r/m count 5S+ni7+n TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 100 SHUSAL 101 SHR 111 SAR AND = And: Reg/memory and register to either 001000dw mad reg r/m 3/10* Immediate to register/memory 1000005wW mod 10 01/m data data if w= 1 | 46" Immediate to accumulator 0010010W data data if w = 1 3/4 8/16 bit TEST = And function to flags, no result: Register/memory and register 1000010W mod reg r/m 3/10 immediate data and register/memory J11711011Ww mod 00 0 rm data data if w= 1 4/10" immediate data and accumulator 1010100w data dataifw=1 a4 8/16 bit OR = Or: Reg/memory and register to either 000010dw mod reg r/m 3/10* Immediate to register/memory 1000005w mod 00 1 r/m data data if w= 1 416" Immediate to accumulator oo00110w data data if w= 1 3/4 8/16 bit XOR = Exclusive or: Reg/memory and register to either 001100dw mod reg r/m as10* Immediate to register/memory 1000005w mod 11 O1/m data data if w= 1 | 416" Immediate to accumulator 0011010W data data if w = 1 3/4 8/16 bit NOT = Invert register/memory: 1111011W mod 04 Or/m 3/10" Notes: *Clock cycles shown for byte transfer, For word operations, add 4 clock cycles for all memory transfers. Indicates instructions not available in 8086 or 8088 microsystems. 80C186/80C188 Microprocessors 97i1 amo PRELIMINARY 80C188 INSTRUCTION SET SUMMARY (continued) ; Clock Function Format Cycles Comment STRING MANIPULATION: MOVS = Move byte/word 1010010w 14* CMPS = Compare byte/word 1010011W 22" SCAS = Scan byte/word 1010111W 15 LODS = Load byte/wd to ALVVAX 1010110w 12* STOS = Store byte/wd from AVA 1010101Ww 10* INS = input byte/wd from DX port** 0110110w 14 OUTS = Output byte/wd to DX port** | 0110t111W 14 Repeated by count in CX (REP/REPE/REPZ/PEPNE/PEPNZ) MOVS = Move string 11110010 1010010w 8+ 8n* CMPS = Compare string 11411001z 1010011W 5 + 22n* SCAS = Scan string 41110012 1010111W 5+ t5n* LODS = Load string 11110010 1010110w 6 + 11in* STOS = Store string 11110010 1010101W 6 +Gn* INS = Input string** 11110010 0110110W 8+ 8n* OUTS = Output string** 11110010 O110111W 8+ 8n* CONTROL TRANSFER CALL = Call: Direct within segment 11101000 disp-low disp-high 19 Register memory indirect 41111111 mod 01 Or/m 17/27 within segment Direct intersegment | 10011010 segment offset Ry segment selector Indirect intersegment | 171141714 mod 01 1 /m | (mod # 11) 54 JMP = Unconditional jump: Shorviong 41101011 disp-low 14 Direct within segment 11101001 disp-low 14 Register/mem indirect within segment | 11111111 mod 10 Or/m 41/24 Direct intersegment 11101010 segment offset 14 segment indirect intersegment 34 RET = Return from CALL: Within segment 11000011 20 Within seg adding immed to SP 11000010 data-low | data-high | 22 intersegment 11001011 30 Intersegment adding immediate toSP | 11001010 data-low | data-high | 33 Notes: Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. Indicates instructions not available in 8086 or 8088 microsystems. WM 0257525 OO4IbLS TTe a 98 80C186/80C188 MicroprocessorsPRELIMINARY 80C188 INSTRUCTION SET SUMMARY (continued) AMD al . Clock Function Format Cycles Comment CONTROL TRANSFER (Continued): JL/JNGE = Jump on less/ not greater or equal 01111700 | disp 43 JLE/JNG = Jump on less/ JB/JNAE = Jump on below/ JBE/JNA = Jump on below or JP/JPE = Jump on parity/ parity even 01111010 disp 413 JMP not JO = Jump on overflow 01110000 disp 4g taken/JMP JS = Jump on sign 01111000 disp 4/13 taken JNE/JNZ = Jump on not equal nat zero 01110101 | disp 43 JNL/JGE = Jump on not less greater or equal 01111101 | disp | 43 JNLE/JG = Jump on not less/ or equaV/greater O114i4114 | disp 43 JNB/JAE = Jump on not below above or equal 01110011 | disp | 43 JNBE/JA = Jump on not below craqualatove = Tovrrorts | ae ans JNP/JPO = Jump on not par/par odd 01111041 413 JNO = Jump on not overflow 01110001 413 UNS = Jump on not sign 01111001 43 JCXZ = Jump on CX zero 11100011 S15 LOOP = Loop GX Times 11100010 616 LOOP not LOOPZ/LOOPE = Loop while reveal = Lasso0001 | disp | ene | takerL0oP LOOPNZ/LOOPNE = Loop while ENTER = Enter Procedure** | 11004000 | data-low | data-high 9 =0 1 L=1 29 L>1 26 + 20(n ~ 1) LEAVE = Leave Procedure** 11001001 8 INT = Interrupt: Type specified 11001101 47 Type 3 11001100 45 if INT. taken/ INTO = Interrupt on overflow 11001110 48/4 if INT. not taken; IRET = Interrupt return 17001111 28 BOUND = Detect value out of range** | 01100010 mod reg t/m 33-35 Notes: *Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. Indicates instructions not available in 8086 or 8088 microsystems. Me 0257525 OO45bbb 935 80C186/80C188 Microprocessors 99il AMD PRELIMINARY 80C188 INSTRUCTION SET SUMMARY (continued) Clock Function Format Cycles | Comment PROCESSOR CONTROL CLC = Clear carry 2 CMC = Complement carry 2 STC = Set carry 11111001 2 CLD = Clear direction 11111100 2 STD = Set direction 14111101 2 CLI = Clear interrupt 11111010 2 STI = Set interrupt 2 HLT = Halt 11110100 2 WAIT = Wait 40011011 6 if TEST = 0 LOCK = Bus lock prefix fi1140000| 2 NOP = No Operation 10010000 3 Footnotes The Effective Address (EA) of the memory operand is com- puted according to the mod and r/m fields: if mod = 11 then r/m is treated as a REG field if mod =00 then DISP = 0*, disp-low and disp-high are absent if mod = 01 then DISP = disp-low sign-extended to 16-bits, disp-high is absent if mod = 10 then DISP = disp-high: disp-low if rm = 000 then EA = (BX) + (Sl) + DISP eifr/m = 001 then EA = tap} + (Dl) + DISP @ if rm = 010 then EA = (BP) + (SI) + DISP if rm = 011 then EA = (BP) + (DI) + DISP if rm = 100 then EA = (Sl) + DISP eif m= 101 then EA= (DY + DISP e if rm = 110 then EA = (BP) + DISP* e if r/m = 111 then EA = (BX) + DISP DISP follows second byte of instruction (before data if required) *except if mod = 00 and r/m = 110 then EA = disp-high: disp-low. EA calculation time is four-clock cycles for all modes, and is included in the execution times given whenever appropriate. Segment Override Prefix CPt T= DET] Reg is assigned according to the following: Segment Reg Register 00 ES 01 cs 10 ss 11 DS REG is assigned according to the following table: 16 Bit (w= 1) 8 Bit (w = 0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX o11 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 141 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment reg- ister. The physical addresses of the destination oper- ands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden. M@@ 0257525 OO4Fbb? 3875 100 80C186/80C188 MicroprocessorsPRELIMINARY PHYSICAL DIMENSIONS For reference only. Dimensions are measured in inches unless otherwise noted. BSC is an ANSI standard for Basic Space Centering. AMD al PL 068 020 042 050 MIN 048 >| fe 042 nd a a) 056 + : A q a q 4 q FY Eh a r Hy 082 800 .890 985 960 f j Bat 995 (956 [ H REF 830 [ al q i qj 0 q a [ h 0 H T q i] yj c NX by Jj 950 013. 090 985 os [2 ae . 8 PL OG 995 ~ foe ata ode TOP VIEW SIDE VIEW M 025752e5 OO4Y5bbS 701 80C186/80C188 Microprocessors 101iN amp PRELIMINARY PHYSICAL DIMENSIONS (continued) PQR 80 (measured in millimeters) 17.10 17.30 Pin 40 23.00 23.40 Pin 1 |.D-* @ Pin 64 Top View Pin 80 | > - 0.80 Basic LI , 3.95 i I MAX [-Aq 2X 2.70 2.90 15590C 0.25 . BM 43 . Side View 7123/93 MH Notes: 1. All dimensions and tolerances conform to ANSI Y 14.6M-1982. LN Datum Plane is located at the mold parting line and is coincident with the bottom of the lead where the lead exits the plastic body. LN These dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. These dimensions do include mald mismatch and are determined at datum plane [-A-]. 4. Daviations from lead-tip true position shall be within 0.076 mm. Lead coplanarity shall be within 0.10 mm. mm 0257525 OO4%bb4 b4e 102 80C186/80C188 MicroprocessorsPRELIMINARY amp PHYSICAL DIMENSIONS (continued) PQT 80 Thin Quad Flat Pack (metric unit) LL 13.80 11.80 14.20 L 9.50 12.10 4 REF : LARARAORIA BERRA NOL oy m4 | ==) cT rT oo | ==] cr | Tr oo | =~ | 9.50 i PREF Fe. fo. po 11.90 = - 12.10 oS | = 13.80 oo = 14,20 a ' rT oo | Pr or | =] ox Fe GOUGH EHU ERO ER REA Top View DetalX TN, Detail i ; MUM 1.20 | CT MAX XN 7 ~~ ee _P Side View Plane 0.25 0.45 Detall X 0.75 20000A Detall Y M 0257525 OO44b70 3bT oe on/oa/ea ed 80C186/80C188 Microprocessors 103