74LVC2G02GT,115 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74LVC2G02 provides a 2-input NOR gate function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using IOFF. The IOFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

2. Features

nWide supply voltage range from 1.65 V to 5.5 V

n5 V tolerant outputs for interfacing with 5 V logic

nHigh noise immunity

n±24 mA output drive (VCC = 3.0 V)

nCMOS low power consumption

nComplies with JEDEC standard:

uJESD8-7 (1.65 V to 1.95 V)

uJESD8-5 (2.3 V to 2.7 V)

uJESD8-B/JESD36 (2.7 V to 3.6 V)

nLatch-up performance exceeds 250 mA

nDirect interface with TTL levels

nInputs accept voltages up to 5 V

nESD protection:

uHBM JESD22-A114E exceeds 2000 V

uMM JESD22-A115-A exceeds 200 V

nMultiple package options

nSpeciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

74LVC2G02

Dual 2-input NOR gate

Rev. 07 — 6 June 2008 Product data sheet

Product data sheet Rev. 07 — 6 June 2008 2 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

3. Ordering information

4. Marking

5. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVC2G02DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm SOT505-2

74LVC2G02DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm SOT765-1

74LVC2G02GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads;

8 terminals; body 1 ×1.95 ×0.5 mm SOT833-1

74LVC2G02GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2

74LVC2G02GM −40 °C to +125 °C XQFN8U plastic extremely thin quad ﬂat package; no leads;

8 terminals; UTLP based; body 1.6 ×1.6 ×0.5 mm SOT902-1

Table 2. Marking codes

Type number Marking code

74LVC2G02DP V02

74LVC2G02DC V02

74LVC2G02GT V02

74LVC2G02GD V02

74LVC2G02GM V02

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)

001aah780

1B 1Y

2B 2Y

001aah781

mna105

Product data sheet Rev. 07 — 6 June 2008 3 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 4. Pin conﬁguration SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8) Fig 5. Pin conﬁguration SOT833-1 (XSON8)

74LVC2G02

1A VCC

1B 1Y

2Y 2B

GND 2A

001aab642

74LVC2G02

VCC

GND

001aab643

Transparent top view

Fig 6. Pin conﬁguration SOT996-2 (XSON8U) Fig 7. Pin conﬁguration XQFN8U

001aai250

74LVC2G02

Transparent top view

GND

VCC

001aae971

1B2B

VCC

GND

Transparent top view

terminal 1

index area

74LVC2G02

Table 3. Pin description

Symbol Pin Description

SOT505-2, SOT765-1,

SOT833-1 and SOT996-2 SOT902-1

1A, 2A 1, 5 7, 3 data input

1B, 2B 2, 6 6, 2 data input

GND 4 4 ground (0 V)

1Y, 2Y 7, 3 1, 5 data output

VCC 8 8 supply voltage

Product data sheet Rev. 07 — 6 June 2008 4 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.

[3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.

For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.

For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.

9. Recommended operating conditions

Table 4. Function table[1]

Input Output

nA nB nY

LLH

XHL

HXL

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +6.5 V

VIinput voltage [1] −0.5 +6.5 V

VOoutput voltage Active mode [1] −0.5 VCC + 0.5 V

Power-down mode [1][2] −0.5 +6.5 V

IIK input clamping current VI<0V −50 - mA

IOK output clamping current VO< 0 V or VO>V

CC -±50 mA

IOoutput current VO=0VtoV

CC -±50 mA

ICC supply current - 100 mA

IGND ground current −100 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb =−40 °C to +125 °C[3] - 300 mW

Table 6. Operating conditions

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 1.65 5.5 V

VIinput voltage 0 5.5 V

VOoutput voltage Active mode 0 VCC V

Power-down mode 0 5.5 V

Tamb ambient temperature −40 +125 °C

∆t/∆V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V

VCC = 2.7 V to 5.5 V - 10 ns/V

Product data sheet Rev. 07 — 6 June 2008 5 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

10. Static characteristics

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Tamb =−40 °C to +85 °C[1]

VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V

VCC = 2.3 V to 2.7 V 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - V

VCC = 4.5 V to 5.5 V 0.7 × VCC -- V

VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V

VCC = 2.3 V to 2.7 V - - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3 × VCC V

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V

IO=−4 mA; VCC = 1.65 V 1.2 1.53 - V

IO=−8 mA; VCC = 2.3 V 1.9 2.13 - V

IO=−12 mA; VCC = 2.7 V 2.2 2.50 - V

IO=−24 mA; VCC = 3.0 V 2.3 2.60 - V

IO=−32 mA; VCC = 4.5 V 3.8 4.10 - V

VOL LOW-level output voltage VI = VIH or VIL

IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V

IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V

IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V

IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V

IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V

IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V

IIinput leakage current VI= 5.5 Vor GND; VCC = 0 V to 5.5 V - ±0.1 ±5µA

IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 µA

ICC supply current VI= 5.5 Vor GND;

VCC = 1.65 V to 5.5 V; IO=0A - 0.1 10 µA

∆ICC additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;

VCC = 2.3 V to 5.5 V - 5 500 µA

CIinput capacitance - 2.5 - pF

Tamb =−40 °C to +125 °C

VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V

VCC = 2.3 V to 2.7 V 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - V

VCC = 4.5 V to 5.5 V 0.7 × VCC -- V

VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V

VCC = 2.3 V to 2.7 V - - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3 × VCC V

Product data sheet Rev. 07 — 6 June 2008 6 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

[1] All typical values are measured at Tamb = 25 °C.

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V

IO=−4 mA; VCC = 1.65 V 0.95 - - V

IO=−8 mA; VCC = 2.3 V 1.7 - - V

IO=−12 mA; VCC = 2.7 V 1.9 - - V

IO=−24 mA; VCC = 3.0 V 2.0 - - V

IO=−32 mA; VCC = 4.5 V 3.4 - - V

VOL LOW-level output voltage VI = VIH or VIL

IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V

IO = 4 mA; VCC = 1.65 V - - 0.70 V

IO = 8 mA; VCC = 2.3 V - - 0.45 V

IO = 12 mA; VCC = 2.7 V - - 0.60 V

IO = 24 mA; VCC = 3.0 V - - 0.80 V

IO = 32 mA; VCC = 4.5 V - - 0.80 V

IIinput leakage current VI= 5.5 Vor GND; VCC = 0 V to 5.5 V - - ±20 µA

IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±20 µA

ICC supply current VI= 5.5 Vor GND;

VCC = 1.65 V to 5.5 V; IO=0A --40µA

∆ICC additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;

VCC = 2.3 V to 5.5 V - - 5000 µA

Table 7. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 07 — 6 June 2008 7 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

11. Dynamic characteristics

[1] Typical values are measured at nominal VCC and at Tamb =25°C.

[2] tpd is the same as tPLH and tPHL.

[3] CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2× fi× N + Σ(CL× VCC2× fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

Σ(CL× VCC2× fo) = sum of outputs.

12. Waveforms

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9.

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

tpd propagation delay nA, nB to nY; see Figure 8 [2]

VCC = 1.65 V to 1.95 V 1.2 3.8 8.9 1.2 11.2 ns

VCC = 2.3 V to 2.7 V 0.8 2.4 5.4 0.8 6.8 ns

VCC = 2.7 V 0.8 3.2 6.0 0.8 7.5 ns

VCC = 3.0 V to 3.6 V 0.6 2.4 4.9 0.6 6.2 ns

VCC = 4.5 V to 5.5 V 0.6 1.8 4.3 0.6 5.5 ns

CPD power dissipation

capacitance per gate; VI = GND to VCC [3] -14-- -pF

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8. Input (nA, nB) to output (nY) propagation delays

001aae972

nA, nB input

nY output

tPLH

tPHL

GND

VOH

VOL

Product data sheet Rev. 07 — 6 June 2008 8 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

Table 9. Measurement points

Supply voltage Input Output

VCC VMVM

1.65 V to 1.95 V 0.5VCC 0.5VCC

2.3 V to 2.7 V 0.5VCC 0.5VCC

2.7 V 1.5 V 1.5 V

3.0 V to 3.6 V 1.5 V 1.5 V

4.5 V to 5.5 V 0.5VCC 0.5VCC

Test data is given in Table 10.

Deﬁnitions for test circuit:

RL = Load resistor.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = Test voltage for switching times.

Fig 9. Load circuitry for switching times

VEXT

VCC

VIVO

001aae235

DUT

PULSE

GENERATOR

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

Table 10. Test data

Supply voltage Input Load VEXT

VCC VItr, tfCLRLtPLH, tPHL

1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩopen

2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ωopen

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen

4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ωopen

Product data sheet Rev. 07 — 6 June 2008 9 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

13. Package outline

Fig 10. Package outline SOT505-2 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(1) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 0.95

0.75 0.38

0.22 0.18

0.08 3.1

2.9 3.1

2.9 0.65 4.1

3.9 0.70

0.35 8°

0°

0.13 0.10.20.5

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.47

0.33

SOT505-2 - - - 02-01-16

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2

1.1

pin 1 index

Product data sheet Rev. 07 — 6 June 2008 10 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

Fig 11. Package outline SOT765-1 (VSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 0.85

0.60 0.27

0.17 0.23

0.08 2.1

1.9 2.4

2.2 0.5 3.2

3.0 0.4

0.1 8°

0°

0.13 0.10.20.4

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.40

0.15

0.21

0.19

SOT765-1 MO-187 02-06-07

0.12

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1

pin 1 index

Product data sheet Rev. 07 — 6 June 2008 11 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

Fig 12. Package outline SOT833-1 (XSON8)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT833-1 - - -

MO-252

- - -

SOT833-1

07-11-14

07-12-07

DIMENSIONS (mm are the original dimensions)

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

e1e1

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 2.0

1.9 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

8×

(2)

4×

(2)

Product data sheet Rev. 07 — 6 June 2008 12 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

Fig 13. Package outline SOT996-2 (XSON8U)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT996-2 - - -- - -

SOT996-2

07-12-18

07-12-21

UNIT A

max

mm 0.5 0.05

0.00 0.35

0.15 3.1

2.9 0.5 1.5 0.5

0.3 0.6

0.4 0.1 0.05

DIMENSIONS (mm are the original dimensions)

XSON8U: plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 x 2 x 0.5 mm

0 1 2 mm

scale

b D

2.1

1.9

E e e1L L1

0.15

0.05

L2v w

0.05

y y1

0.1

eAC B

vMCw M

terminal 1

index area

B A

detail X

AA1

Product data sheet Rev. 07 — 6 June 2008 13 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

Fig 14. Package outline SOT902-1 (XQFN8U)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT902-1 MO-255- - - - - -

SOT902-1

05-11-25

07-11-14

UNIT A

max

mm 0.5

0.25

0.15

0.05

0.00 1.65

1.55 0.35

0.25 0.15

0.05

DIMENSIONS (mm are the original dimensions)

XQFN8U: plastic extremely thin quad flat package; no leads;

8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm

bDLe1

1.65

1.55

eE L1v

0.10.55 0.5

0.05

0.05 0.05

0 1 2 mm

scale

terminal 1

index area

terminal 1

index area

B A

detail X

AC B

∅ vMC∅ wM

metal area

not for soldering

Product data sheet Rev. 07 — 6 June 2008 14 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

14. Abbreviations

15. Revision history

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC2G02_7 20080606 Product data sheet - 74LVC2G02_6

Modiﬁcations: •Added type number 74LVC2G02GD (XSON8U package)

74LVC2G02_6 20080222 Product data sheet - 74LVC2G02_5

74LVC2G02_5 20070904 Product data sheet - 74LVC2G02_4

74LVC2G02_4 20060515 Product data sheet - 74LVC2G02_3

74LVC2G02_3 20050201 Product speciﬁcation - 74LVC2G02_2

74LVC2G02_2 20040915 Product speciﬁcation - 74LVC2G02_1

74LVC2G02_1 20031015 Product speciﬁcation - -

Product data sheet Rev. 07 — 6 June 2008 15 of 16

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

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reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

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damage. NXP Semiconductors accepts no liability for inclusion and/or use of

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therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

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Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LVC2G02

Dual 2-input NOR gate

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 June 2008

Document identifier: 74LVC2G02_7

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

17 Contact information. . . . . . . . . . . . . . . . . . . . . 15

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16