SN55HVD251 SN65HVD251 www.ti.com D DRJ SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 P INDUSTRIAL CAN TRANSCEIVER Check for Samples: SN55HVD251, SN65HVD251 FEATURES DESCRIPTION * The HVD251 is intended for use in applications employing the Controller Area Network (CAN) serial communication physical layer in accordance with the ISO 11898 Standard. The HVD251 provides differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 megabits per second (Mbps). 1 * * * * * * * * * * (1) Drop-In Improved Replacement for the PCA82C250 and PCA82C251 Bus-Fault Protection of 36 V Meets or Exceeds ISO 11898 Signaling Rates(1) Up to 1 Mbps High Input Impedance Allows up to 120 Nodes on a Bus Bus Pin ESD Protection Exceeds 14 kV HBM Unpowered Node Does Not Disturb the Bus Low-Current Standby Mode -- 200 A Typical Thermal Shutdown Protection Glitch-Free Power-Up and Power-Down Bus Protection For Hot-Plugging DeviceNet Vendor ID # 806 The signaling rate of a line is the number of voltage transitions that are made per second expressed in bps (bits per second). APPLICATIONS * * * * CAN Data Buses Industrial Automation SAE J1939 Standard Data Bus Interface NMEA 2000 Standard Data Bus Interface Designed for operation in harsh environments, the device features cross-wire, overvoltage and loss of ground protection to 36 V. Also featured are overtemperature protection as well as -7 V to 12 V common-mode range, and tolerance to transients of 200 V. The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial, building automation, and automotive applications. Rs, pin 8, selects one of three different modes of operation: high-speed, slope control, or low-power mode. The high-speed mode of operation is selected by connecting pin 8 to ground, allowing the transmitter output transistors to switch as fast as possible with no limitation on the rise and fall slope. The rise and fall slope can be adjusted by connecting a resistor to ground at pin 8; the slope is proportional to the pin's output current. Slope control with an external resistor value of 10 k gives ~ 15 V/s slew rate; 100 k gives ~ 2 V/s slew rate. If a high logic level is applied to the Rs pin 8, the device enters a low-current standby mode where the driver is switched off and the receiver remains active. The local protocol controller returns the device to the normal mode when it transmits to the bus. function diagram (positive logic) D GND 1 8 RS 2 7 VCC 3 6 R 4 5 CANH CANL Vref VCC 3 1 D RS 8 R 4 5 V ref 7 CANH 6 CANL 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2010, Texas Instruments Incorporated SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE RANGE SN65HVD251D 8-pin Small Outline Integrated Circuit (SOIC) -40C to 125C VP251 SN65HVD251P 8-pin Dual Inline Package (DIP) -40C to 125C 65HVD251 SN55HVD251DRJ 8-pin Small Outline No-Lead (SON) -55C to 125C SN55HVD251 ABSOLUTE MAXIMUM RATINGS (1) MARKED AS (2) Values Supply voltage range, VCC -0.3 V to 7 V Voltage range at any bus terminal (CANH or CANL) -36 V to 36 V Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b CANH, CANL 200 V Input voltage range, VI (D, Rs, or R) -0.3 V to VCC + 0.5 Receiver output current, IO -10 mA to 10 mA Human Body Model Electrostatic discharge (3) Charged-Device Model Electrical fast transient/burst (4) IEC 61000-4-4, Classification B CANH, CANL and GND 14 kV All pins 6 kV All pins 1 kV CANH, CANL 3 kV (see the Package Dissipation Ratings Table) Continuous total power dissipation (1) (2) (3) (4) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. PACKAGE DISSIPATION RATINGS PACKAGE SOIC (D) PDIP (P) SON (DRJ) (1) (2) (3) 2 DERATING FACTOR ABOVE TA = 25C (1) CIRCUIT BOARD MODEL TA = 25C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING Low-K (2) 576 mW 4.8 mW/C 288 mW 96 mW High-K (3) 924 mW 7.7 mW/C 462 mW 154 mW Low-K (2) 888 mW 7.4 mW/C 444 mW 148 mW High-K (3) 1212 mW 10.1 mW/C 606 mW 202 mW Low-K (2) 403 mW 4.03 mW/C 262 mW 100 mW High-K (no Vias) (3) 1081 mW 10.8 mW/C 703 mW 270 mW High-K (with Vias) 2793 mW 27.9 mW/C 1815 mW 698 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the Low-K thermal metric definitions of EIA/JESD51-3. In accordance with the High-K thermal metric definitions of EIA/JESD51-7. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 THERMAL CHARACTERISTICS PARAMETER qJB TEST CONDITIONS Junction-to-board thermal resistance MIN TYP D 78.7 P 48.9 DRJ qJC Junction-to-case thermal resistance TSD Device power dissipation UNITS C/W 73 D 44.6 P 66.6 DRJ PD MAX C/W 52 VCC = 5 V, Tj = 27C, RL = 60, RS at 0 V, Input to D a 500-kHz 50% duty cycle square wave 97.7 mW VCC = 5.5 V, Tj = 130C, RL = 60, RS at 0 V, Input to D a 500-kHz 50% duty cycle square wave 142 mW 165 C Thermal shutdown junction temperature RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM Supply voltage, VCC Voltage at any bus terminal (separately or common mode) VI or VIC High-level input voltage, VIH D input Low-level input voltage, VIL D input V (1) 12 V -7 Input voltage at Rs for standby, VI(Rs) V 0.3 VCC V -6 6 V 0 VCC V 0.75 VCC VCC V 0 100 k Input voltage to Rs, VI(Rs) Rs wave-shaping resistance Driver -50 Receiver mA -4 Driver Low-level output current, IOL 50 Receiver Operating free-air temperature, TA mA 4 SN65HVD251 -40 125 SN55HVD251 -55 125 Junction temperature, TJ (1) UNIT 5.5 0.7 VCC Differential input voltage, VID High-level output current, IOH MAX 4.5 C 145 C The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. SUPPLY CURRENT over operating free-air temperature range (unless otherwise noted) PARAMETER ICC (1) Supply current TEST CONDITIONS MIN TYP (1) MAX UNIT Standby Rs at VCC, D at VCC Dominant D at 0 V, 60 load, Rs at 0 V 275 65 Recessive D at VCC, no load, Rs at 0 V 14 A mA All typical values are at 25C and with a 5-V supply. Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 Submit Documentation Feedback 3 SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted). PARAMETER VO(D) VO(R) VOD(D) TEST CONDITIONS Bus output voltage (Dominant) CANH Bus output voltage (Recessive) CANH CANL CANL Differential output voltage (Dominant) MIN TYP (1) 2.75 Figure 1 and Figure 2 , D at 0 V Rs at 0 V, T -40C MAX UNIT 3.5 4.5 0.5 Figure 1 and Figure 2 , D at 0.7VCC, Rs at 0 V, 2 2 2.5 3 3 V 2 2.5 Figure 1 , D at 0 V, Rs at 0 V 1.5 2 3 V Figure 3 , D at 0 V, Rs at 0 V, RNODE = 330 1.2 2 3.1 V Figure 3 , D at 0 V, Rs at 0 V, RNODE = 165 , VCC 4.75 V 1.2 2 3.1 V mV Figure 1 and Figure 2 , D at 0.7 VCC -120 12 D at 0.7 VCC, no load, T 85C -0.5 0.05 VOD(R) Differential output voltage (Recessive) VOC(pp) Peak-to-peak common-mode output voltage Figure 9, Rs at 0 V IIH High-level input current, D Input D at 0.7 VCC -40 0 A IIL Low-level input current, D Input D at 0.3 VCC -60 0 A 600 Figure 11, VCANH at -7 V, CANL Open Short-circuit steady-state output current CO Output capacitance See receiver input capacitance IOZ High-impedance output current See receiver input current IIRs(s) Rs input current for standby Rs at 0.75 VCC IIRs(f) Rs input current for full speed operation Rs at 0 V 2.5 Figure 11, VCANL at -7 V, CANH Open -2 Figure 11, VCANL at 12 V, CANH Open (1) mV -200 Figure 11, VCANH at 12 V, CANL Open IOS(SS) V mA 200 -10 A -550 0 A All typical values are at 25C and with a 5-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted). PARAMETER tpLH TEST CONDITIONS Propagation delay time, low-to-high-level output TYP MAX Figure 4, Rs at 0 V MIN 40 70 Figure 4, Rs with 10 k to ground 90 125 Figure 4, Rs with 100 k to ground 500 800 85 125 Figure 4, Rs at 0 V tpHL Propagation delay time, high-to-low-level output Figure 4, Rs with 10 k to ground 200 260 Figure 4, Rs with 100 k to ground 1150 1450 Figure 4, Rs at 0 V tsk(p) Pulse skew (|tpHL - tpLH|) tr Differential output signal rise time tf Differential output signal fall time tr Differential output signal rise time tf Differential output signal fall time tr Differential output signal rise time tf Differential output signal fall time ten Enable time from standby to dominant 4 Submit Documentation Feedback 45 85 Figure 4, Rs with 10 k to ground 110 180 Figure 4, Rs with 100 k to ground 650 900 35 80 100 35 80 100 100 150 250 100 150 250 600 950 1550 600 950 1550 Figure 4, Rs at 0 V Figure 4, Rs with 10 k to ground Figure 4, Rs with 100 k to ground Figure 8 0.5 UNIT ns s Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT- Negative-going input threshold voltage Vhys Hysteresis voltage (VIT+ - VIT-) VOH High-level output voltage Figure 6, IO = -4mA VOL Low-level output voltage Figure 6, IO = 4mA MIN TYP MAX UNIT 750 Rs at 0 V, (See Table 1) 500 900 650 mV 100 0.8 VCC V 0.2 VCC CANH or CANL at 12 V II CANH or CANL at 12 V, VCC at 0 V Bus input current CANH or CANL at -7 V CANH or CANL at -7 V, VCC at 0 V V 600 Other bus pin at 0 V, Rs at 0 V, D at 0.7 VCC 715 A -460 -340 CI Input capacitance, (CANH or CANL) Pin-to-ground, VI = 0.4 sin (4E6pt) + 0.5 V, D at 0.7 VCC 20 pF CID Differential input capacitance Pin-to-pin, VI = 0.4 sin (4E6pt) + 0.5 V, D at 0.7 VCC 10 RID Differential input resistance D at 0.7 VCC, Rs at 0 V 40 100 k RIN Input resistance, (CANH or CANL) D at 0.7 VCC, Rs at 0 V 20 50 k Receiver noise rejection See Figure 13 pF RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX tpLH Propagation delay time, low-to-high-level output 35 50 tpHL Propagation delay time, high-to-low-level output 35 50 tsk(p) Pulse skew (|tpHL - tpLH|) tr Output signal rise time tf Output signal fall time tp(sb) Propagation delay time in standby Figure 6 20 2 4 2 Figure 12, Rs at VCC UNIT ns 4 500 VREF-PIN CHARACTERISTICS over recommended operating conditions (unless otherwise noted). PARAMETER VO TEST CONDITIONS -5 A < IO < 5 A Reference output voltage -50 A < IO < 50 A MIN TYP MAX 0.45 VCC 0.55 VCC 0.4 VCC 0.6 VCC UNIT V DEVICE SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN Figure 10, Rs at 0 V tloop1 tloop2 tloop2 Total loop delay, driver input to receiver output, recessive to dominant Total loop delay, driver input to receiver output, dominant to recessive Total loop delay, driver input to receiver output, dominant to recessive TYP MAX 60 100 Figure 10, Rs with 10 k to ground 100 150 Figure 10, Rs with 100 k to ground 440 800 Figure 10, Rs at 0 V 115 150 Figure 10, Rs with 10 k to ground 235 290 Figure 10, Rs with 100 k to ground 1070 1450 105 145 Figure 10, Rs at 0 V, VCC from 4.5 V to 5.1 V, Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 Submit Documentation Feedback UNIT ns ns ns 5 SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION IO(CANH) VO(CANH) D VOD II IIRs Rs VI 60 W + 1% + VO(CANH) + VO(CANL) 2 VOC IO(CANL) VI(Rs) _ VO(CANL) Figure 1. Driver Voltage, Current, and Test Definition Dominant Recessive 93.5 V VO(CANH) 92.5 V 91.5 V VO(CANL) Figure 2. Bus Logic State Voltage Definitions CANH D VOD VI RNODE 60 W 1% + _ RS CANL -7 V VTEST 12 V RNODE Figure 3. Driver VOD 6 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 CANH D VI RL = 60 W 1% + VI(Rs) _ Rs (see Note A) CL = 50 pF 20% (see Note B) VO CANL VCC VCC/2 VI VCC/2 0V tPHL tPLH 0.9V VO 90% 10% tr VO(D) 0.5V VO(R) tf Figure 4. Driver Test Circuit and Voltage Waveforms CANH R VI(CANH) VI(CANH) + VI(CANL) VIC = 2 VI(CANL) IO VID VO CANL Figure 5. Receiver Voltage and Current Definitions CANH R VI CANL (see Note A) 1.5 V IO CL = 15 pF +20% (see Note B) VO 3.5 V VI 2.4 V 2V 1.5 V tPLH VO tPHL 0.7 VCC 10% 90% tr VOH 0.3 VCC 10% VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR 125 kHz, 50% duty cycle, tr 6ns, tf 6ns, ZO = 50. B. CL includes instrumentation and fixture capacitance within 20%. Figure 6. Receiver Test Circuit and Voltage Waveforms Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 Submit Documentation Feedback 7 SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com CANH R CANL 100 W Pulse Generator 15 ms Duration 1% Duty Cycle tr, tr 3 100 ns D at 0 V or VCC RS at 0 V or VCC A. This test is conducted to test survivability only. Data stability at the R output is not specified. Figure 7. Test Circuit, Transient Overvoltage Test Table 1. Receiver Characteristics Over Common Mode Voltage INPUT DIFFERENTIAL INPUT OUTPUT VCANH VCANL |VID| 12 V 11.1 V 900 mV L R -6.1 V -7 V 900 mV L -1 V -7 V 6V L 12 V 6V 6V L -6.5 V -7 V 500 mV H 12 V 11.5 V 500 mV H -7 V -1 V 6V H 6V 12 V 6V H open open X H VOL VOH DUT CANH 0V VI D 60 W 1% Rs CANL R + VO _ 15 pF 20% VCC 0.7 VCC VI 0V VOH 0.3 VCC VO ten 0.3 VCC VOL Figure 8. ten Test Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 CANH 27 W 1% D VI CANL 27 W 1% RS 50 pF 20% VOC VOC(PP) VOC A. The input pulse is supplied by a generator having the following characteristics: PRR 125 kHz, 50% duty cycle, tr 6ns, tf 6ns, ZO = 50. Figure 9. Peak-to-Peak Common Mode Output Voltage DUT CANH VI D 60 W + 1% 10 kW or 100 kW + 5% _ RS CANL VRs + R + VO _ 15 pF + 20% VCC 50% D Input 0V tLoop2 tLoop1 VOH 0.7 Vcc R Output 0.3 Vcc VOL Figure 10. tLOOP Test Circuit and Voltage Waveforms Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 Submit Documentation Feedback 9 SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com IOS 0 V or VCC CANH D CANL Rs Vin -7 V or 12 V JIOS(SS)J JIOS(P)J 15 s 0V 12 V Vin 0V 10 ms or 0V Vin -7 V Figure 11. Driver Short-Circuit Test CANH R VI (see Note A) CANL CL = 15 pF 1.5 V VO (see Note B) 3.5 V 2.4 V VI 1.5 V tp(sb) VOH VO 0.3 VCC VOL A. The input pulse is supplied by a generator having the following characteristics: PRR 125 kHz, 50% duty cycle, tr 6ns, tf 6ns, ZO = 50 . B. CL includes instrumentation and fixture capacitance within 20%. Figure 12. Receiver Propagation Delay in Standby Test Circuit and Waveform 10 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 DEVICE INFORMATION 5V R2+1% R1+1% CANH + R VID - CANL Vac R1+1% VI R2+1% VID R1 R2 500 mV 50 W 450 W 900 mV 50 W 227 W 12 V VI -7 V A. All input pulses are supplied by a generator having the following characteristics: fIN < 1.5 MHz, TA = 25C, VCC = 5 V. B. The receiver output should not change state during application of the common-mode input waveform. Figure 13. Common-Mode Input Voltage Rejection Test FUNCTION TABLES Table 2. DRIVER INPUTS D Voltage at Rs, VRs OUTPUTS CANH BUS STATE CANL L VRs < 1.2 V H L Dominant H VRs < 1.2 V Z Z Recessive Open X Z Z Recessive X VRs > 0.75 VCC Z Z Recessive X Open Z Z Recessive Table 3. RECEIVER (1) DIFFERENTIAL INPUTS [VID = V(CANH) - V(CANL)] OUTPUT R (1) VID 0.9 V L 0.5V < VID < 0.9 V ? VID 0.5 V H Open H H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 Submit Documentation Feedback 11 SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com D Input R Output Vcc Vcc 100 kW 1 kW 15 W Input Output 9V 9V CANL Input CANH Input Vcc 110 kW Vcc 110 kW 9 kW 45 kW 9 kW 45 kW Input Input 40 V 9 kW 40 V CANH and CANL Outputs 9 kW Rs Input Vcc Vcc Output 40 V + Input Figure 14. Equivalent Input and Output Schematic Diagrams 12 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 TYPICAL CHARACTERISTICS RECESSIVE-TO-DOMINANT LOOP DELAY vs FREE-AIR TEMPERATURE DOMINANT-TO-RECESSIVE LOOP DELAY vs FREE-AIR TEMPERATURE SUPPLY CURRENT (RMS) vs SIGNALING RATE 150 33 72 tLOOP2 - Loop Time - ns VCC = 4.5 V VCC = 5 V 70 68 66 VCC = 5.5 V VCC = 5.5 V VCC = 5 V 140 135 130 VCC = 4.5 V 64 125 62 -40 -25 -10 5 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C 31 30 29 28 27 26 25 0 35 50 65 80 95 110 125 250 500 750 1000 1250 1500 1750 2000 Signaling Rate - kbps Figure 15. Figure 16. Figure 17. DRIVER OUTPUT VOLTAGE vs OUTPUT CURRENT DRIVER DRIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT DOMINANT DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 4.5 VOD - Driver Differential Output Voltage - V 5 VOD - Driver Output Voltage - V VCC = 5 V, TA = 25C, RS = 0 V, RL = 60 , CL = 50 pF 32 TA - Free-Air Temperature - C 4.5 4 CANH 3.5 VCC = 5 V, TA = 25C, RS = 0 V, D at 0V 3 2.5 2 1.5 CANL 1 0.5 0 20 0 10 20 30 40 50 60 70 VCC = 5 V, TA = 25C, RS = 0 V, D at 0V 4 3.5 3 2.5 2 1.5 1 0.5 0 80 VOD(D) - Dominant Differential Output Voltage - V tLOOP1 - Loop Time - ns 145 ICC - RMS Supply Current - mA RS = 0 V RS = 0 V 74 0 IO - Driver Output Current - mA 10 20 30 40 50 60 70 80 IO - Driver Output Current - mA 3 VCC = 5.5 V 2.5 2 VCC = 4.5 V VCC = 5 V 1.5 1 RS = 0 V, D at 0V, RL = 60 0.5 0 -55 -40 0 25 70 85 125 TA - Free-Air Temperature - C Figure 18. Figure 19. Figure 20. DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE DIFFERENTIAL OUTPUT TRANSITION TIME vs SLOPE RESISTANCE (Rs) INPUT RESISTANCE MATCHING vs FREE-AIR TEMPERATURE 50 40 30 20 10 0 TA = 25C 900 800 VCC = 5.5 V VCC = 5 V 700 600 VCC = 4.5 V 500 400 300 200 Input Resistance Matching - % TA = 25C, RS = 0 V, D at 0V, RL = 60 tf - Differential Output Fall Time - ns IO - Driver Output Current - mA 0 1000 60 2 3 4 5 10 20 30 40 50 60 70 80 90 100 RS - Slope Resistance - kW VCC - Supply Voltage - V Figure 21. -1 -1.50 VCC = 5 V -2 VCC = 4.5 V -2.50 -3 0 6 VCC = 5.5 V 100 0 1 -0.50 Figure 22. Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 -50 0 50 100 150 TA - Free-Air Temperature - C Figure 23. Submit Documentation Feedback 13 SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com APPLICATION INFORMATION The basics of bus arbitration require that the receiver at the sending node designate the first bit as dominant or recessive after the initial wave of the first bit of a message travels to the most remote node on a network and back again. Typically, this sample is made at 75% of the bit width, and within this limitation, the maximum allowable signal distortion in a CAN network is determined by network electrical parameters. Factors to be considered in network design include the 5 ns/m propagation delay of typical twisted-pair bus cable; signal amplitude loss due to the loss mechanisms of the cable; and the number, length, and spacing of drop-lines (stubs) on a network. Under strict analysis, variations among the different oscillators in a system must also be accounted for with adjustments in signaling rate and stub & bus length. Table 4 lists the maximum signaling rates achieved with the SN65HVD251 in high-speed mode with several bus lengths of category-5, shielded twisted-pair (CAT 5 STP) cable. Table 4. Maximum Signaling Rates for Various Cable Lengths BUS LENGTH (m) SIGNALING RATE (kbps) 30 1000 100 500 250 250 500 125 1000 62.5 The ISO 11898 standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A bus with a large number of nodes requires a transceiver with high input impedance such as the HVD251. The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120- characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as short as possible to minimize signal reflections. Connectors, while not specified by the ISO 11898 standard, should have as little effect as possible on standard operating parameters such as capacitive loading. Although unshielded cable is used in many applications, data transmission circuits employing CAN transceivers are usually used in applications requiring a rugged interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these electronically harsh environments, and when coupled with the -2-V to 7-V common-mode range of tolerable ground noise specified in the standard, helps to ensure data integrity. The HVD251 extends data integrity beyond that of the standard with an extended -7-V to 12-V range of common-mode operation. NOISE MARGIN 900 mV Threshold RECEIVER DETECTION WINDOW 75% SAMPLE POINT 500 mV Threshold NOISE MARGIN ALLOWABLE JITTER Figure 24. Typical CAN Differential Signal Eye-Pattern 14 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 24, the differential signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all effects of systemic and random distortion, and displays the time during which a signal may be considered valid. The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a more effective representation of the jitter at the input of a receiver. As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a receiver. Different sources induce noise onto a signal. The more obvious noise sources are the components of a transmission circuit themselves; the signal transmitter, traces & cables, connectors, and the receiver. Beyond that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC and ground bounce, and electromagnetic interference from near-by electrical equipment. The balanced receiver inputs of the HVD251 mitigate most sources of signal corruption, and when used with a quality shielded twisted-pair cable, help meet data integrity. Typical Application Bus Lines - 40 m max CANH 120 120 Stub Lines -- 0.3 m max CANL Vref RS VCC 5V 0.1 F SN65HVD251 Vref RS VCC CANTX 0.1 F SN65HVD251 GND D 5V Vref RS VCC D CANRX CANTX R CANRX 0.1 F SN65HVD230 GND R 3.3 V GND D CANTX R CANRX TMS320F243 TMS320F243 TMS320LF2407A Sensor, Actuator, or Control Equipment Sensor, Actuator, or Control Equipment Sensor, Actuator, or Control Equipment Figure 25. Typical HVD251 Application Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 Submit Documentation Feedback 15 SN55HVD251 SN65HVD251 SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 www.ti.com REVISION HISTORY Changes from Original (November 2002) to Revision A * Page Changed multiple items within the document. ...................................................................................................................... 1 Changes from Revision A (September 2003) to Revision B Page * Changed the front page format. ............................................................................................................................................ 1 * Changed DESCRIPTION text From: and tolerance to transients of 50 V To: and tolerance to transients of 200 V ........ 1 Changes from Revision B (September 2003) to Revision C Page * Changed the front page format. ............................................................................................................................................ 1 * Added the SN65HVD251P Package option to the Ordering Information table. ................................................................... 2 * Changed the ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS table values ....................................................... 2 * Changed the THERMAL CHARACTERISTICS table values ................................................................................................ 3 * Changed Junction temperature, TJ - SOIC Package MAX value From 150C To: 145C ................................................... 3 Changes from Revision C (September 2005) to Revision D Page * Added device SN55HVD251 ................................................................................................................................................ 1 * Added the DRJ Package. ..................................................................................................................................................... 1 * Changed the data sheet title From: CAN TRANSCEIVER To: INDUSTRIAL CAN TRANSCEIVER ................................... 1 * Deleted APPLICATIONS bullets: DeviceNetTM Data Buses, Smart Distributed Systems (SDSTM), and ISO 11783 Standard Data Bus Interface ................................................................................................................................................ 1 * Deleted last paragraph from the DESCRIPTION - "The HVD251 may be used..." .............................................................. 1 * Added the SN55HVD251DRJ Package to the Ordering Information table. .......................................................................... 2 * Added Electrical fast transient/burst to the Abs Max Ratings table ...................................................................................... 2 * Changed table title From: ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS To: PACKAGE DISSIPATION RATINGS .............................................................................................................................................................................. 2 * Added the SON (DRJ) option to the PACKAGE DISSIPATION RATINGS table ................................................................. 2 * Added DRJ to the Junction-to-board thermal resistance ...................................................................................................... 3 * Added DRJ to the Junction-to-case thermal resistance ....................................................................................................... 3 * Deleted the condition - over recommended operating conditions (unless otherwise noted). From the RECOMMENDED OPERATING CONDITIONS table .......................................................................................................... 3 * Added SN55HVD251 to the Operating free-air temperature, TA in the ROC table .............................................................. 3 * Added the SUPPLY CURRENT table ................................................................................................................................... 3 * Deleted ICC - Supply current from the DRIVER ELECTRICAL CHARACTERISTICS ........................................................ 4 * Added T -40C to VO(D) Test Conditions in the DRIVER ELECTRICAL CHARACTERISTICS ......................................... 4 * Added RNODE = 330 to Differential output voltage (Dominant) (second line of Test Conditions) in the DRIVER ELECTRICAL table ............................................................................................................................................................... 4 * Added a third line of Test Conditions to Differential output voltage (Dominant) in the DRIVER ELECTRICAL table .......... 4 * Added T 85C to VOD(R) Test Conditions in the DRIVER ELECTRICAL CHARACTERISTICS ......................................... 4 * Added TYP values to the Differential output signal rise and fall times in the DRIVER SWITCHING CHARACTERISTIC table ...................................................................................................................................................... 4 * Deleted ICC - Supply current from the RECEIVER ELECTRICAL CHARACTERISTICS .................................................... 5 * Added Receiver noise rejection row to the RECEIVER ELECTRICAL CHARACTERISTIC table ....................................... 5 * Changed Figure 3 - Driver VOD, lable RNODE was 3301% ................................................................................................ 6 16 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 SN55HVD251 SN65HVD251 www.ti.com SLLS545E - NOVEMBER 2002 - REVISED MARCH 2010 * Changed Table 1 header From: MEASURED To: DIFFERENTIAL INPUT ......................................................................... 8 * Added Note B to Figure 13 ................................................................................................................................................. 11 * Added a row ( X Open) to Table 2 - Driver ......................................................................................................................... 11 * Changed Figure 15 title From: tLOOP1-LOOP TIME To: RECESSIVE-TO-DOMINANT LOOP DELAY .................................. 13 * Changed Figure 16 title From: tLOOP2-LOOP TIME To: DOMINANT-TO-RECESSIVE LOOP DELAY .................................. 13 * Changed Figure 18 From: DRIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE To: DRIVER OUTPUT VOLTAGE vs OUTPUT CURRENT ..................................................................................................... 13 * Changed Figure 19 From: DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE To: DRIVER DRIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT ........................................................................ 13 * Changed Figure 22 title From: DIFFERENTIAL OUTPUT FALL TIME To: DIFFERENTIAL OUTPUT TRANSITION TIME ................................................................................................................................................................................... 13 Changes from Revision D (February 2010) to Revision E * Page Deleted device number SN65HVD251DR, added the Temperature Range to the ORDERING INFORMATION table ....... 2 Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN55HVD251 SN65HVD251 Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN55HVD251DRJR ACTIVE SON DRJ 8 SN65HVD251D ACTIVE SOIC D 8 75 SN65HVD251DG4 ACTIVE SOIC D 8 75 SN65HVD251DR ACTIVE SOIC D SN65HVD251DRG4 ACTIVE SOIC SN65HVD251P ACTIVE SN65HVD251PE4 ACTIVE 1000 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN65HVD251 : * Automotive: SN65HVD251-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN55HVD251DRJR SON DRJ 8 1000 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 SN65HVD251DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN55HVD251DRJR SON DRJ 8 1000 210.0 185.0 35.0 SN65HVD251DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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