TPS54395RSAT - Texas Instruments

Input Voltage

PGND

SW1

VIN1

VBST1

EN1

VFB2

VFB1

GND VREG5

PGND1

VIN2

VBST2

EN2

SW2

SS1

SS2

PGND2

TPS54395

HTSSOP16

PGND

SGND SGND

C11

VO1

C21

R11

R21

L11 C31 C32 L12

C12

VO2

C22

R12

R22

SGND

C41 C42

SGND

Vout(50mV/div)

Iout(2A/div)

100 s/divm

TPS54395

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SLVSBC8A –JUNE 2012–REVISED MAY 2013

3A Dual Channel Synchronous Step-Down Switcher with Integrated FET

Check for Samples: TPS54395

1FEATURES APPLICATIONS

2• D-CAP2™ Control Mode • Point-of-Load Regulation in Low Power

Systems for Wide Range of Applications

– Fast Transient Response – Digital TV Power Supply

– No External Parts Required For Loop

Compensation – Networking Home Terminal

– Compatible with Ceramic Output – Digital Set Top Box (STB)

Capacitors – DVD Player/Recorder

• Wide Input Voltage Range : 4.5 V to 18 V – Gaming Consoles and Other

• Output Voltage Range : 0.76V to 7.0V DESCRIPTION

• Highly Efficient Integrated FETs Optimized for The TPS54395 is a dual, adaptive on-time D-CAP2™

Low Duty Cycle Applications mode synchronous buck converter. The TPS54395

– 90 mΩ(High Side) and 60 mΩ(Low Side) enables system designers to complete the suite of

• High Initial Reference Accuracy various end equipment’s power bus regulators with a

cost effective, low component count, and low standby

• Supports Constant 3A at Both Channels current solution. The main control loops of the

• Low-Side rDS(on) Loss-Less Current Sensing TPS54395 use the D-CAP2™ mode control which

• Adjustabel Soft Start provides a very fast transient response with no

• Non-Sinking Pre-Biased Soft Start external compensation components. The adaptive on-

time control supports seamless transition between

• 700 kHz Switching Frequency PWM mode at higher load conditions and Eco-

• Cycle-by-Cycle Over-Current Limit Control mode™ operation at light loads. Eco-mode™ allows

• OCL/UVLO/TSD Protections the TPS54395 to maintain high efficiency during

lighter load conditions. The TPS54395 is able to

• Hiccup Timer for Overload Protection adapt to both low equivalent series resistance (ESR)

• Adaptive Gate Drivers with Integrated Boost output capacitors such as POSCAP or SP-CAP, and

PMOS Switch ultra-low ESR, ceramic capacitors. The device

• OCP Constant Due To Thermally Compensated provides convenient and efficient operation with input

rDS(on) with 4000ppm/℃℃ voltages from 4.5V to 18V.

• 16-Pin HTSSOP, 16-Pin VQFN The TPS54395 is available in a 4.4 mm × 5 mm 16-

pin TSSOP (PWP) and 4 mm x 4 mm 16-pin VQFN

• Auto-Skip Eco-mode™　　for High Efficiency at (RSA) package, and is specified for an ambient

Light Load temperature range from –40°C to 85°C.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP2, Eco-mode, Eco-Mode are trademarks of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

TAPACKAGE(2) (3) ORDERING PART NUMBER PINS OUTPUT SUPPLY

TPS54395PWPR Tape-and-Reel

PWP 16

TPS54395PWP Tube

–40℃to 85℃TPS54395RSAR

RSA 16 Tape-and-Reel

TPS54395RSAT

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) All packaging options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)(1) (2)

VALUE UNIT

VIN1, VIN2, EN1, EN2 –0.3 to 20

VBST1, VBST2 –0.3 to 26

VBST1, VBST2 (10ns transient) –0.3 to 28

Input voltage range VBST1–SW1 , VBST2–SW2 –0.3 to 6.5 V

VFB1, VFB2 –0.3 to 6.5

SW1, SW2 –2 to 20

SW1, SW2 (10ns transient) –3 to 22

VREG5, SS1, SS2 –0.3 to 6.5

Output voltage range V

PGND1, PGND2 –0.3 to 0.3

Human Body Model (HBM) 2 kV

Electrostatic discharge Charged Device Model (CDM) 500 V

TAOperating ambient temperature range –40 to 85 °C

TSTG Storage temperature range –55 to 150 °C

TJJunction temperature range –40 to 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to IC GND terminal.

THERMAL INFORMATION TPS54395

THERMAL METRIC(1) UNITS

PWP (16) PINS PWP (16) PINS

θJA Junction-to-ambient thermal resistance 41.4 32.8

θJCtop Junction-to-case (top) thermal resistance 27.8 35.4

θJB Junction-to-board thermal resistance 23.2 9.9 °C/W

ψJT Junction-to-top characterization parameter 0.9 0.4

ψJB Junction-to-board characterization parameter 23.0 10.0

θJCbot Junction-to-case (bottom) thermal resistance 3.5 1.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Product Folder Links: TPS54395

TPS54395

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SLVSBC8A –JUNE 2012–REVISED MAY 2013

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted) VALUES UNIT

MIN MAX

Supply input voltage range VIN1, VIN2 4.5 18 V

VBST1, VBST2 –0.1 24

VBST1, VBST2 (10ns transient) –0.1 27

VBST1–SW1, VBST2–SW2 –0.1 5.7

Input voltage range VFB1, VFB2 –0.1 5.7 V

EN1, EN2 –0.1 18

SW1, SW2 –1.0 18

SW1, SW2 (10ns transient) –3 21

VREG5, SS1, SS2 –0.1 5.7

Output voltage range PGND1, PGND2 –0.1 0.1 V

VO1, VO2 0.76 7.0

TAOperating free-air temperature –40 85 °C

TJOperating Junction Temperature –40 150 °C

ELECTRICAL CHARACTERISTICS(1)

over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

TA= 25°C, EN1 = EN2 = 5 V,

IIN VIN supply current 1200 2000 µA

VFB1 = VFB2 = 0.8 V

IVINSDN VIN shutdown current TA= 25°C, EN1 = EN2 = L after H 15 20 µA

FEEDBACK VOLTAGE

VVFBTHLx VFBx threshold voltage TA= 25°C, CH1 = 3.3 V, CH2 = 1.5 V 758 765 773 mV

TCVFBx Temperature coefficient On the basis of 25°C(2) –115 115 ppm/℃

IVFBx VFBx Input Current VFBx = 0.8 V, TA= 25°C –0.4 0.2 0.4 µA

VREG5 OUTPUT

TA= 25°C, 6 V < VIN1 < 18 V,

VVREG5 VREG5 output voltage 5.5 V

IVREG = 5 mA

VIN1 = 6 V, VREG5 = 4.0 V,

IVREG5 Output current 75 mA

TA= 25°C(2)

MOSFETs

rDS(on)H High side switch resistance TA= 25℃, VBSTx-SWx = 5.5 V (2) 90 mΩ

rDS(on)L Low side switch resistance TA= 25℃(2) 60 mΩ

ON-TIME TIMER CONTROL

TON1 SW1 On Time SW1 = 12 V, VO1 = 1.2 V 165 ns

TON2 SW2 On Time SW2 = 12 V, VO2 = 1.2 V 165 ns

TOFF1 SW1 Min off time TA= 25℃, VFB1 = 0.7 V(2) 220 ns

TOFF2 SW2 Min off time TA= 25℃, VFB2 = 0.7 V(2) 220 ns

SOFT START

ISSC SSx charge current VSSx = 0.5 V, TA= 25℃–8.4 –8.0 –7.6 µA

TCISSC ISSC temperature coefficient On the basis of 25°C(2) –5 4 nA/°C

ISSD SSx discharge current VSSx = 0.5 V 3 7 10 mA

(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.

(2) Specified by design. Not production tested.

Product Folder Links: TPS54395

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

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ELECTRICAL CHARACTERISTICS(1) (continued)

over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

UVLO

VREG5 rising 3.83

VUVREG5 VREG5 UVLO threshold V

Hysteresis 0.6

LOGIC THRESHOLDs

VENxH ENx H-level threshold voltage 2.0 V

VENxL ENx L-level threshold voltage 0.4 V

RENx_IN ENx input resistance ENx = 12V 225 450 900 kΩ

CURRENT LIMITs

IOCLx Current limit LOUTx = 2.2 µH(3) 3.5 4.7 6.5 A

OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION (UVP, OVP)

VUVP Output UVP trip threshold measured on VFBx 63% 68% 73%

TUVPDEL Output UVP delay time 1.5 ms

TUVPEN Output UVP enable delay UVP enable delay / softstart time x 1.4 x 1.7 x 2.0

THERMAL SHUTDOWN

Shutdown temperature(3) 155

TSD Thermal shutdown threshold °C

Hysteresis(3) 25

(3) Specified by design. Not production tested.

Product Folder Links: TPS54395

SW1

VIN1

VBST 1

EN1

VFB2

VFB1

GND VREG5

PGND1

VIN2

VBST2

EN2

SW 2

SS1

SS2

PGND 2

TPS54395

HTSSOP16

PowerPAD

VFB1

VFB2

VIN1

SW2

VBST2

VBST1

EN1

75 6

PGND2

PGND1

SW1

VIN2

SS1

10 GND

SS2

EN2

16 15

VREG5

TPS54395

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SLVSBC8A –JUNE 2012–REVISED MAY 2013

DEVICE INFORMATION

HTSSOP PACKAGE RSA PACKAGE (TOP VIEW)

(TOP VIEW)

PIN FUNCTIONS(1)

PIN I/O DESCRIPTION

NAME PWP RSA

VIN1 1 3 I Power inputs and connects to both high side NFET drains.

Supply Input for 5.5V linear regulator.

VIN2 16 2 I

VBST1 2 4 I Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor

between VBSTx and SWx pins. An internal diode is connected between VREG5 and

VBST2 15 1 I VBSTx

SW1 3 5 I/O Switch node connections for both the high-side NFETs and low–side NFETs. Input of

current comparator.

SW2 14 16 I/O

PGND1 4 6 I/O Ground returns for low-side MOSFETs. Input of current comparator.

PGND2 13 15 I/O

EN1 5 7 I Enable. Pull High to enable according converter.

EN2 12 14 I

SS1 6 8 O Soft-Start Programming Pin. Connect Capacitor from SSx pin to GND to program Soft-

Start time.

SS2 11 13 O

VFB1 7 9 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.

VFB2 10 12 I

GND 8 10 I/O Signal GND. Connect sensitive SSx and VFBx returns to GND at a single point.

Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at

VREG5 9 11 O least 1.0 µF. VREG5 is active when ENx is high.

Exposed Thermal Back Back I/O Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must

Pad side side be connected to GND.

(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.

Product Folder Links: TPS54395

SW1

VBST1

EN1

VFB2

VFB1

GND

SS2

VREG5

PGND1

0. 1uF

VO1

1. 0 uF

VIN1

VBST2

EN2

SW2

VO2

0.1uF

VIN1

VIN2

5VREG

Logic

PGND2

SW2

EN Logic

UV1

Protection

Logic

Ref1

Ref2 SS2

SS1

UV2

UV1

UV2 UVLO

UVLO

SoftStart

REF

TSD

Ref1

Ref2

- 32

SS1

SS2

CSS1

CSS2

PGND1

PGND2

Err

Comp

Err

Comp

CH1 Min- off timer

CH2 Min- off timer

Ref_OCL

PGND2

VIN1

VIN2

OCP2 ZC2

SW2

SW1

Ref_OCL

OCP1 ZC1

SW1

PGND1

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

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FUNCTIONAL BLOCK DIAGRAM

Product Folder Links: TPS54395

C4x(nF) VFBx(V) C4x(nF) 0.765 V

T (ms) = =

I ( A) 8 A

´ ´

m m

( )

INx Ox Ox

Ox(LL)

SW INx

V V V

I = 2 L1x V

- ´

´ ´ f

TPS54395

www.ti.com

SLVSBC8A –JUNE 2012–REVISED MAY 2013

OVERVIEW

The TPS54395 is a 3A/3A dual synchronous step-down (buck) converter with two integrated N-channel

MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™

control reduces the required output capacitance to meet a specific level of performance. Proprietary internal

circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS54395 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an

internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal

timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a

pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset

and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.

An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR

induced output ripple from D-CAP™ control.

PWM Frequency and Adaptive On-Time Control

TPS54395 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS54395 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set

the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,

therefore, when the duty ratio is VOx/VINx, the frequency is constant.

Auto-Skip Eco-Mode™ Control

The TPS54395 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current

decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where

its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous

conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load

current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the

same as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with

smaller load current to the nominal output voltage. The transition point to the light load operation IOx(LL) current

can be estimated with Equation 1 with 700-kHz used as fSW.

(1)

Soft Start and Pre-Biased Soft Start

The soft start time is adjustable. When the ENx pin becomes high, 8-µA current begins charging the capacitor

which is connected from the SSx pin to GND. Smooth control of the output voltage is maintained during start up.

The equation for the slow start time is shown in Equation 2. VFBx voltage is 0.765-V and SSx pin source current

is 8-µA.

(2)

The TPS54395 contains a unique circuit to prevent current from being pulled from the output during startup if the

output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start

becomes greater than internal feedback voltage VFBx), the controller slowly activates synchronous rectification

by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a

cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.

This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx)

starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.

Product Folder Links: TPS54395

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

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Current Sensing and Over-Current Protection

The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit.

The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx

pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the

measurement accuracy, the voltage sensing is temperature compensated.

During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx,

VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current

decreases linearly. The average value of the switch current is the load current IOx. If the sensed voltage on the

low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on

until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle

begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is

monitored in the same manner.

Important considerations for this type of over-current protection: The load current is one half of the peak-to-peak

inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage

tends to fall as the demanded load current may be higher than the current available from the converter. When

the over current condition is removed, the output voltage returns to the regulated value. This protection is non-

latching.

Undervoltage Protection and Hiccup Mode

Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition.

If the OCL comparator circuit detects an over-current event the output voltage falls. When the feedback voltage

falls below 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay

counter begins counting. After counting UVP delay time, the TPS54395 shuts off the power supply for a given

time (7x UVP Enable Delay Time) and then tries to re-start the power supply. If the over-load condition has been

removed, the power supply starts and operates normally; otherwise, the TPS54395 detects another over-current

event and shuts off the power supply again, repeating the previous cycle. Excess heat due to overload lasts for

only a short duration in the hiccup cycle, therefore the junction temperature of the power device is much lower.

UVLO Protection

Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower

than the UVLO threshold, the TPS54395 shuts down. As soon as the voltage increases above the UVLO

threshold, the converter starts again.

Thermal Shutdown

TPS54395 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the device

shuts down. When the temperature falls below the threshold, the IC starts again.

When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is

lower than 155°C. As long as VIN1 rises, TJmust be kept below 110°C.

Product Folder Links: TPS54395

0 2 4 6 8 10 12 14 16 18 20

V - Input Voltage - V

3.2

3.22

3.24

3.26

3.28

3.3

3.32

3.34

3.36

3.38

3.4

V - Output Voltage - V

I = 10 mA

I = 1 A

V = 18 V

0 0.5 1 1.5 2 2.5 3

I - Output Current - A

1.45

1.46

1.47

1.48

1.49

1.5

1.51

1.52

1.53

1.54

1.55

V - Output Voltage - V

V = 12 V

V = 5 V

0 0.5 1 1.5 2 2.5 3

I - Output Current - A

3.2

3.22

3.24

3.26

3.28

3.3

3.32

3.34

3.36

3.38

3.4

V - Output Voltage - V

V = 6 V

V = 12 V

V = 18 V

EN Input Current - Am

0 5 10 15 20

EN Input Voltage - V

EN1

EN2

-50 0 50 100 150

T - Junction Temperature - °C

200

400

600

800

1000

1200

1400

1600

1800

2000

I - Supply Current - A

CC m

VIN1 = VIN2 = 12 V,

EN1 = EN2 = ON

IIN

-50 0 50 100 150

T - Junction Temperature - °C

Ivccsdn - Shutdown Current - Am

IVINSDN

TPS54395

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SLVSBC8A –JUNE 2012–REVISED MAY 2013

TYPICAL CHARACTERISTICS

One output is enabled unless otherwise noted. VI= VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).

Figure 1. Input Current vs Junction Temperature Figure 2. Input Shutdown Current vs Junction Temperature

Figure 3. EN Current vs EN Voltage (VEN=12V) Figure 4. VO1=3.3V Output Voltage vs Output Current

Figure 5. VO2=1.5V Output Voltage vs Output Current Figure 6. VO1=3.3V Output Voltage vs Input Voltage

Product Folder Links: TPS54395

Vout2(0.5V/div)

400 s/divm

SS2(2V/div)

EN2(10V/div)

100

Efficiency - %

0 0.5 1 1.5 2 2.5 3

I - Output Current - A

V = 6 V

V = 18 V

V = 12 V

Vout(50mV/div)

100 s/divm

Iout(2A/div)

Vout(1V/div)

SS1(2V/div)

400 s/divm

EN1(10V/div)

1.45

1.46

1.47

1.48

1.49

1.5

1.51

1.52

1.53

1.54

1.55

V - Output Voltage - V

0 2 4 6 8 10 12 14 16 18 20

V - Input Voltage - V

I = 10 mA

I = 1 A

Iout(2A/div)

100 s/divm

Vout(50mV/div)

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

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TYPICAL CHARACTERISTICS (continued)

One output is enabled unless otherwise noted. VI= VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).

Figure 7. VO2=1.5V Output Voltage vs Input Voltage Figure 8. VO1=3.3V, 0A to 3A Load Transient Response

Figure 9. VO2=1.5V, 0A to 3A Load Transient Response Figure 10. VO1=3.3V, SoftStart

Figure 11. VO2=1.5V, SoftStart Figure 12. VO1=3.3V, Efficiency vs Output Current

Product Folder Links: TPS54395

I = 1 A

0 2 4 6 8 10 12 14 16 18 20

V - Input Voltage - V

400

450

500

550

600

650

700

750

800

fsw - Switching Frequency - kHz

0.01 0.1 1 10

I - Output Current - A

100

200

300

400

500

600

700

800

fsw - Switching Frequency - kHz

V = 12 V

0 2 4 6 8 10 12 14 16 18 20

V - Input Voltage - V

400

450

500

550

600

650

700

750

800

fsw - Switching Frequency - kHz

I = 1 A

100

Efficiency - %

0.001 0.1 10

I - Output Current - A

0.01 1

V = 6 V

V = 12 V

V = 18 V

100

Efficiency - %

0.001 0.1 10

I - Output Current - A

V = 6 V

V = 12 V

V = 18 V

0.01 1

100

Efficiency - %

0 0.5 1 1.5 2 2.5 3

I - Output Current - A

V = 5 V

V = 12 V

V = 18 V

TPS54395

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SLVSBC8A –JUNE 2012–REVISED MAY 2013

TYPICAL CHARACTERISTICS (continued)

One output is enabled unless otherwise noted. VI= VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).

Figure 13. VO1=3.3V, Efficiency vs Output Current Figure 14. VO2=1.5V, Efficiency vs Output Current

Figure 15. VO2=1.5V, Efficiency vs Output Current Figure 16. VO1=3.3V, SW-frequency vs Input Voltage

Figure 17. VO2=1.5V, SW-frequency vs Input Voltage Figure 18. VO1=3.3V, SW-frequency vs Output Current

Product Folder Links: TPS54395

VIN2(50mV/div)

SW2(5V/div)

V = 1.5 V

VIN1(50mV/div)

SW1(5V/div)

V = 3.3 V

V 2(10mV/div)O

SW2(5V/div)

V = 1.5 V

100

200

300

400

500

600

700

800

fsw - Switching Frequency - kHz

0.01 0.1 1 10

I - Output Current - A

V = 12 V

V 1(10mV/div)

SW1(5V/div)

V = 3.3 V

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

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TYPICAL CHARACTERISTICS (continued)

One output is enabled unless otherwise noted. VI= VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).

Figure 19. VO2=1.5V, SW-frequency vs Output Current Figure 20. VO1=3.3V, VO1 Ripple Voltage (IO1= 3A)

Figure 21. VO2=1.5V, Ripple Voltage (IO2= 3A) Figure 22. VIN1 Input Voltage Ripple (IO1= 3A)

Figure 23. VIN2 Input Voltage Ripple (IO2= 3A)

Product Folder Links: TPS54395

F =

2 L1x C1x´p

R1x

V = 0.765 V 1+

R2x

æ ö

´ç ÷

è ø

VINx

12V ± 10%

PGND

SW1

VIN1

VBST1

EN1

VFB2

VFB1

GND VREG5

PGND1

VIN2

VBST2

EN2

SW2

SS1

SS2

PGND2

TPS54395

HTSSOP16

PGND

SGND SGND

C11

10 Fm

VO1

3.3 V

C21

22 F

R11

73.2 kW

R21

22.1 kW

L11

2.2 HmC31

0.1 Fm

C32

0.1 Fm

L12

1.5 Hm

C12

10 FmVO2

1.5 V

C22

22 F

R12

21.5 kW

R22

22.1 kW

SGND

C41 C42

SGND

TPS54395

www.ti.com

SLVSBC8A –JUNE 2012–REVISED MAY 2013

DESIGN GUIDE

Step By Step Design Procedure

To begin the design process, you must know a few application parameters:

• Input voltage range

• Output voltage

• Output current

In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated

switching frequency of 700 kHz is used.

Figure 24. Schematic Diagram for the Design Example

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use

1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOx.

To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values

will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable.

(3)

Output Filter Selection

The output filter used with the TPS54395 is an LC circuit. This LC filter has double pole at:

(4)

Product Folder Links: TPS54395

( )

Ox INx Ox

C2x(RMS)

INx SW

V V V

I = 12 V L1x

´ -

´ ´ ´ f

2 2

L1x(RMS) Ox L1x

I I I

= + D

L1x

L1xpeak Ox

ΔI

I = I + 2

INx(MAX) Ox

L1x

INx(MAX) SW

V V

ΔI = V L1x

´f

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

www.ti.com

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal

gain of the TPS54395. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls

off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that

reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the

zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole

of Equation 4 is located below the high frequency zero but close enough that the phase boost provided by the

high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the

values recommended in Table 1.

Table 1. Recommended Component Values

Output Voltage (V) R1x (kΩ) R2x (kΩ) Cffx (pF)(1) L1x (µH) C2x (µF)

1 6.81 22.1 1.5 - 2.2 20 - 68

1.05 8.25 22.1 1.5 - 2.2 20 - 68

1.2 12.7 22.1 1.5 - 2.2 20 - 68

1.5 21.5 22.1 1.5 - 2.2 20 - 68

1.8 30.1 22.1 5 - 22 2.2 - 3.3 20 - 68

2.5 49.9 22.1 5 - 22 2.2 - 3.3 20 - 68

3.3 73.2 22.1 5 - 22 2.2 - 3.3 20 - 68

5 124 22.1 5 - 22 4.7 20 - 68

6.5 165 22.1 5 - 22 4.7 20 - 68

(1) Optional

For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward

capacitor (Cffx) in parallel with R1x.

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,

Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak

current and the RMS or heating current rating must be greater than the calculated RMS current.

For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the

peak current of Equation 6 and the RMS current of Equation 7.

(5)

(6)

(7)

For the above design example, the calculated peak current is 3.46 A and the calculated RMS current is 3.01 A

for VO2. The inductor used is a TDK CLF7045T-2R2N with a rated current of 5.5A based on the inductance

change, and of 4.3A based on the temperature rise.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS54395 is intended for use

with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use Equation 8

to determine the required RMS current rating for the output capacitor(s).

(8)

For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩeach.

The calculated RMS current is 0.19A and each output capacitor is rated for 4A.

Product Folder Links: TPS54395

TPS54395

www.ti.com

SLVSBC8A –JUNE 2012–REVISED MAY 2013

Input Capacitor Selection

The TPS54395 requires an input decoupling capacitor and a bulk capacitor is needed depending on the

application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1

µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the

SWx node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage.

Bootstrap Capacitor Selection

A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is

recommended to use ceramic capacitors with a dielectric of X5R or better.

VREG5 Capacitor Selection

A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is

recommended to use a ceramic capacitor with a dielectric of X5R or better.

Thermal Information

This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to

the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of

thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical

schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.

This design optimizes the heat transfer from the integrated circuit (IC).

For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating

abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature

No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.

The exposed thermal pad dimensions for this package are shown in the following illustration.

Figure 25. Thermal Pad Dimensions

Layout Considerations

1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal

pad.

2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and

inductance and to minimize radiated emissions.

3. Keep analog and non-switching components away from switching components.

4. Make a single point connection from the signal ground to power ground.

5. Do not allow switching currents to flow under the device.

6. Keep the pattern lines for VINx and PGNDx broad.

Product Folder Links: TPS54395

SW1

VIN1

VBST1

EN1

VFB1

GND VREG 5

PGND1

VIN2

VBST2

EN2

SW2

SS1

PGND2

VFB2

VIN2

BIAS

CAP

VIN HIGH

FREQUENCY

BYPASS

CAPACITOR

～0.1µF

VIN INPUT

BYPASS

CAPACITOR

10µF x2

OUTPUT

INDUCTOR

OUTPUT

FILTER

CAPACITOR

POWER GND

TO ENABLE

CONTROL

Keep

distance more

than 1inch

Recommend to keep

distance more than 3-4mm.

(to avoid noise scattering,

especially GND plane.)

To feedback

resisters

VO2

Feedback

resisters

GND

PLANE

2,3 or bottom

layer

Symmetrical Layout

for CH1 and CH2

Switching noise

flows through IC

and CIN . It avoids

the thermal Pad.

Via to GND Plane

- Blue parts can be placed on the bottom side

- Connect the SWx pins through another layer with the inductor

(yellow line)

SS2

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

www.ti.com

7. Exposed pad of device must be soldered to PGND.

8. VREG5 capacitor should be placed near the device, and connected to GND.

9. Output capacitors should be connected with a broad pattern to the PGND.

10. Voltage feedback loops should be as short as possible, and preferably with ground shields.

11. Kelvin connections should be brought from the output to the feedback pin of the device.

12. Providing sufficient vias is preferable for VIN, SW and PGND connections.

13. PCB pattern for VIN, SW, and PGND should be as broad as possible.

14. VIN Capacitor should be placed as near as possible to the device.

Figure 26. TPS54395 Layout

Product Folder Links: TPS54395

EXPOSED THERMAL

PAD AREA

BOOST

CAPACITOR

VOUT2

VIA to Internal or

Bottom Layer Ground Plane

OUTPUT2

INDUCTOR

OUTPUT2

FILTER

CAPACITORS

TO POWER

GOOD PULL

UP 2

ANALOG

GROUND

TRACE

VIN INPUT

BYPASS

CAPACITORS

VIN

FEEDBACK

RESISTORS

Etch on Bottom Layer,

Internal Layer or

Under Component

BIAS

CAP

VIN HIGH

FREQUENCY

BYPASS

CAPACITOR

VBST1

SW1 SW2

VIN1

VIN2

VFB1

VREG5

GND

PG2

EN2

PGND2

PGND1

14 13

VFB2

VBST2

E 1N

PG1

TO ENABLE

CONTROL

BOOST

CAPACITOR

OUTPUT1

INDUCTOR

OUTPUT1

FILTER

CAPACITORS

VIN INPUT

BYPASS

CAPACITORS

FEEDBACK

RESISTORS

POWER

GROUND

VIN HIGH

FREQUENCY

BYPASS

CAPACITOR

KEEP

VIAS > 3-4 mm

FROM OUTPUT

CAPACITORS

KEEP OUTPUT

VIAS > 25 mm

FROM INPUT VIAS

KEEP

VIAS > 3-4 mm

FROM INPUT

CAPACITORS

NOTE: IT IS POSSIBLE TO PLACE

SOME COMPONENTS SUCH AS

BOOST CAPACITOR AND FEEDBACK

RESISTORS ON BOTTOM LAYER

VOUT1

TO ENABLE

CONTROL

POWER

GROUND

KEEP

VIAS > 3-4 mm

FROM OUTPUT

CAPACITORS

KEEP OUTPUT

VIAS > 25 mm

FROM INPUT VIAS

KEEP

VIAS > 3-4 mm

FROM INPUT

CAPACITORS

Internal or Bottom

Layer Ground Plane

VIA to internal or

Bottom Layer Etch

Etch or Copper Fill

on Top Layer

INTERNAL OR

BOTTOM LAYER

GROUND PLANE

TO POWER

GOOD PULL

UP 1

TPS54395

www.ti.com

SLVSBC8A –JUNE 2012–REVISED MAY 2013

Figure 27. RSA Package Layout

Product Folder Links: TPS54395

TPS54395

SLVSBC8A –JUNE 2012–REVISED MAY 2013

www.ti.com

REVISION HISTORY

Changes from Original (June 2012) to Revision A Page

• Added 16-pin VQFN to the Features and Description .......................................................................................................... 1

• Added the 16-pin package to the Ordering Information table ............................................................................................... 2

• Added the RSA package to the Thermal Information table .................................................................................................. 2

• Added the RSA 16 pin package pinout image, pin names and functions to the DEVICE INFORMATION section ............. 5

• Added Figure 27 ................................................................................................................................................................. 17

Product Folder Links: TPS54395

PACKAGE OPTION ADDENDUM

www.ti.com 4-Jul-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS54395PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54395

TPS54395PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54395

TPS54395RSAR ACTIVE QFN RSA 16 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS

54395

TPS54395RSAT ACTIVE QFN RSA 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS

54395

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 4-Jul-2013

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS54395PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TPS54395RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TPS54395RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS54395PWPR HTSSOP PWP 16 2000 367.0 367.0 38.0

TPS54395RSAR QFN RSA 16 3000 367.0 367.0 35.0

TPS54395RSAT QFN RSA 16 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

14X 0.65

4.55

16X 0.30

0.19

TYP

6.6

6.2

0.15

0.05

0.25

GAGE PLANE

-80

1.2 MAX

3.55

2.68

2.46

1.75

B4.5

4.3

NOTE 3

5.1

4.9

0.75

0.50

(0.15) TYP

PowerPAD TSSOP - 1.2 mm max heightPWP0016J

SMALL OUTLINE PACKAGE

4223595/A 03/2017

0.1 C A B

PIN 1 INDEX

AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

SEATING

PLANE

PowerPAD is a trademark of Texas Instruments.

A 20

DETAIL A

TYPICAL

SCALE 2.500

THERMAL

PAD

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

(3.4)

NOTE 8

(5)

NOTE 8

(1.35) TYP

(0.65)

(1.3) TYP

( 0.2) TYP

VIA

(2.46)

(3.55)

PowerPAD TSSOP - 1.2 mm max heightPWP0016J

SMALL OUTLINE PACKAGE

4223595/A 03/2017

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

8. Size of metal pad may vary due to creepage requirement.

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

SEE DETAILS

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

(3.55)

BASED ON

0.125 THICK

STENCIL

(2.46)

BASED ON

0.125 THICK

STENCIL

PowerPAD TSSOP - 1.2 mm max heightPWP0016J

SMALL OUTLINE PACKAGE

4223595/A 03/2017

2.08 X 3.000.175 2.25 X 3.240.15 2.46 X 3.55 (SHOWN)0.125 2.75 X 3.970.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

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Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

TPS54395PWP TPS54395PWPR TPS54395RSAT TPS54395RSAR