Freescale Semiconductor
Data Sheet Document Number: MSC7116
Rev. 13, 4/2008
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
MSC7116
MAP-BGA–400
17 mm ×17 mm
•StarCore
® SC1400 DSP extended core with one SC1400 DSP
cor e, 192 Kb yte of i nternal SRAM M1 me mory, 16 wa y 16 Kbyte
instruction cache (ICache), four-entry write buffer , programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
• 192 Kbyte M2 memory for critical data and temporary data
buffering.
• 8 Kbyt e boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
between fou r mast er ports and six slave p ort s, where each port
connec ts to an AHB-Lite bus; fixed or round robi n priority
programmab le at each slave port; programmable bus parki ng at
each slave port; low power mode.
• Inte rnal PLL g enerate s up to 266 MHz clock for the S C1400 core
and up to 133 MHz for t he crossbar switch, DMA channels, M2
memory, and other periph erals.
• Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
• DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 133 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
• Progra mmable mem ory interfa ce with ind e pend e nt read buffers,
programmable predictive read feature for each buffer , and a write
buffer.
• System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite maste r buses; and has address
out-of-range detection on each crossbar switch buses.
• Event port collects and counts important signal events including
DMA and interrupt requests an d trigger events su ch as interrupts,
breakpoints, DMA t ransfers, or wake-up ev ents; units ope rate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
• Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between chann el s using 32 interna l prio rity level s, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
• Two independent TDM modules with independent receive and
transmit, programmable sharing of frame sync and cloc k,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 cha nnels, with gl ueles s interfa ce to E1/T1 fr ames and MV IP,
SCAS, and H.110 buses.
• Ethernet controller with support for 10/100 Mbps MII/RMII
designed to comply with IEEE Std. 80 2.3™, 802.3u™, 802.3x™,
and 802. 3ac™; with internal receive and transmit FIFOs and a
FIFO controller; direct access to internal memories via its own
DMA controller; full and half duplex operation; programmable
maximum frame length; virtual l ocal area network ( VLAN) tag
and priority support; retransmission of transmit FIFO following
collision; CRC generation and verification for inbound and
outbo und packets; and ad dress recognition i ncluding
promiscuous, broadcast, individual address. hash/exact match,
and multicast ha sh matc h.
• UART with full-du pl ex oper atio n up to 5 .0 Mb ps.
• Up to 41 general-purpose input/output (GPIO) ports.
•I
2C interface that allows booting from EEPROM devices up to 1
Mbyte.
• Two quad timer modules, each with sixteen configurable 16-bit
timers.
• fieldBIST™ u nit detects and p rovides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated sp eed, is free from
reliability de fec ts, a n d r eport s di agno stic s fo r part ia l o r com p lete
device ino per ab ility.
• Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
• Optional booti ng external host via 8-bit or 16-bit access through
the HDI16, I2C, or SPI using in the boot ROM to access serial SPI
Flash /E EPROM devices; different clocking opt ions during boot
with the PLL on or off using a variety of input frequency ranges.
Low-Cost 16-bit DSP with
DDR Contr oller an d 10 /1 00
Mbps Ethernet MAC
MSC7116 Data Sheet, Rev. 13
Freesca le Sem ico nd uctor2
Table of Contents
1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 MAP-BGA Ball La you t Diagrams . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location . . . . . . . . . . . . . . . . . . . . . . .6
2 Ele c t r i c a l C h a ra c t e r i s t i c s . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Max imum Ra ting s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19
2.4 DC Electrical Chara c te ristics . . . . . . . . . . . . . . . . . . . .19
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .41
3.1 Thermal Desig n Consid e r a tions . . . . . . . . . . . . . . . . . .41
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .42
3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .49
3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.5 DDR Memory System Guidelines. . . . . . . . . . . . . . . . .54
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6 Pro duct D o c u ment a ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
7 Revisio n History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
List of Figures
Figure 1. MSC 7 116 Blo c k Diagr a m. . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. MSC7116 Molded Array Proces s-B all Grid Array
(MAP-BGA), To p Vie w . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. MSC7116 Molded Array Proces s-B all Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Timing Diagram for a Reset Configuration Write . . . . 25
Figure 5. DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26
Figure 6. DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27
Figure 7. DDR DRAM AC Test Load. . . . . . . . . . . . . . . . . . . . . 28
Figure 8. TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Ethernet Receive Signal Timing. . . . . . . . . . . . . . . . . 29
Figure 11. Ethernet Receive Signal Timing. . . . . . . . . . . . . . . . . 30
Figure 12. Asynchronous Input Signal Timing. . . . . . . . . . . . . . . 30
Figure 13. Serial Management Channel T iming . . . . . . . . . . . . . 31
Figure 14. Read Timing Diagram, Single Data Strobe . . . . . . . . 33
Figure 15. Read Timing Diagram, Double Data Strobe. . . . . . . . 33
Figure 16. Write Timing Diagram, Single Data Strobe. . . . . . . . . 34
Figure 17. Write Timing Diagram, Double Data Strobe. . . . . . . . 34
Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0. . 35
Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 35
Figure 20. I2C Timin g Diagr a m . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. UART Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 24. EVNT Pin T i ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25. GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26. Test Clock Input Ti ming Diagram . . . . . . . . . . . . . . . . 39
Figure 27. Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 40
Figure 28. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 40
Figure 29. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30. Voltage Sequencing Case 1. . . . . . . . . . . . . . . . . . . . 43
Figure 31. Voltage Sequencing Case 2. . . . . . . . . . . . . . . . . . . . 44
Figure 32. Voltage Sequencing Case 3. . . . . . . . . . . . . . . . . . . . 45
Figure 33. Voltage Sequencing Case 4. . . . . . . . . . . . . . . . . . . . 46
Figure 34. Voltage Sequencing Case 5. . . . . . . . . . . . . . . . . . . . 47
Figure 35. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 48
Figure 36. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 54
Figure 37. SSTL Power Value. . . . . . . . . . . . . . . . . . . . . . . . . . . 55
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 3
Figure 1. MSC7116 Block Diagram
MUX
Boot ROM
(8 KB)
RS-232
APB
APB Bridge
64
UART
External
Memory
M2
SRAM
Interrupts
Interrupt Control
HDI16
32
Host
Interface
(HDI16)
External Bus
Timers
2 TDMs
DSP
Extended
Note: The arrows show the
Interface
Port
32
128
32
(192 KB)
SC1400
Core
Cache
Instruction
(16 KB)
Extended
Core
Interface
Unit
Fetch
M1
SRAM
(192 KB)
64
64
128
64
64
AHB-Lite Crossbar Switch
TDM
PXAXB
128 64
64
PLL/Clock
PLL/Clock
128
64
128
MUX
OCE10
Trace
Buffer
(8 KB)
to/fr o m OCE10
IB Bridge
32 Events
32
IPBus
to DMA
to EMI
Core
AMIC
AMEC
ASM1
ASM2
ASEMI
ASTH
ASAPB
from
IPBus
I2C
I2C
Watchdog
Event Port
BTMs
ASIB
GPIO
GPIO
Ethernet
MAC
AMENT
64
MII/RMII
direction of the transfer.
DMA
(32 Channel)
64
JTAG
JTAG Port AMDMA
to IPBu s
System Ctrl
MSC7116 Data Sheet, Rev. 13
Pin Assignments
Freesca le Sem ico nd uctor4
1 Pin Assignments
This section includes diagrams of the MSC711 6 package ball grid array layouts an d pinout allocation tables.
1.1 MAP-BGA Ball Layout Diagrams
Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location in dex num bers.
Figure 2. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
1234567891011121314151617181920
A GND GND DQM1 DQS2 CK CK HD15 HD12 HD10 HD7 HD6 HD4 HD1 HD0 GND BM3 NC NC NC NC
BVDDM NC CS0 DQM2 DQS3 DQS0 CKE WE HD14 HD11 HD8 HD5 HD2 NC BM2 NC NC NC NC NC
C D24 D30 D25 CS1 DQM3 DQM0 DQS1 RAS CAS HD13HD9HD3NCNCNCNCNCNCNCNC
DVDDM D28 D27 GND VDDM VDDM VDDM VDDM VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDC NC NC NC
E GND D26 D31 VDDM VDDM VDDC VDDC VDDC VDDC VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDC VDDC NC NC NC
FVDDM D15 D29 VDDC VDDC VDDC GND GND GND VDDM VDDM GND GND GND VDDIO VDDC VDDC NC NC NC
G GND D13 GND VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC NC NC
HD14D12D11
VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC HA2 HA1
JD10
VDDM D9 VDDM VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDC HA3 HACK HREQ
K D0 GND D8 VDDC VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC HA0 HDDS HDS
L D1 GND D3 VDDC VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDIO VDDC HCS2 HCS1 HRW
MD2
VDDM D5 VDDM VDDM GND GND GND GND GND GND GND GND GND GND VDDC VDDC SDA UTXD URXD
ND4D6
VREF VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDC VDDC CLKIN SCL VSSPLL
PD7D17D16
VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC PORESET TPSEL VDDPLL
R GND D19 D18 VDDM VDDM VDDM GND VDDM GND VDDM GND GND VDDIO GND VDDIO VDDIO VDDC TDO EE0 TEST0
TVDDM D20 D22 VDDM VDDM VDDC VDDM VDDM VDDC VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDC VDDC MDIO TMS HRESET
U GND D21 D23 VDDM VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC COL TCK TRST
VVDDM NC A13 A11 A10 A5 A2 BA0 NC EVNT0 EVNT4 T0TCK T1RFS T1TD TX_ER RXD2 RXD0 TX_EN CRS TDI
WGND
VDDM A12 A8 A7 A6 A3 NC EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER MDC
YVDDM GNDA9A1A0A4BA1NMIEVNT3 T0RCK T0RD TOTD T1RCK T1TCK TXD3 RXCLK TXD0 RXD1 GND RX_DV
Top View
Pin Assignments
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 5
Figure 3. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A NC NC NC NC BM3 GND HD0 HD1 HD4 HD6 HD7 HD10 HD12 HD15 CK CK DQS2 DQM1 GND GND
B NC NC NC NC NC BM2 NC HD2 HD5 HD8 HD11 HD14 WE CKE DQS0 DQS3 DQM2 CS0 NC VDDM
C NCNCNCNCNCNCNCNCHD3HD9HD13CASRAS DQS1 DQM0 DQM3 CS1 D25 D30 D24
D NCNCNCVDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDDM VDDM VDDM VDDM GND D27 D28 VDDM
E NCNCNCVDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDD VDD VDD VDD VDDM VDDM D31 D26 GND
F NCNCNCVDD VDD VDDIO GND GND GND VDDM VDDM GND GND GND VDD VDD VDD D29 D15 VDDM
G NCNCNCVDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM GND D13 GND
HHA1HA2NC
VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM D11 D12 D14
J HREQ HACK HA3 VDD VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM VDDM D9 VDDM D10
KHDS
HDDS HA0 VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDD D8 GND D0
L HRW HCS1 HCS2 VDD VDDIO VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDD D3 GND D1
MURXDUTXDSDAVDD VDD GND GND GND GND GND GND GND GND GND GND VDDM VDDM D5 VDDM D2
NVSSPLL SCL CLKIN VDD VDD VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM VREF D6 D4
PVDDPLL TPSEL PORESET VDD VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM D16 D17 D7
R TEST0 EE0 TDO VDD VDDIO VDDIO GND VDDIO GND GND VDDM GND VDDM GND VDDM VDDM VDDM D18 D19 GND
THRESET TMS MDIO VDD VDD VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDD VDDM VDDM VDD VDDM VDDM D22 D20 VDDM
UTRSTTCK COL VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDM D23 D21 GND
V TDI CRS TX_EN RXD0 RXD2 TX_ER T1TD T1RFS T0TCK EVNT4 EVNT0 NC BA0 A2 A5 A10 A11 A13 NC VDDM
W MDC RX_ER TXCLK TXD1 RXD3 TXD2 T1TFS T1RD T0TFS T0RFS EVNT2 EVNT1 NC A3 A6 A7 A8 A12 VDDM GND
Y RX_DV GND RXD1 TXD0 RXCLK TXD3 T1TCK T1RCK TOTD T0RD T0RCK EVNT3 NMI BA1A4A0A1A9GND
VDDM
Bottom View
MSC7116 Data Sheet, Rev. 13
Pin Assignments
Freesca le Sem ico nd uctor6
1.2 Signal List By Ball Location
Table 1 lists the signals sorted by ball number and conf iguration.
Table 1. MSC7116 Signals by Ball Designator
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
A1 GND
A2 GND
A3 DQM1
A4 DQS2
A5 CK
A6 CK
A7 GPIC7 GPOC7 HD15
A8 GPIC4 GPOC4 HD12
A9 GPIC2 GPOC2 HD10
A10 reserved HD7
A11 reserved HD6
A12 reserved HD4
A13 reserved HD1
A14 reserved HD0
A15 GND
A16 BM3 GPID8 GPOD8 reserved
A17 NC
A18 NC
A19 NC
A20 NC
B1 VDDM
B2 NC
B3 CS0
B4 DQM2
B5 DQS3
B6 DQS0
B7 CKE
B8 WE
B9 GPIC6 GPOC6 HD14
B10 GPIC3 GPOC3 HD11
B11 GPIC0 GPOC0 HD8
B12 reserved HD5
B13 reserved HD2
Pin Assignments
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 7
B14 NC
B15 BM2 GPID7 GPOD7 reserved
B16 NC
B17 NC
B18 NC
B19 NC
B20 NC
C1 D24
C2 D30
C3 D25
C4 CS1
C5 DQM3
C6 DQM0
C7 DQS1
C8 RAS
C9 CAS
C10 GPIC5 GPOC5 HD13
C11 GPIC1 GPOC1 HD9
C12 reserved HD3
C13 NC
C14 NC
C15 NC
C16 NC
C17 NC
C18 NC
C19 NC
C20 NC
D1 VDDM
D2 D28
D3 D27
D4 GND
D5 VDDM
D6 VDDM
D7 VDDM
D8 VDDM
D9 VDDM
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
MSC7116 Data Sheet, Rev. 13
Pin Assignments
Freesca le Sem ico nd uctor8
D10 VDDM
D11 VDDIO
D12 VDDIO
D13 VDDIO
D14 VDDIO
D15 VDDIO
D16 VDDIO
D17 VDDC
D18 NC
D19 NC
D20 NC
E1 GND
E2 D26
E3 D31
E4 VDDM
E5 VDDM
E6 VDDC
E7 VDDC
E8 VDDC
E9 VDDC
E10 VDDM
E11 VDDIO
E12 VDDIO
E13 VDDIO
E14 VDDIO
E15 VDDIO
E16 VDDC
E17 VDDC
E18 NC
E19 NC
E20 NC
F1 VDDM
F2 D15
F3 D29
F4 VDDC
F5 VDDC
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
Pin Assignments
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 9
F6 VDDC
F7 GND
F8 GND
F9 GND
F10 VDDM
F11 VDDM
F12 GND
F13 GND
F14 GND
F15 VDDIO
F16 VDDC
F17 VDDC
F18 NC
F19 NC
F20 NC
G1 GND
G2 D13
G3 GND
G4 VDDM
G5 VDDM
G6 GND
G7 GND
G8 GND
G9 GND
G10 GND
G11 GND
G12 GND
G13 GND
G14 GND
G15 VDDIO
G16 VDDIO
G17 VDDC
G18 NC
G19 NC
G20 NC
H1 D14
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
MSC7116 Data Sheet, Rev. 13
Pin Assignments
Freesca le Sem ico nd uctor10
H2 D12
H3 D11
H4 VDDM
H5 VDDM
H6 GND
H7 GND
H8 GND
H9 GND
H10 GND
H11 GND
H12 GND
H13 GND
H14 GND
H15 VDDIO
H16 VDDIO
H17 VDDC
H18 NC
H19 reserved HA2
H20 reserved HA1
J1 D10
J2 VDDM
J3 D9
J4 VDDM
J5 VDDM
J6 VDDM
J7 GND
J8 GND
J9 GND
J10 GND
J11 GND
J12 GND
J13 GND
J14 GND
J15 GND
J16 VDDIO
J17 VDDC
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
Pin Assignments
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 11
J18 GPIC11 GPOC11 HA3
J19 reserved HACK/H ACK or HRRQ/HRRQ
J20 HDSP reserved HREQ/HREQ or HTRQ/HTRQ
K1 D0
K2 GND
K3 D8
K4 VDDC
K5 VDDM
K6 GND
K7 GND
K8 GND
K9 GND
K10 GND
K11 GND
K12 GND
K13 GND
K14 GND
K15 VDDIO
K16 VDDIO
K17 VDDC
K18 reserved HA0
K19 reserved HDDS
K20 reserved HDS/HDS or HWR/HWR
L1 D1
L2 GND
L3 D3
L4 VDDC
L5 VDDM
L6 GND
L7 GND
L8 GND
L9 GND
L10 GND
L11 GND
L12 GND
L13 GND
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
MSC7116 Data Sheet, Rev. 13
Pin Assignments
Freesca le Sem ico nd uctor12
L14 VDDIO
L15 VDDIO
L16 VDDIO
L17 VDDC
L18 GPIB11 GPOB11 HCS2/HCS2
L19 reserved HCS1/HCS1
L20 reserved HRW or HRD/HRD
M1 D2
M2 VDDM
M3 D5
M4 VDDM
M5 VDDM
M6 GND
M7 GND
M8 GND
M9 GND
M10 GND
M11 GND
M12 GND
M13 GND
M14 GND
M15 GND
M16 VDDC
M17 VDDC
M18 GPIA14 IRQ15 GPOA14 SDA
M19 GPIA12 IRQ3 GPOA12 UTXD
M20 GPIA13 IRQ2 GPOA13 URXD
N1 D4
N2 D6
N3 VREF
N4 VDDM
N5 VDDM
N6 VDDM
N7 GND
N8 GND
N9 GND
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
Pin Assignments
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 13
N10 GND
N11 GND
N12 GND
N13 GND
N14 GND
N15 VDDIO
N16 VDDC
N17 VDDC
N18 CLKIN
N19 GPIA15 IRQ14 GPOA15 SCL
N20 VSSPLL
P1 D7
P2 D17
P3 D16
P4 VDDM
P5 VDDM
P6 VDDM
P7 GND
P8 GND
P9 GND
P10 GND
P11 GND
P12 GND
P13 GND
P14 GND
P15 VDDIO
P16 VDDIO
P17 VDDC
P18 PORESET
P19 TPSEL
P20 VDDPLL
R1 GND
R2 D19
R3 D18
R4 VDDM
R5 VDDM
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
MSC7116 Data Sheet, Rev. 13
Pin Assignments
Freesca le Sem ico nd uctor14
R6 VDDM
R7 GND
R8 VDDM
R9 GND
R10 VDDM
R11 GND
R12 GND
R13 VDDIO
R14 GND
R15 VDDIO
R16 VDDIO
R17 VDDC
R18 TDO
R19 reserved EE0/DBREQ
R20 TEST0
T1 VDDM
T2 D20
T3 D22
T4 VDDM
T5 VDDM
T6 VDDC
T7 VDDM
T8 VDDM
T9 VDDC
T10 VDDM
T11 VDDM
T12 VDDIO
T13 VDDIO
T14 VDDIO
T15 VDDIO
T16 VDDC
T17 VDDC
T18 reserved MDIO
T19 TMS
T20 HRESET
U1 GND
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
Pin Assignments
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 15
U2 D21
U3 D23
U4 VDDM
U5 VDDC
U6 VDDC
U7 VDDC
U8 VDDC
U9 VDDC
U10 VDDC
U11 VDDC
U12 VDDC
U13 VDDC
U14 VDDC
U15 VDDC
U16 VDDC
U17 VDDC
U18 reserved COL
U19 TCK
U20 TRST
V1 VDDM
V2 NC
V3 A13
V4 A11
V5 A10
V6 A5
V7 A2
V8 BA0
V9 NC
V10 reserved EVNT0
V11 SWTE GPIA16 IRQ12 GPOA16 EVNT4
V12 GPIA8 IRQ6 GPOA8 T0TCK
V13 GPIA4 IRQ1 GPOA4 T1RFS
V14 GPIA0 IRQ11 GPOA0 T1TD
V15 GPIA28 IRQ17 GPOA28 TX_ER reserved
V16 GPID6 GPOD6 RXD2 reserved
V17 GPIA22 IRQ22 GPOA22 RXD0
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
MSC7116 Data Sheet, Rev. 13
Pin Assignments
Freesca le Sem ico nd uctor16
V18 GPIA24 IRQ24 GPOA24 TX_EN
V19 reserved CRS
V20 TDI
W1 GND
W2 VDDM
W3 A12
W4 A8
W5 A7
W6 A6
W7 A3
W8 NC
W9 GPIA17 IRQ13 GPOA17 EVNT1 CLKO
W10 BM0 GPIC14 GPOC14 EVNT2
W11 GPIA10 IRQ5 GPOA10 T0RFS
W12 GPIA7 IRQ7 GPOA7 T0TFS
W13 GPIA3 IRQ8 GPOA3 T1RD
W14 GPIA1 IRQ10 GPOA1 T1TFS
W15 GPID4 GPOD4 TXD2 reserved
W16 GPIA27 IRQ18 GPOA27 RXD3 reserved
W17 GPIA19 IRQ19 GPOA19 TXD1
W18 GPIA23 IRQ23 GPOA23 TXCLK or REFCLK
W19 GPIA26 IRQ26 GPOA26 RX_ER
W20 H8BIT reserved MDC
Y1 VDDM
Y2 GND
Y3 A9
Y4 A1
Y5 A0
Y6 A4
Y7 BA1
Y8 reserved NMI reserved
Y9 BM1 GPIC15 GPOC15 EVNT3
Y10 GPIA11 IRQ4 GPOA11 T0RCK
Y11 GPIA9 GPOA9 T0RD
Y12 GPIA6 GPOA6 T0TD
Y13 GPIA5 IRQ0 GPOA5 T1RCK
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 17
2 Electrica l Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications. For additional information, see the MSC711x Reference Manual.
2.1 Maximum Ratings
In calculating timing requirements, adding a maximum value of one specification to a minimum value of anoth er specification
does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values
in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that can never exist.
Y14 GPIA2 IRQ9 GPOA2 T1TCK
Y15 GPIA29 IRQ16 GPOA29 TXD3 reserved
Y16 GPID5 GPOD5 RXCLK reserved
Y17 GPIA20 IRQ20 GPOA20 TXD0
Y18 GPIA21 IRQ21 GPOA21 RXD1
Y19 GND
Y20 GPIA25 IRQ25 GPOA25 RX_DV or CRS_DV
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or VDD).
Table 1. MSC7116 Signals by Ball Designator (continued)
Number
Signal Names
End of Reset
Software Controlled Hardware Controlled
GPI Enabled
(Default) Interrupt
Enabled GPO Enabled Primary Alternate
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor18
Table 2 describes the maximum electrical ratings for the MSC7116.
2.2 Recommended Operating Conditions
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 2. Absolute Maximum Ratings
Rating Symbol Value Unit
Core supply voltage VDDC 1.5 V
Memo ry supply voltage VDDM 4.0 V
PLL supply voltage VDDPLL 1.5 V
I/O supply voltage VDDIO –0.2 to 4 .0 V
Input voltage VIN (GND – 0.2) to 4.0 V
Reference voltage VREF 4.0 V
Maximum operat ing temperature TJ105 °C
Minimum operating temperature TA–40 °C
Storage temperature range TSTG –55 to +150 °C
Notes: 1. Functional operating conditions are given in Table 3.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permane nt damage.
3. Section 3.1, Thermal Design Considerations includes a formula for computing the chip junction temperature (TJ).
Table 3. Recommended Operating Conditions
Rating Symbol Value Unit
Core supply voltage VDDC 1.14 to 1.26 V
Memo ry supply voltage VDDM 2.38 to 2.63 V
PLL supply voltage VDDPLL 1.14 to 1.26 V
I/O supply voltage VDDIO 3.14 to 3.47 V
Reference voltage VREF 1.19 to 1.31 V
Operating temperature range TJ
TA
maxi mum: 105
minimum: –40 °C
°C
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 19
2.3 Thermal Characteristics
Table 4 describes thermal characteristics of the MSC7116 for the MAP-BGA package.
Section 3.1, Thermal Desig n Considerations explains these characteristics in detail.
2.4 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC7116.
Note: The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO
and VDDC vary by +2 perce nt or both vary by –2 percent).
Table 4. Thermal Characteristics for MAP-BGA Package
Characteristic Symbol
MAP-BGA 17 × 17 mm5
Unit
Natural
Convection 200 ft/min
(1 m/s) airflow
Junction-to-ambient1, 2 RθJA 39 31 °C/W
Junction-to-ambient , four-layer board1, 3 RθJA 23 20 °C/W
Junction-to-board4RθJB 12 °C/W
Junction-to-case5RθJC 7°C/W
Junction-to-package-top6ΨJT 2°C/W
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mountin g site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDE C JESD51-2 with the single layer board horizontal.
3. Per JED EC JESD 51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Table 5. DC Electrical Characteristics
Characteristic Symbol Min Typical Max Unit
Core and PLL voltage VDDC
VDDPLL
1.14 1.2 1.26 V
DRAM interface I/O voltage1VDDM 2.375 2.5 2.625 V
I/O voltage VDDIO 3.135 3.3 3.465 V
DRAM interface I/O reference voltage2VREF 0.49 × VDDM 1.25 0.51 × VDDM V
DRAM interface I/O termination voltage3VTT VREF – 0.04 VREF VREF + 0.04 V
Input high CLKIN voltage VIHCLK 2.4 3.0 3.465 V
DRAM interface input high I/O voltage VIHM VREF + 0.28 VDDM VDDM + 0.3 V
DRAM interface input low I/O voltage VILM –0.3 GND VREF – 0.18 V
Input leakage current, VIN = VDDIO IIN –1.0 0.09 1 µA
VREF input leakage current IVREF —— 5µA
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor20
Table 6 lists the DDR DRAM capacitance.
Tri-state (high impedance off state) leakage current,
VIN = VDDIO
IOZ –1.0 0.09 1 µA
Signal low input current, VIL = 0.4 V IL–1.0 0.09 1 µA
Signal high input current, VIH = 2.0 V IH–1.0 0.09 1 µA
Output high voltage, IOH = –2 mA, except open drain pins VOH 2.0 3.0 — V
Output low voltage, IOL= 5 mA VOL —00.4V
Typical power at 266 MHz5P — 293.0 — mW
Notes: 1. The value of VDDM at the MSC7116 device must remain within 50 mV of VDDM at the DRAM device at all times.
2. VREF must be equal to 50% of VDDM and track VDDM variations as measured at the receiver. Peak-to-peak noise must not
exceed ±2% of the DC value.
3. VTT is not applied directly to the MSC7116 device. It is the level measured at the far end signal termination. It should be equal
to VREF. This rail should track variations in the DC level of VREF.
4. Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤ VOUT ≤ VDDM.
5. The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 300 MHz, 1.2 V core).
Table 6. DDR DRAM Capacitance
Parameter/Condition Symbol Max Unit
Input/output capacitance: DQ, DQS CIO 30 pF
Delta input/output capacitance: DQ, DQS CDIO 30 pF
Note: These values were measured under the following conditions:
• VDDM = 2.5 V ± 0.125 V
• f = 1 MHz
• TA = 25°C
• VOUT = VDDM/2
• VOUT (peak to peak) = 0.2 V
Table 5. DC Electrical Characteristics (continued)
Characteristic Symbol Min Typical Max Unit
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 21
2.5 AC Timings
This section presents ti mi ng diagr ams and specifications for individual signals and parallel I/O outputs and inputs. All AC
timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the
following equations to com pute the delay:
— Standard interface: 2.45 + (0.054 × Cload) ns
— DDR interface: 1.6 + (0.002 × Cload) ns
2.5.1 Clock and Timing Signals
The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core,
reference, and peripherals) and external (CLKO) cloc ks. You must e nsure that maximum frequency values are not exceeded (see
Section 2.5.2 for the allowable ranges when using the PLL).
Table 6. Maximum Frequencies
Characteristic Maximum in MHz
Core clock frequency (CLO CK ) 266
External output clock frequency (CLKO) 67
Memo ry clock frequency (CK , CK) 133
TDM clock frequency (T xRCK , TxTCK) 50
Table 7. Clock Frequencies in MHz
Characteristic Symbol Min Max
CLKIN frequency FCLKIN 10 100
CLOCK frequency FCORE — 266
CK, C K frequency FCK — 133
TDMxRCK, TDMxT CK frequency FTDMCK —50
CLKO frequency FCKO —67
AHB/IPBus/APB clock frequency FBCK — 133
Note: The rise and fall time of external clocks should be 5 ns maximum
Table 8. System Clock Parameters
Characteristic Min Max Unit
CLKIN frequency 10 100 MHz
CLKIN slope —5ns
CLKIN frequency jitter (peak-to-peak) — 1000 ps
CLKO frequency jitter (peak-to-peak) — 133 ps
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor22
2.5.2 Configuring Clock Frequencies
This section describes im portant requirements for configuring clock frequencies in the MSC7116 device when using the PLL
bloc k. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):
•PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency FCLKIN. The output
of the divider block is the input to the multiplier block.
•PLLMLTF field. Specifies the PLL multiplication factor (PLLMLTF + 1). The output from the multiplier block is the
loop frequency FLOOP.
•RNG field. Selects the available PLL frequency range fo r FVCO, either FLOOP when the RNG bit is set (1) or FLOOP/2
when the RNG bit is cleared (0).
•CKSEL field. Selects FCLKIN, FVCO, o r FVCO/2 as the source for the core clock.
There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the
allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines
to configure the device clocking when using the PLL. Refer to the Cl ock and Po wer Management chapter in the MSC711x
Reference Manual for details on th e clock pro gramming model.
2.5.2.1 PLL Multiplier Restrictions
There are two restrictions for correct usage of the PLL block:
• The input frequency to the PLL multiplier block (that is, the output of the divid er) mus t be in the range 10–2 5 MHz.
• The output frequency of the PLL multiplier must be in the range 266–532 MHz.
When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet
these constraints.
2.5.2.2 Input Division Factors and Corresponding CLKIN Frequency Range
The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 9.
Table 9. CLKIN Frequency Ranges by Divide Factor Value
PLLDVF
Fie ld Value Input Divide
Factor CLKIN Frequency Range Comments
0x00 1 10 to 25 MHz Input Division by 1
0x01 2 20 to 50 MHz Input Division by 2
0x02 3 30 to 75 MHz Input Division by 3
0x03 4 40 to 100 MHz I nput Division by 4
0x04 5 50 to 100 MHz I nput Division by 5
0x05 6 60 to 100 MHz I nput Division by 6
0x06 7 70 to 100 MHz I nput Division by 7
0x07 8 80 to 100 MHz I nput Division by 8
0x08 9 90 to 100 MHz I nput Division by 9
0x09 10 100 MHz Input Division by 10
Note: The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–10.
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 23
2.5.2.3 Multiplication Factor Range
The multiplier block output frequency ranges d epend on the divided input clock frequency as shown in Table 10.
2.5.2.4 Allowed Core Clock Frequency Range
The frequency deliver ed to the core, extended core, and peripherals depen ds on the value of the CLKCTRL[RNG] bit as shown
in Table 11.
This bit along with the CKSEL determines the frequency range of the core clock.
2.5.2.5 Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this
restriction.
Table 10. PLLMLTF Ranges
Multiplier Block (Loop) Output Range Minimum PLLMLTF Value Maximum PLLMLTF Value
266 ≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz 266/Divided Input Clock 532/Divided Input Clock
Note: This table results from the allowed range for FLoop. The minimum and maximum multiplication factors are dependent on the
frequency of the Divided Input Clock.
Table 11. Fvco Frequency Ranges
CLKCTRL[RNG] Value Allowed Range of Fvco
1 266 ≤ Fvco ≤ 532 MHz
0 133 ≤ Fvco ≤ 266 MHz
Note: This table results from the allowed range for Fvco, which is FLoop modified by CLKCTRL[RNG].
Table 12. Resulting Ranges Permitted for the Core Clock
CLKCTRL[CKSEL] CLKCTRL[RNG] Resulting
Division
Factor
Allowed Range
of Core Clock Comments
11 1 1 Reserved Reserved
11 0 2 133 ≤ core clock ≤ 266 MHz Limited by range of PLL
01 1 2 133 ≤ core clock ≤ 266 MHz Limited by range of PLL
01 0 4 66.5 ≤ core clock ≤ 133 MHz Limited by range of PLL
Note: This table results from the allowed range for FOUT, which depends on clock selected via CLKCTRL[CKSEL].
Table 13. Core Clock Rang es When U sing DDR
DDR Type Allowed Frequency
Range for DDR CK Corresponding Range
for the Core Clock Comments
DDR 200 (PC-1600) 83–100 MHz 166 ≤ core clock ≤ 200 MHz Core limited to 2 × maximum DDR frequency
DDR 266 (PC-2100)
DDR 333 (PC-2600) 83–133 MHz 166 ≤ core clock ≤ 266 MHz Core limited to 2 × maximum DDR frequency
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor24
2.5.3 Reset Timing
The MSC7116 device has several inputs to the reset logic. All MSC7116 reset sources ar e f ed into the reset controller, which
takes dif fer ent actions dep endin g on the source o f the r eset. The res et status regist er ind icates the most recen t sources to cause
a reset. Table 14 describes th e reset sources .
Table 15 summarizes the reset actions that occur as a result of the different reset sources.
2.5.3.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally fo r at least 16 CLKIN cycles after
external power to the MSC7116 reaches at least 2/3 VDD.
Table 14. Reset Sources
Name Direction Description
Power-on reset
(PORESET)Input Initiates the power-on reset flow that resets the MSC7116 and configures various attributes of the
MSC7116. On PORESE T, the entire MSC7116 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
External Hard
reset (HRESET)Input/ Output Initiates the hard reset flow that configures various attributes of the MSC7116. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
Software
watchdog reset Internal When the MSC7116 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor
reset Internal When the MSC7116 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
JTAG EXTEST,
CLAMP, or
HIGHZ command
Internal When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
Table 15. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)Hard Reset
(HRESET)Soft Reset
(SRESET)
External only
External or
Internal (Software
Watchdog or Bus
Monitor)
JTAG Command:
EXTEST, CLAMP,
or HIGHZ
Configuration pins sampled (refer to Section 2.5.3.1 fo r
details).Yes No No
PLL and clock synthesis states Reset Yes No No
HRESET Driven Yes Yes No
Software watchdog and bus time-out monitor registers Yes Yes Yes
Clock synthesis modules (STOP CTR L, HLTREQ, and
HLTACK) res e t Yes Yes Yes
Extended core reset Yes Yes Yes
Peripheral modules reset Yes Yes Yes
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 25
2.5.3.2 Reset Configuration
The MSC7116 has two mechanisms for wri ting the reset configuration:
• From a host through the host interface (HDI16)
• From memory through the I2C interface
Five signal levels (see Chapter 1 for signal description details) are s ampled on PORESET de assertion to defi ne the boot a nd
operatin g condi t ions:
•BM[0–1]
•SWTE
•H8BIT
• HDSP
2.5.3.3 Reset Timing Tables
Table 16 and Figure 4 describe the reset timing for a reset configuration write.
Table 16. Timing for a Reset Configuration Writ e
No. Characteristics Expression Unit
1 Required external PORESET duration minimum 16/FCLKIN clocks
2 Delay from PORESET deassertion to HRESET deassertion 521/FCLKIN clocks
Note: Timings are not tested, but are guaranteed by design.
Figure 4. Timing Diagram for a Reset Configuration Write
PORESET
PORESET
Internal
HRESET
Input
Output (I/O)
Configuration Pins
are sam p led
2
1
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor26
2.5.4 DDR DRAM Controller Timing
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1 DDR DRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR DRAM interface.
2.5.4.2 DDR DRAM Output AC Timing Specifications
Table 18 and Table 19 list the output AC timing specifications and measurement conditions for the DDR DRAM
interface.
Table 17. DDR DRAM Input AC Timing
No. Parameter Symbol Min Max Unit
— AC input low voltage VIL —V
REF – 0.31 V
— AC input high voltage VIH VREF + 0.31 VDDM + 0.3 V
201 Max imum Dn input setup skew relative to DQSn input — — 900 ps
202 Max imum Dn input hold skew relative to DQSn input — — 900 ps
Notes: 1. Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤ n ≤ 7).
2. See Table 18 for tCK value.
3. Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
Figure 5. DDR DRAM Input Timing Diagram
Table 18. DDR DRAM Output AC Timing
No. Parameter Symbol Min Max Unit
200 CK cycle time, (CK/CK crossing)1
• 100 MHz (DDR200)
• 150 MHz (DDR300)
tCK 10
6.67 —
—ns
ns
204 An/RAS/CAS/WE/CKE output setup with respect to CK tDDKHAS 0.5 × tCK – 1000 — ps
205 An/RAS/CAS/WE/CKE output hold with respect to CK tDDKHAX 0.5 × tCK – 1000 — ps
206 CSn output setup with respect to CK tDDKHCS 0.5 × tCK – 1000 — ps
207 CSn output hold with respect to CK tDDKHCX 0.5 × tCK – 1000 — ps
208 CK to DQSn2tDDKHMH –600 600 ps
Dn
DQSn
D1
D0
201
202 202
201
Note: DQS centering is done internally.
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 27
Figure 6 shows the DDR D RAM output timing diagram.
209 Dn/D QMn output setup with respect to DQSn3tDDKHDS,
tDDKLDS
0.25 × tCK – 750 — ps
210 Dn/D QMn output hold with respect to DQSn3tDDKHDX,
tDDKLDX
0.25 × tCK – 750 — ps
211 DQ Sn pream ble start4tDDKHMP –0.25 × tCK —ps
212 DQSn epilogue end5tDDKHME –600 600 ps
Notes: 1. All CK/CK refere nced measur ements are made from the crossi ng of the two signals ±0.1 V.
2. tDDKHMH can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 600 ps before
the CK/CK crossing and no later than 600 ps after the crossing time; the device uses 1200 ps of the skew budget (the interval
from –600 to +600 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
3. Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
4. Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
5. All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write-to-read turn-around times. This is already guaranteed by the memory controller operation.
Figure 6. DDR DRAM Output Timing Diagram
Table 18. DDR DRAM Output AC Timing (continued)
No. Parameter Symbol Min Max Unit
An
Dn
DQSn
CK
CK
D1D0
Write A0 NOOP
RAS
CAS
WE
CKE
200
208
209
209 212
210 210
211
206
204
207
205
DQMn
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor28
Figure 7 provides the AC tes t lo ad for the DDR DRAM bus.
2.5.5 TDM Timing
Figure 7. DDR DRAM AC Test Load
Table 19. DDR DRAM Measurement Conditions
Symbol DDR DRAM Unit
VTH1VREF ± 0.31 V V
VOUT20.5 × VDDM V
Notes: 1. Data input threshold measurement point.
2. Data output measurement point.
Table 20. TDM Ti ming
No. Characteristic Expression Min Max Units
300 TDMxRCK/TDMxTCK TC 20.0 — ns
301 TDMxRCK/TDMxTCK High Pulse Width 0.4 × TC 8.0 — ns
302 TDMxRCK/TDM xT CK Low Pulse Width 0.4 × TC 8.0 — ns
303 TDM all input Setup time 3.0 — ns
304 TDMxRD Hold time 3.5 — ns
305 TDMxTF S/TDM xRFS input Hold time 2.0 — ns
306 TDMxTCK High to TDMxTD output active 4.0 — ns
307 TDMxTCK High to TDMxTD output valid — 14.0 ns
308 TDMxTD hold time 2.0 — ns
309 TDMxTCK High to TDMxTD output high impedance — 10.0 ns
310 TDMxTFS/TDMxRFS output valid — 13.5 ns
311 TDMxTFS/TDM xRF S output hold time 2.5 — ns
Notes: 1. Output values are based on 30 pF capacitive load.
2. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge
they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x
Reference Manual f or details. TDMxTCK and TDM xRCK are shown using the rising edge.
Figure 8. TDM Receive Signals
Output Z0 = 50 ΩVOUT
RL = 50 Ω
TDMxRCK
TDMxRD
TDMxRFS
300
301 302
303
303 304
305
311
310
TDMxRFS (output)
~
~
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 29
2.5.6 Ethernet Timing
2.5.6.1 Receive Signal Timing
Figure 9. TDM Transmit Signals
Table 21. Receive Signal Timing
No. Characteristics Min Max Unit
800 Receive clock period:
• MII: RXCLK (max frequency = 25 MHz)
• RMII: REFCLK (max frequency = 50 MHz) 40
20 —
—ns
ns
801 Receive clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
802 Receive clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
803 RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time 4 — ns
804 Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time 2 — ns
Figure 10. Ethernet Receive Signa l Timing
TDMxTCK
TDMxTD
~
~
~
~
306
307 309
308
300
301 302
311
310
TDMxRCK
TDMxTFS (output)
TDMxTFS (input) 303 305
Valid
Receive
RX_DV
RXDn
RX_ER
803 804
clock
800
802 801
CRS_DV
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor30
2.5.6.2 Transmit Signal Timing
2.5.6.3 Asynchronous Input Signal Timing
Table 22. Transmit Signal Timing
No. Characteristics Min Max Unit
800 Transmit clock period:
• MII: TXCLK
• RMII: REFCLK 40
20 —
—ns
ns
801 Transmit clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
802 Transmit clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
805 Transmit clock to TXDn, TX_EN, TX_ER invalid 4 — ns
806 Transmit clock to TXDn, TX_EN, TX_ER valid — 14 ns
Figure 11. Ethernet Receive Signal Timing
Table 23. Asynchronous Input Signal T iming
No. Characteristics Min Max Unit
807 • MII: CRS and COL minimum pulse width (1.5 × TXCLK period)
• RMII: CRS_DV minimum pulse width (1.5 x REFCLK period) 60
30 —
—ns
ns
Figure 12. Asynchronous Input Signal Timing
Valid
Transmit
TX_EN
TXDn
TX_ER
805
806
clock
800
801 802
CRS
COL 807
CRS_DV
Electrical Characteri stics
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 31
2.5.6.4 Management Interface Timing
Table 24. Ethernet Controller Management Interface Timing
No. Characteristics Min Max Unit
808 MDC period 400 — ns
809 MDC pulse width high 160 — ns
810 MDC pulse width low 160 — ns
811 MDS falling edge to MDIO output invalid (minimum propagation delay) 0 — ns
812 MDS falling edge to MDIO output valid (maximum propagation delay) — 15 ns
813 MDIO input to MDC rising edge setup time 10 — ns
814 MDC rising edge to MDIO input hold time 10 — ns
Figure 13. Serial Management Channel Timing
MDC (output)
MDIO (output)
MDIO (input)
809
808
810
811
812
814
813
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freesca le Sem ico nd uctor32
2.5.7 HDI16 Signals
Table 25. Host Interface (HDI16) Timing1, 2
No. Characteristics3Expression Value Unit
40 Host Interface Clock period TCORE Note 1 ns
44a Read data strobe minimum assertion width4
HACK read minimum assertion width 2.0 × TCORE + 9.0 Not e 11 ns
44b Read data strobe minimum deassertion width4
HACK read minimum deassertion width 1.5 × TCORE Note 11 ns
44c Read data strobe minimum deassertion width4 after “Last Data Register”
reads5,6, or between two consecutive CVR, ICR, or ISR reads7
HACK minimum deassertion width after “Last Data Register” reads5,6
2.5 × TCORE Note 11 ns
45 Write data strobe minimum assertion width8
HACK write minimum assertion width 1.5 × TCORE Note 11 ns
46 Write data strobe minimum deassertion width8
HACK write minimum deassertion width after ICR, CVR and Data Register
writes52.5 × TCORE Note 11 ns
47 Host data input minimum setup time before write data strobe deassertion8
Host data input minimum setup time before HACK write deassertion — 2.5 ns
48 Host data input minimum hold time after write data strobe deassertion8
Host data input minimum hold time after HACK write deassertion — 2.5 ns
49 Read data strobe minimum assertion to output data active from high
impedance4
HACK read minimum assertion to output data active from high impedance — 1.0 ns
50 Read data strobe maximum asser tion to output data valid4
HACK read maximum assertion to output data valid (2.0 × TCORE) + 8.0 Note 11 ns
51 Read data strobe maximum deassertion to output data high impedance4
HACK read maximum deassertion to output data high impedance — 9.0 ns
52 Output data minimum hold time after read data strobe deassertion4
Output data minimum hold time after HACK read deassertion — 1.0 ns
53 HCS[1–2] minimum assertion to read data strobe assertion4—0.5ns
54 HCS[1–2] minimum assertion to write data strobe assertion8—0.0ns
55 HCS[1–2] maximum assertion to output data valid (2.0 × TCORE) + 6.0 Note 11 ns
56 HCS[1–2] minimum hold time after data strobe deassertion9—0.5ns
57 HA[0–2], HRW minimum setup time before data strobe assertion9—5.0ns
58 HA[0–2], HRW minimum hold time after data strobe deassertion9—5.0ns
61 Maximum delay from read data strobe deassertion to host request
deassertion for “Last Data Register” read4, 5, 10 (3.0 × TCORE) + 6.0 Note 11 ns
62 Maximum delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write5,8,10 (3.0 × TCORE) + 6.0 Note 11 ns
63 Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion. (2.0 × TCORE) + 1.0 Note 11 ns
64 Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion (5.0 × TCORE) + 6.0 Note 11 ns
Notes: 1. TCORE = core clock period. At 300 MHz, TCORE = 3.333 ns.
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. VDD = 3.3 V ± 0.15 V; TJ = –40°C to +105 °C, CL = 30 pF for maximum delay timings and CL = 0 pF for minimum delay timings.
4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5. For 64-bit transfers, the “last data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6. This timing is applicable only if a read from the “last data register” is followed by a read from the RX[0–3] registers without first
polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7. This timing is applicable only if two consecutive reads from one of these registers are executed.
8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
11. Compute the value using the expression.
12. The read and write data strobe mi nimum deassertion width for non-”last data register” accesses in single and dual data strobe
modes is based on timings 57 and 58.
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 33
Figure 14 and Figure 15 show HDI16 read signal timing. Figure 16 and Figure 17 show HDI16 write signal timing.
Figure 14. Read Timing Diagram, Single Data Strobe
Figure 15. Read Timing Diagram, Double Data Strobe
HDS
HA[0–2]
HCS[1–2]
HD[0–15]
50
55 44c
44b
44a
53
52
5857
51
49
61
56
HREQ (single host request)
HRW
57 58
HRRQ (double host request)
HRD
HA[0–2]
HCS[1–2]
HD[0–15]
50
55 44a
44b
44a
53
52
5857
51
49
56
61
HREQ (single host request)
HRRQ (double host request)
MSC7116 Data Sheet, Rev. 13
Freesca le Sem ico nd uctor34
Figure 16. Write Timing Diagram, Single Data Strobe
Figure 17. Wr ite Timing Diagram, Double Data Strobe
HDS
HA[0–2]
HCS[1–2]
HD[0–15]
47
46
45
54
5857
56
HRW
57 58
48
62
HREQ (single host request)
HTRQ (double host request)
HWR
HA[0–2]
HCS[1–2]
HD[0–15]
47
46
45
54
48
5857 56
62
HREQ (single host request)
HTRQ (double host request)
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 35
Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0
Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0
RX[0–3]
Read
Data
Valid
64
44a
63
44b
51
50
49 52
(Output)
HREQ
HACK
HD[0–15]
(Output)
TX[0–3]
Write
Data
Valid
63
64
46
45
47 48
(Output)
HREQ
HACK
HD[0–15]
(Input)
MSC7116 Data Sheet, Rev. 13
Freesca le Sem ico nd uctor36
2.5.8 I2C Timing
Table 26. I2C Timing
No. Characteristic Fast Unit
Min Max
450 SCL clock frequency 0 400 kHz
451 Hold time START condition (SCL clock period/2) – 0.3 — μs
452 SCL low period (SCL clock period/2) – 0.3 — μs
453 SCL high period (SCL clock period/2) – 0.1 — μs
454 Repeated START set-up time (not shown in figure) 2 × 1/FBCK —μs
455 Data hold time 0 — μs
456 Data set-up time 250 — ns
457 SDA and SCL rise time — 700 ns
458 SDA and SCL fall time — 300 ns
459 Set-up time for STOP (SCL clock period/2) – 0.7 — μs
460 Bus free time between STOP and START (SCL clock period/2) – 0.3 — μs
Note: SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance
on SDA and SCL is 400 pF.
Figure 20. I2C Timing Diagram
SCL
SDA Data Byte
Start Condition Stop Condition
A
C
K
78
9
456123
Start Condition
458
458 457
457
460459
451 452
453
SCL
SDA Data By te
Start Condition
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 37
2.5.9 UART Timing
2.5.10 EE Timing
Figure 24 shows the signal behavior of the EE pin.
Table 27. UART Timing
No. Characteristics Expression M in Max Unit
— Internal bus clock (APBCLK) FCORE/2 — 133 MHz
— Internal bus clock period (1/APBCLK) TAPBCLK 7.52 — ns
400 URXD and UTXD inputs high/low duration 16 × TAPBCLK 120.3 — ns
401 URXD and UTXD inputs rise/fall time — 5 ns
402 UTXD output rise/fall time — 5 ns
Figure 21. UART Input Timing
Figure 22. UART Output Timing
Table 28. EE 0 Timing
Number Characteristics Type Min
65 EE0 input to the core Asynchronous 4 core clock periods
66 EE0 output from the core Synchronous to core clock 1 core clock period
Notes: 1. The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2. Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1 4 0 0 Core Reference Manu al for details.
3. Refer to Table 1-11 on page 1-16 for details on EE pin functionality.
Figure 23. EE Pin Timing
UTXD, URXD
400
inputs
400
401 401
UTXD
Output
402 402
EE0 In 65
EE0 Out 66
MSC7116 Data Sheet, Rev. 13
Freesca le Sem ico nd uctor38
2.5.11 Event Timing
Figure 24 shows the signal behavior of the EVNT pins.
2.5.12 GPIO Timing
Figure 25 shows the signal behavior of the GPI/GPO pins.
Table 29. EVNT Signal Timing
Number Characteristics Type Min
67 EVNT as input Asynchronous 1.5 × APBCLK periods
68 EVNT as output Synchronous to core clock 1 APBCLK period
Notes: 1. Refer to Table 27 for a definition of the APBCLK period.
2. Direction of the EVNT signal is configured through the GPIO and Event port registers.
3. Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality.
Figure 24. EVNT Pin Timing
Table 30. GPIO Signal Timing1,2,3
Number Characteristics Type Min
601 GPI4.5 Asy n chronous 1.5 × APBCLK periods
602 GPO5Synchronous to core clock 1 APBCLK period
603 Port A edge-sensitive interrupt A syn chronous 1.5 × APBCLK periods
604 Port A level-sensitive interrupt Asynchronous 3 × AP BCLK periods6
Notes: 1. Refer to Table 27 for a definition of the APBCLK period.
2. Direction of the GPIO signal is configured through the GPIO port registers.
3. Refer to Section 1.5 for details on GPIO pin functionality.
4. GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
5. The output signals cannot toggle faster than 75 MHz.
6. Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
Figure 25. GPI/GPO Pin Timing
EVNT in 67
EVNT out 68
GPI 601
GPO 602
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 39
2.5.13 JTAG Signals
Table 31. JTAG Timing
No. Characteristics All frequencies Unit
Min Max
700 TCK frequency of operation (1/(TC × 3)
Note: TC = 1/CLOCK which is the period of the core clock. The TCK
frequency must less than 1/3 of the core frequency with an absolute
maximum limit of 40 MHz.
0.0 40.0 MHz
701 TCK cycle time 25.0 — ns
702 TCK clock pulse width measured at VM = 1.6 V 11.0 — ns
703 TCK rise and fall times 0.0 3.0 ns
704 Boundary scan input data set-up time 5.0 — ns
705 Boundary scan input data hold time 14.0 — ns
706 TCK low to output data valid 0.0 20.0 ns
707 TCK low to output high impedance 0.0 20.0 ns
708 TMS, TDI data set-up time 5.0 — ns
709 TMS, TDI data hold time 14.0 — ns
710 TCK low to TDO data valid 0.0 24.0 ns
711 TCK low to TDO high impedance 0.0 10.0 ns
712 TRST assert time 100.0 — ns
Note: All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface.
Figure 26. Test Clock Input Timing Diagram
TCK
(Input)
VMVM
VIH VIL
701
702
703703
MSC7116 Data Sheet, Rev. 13
Freesca le Sem ico nd uctor40
Figure 27. Boundary Scan (JTAG) Timing Diagram
Figure 28. Test Access Port Timing Diagram
Figure 29. TRST Timing Diagram
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
VIH
VIL
Input Data Valid
Output Data Valid
705704
706
707
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
VIH
VIL
Input Data Valid
Output Data Valid
TMS
708 709
710
711
TRST
(Input)
712
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 41
3 Hardware Design Considerations
This section described various areas to consider when incorporating the MSC7116 device into a system design.
3.1 Thermal Design Considerations
An estimation of the chip-junctio n temp erat ure, TJ, in °C can be obtained from the following:
TJ = TA + (RθJA × PD)Eqn.1
where
TA = ambient temperature near the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = PINT + PI/O = power dissipation in the package (W)
PINT = IDD × VDD = internal power dissip ation (W)
PI/O = power dissipated from device on output pins (W)
The power dissipation values for the MSC7116 are listed in Table 4. The ambient temperature for the device is the air
temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC
standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the
value determined on a single layer board and the value obtained on a board with two planes. The value that more closely
approximates a specific application depends on the power dissipated by other compon ents on the print ed circuit b oard (PCB).
The value ob tained us ing a s ingle layer board is approp riate fo r tightly packed PCB con figurations. Th e valu e obtai ned usi ng a
board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural
convection) and well separated component s. Bas e d on an estimation of junction temperature using this technique, determine
whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the
device thermal junction temperature below its maximum. If TJ appears to b e too high , either lower the ambien t temperatu re o r
the power dissipation of the chip.
You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is
recommended) or an infrared temperature sensor on a spot on the device case. Use the following equation to determine TJ:
TJ = TT + (ΨJT × PD)Eqn.2
where
TT = thermocouple (or infrared) temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor42
3.2 Power Supply Design Considerations
This section outlines the MSC7116 power considerations: power supply, power sequencing, power planes, decoupling, power
suppl y fil tering, and power consumpt i on. It also pr esent s a recommended power supply desi gn and options fo r low- power
consumption. For inform ation on AC/DC electrical specifications and thermal characteristics, refer to Section 2.
3.2.1 Power Supply
The MSC7116 requires four input voltages, as shown in Table 32.
You should su pply the MSC7116 core voltage via a variable switching supply or regulator to allow for compatibility with
possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across VDDC
and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and reference voltages supply
the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM and GND. The refer ence vo ltage
is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 × VDDM. Refer to the JEDEC standard JESD8
(Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements.
3.2.2 Power Sequencing
One consequence of multiple power supplies is that the voltage rails ramp up at dif ferent rates when power is initially applied.
The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is
extremely important to observe the power up and power down sequences at the board level to avoid latc h-up , forward bi asing
of ESD devices, and excessive currents, which all lead to severe device damage.
Note: There are five poss ible power-u p/power-do wn sequence cas es. The first four cases listed in the following sections are
recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated
for current spike risks based on actual information for the specific application.
Table 32. MSC7116 Voltages
Voltage Symbol Value
Core VDDC 1.2 V
Memory VDDM 2.5 V
Reference VREF 1.25 V
I/O VDDIO 3.3 V
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 43
3.2.2.1 Case 1
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V) supply second.
3. Turn on the VDDM (2.5 V) supply third.
4. Turn on the VREF (1.25 V) supply fourth (last) .
The power-down sequence is as follows:
1. Turn off the VRE F (1.25 V) supply first.
2. Turn off the VDDM (2.5 V) supply second.
3. Turn off the VDDC (1.2 V) supply third.
4. Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
• Make sure that the time interval between the ramp-down of VDDIO and VDDC is less than 10 ms.
• Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
• Refer to Figure 30 for relative timing for power sequencing case 1.
Figure 30. Voltage Sequencing Case 1
Time
Voltage
Ramp-down
Ramp-up VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
<10 ms
<10 ms
<10 ms
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor44
3.2.2.2 Case 2
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V) and VDDM (2.5 V) supplies simultaneously (second).
3. Turn on the VREF (1.25 V) supply last (third).
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDC/VDDM is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VRE F (1.25 V) supply first.
2. Turn off the VDDM (2.5 V) supply second.
3. Turn off the VDDC (1.2 V) supply third.
4. Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
• Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
• Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
• Refer to Figure 31 for relative timin g for Case 2.
Figure 31. Voltage Sequencing Case 2
Time
Voltage
Ramp-down
Ramp-up VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
<10 ms
<10 ms
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 45
3.2.2.3 Case 3
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V) supply second.
3. Turn on the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (third).
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (first).
2. Turn off the VDDC (1.2 V) supply second.
3. Turn of the VDDIO (3.3 V) supply third (last).
Use the following guidelines:
• Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
• Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for
power-up and power-down.
• Refer to Figure 32 for relative timin g for Case 3.
Figure 32. Voltage Sequencing Case 3
Time
Voltage
Ramp-down
Ramp-up VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
<10 ms
<10 ms
<10 ms
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor46
3.2.2.4 Case 4
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V), VDDM (2.5 V), and VREF (1.25 V) supplies simu ltaneously (second).
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VDDC (1.2 V), VREF (1.25 V), and VDDM (2.5 V) supplies simultaneously (first).
2. Turn of the VDDIO (3.3 V) supply last.
Use the following guidelines:
• Make sure that t he time interv al between the ramp-u p or ramp -do wn time fo r VDDC and VDDM is less than 10 ms for
power-up and power-down.
• Refer to Figure 33 for relative timin g for Case 4.
Figure 33. Voltage Sequencing Case 4
Time
Voltage
Ramp-down
Ramp-up VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
<10 ms
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 47
3.2.2.5 Case 5 (not recommended for new designs)
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDM (2.5 V) supply second.
3. Turn on the VDDC (1.2 V) supply third.
4. Turn on the VREF (1.25 V) supply fourth (last) .
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDM is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VRE F (1.25 V) supply first.
2. Turn off the VDDC (1.2 V) supply second.
3. Turn off the VDDM (2.5 V) supply third.
4. Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
• Make sure that the time interval between the ramp-down of VDDIO and VDDM is less than 10 ms.
• Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 2 ms for
power-up and power-down.
• Refer to Figure 34 for relative timing for power sequencing case 5.
Note: Cases 1, 2, 3, and 4 are recommended for system design. Designs that use Case 5 may have large current spikes on
the VDDM supply at startup and is not recommended for most designs. If a design uses case 5, it must accommodate
the potential current spikes. Verify risks related to current spikes using actual information for the specific application.
Figure 34. Voltage Sequencing Case 5
Time
Voltage
Ramp-down
Ramp-up VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
<2 ms
<2 ms
<10 ms
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor48
3.2.3 Power Planes
Each power supply pin (VDDC, VDDM, and VDDIO) sh ould h ave a low- impedan ce p ath to the board po wer supply. Each GND pi n
should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.
The MSC7116 VDDC power supply pins should be bypassed to groun d using decoupling capacitors. The capacitor leads and
associated printed circu it traces connecting to de vice power pins and GND s hould be kept to le ss than half an inch pe r capacitor
lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5
for DDR Controller power guidelines.
3.2.4 Decoupling
Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor
values of 0.01 μF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level
should cons ist of a 0.01 µF high frequenc y capacitor with low ef fective series r esistance ( ESR) and effective series inductance
(ESL) for every two to three voltage pins. The second decoupling level should con sist of two bulk/tantalum decoupling
capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) moun ted as closely as poss ibl e to the MSC 7116 voltage pins.
Additionally, the maxim um drop bet ween the power supply and the DSP device should b e 15 mV at 1 A.
3.2.5 PLL Power Supply Filtering
The MSC7116 VDDPLL power signal provides power to the clock generation PLL. To ensure stability of the internal clock, the
power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. VDDPLL
can be connected to VDDC throug h a 2 Ω resistor. VSSPLL can be tied directly to the GND plane. A circuit similar to the one
shown in Figure 35 is reco mmend ed. The PLL loop filter s hould b e placed as clo sely as po ssible to the VDDPLL pin (wh ich ar e
located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 µF capacitor should
be closest to VDDPLL, followed by the 0.1 µF capacitor, the 10 µF capacitor, and finally the 2-Ω resistor to VDDC. These traces
should be kept short.
3.2.6 Power Consumption
You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:
•Extended core. Us e the SC1400 Stop and Wait modes by issuing a stop or wait instr uction.
•Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
•AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
•Peripheral subsys tem. Halt the individual on-device peripherals such as the DDR memory contr oller , Ethe rnet MAC,
HDI16, TDM, UART, I2C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
Figure 35. PLL Power Supply Filter Circuits
VDDC VDDPLL
2 Ω
0.1 µF 0.01 µF
10 µF
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 49
3.2.7 Power Supply Design
One of the most common ways to derive power is to use either a simple fixed or adjustable linear regulator . For the system I/O
voltage supply, a simple fixed 3.3 V supply can be used. However, a separate adjustable linear regulator supply for the core
voltage VDDC should be implemented. For the memory power supply, regulators are available that take care o f all DDR power
requirements.
3.3 Estimated Power Usage Calculations
The following equations permit estimated power usage to be calculat ed for i ndividua l design cond itions. Ov erall power is
derived by totaling the power used by each of the major subsystems:
PTOTAL = PCORE + PPERIPHERALS + PDDRIO + PIO + PLEAKAGE Eqn. 3
This equation combines dynamic and static power. Dynamic power is determined using the generic equation:
C × V2 × F × 10–3 mW Eqn. 4
where, C = load capacitance in pF
V = peak-to-peak voltage swing in V
F = frequency in MHz
3.3.1 Core Power
Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core load
capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 266 MHz. This yields:
PCORE = 750 pF × (1.2 V)2 × 266 MHz × 10–3 = 287 mW Eqn. 5
This equation allows for adjustments to voltage and frequency if necessary.
Table 33. Recommended Power Sup ply Ratings
Supply Symbol Nominal Voltage Current Rating
Core VDDC 1.2 V 1.5 A per device
Memory VDDM 2.5 V 0.5 A per device
Reference VREF 1.25 V 10 µA per device
I/O VDDIO 3.3 V 1.0 A per device
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor50
3.3.2 P eriphe ra l Power
Peripherals include the DDR memory controller, Ethernet controller, DMA controller , HDI16, TDM, UART, timers, GPIOs,
and the I2C module. Basic power consumption by each module is assumed to be the same and is computed by using the
following equatio n wh ich assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 133
MHz. This yields:
PPERIPHERAL = 20 pF × (1.2 V)2 × 133 MHz × 10–3 = 3.83 mW per peripheral Eqn. 6
Multiply this value by the number of periphe rals used in the application to compute the total peripheral power consumpt ion.
3.3.3 External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on over all system si gnal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7116
device, the 2.5 V power source provides the power for the terminatio n, whic h is a stat ic valu e of 16 m A per s ignal driven high .
The dynamic power is computed, however , using a dif ferential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
PDDRIO = PSTATIC + PDYNAMIC Eqn. 7
PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V Eqn. 8
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)2 × 266 MHz × 10–3 mW Eqn. 9
pin activity value = (active data lines × % activity × % data switching) + (active address lines × % activity) Eqn. 10
As an example, assume the following:
unus ed pins = 16 (DDR uses 16-pi n mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)2 × 266 × 10–3) = 326.3 mW Eqn. 11
3.3.4 External I/O Power
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per
signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 33 MHz,
which yields:
PIO = 20 pF × (3.3 V)2 × 33 MHz × 10–3 = 7.19 mW per I/O line Eqn. 12
Multiply this number by the number of I /O sig nal lines used in the application desi gn to com pute th e tot al I/O power.
Note: The si gnal loading d epend s on the boar d routing. F or s yste ms us ing a s ingle DDR device, the load co uld be as lo w as
7 pF.
3.3.5 Leakage Power
The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The
observed leakage value at room temperature is 64 mW.
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 51
3.3.6 Example To tal Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
PTOTAL = 287 + (4 × 3.83) + 326.3 + (10 × 7.19) + 64 = 764.52 mW Eqn. 13
3.4 Reset and Boot
This section describes the recommendations for configuring the MSC7116 at reset and boot.
3.4.1 Reset Circuit
HRESET is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less curr ent loading from the bus-hold drivers overcomes this issue. T o avoid exceeding the MSC7116 output
current, the pull-up valu e should not be too small ( a 1 KΩ pu ll-up resistor is used i n the M S C711xADS referenc e design).
3.4.2 R eset Configurati on Pins
Table 34 shows the MSC7116 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET. For details, refer to the Reset ch apter o f the MSC711x Reference Manual.
Table 34. Reset Configuration Signals
Signal Description Settings
BM[3–0] D e termines boot mode. See Table 35 for details.
SWTE Determines watchdog functionality. 0 Watchdog timer disabled.
1 Watchdog timer enabled.
HDSP Configures HDI16 strobe polarity. 0 Host Data strobes active low.
1 Host Data strobes active high.
H8BIT C onfigures HDI16 operation mode. 0 HDI16 port configured for 16-bit operation.
1 HDI16 port configured for 8-bit operation.
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor52
3.4.3 Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Thus, the device operates
slowly during the b oot process. A fter the boo t program is loaded, it can enable the PLL and start the device operating at a higher
speed. The MSC71 16 can boo t from an external host throug h the HDI16 or do wnload a user prog ram through th e I2C port. The
boot op erati ng m ode i s set by conf i gur in g t he BM[0–3] signals sampled at the risi ng ed ge of PORESET, as shown in Table 35.
See the MSC711x Reference Manual for detail s of boot pr ogram operation.
3.4.3.1 HDI16 Boot
If the MSC7116 device boots from an external host through the HDI16, the port is configured as follows:
• Operate in Non-DMA mode.
• Operate in polled mode on the device side.
• Operate in polled mode on the external host side.
• External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
Table 35. Boot Mode Source Selection
BM[3–0] Boot
Port Input Clock
Frequency Clock
Divide PLL CKSEL RNG
Bit Core Clock
Frequency Comments
HDI Boot Modes
0000 HDI16 < Fmax N/A N/A 00 0 < Fmax Not clocked by the PLL.
Can boot as 8- or 16-bit HDI.
0101 HDI16 22.2-25 MHz 1 12 11 1 266–300 MHz Can boot as 8- or 16-bit HDI.
0010 HDI16 25-33.3 MHz 2 32 01 1 200–266 MHz
0111 HDI16 33-66 MHz 3 12 11 1 132–264 MHz
0100 HDI16 44.3-50 MHz 2 12 11 1 266–300 MHz
SPI Boot Modes - Using HA3, HCS2, BM3, BM2 Pins
1000 SPI (SW) < Fmax N/A N/A 00 0 < Fmax T he boot program automatically
determines whether EEPROM
or Flash memory.
1001 SPI (SW) 15.6-25 MHz 1 17 11 0 133–212.5 MHz
1010 SPI (SW) 33-50 MHz 2 16 11 0 132–200 MHz
1011 SPI (SW) 44.3-75 MHz 3 18 11 0 133–225 MHz
SPI Boot Modes - Using URXD, UTXD, SCL, SDA Pins
1100 SPI (SW) < Fmax N/A N/A 00 0 < Fmax Boots through different set of
pins.
I2C Boot Modes
0001 I2C < 100 MHz N/ A N/A 00 0 < 100 MHz Not clocked by the PLL.
I2C is limited to a maximum bit
rate of 400 Kbps. With a clock
divider of 128, this limits the
maximum input clock frequency
to 100 MHz.
Reserved
0011 Reserved — — — — — — —
0110 Reserved — — — — — — —
1101 Reserved — — — — — — —
1110 Reserved — — — — — — —
1111 Reserved — — — — — — —
Notes: 1. The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.
2. The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.
3. Fmax is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 53
When booting from a power-on reset, the HDI16 is additionally configur able as follo ws:
• 8- or 16-bit mode as specified by the H8BIT pin.
• Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note: When the HDI16 is used fo r boot ing or other pu rposes , bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
3.4.3.2 I2C Boot
When the MSC7116 device is configured to boot from the I2C port, the boot program configures the GPIO pins for I2C
operation. Then the MSC7116 d evice in itiates accesses to the I2C module, downloading data to the MSC7116 device. The I2C
interface is configured as follows:
• PLL is disabled and bypassed so that the I2C module is clocked with the IPBus clock.
•I
2C interface operates in master mode and polling is used.
• EPROM operates in slave mode.
• Clock divider is set to 128.
• Address of slave during boot is 0xA0.
The IPBus clock is internally divid ed to gene r ate the bit clock, as follows:
• CLKIN must be a maximum of 100 MHz
• PLL is bypassed.
• IPBus clock = CLKIN/2 is a maximum of 50 MHz.
•I
2C bit clock must be less than or equal to :
— IPBus clock/I2C clock divider
— 50 MHz (max)/128
— 390.6 KHz
This satisfies the maximum clock rate requirement of 400 kbps for the I2C interf ace. For details on th e bo ot p roce dure, s ee th e
“Boot Program” chapter of the MSC711x Reference Manual.
3.4.3.3 SPI Boot
When the MSC7116 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI
operation. Then the MSC7116 device initiates accesses to the SPI module, downloading data to the MSC7116 device. When
the SPI routines run in the boot ROM, th e MSC7116 is always configured as the SPI master. Booting through the SPI is
supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory
device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum
frequency of 4 Mbps. Otherwise, the routines for acces sing a serial Flash are used, and they can run at faster speeds. Boot ing is
perfor med throu gh one of two set s of pins:
• Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.
• Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL.
In either conf iguration, an error d uring SPI boot is flagged o n the EVNT3 pin. For details on the boot pr ocedure, see the “Boot
Program” chapter of the MSC711x Reference Manual .
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor54
3.5 DDR Memory System Guidelines
MSC7116 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM
memory modules with Class 2 Series Stub T ermination Logic 2.5 V (SSTL_2). There are two termination techniques, as sh own
in Figure 36. Techniq ue B is th e most popular termination technique.
Figure 37 illustrates the power wattage for the resistors . Typical values for the resistors are as follows:
• RS = 22 Ω
•RT = 24 Ω
Figure 36. SSTL Termination Techniques
Controller
Address
Command
Chip Selects
Data
Strobes
Mask
VREF
VTT Terminator
VTT
Generator
DDR
Bank DDR
Bank
VTT
SSTL_2
SSTL_2
SSTL_2
RS
RT
RT
RS
Controller
Address
Command
Chip Selects
Data
Strobes
Mask
VTT Terminator Island
VTT
Generator
DDR
Bank DDR
Bank
SSTL_2
SSTL_2
SSTL_2
RS
RT
RT
RS
Technique A
Technique B
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 55
3.5.1 VREF and VTT Design Constraints
VTT and VREF are isolated power supp lies at the sam e voltage, with VTT as a high current power sou rce. This section ou tlines
the voltage su ppl y desig n needs and goals:
• Minimize the noise on both rails.
•V
TT must track variation in the VREF DC of fsets. Although they are isolated supplies, one possible solution is to use a
single IC to generate both signals.
• Both references should have minimal drift over temperature and source supply.
• It is important to minimize the noise from couplin g ont o VREF as follows:
— Isolate VREF and shield it with a ground trace.
— Use 15–20 mm track.
— Use 20–30 mm clearance between other traces for isolating.
— Use the outer layer route when possible.
— Use distributed decoupling to localize transient currents and re turn path and decouple with an inductance less than
3 nH.
• Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.
• Use a wide island trace on the outer layer:
— Place the island at the end of the bus.
— Decouple both ends of the bus.
— Use distributed decoupling across the island.
— Place SSTL termination resistors inside the VTT island and ensure a good, solid connection.
• Place the VTT regulator as closely as possib le to the ter mination island.
— Reduce inductance and return path.
— Tie current se nse pin at the midpoint of the is land.
3.5.2 Decoupling
The DDR decoupling considerations are as follows:
• DDR memory requires significantly more burst current than previous SDRAMs.
• In the worst case, up to 64 drivers may be switching states.
• Pay special attention and decouple discrete ICs per manufacturer guidelines.
• Leverage VTT island topology to minimize the nu mber o f capacitor s required to supply the burst current needs of the
termination rail.
• See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel
(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).
Figure 37. SSTL Power Value
Driver
Receiver
VREF
VDDQ
VSS
V
TT
RS
RT
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freesca le Sem ico nd uctor56
3.5.3 General Routing
The general routing considerations for the DDR are as follows:
• All DDR signals must be routed next to a solid reference:
— For data, next to solid ground planes.
— For address/command, power planes if necessary.
• All DDR signals must be impedance contro lled. This is system dependent, but typical values ar e 50– 60 ohm .
• Minimize other cr oss-talk opportunities. As possible, maintain at leas t a four times the trace width s pacing between all
DDR signals to non-DDR sig nals.
• Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
• Signal group routing priorities are as follows:
— DDR clocks.
— Route MVTT/MVREF.
— Data group.
— Command/address.
• Minimize data bit jitter by trace matching.
3.5.4 R outing Clock Distri bution
The DDR clock distribution considerations are as follows:
• DDR controller supports six clock pairs:
— 2 DIMM modules.
— Up to 36 discrete chips.
• For route traces as for any other differential signals:
— Maintain proper diff erence pair spacing.
— Match pair traces within 25 mm.
• Match all clock traces to within 100 mm.
• Keep all clocks equally loaded in the system.
• Route clocks on inner critical layers.
3.5.5 Data Routing
The DDR data routing considerations are as follows:
• Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
• Take care to match trace lengths, which is extremely important.
• To make trace matching easier, let adjacent groups be routed on alternate critical layers.
• Pin swap bits within a byte group to facilitate routing (discrete case) .
• Tight trace matching is recommended within the DDR data grou p. Keep each 8-b it datum and its DM sig nal within ±
25 mm of its respectiv e strobe.
• Minimize lengths across the entire DDR channel:
— Between all groups maintain a delta of no more than 500 mm.
— Allows greater flexibility in the d esign for readjustments as needed.
• DDR data group separation:
— If stack-up allows, keep DDR data groups away from the address and control nets.
— Route address and control on separate critical layers.
— If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
Ordering Information
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 57
3.6 Connectivity Guidelines
This section summarizes the conn ectio ns and special conditions, such as pull-up or pull-down resistors, for the MSC 7116
device. Following are guidelines for signal groups and configuration settings:
•Clock and reset signals.
—SWTE is used to configure the MSC7116 device and is sampled on the deassertion of PORESET, so it should be
tied to VDDC or GND either directly or through pull-up or pull-down resistors until PORESET is deasserted. After
PORESET, this signal can be left floating.
—BM[0–1] configure the MSC71 16 device and are sampled until PORESET is deasserted, so they should be tied to
VDDIO or GND either directly or through pull-up or pull-down resistors.
—HRESET should be pulled up.
•Inte rr up t si gnals. When used, IRQ pins must be pulled up.
•HDI16 signals.
— When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor.
However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be
pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with
the HRESET signal as the enable.
— When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down,
depending on the required boot mode settings.
•Ethernet MAC/TDM2 signals. The MDIO signal requires an external pull-up resistor.
•I2C signals. The SCL and SDA signals, when programmed for I2C, requires an external pull-up resistor.
•General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an output
pin.
• Other signals.
—The
TEST0 pin must be connected to ground.
—The
TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary
scan.
— Pins labelled NO CONNECT (NC) must not be connected.
— When a 16-pin do uble data rate (DDR) interface is used, the 16 unused data pins should be no connects (floating)
if the used lines are terminated.
— Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the EVNT
pins, and DBREQ to HRRQ.
4 Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Part Supply Voltage Package Type Pin
Count
Core
Frequency
(MHz) Solder Spheres Order Number
MSC7 116 1.2 V core
2.5 V memory
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA) 400 266 Lead-free MSC7116VM1000
Lead-bearing MSC7116VF1000
MSC7116 Data Sheet, Rev. 13
Package Information
Freesca le Sem ico nd uctor58
5 Package Information
6 Product Documentation
•MSC711x Reference Manual (MSC711xRM). Includes fun ctional descriptions of the extended cores and all th e
internal subsystems including configuration and pro gram ming information.
•Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7116 device.
•SC140/SC 1400 DSP Cor e Refer ence Manual. Covers the SC140 and SC1400 core architecture, control registers, clock
registers, program control, and instruction set.
Figure 38. MSC7116 Mechanical Information, 400-pin MAP-BGA Package
CASE 1568-01
Notes:
1. All dimensions in millimeters.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Maximum solder ball diameter
measured parallel to Datum A
.
4. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
5. Parallelism measurement sha
ll
exclude any effect of mark on
top surface of package.
Revision History
MSC7116 Data Sheet, Rev. 13
Freescale Semicond uc tor 59
7 Revision History
Table 36 provi des a r evision history for this data sheet.
Table 36. Document Revision History
Revision Date Description
0 Apr 2004 • Initial pu blic release.
1 May 2004 • Added order ing information and new pack age optio ns.
2 Aug. 2004 • Update d clock pa ra m eter valu es .
• Updated DDR timing speci fic at ions .
• Updated I2C timing specifications.
3 Sep. 2004 • Updated Figures 1-2 and 1-2 to correct HDSP and DBREQ.
• Corrected EE0 port reference.
• Update d ball loc a tio n for HDS P.
4 Jan. 2005 • A dded signal HA3.
• Updated absolute maximum rat i ngs, DDR DRAM capacitance specifications, clock p aramet ers, reset
timing, and TDM timing.
• Added note for timing reference for I2C interface.
• Expanded GPIO timing i nf ormati on.
• Corrected pin T20 and K20 sig nal designa tion.
• Corrected sign al names to GPAO 15 and IRQ2.
• Expanded design guidelines in Chapter 4.
5 Mar. 2005 • Updated features list.
• Updated power specifications.
• Changed CLKIN frequency range.
• Added clock conf iguration infor mation.
• Updated JTAG timings.
6 Apr. 2005 • Added recommended power supply ratings and updated equations to estimate p ower consumpti on.
7 Oct. 2005 • U pdated core an d total power consumption examples.
8 Dec. 2005 • Added information about the new mask set 1M88B. Affected all sections.
9 Nov. 2006 • Updated arrows in Host DMA Writing Timing figure.
• Updated boot overview in Section 4.4.3.
10 Apr. 2007 • Remo ved erron eous references to VCCSYN and V CCSYN1.
11 Jul. 2007 • Updated to new data sheet format. Reorganized an d renumbered sect ions, figures, and tables.
• Removed all references to obsolete mask set 1L44X and corresponding specification values.
• Added a note to clarify the definition of TCK timing 700 in new Table 31.
• Reworked rese t and boot sec tio n s.
• Expanded I2C boot information and added SPI boot information.
• Removed obsolete part n umbers.
12 Aug 2007 • The power-up and power-down sequences described in Section 3.2 starting on page 42 have been expa nded
to five possibl e design scen ari os/ cases. These ca ses replace the previously recommended
power-up/power-down sequence recommendations. Section 3.2 has been clarified by addi ng subsect ion
headings.
13 Apr 2008 • Change the PLL filter resistor from 20 Ω to 2 Ω in Section 3.2.5.
Document Number: MSC7116
Rev. 13
4/2008
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