Freescale Semiconductor
Data Sheet Document Number: MSC7116
Rev. 13, 4/2008
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
MSC7116
MAP-BGA–400
17 mm ×17 mm
•StarCore
® SC1400 DSP extended core with one SC1400 DSP
cor e, 192 Kb yte of i nternal SRAM M1 me mory, 16 wa y 16 Kbyte
instruction cache (ICache), four-entry write buffer , programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
• 192 Kbyte M2 memory for critical data and temporary data
buffering.
• 8 Kbyt e boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
between fou r mast er ports and six slave p ort s, where each port
connec ts to an AHB-Lite bus; fixed or round robi n priority
programmab le at each slave port; programmable bus parki ng at
each slave port; low power mode.
• Inte rnal PLL g enerate s up to 266 MHz clock for the S C1400 core
and up to 133 MHz for t he crossbar switch, DMA channels, M2
memory, and other periph erals.
• Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
• DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 133 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
• Progra mmable mem ory interfa ce with ind e pend e nt read buffers,
programmable predictive read feature for each buffer , and a write
buffer.
• System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite maste r buses; and has address
out-of-range detection on each crossbar switch buses.
• Event port collects and counts important signal events including
DMA and interrupt requests an d trigger events su ch as interrupts,
breakpoints, DMA t ransfers, or wake-up ev ents; units ope rate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
• Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between chann el s using 32 interna l prio rity level s, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
• Two independent TDM modules with independent receive and
transmit, programmable sharing of frame sync and cloc k,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 cha nnels, with gl ueles s interfa ce to E1/T1 fr ames and MV IP,
SCAS, and H.110 buses.
• Ethernet controller with support for 10/100 Mbps MII/RMII
designed to comply with IEEE Std. 80 2.3™, 802.3u™, 802.3x™,
and 802. 3ac™; with internal receive and transmit FIFOs and a
FIFO controller; direct access to internal memories via its own
DMA controller; full and half duplex operation; programmable
maximum frame length; virtual l ocal area network ( VLAN) tag
and priority support; retransmission of transmit FIFO following
collision; CRC generation and verification for inbound and
outbo und packets; and ad dress recognition i ncluding
promiscuous, broadcast, individual address. hash/exact match,
and multicast ha sh matc h.
• UART with full-du pl ex oper atio n up to 5 .0 Mb ps.
• Up to 41 general-purpose input/output (GPIO) ports.
•I
2C interface that allows booting from EEPROM devices up to 1
Mbyte.
• Two quad timer modules, each with sixteen configurable 16-bit
timers.
• fieldBIST™ u nit detects and p rovides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated sp eed, is free from
reliability de fec ts, a n d r eport s di agno stic s fo r part ia l o r com p lete
device ino per ab ility.
• Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
• Optional booti ng external host via 8-bit or 16-bit access through
the HDI16, I2C, or SPI using in the boot ROM to access serial SPI
Flash /E EPROM devices; different clocking opt ions during boot
with the PLL on or off using a variety of input frequency ranges.
Low-Cost 16-bit DSP with
DDR Contr oller an d 10 /1 00
Mbps Ethernet MAC