TPS731xx
GNDEN NR
IN OUT
VIN VOUT
Optional Optional
Optional
ON
OFF
DBVPACKAGE
SOT23
(TOPVIEW)
OUT
NR/FB
IN
GND
EN
1
2
3
5
4
TypicalApplicationCircuitforFixed-VoltageVersions
TPS731xx
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.......................................................................................................................................... SBVS034M SEPTEMBER 2003REVISED AUGUST 2009
Cap-Free, NMOS, 150mA Low Dropout Regulator
with Reverse Current Protection
1FEATURES DESCRIPTION
2 Stable with No Output Capacitor or Any Value The TPS731xx family of low-dropout (LDO) linear
or Type of Capacitor voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
Input Voltage Range of 1.7V to 5.5V topology is stable using output capacitors with low
Ultralow Dropout Voltage: 30mV Typ ESR, and even allows operation without a capacitor.
Excellent Load Transient Response—with or It also provides high reverse blockage (low reverse
without Optional Output Capacitor current) and ground pin current that is nearly constant
over all values of output current.
New NMOS Topology Provides Low Reverse
Leakage Current The TPS731xx uses an advanced BiCMOS process
to yield high precision while delivering very low
Low Noise: 30μVRMS Typ (10kHz to 100kHz) dropout voltages and low ground pin current. Current
0.5% Initial Accuracy consumption, when not enabled, is under 1μA and
1% Overall Accuracy over Line, Load, and ideal for portable applications. The extremely low
Temperature output noise (30μVRMS with 0.1μF CNR) is ideal for
powering VCOs. These devices are protected by
Less Than 1μA Max IQin Shutdown Mode thermal shutdown and foldback current limit.
Thermal Shutdown and Specified Min/Max
Current Limit Protection
Available in Multiple Output Voltage Versions
Fixed Outputs of 1.20V to 5.0V
Adjustable Outputs from 1.20V to 5.5V
Custom Outputs Available
APPLICATIONS
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
space
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS731xx
SBVS034M SEPTEMBER 2003REVISED AUGUST 2009..........................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS731xx yy yz XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Zis package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
PARAMETER TPS731xx UNIT
VIN range –0.3 to 6.0 V
VEN range –0.3 to 6.0 V
VOUT range –0.3 to 5.5 V
VNR, VFB range –0.3 to 6.0 V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, TJ–55 to +150 °C
Storage temperature range –65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR TA25°C TA= 70°C TA= 85°C
BOARD PACKAGE RΘJC RΘJA ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING
Low-K (2) DBV 64°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW
High-K (3) DBV 64°C/W 180°C/W 5.6mW/°C 560mW 310mW 225mW
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
TPS731xx
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.......................................................................................................................................... SBVS034M SEPTEMBER 2003REVISED AUGUST 2009
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= -40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1μF, unless otherwise noted. Typical values are at TJ= +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 1.7 5.5 V
VFB Internal reference (TPS73101) TJ= +25°C 1.198 1.20 1.210 V
Output voltage range (TPS73101)(2) VFB 5.5 VDO V
Nominal TJ= +25°C –0.5 +0.5
VOUT Accuracy(1) (3) %
VOUT + 0.5V VIN 5.5V;
VIN, IOUT, and T –1.0 ±0.5 +1.0
10 mA IOUT 150mA
ΔVOUT%/ΔVIN Line regulation(1) VOUT(nom) + 0.5V VIN 5.5V 0.01 %/V
1mA IOUT 150mA 0.002
ΔVOUT%/ΔIOUT Load regulation %/mA
10mA IOUT 150mA 0.0005
Dropout voltage(4)
VDO IOUT = 150mA 30 100 mV
(VIN = VOUT (nom) 0.1V)
ZO(DO) Output impedance in dropout 1.7 V VIN VOUT + VDO 0.25
ICL Output current limit VOUT = 0.9 × VOUT(nom) 150 360 500 mA
ISC Short-circuit current VOUT = 0V 200 mA
IREV Reverse leakage current(5) (–IIN) VEN 0.5V, 0V VIN VOUT 0.1 10 μA
IOUT = 10mA (IQ) 400 550
IGND GND pin current μA
IOUT = 150mA 550 750
VEN 0.5V, VOUT VIN 5.5,
ISHDN Shutdown current (IGND) 0.02 1 μA
–40°C TJ+100°C
IFB FB pin current (TPS73101) 0.1 0.3 μA
f = 100Hz, IOUT = 150 mA 58
Power-supply rejection ratio
PSRR dB
(ripple rejection) f = 10kHz, IOUT = 150 mA 37
COUT = 10μF, No CNR 27 × VOUT
Output noise voltage
VNμVRMS
BW = 10Hz - 100kHz COUT = 10μF, CNR = 0.01μF 8.5 × VOUT
VOUT = 3V, RL= 30
tSTR Startup time 600 μs
COUT = 1μF, CNR = 0.01μF
VEN(HI) EN pin high (enabled) 1.7 VIN V
VEN(LO) EN pin low (shutdown) 0 0.5 V
IEN(HI) EN pin current (enabled) VEN = 5.5V 0.02 0.1 μA
Shutdown Temp increasing +160
TSD Thermal shutdown temperature °C
Reset Temp decreasing +140
TJOperating junction temperature –40 +125 °C
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
(2) TPS73101 is tested at VOUT = 2.5V.
(3) Tolerance of external resistors not included in this specification.
(4) VDO is not measured for fixed output versions with VOUT(nom) < 1.8V since minimum VIN = 1.7V.
(5) Fixed-voltage versions only; refer to the Applications section for more information.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Servo
Error
Amp
Ref
27k
8k
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R1
R2
EN
GND
IN
R1+ R2= 80k
4MHz
Charge Pump
VO
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
R1
Short
23.2k
28.0k
39.2k
44.2k
46.4k
52.3k
R2
Open
95.3k
56.2k
36.5k
33.2k
30.9k
30.1k
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
NOTE: VOUT = (R1 + R2)/R2 × 1.204;
R1R2 19k for best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Thermal
Protection
Bandgap
OUT
FB
R1
R2
EN
GND
IN
80k
8k
27k
4MHz
Charge Pump
TPS731xx
SBVS034M SEPTEMBER 2003REVISED AUGUST 2009..........................................................................................................................................
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FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Fixed Voltage Version
Figure 2. Adjustable Voltage Version
4Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5
TPS731xx
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.......................................................................................................................................... SBVS034M SEPTEMBER 2003REVISED AUGUST 2009
PIN CONFIGURATION
PIN DESCRIPTIONS
SOT23
(DBV)
NAME PIN NO. DESCRIPTION
IN 1 Input supply
GND 2 Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
EN 3 mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to
IN if not used.
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the
NR 4 internal bandgap, reducing output noise to very low levels.
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
FB 4 output voltage of the device.
OUT 5 Output of the regulator. There are no output capacitor requirements for stability.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
Change in VOUT (%)
0 15 30 45 60 75 90 105 120 135 150
IOUT (mA)
Referred to IOUT = 10mA
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
Change in VOUT (%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIN VOUT (V)
+125_C+25_C
40_C
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
50
40
30
20
10
0
VDO (mV)
0 30 60 90 120 150
IOUT (mA)
+125_C
TPS73125DBV
+25_C
40_C
50
40
30
20
10
0
VDO (mV)
50 25 0 25 50 75 100 125
Temperature (_C)
TPS73125DBV
IOUT = 150mA
30
25
20
15
10
5
0
Percent of Units (%)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOUT Error (%)
IOUT = 10mA
18
16
14
12
10
8
6
4
2
0
Percent of Units (%)
100
90
80
70
60
50
40
30
20
10
0
10
20
30
40
50
60
70
80
90
100
Worst Case dVOUT/dT (ppm/_C)
IOUT = 10mA
All Voltage Versions
TPS731xx
SBVS034M SEPTEMBER 2003REVISED AUGUST 2009..........................................................................................................................................
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TYPICAL CHARACTERISTICS
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 5. Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
Figure 7. Figure 8.
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ICL
400
350
300
250
200
150
100
50
0
OutputCurrent(mA)
ISC
-0.5 0 1.0 1.5 2.0 2.5 3.0 3.5
OutputVoltage(V)
0.5
TPS73133
1
0.1
0.01
IGND (µA)
50 25 0 25 50 75 100 125
Temperature (_C)
VENABLE = 0.5V
VIN = VO+ 0.5V
TPS731xx
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.......................................................................................................................................... SBVS034M SEPTEMBER 2003REVISED AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE CURRENT LIMIT vs VOUT (FOLDBACK)
Figure 11. Figure 12.
CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE
Figure 13. Figure 14.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
40
35
30
25
20
15
10
5
0
PSRR(dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V V-(V)
IN OUT
Frequency=10kHz
C =10 F
V =2.5V
I =100mA
m
OUT
OUT
OUT
10k10
90
80
70
60
50
40
30
20
10
0
RippleRejection(dB)
100 1k 100k 1M 10M
Frequency(Hz)
I =1mA
OUT
C =1 Fm
OUT
I =Any
OUT
C =0 Fm
OUT
V =V +1V
IN OUT
I =1mA
OUT
C =Any
OUT
I =1mA
OUT
C =10 Fm
OUT
I =100mA
OUT
C =Any
OUT
I =100mA
OUT
C =10 Fm
OUT
I =100mA
O
C =1 Fm
O
1
0.1
0.01
eN(µV/Hz)
10 100 1k 10k 100k
Frequency (Hz)
COUT = 1µF
COUT = 0µF
COUT = 10µF
IOUT = 150mA
1
0.1
0.01
eN(µV/Hz)
10 100 1k 10k 100k
Frequency (Hz)
IOUT = 150mA
COUT = 1µF
COUT = 0µF
COUT = 10µF
60
50
40
30
20
10
0
VN(RMS)
COUT (µF)
0.1 1 10
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
CNR = 0.01µF
10Hz < Frequency < 100kHz
140
120
100
80
60
40
20
0
VN(RMS)
CNR (F)
1p 10p 100p 1n 10n
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
TPS731xx
SBVS034M SEPTEMBER 2003REVISED AUGUST 2009..........................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN VOUT
Figure 15. Figure 16.
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY
CNR = 0μF CNR = 0.01μF
Figure 17. Figure 18.
RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR
Figure 19. Figure 20.
8Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
10µs/div
40mV/tick
40mV/tick
40mV/tick
25mA/tick
VIN = 3.8V COUT = 0µF
COUT = 1µF
COUT = 10µF
10mA
150mA
VOUT
VOUT
VOUT
IOUT
10µs/div
50mV/div
50mV/div
1V/div
VOUT
VOUT
VIN
IOUT = 150mA
5.5V
4.5V
dVIN
dt = 0.5V/µs
COUT = 0µF
COUT = 100µF
100µs/div
1V/div
1V/div
RL= 20
COUT = 10µF
2V
0V
RL= 1k
COUT = 0µF
RL= 20
COUT = 1µF
VOUT
VEN
100µs/div
1V/div
1V/div
RL= 20
COUT = 10µF
2V
0V
RL= 1k
COUT = 0µF
RL= 20
COUT = 1µF
VOUT
VEN
6
5
4
3
2
1
0
1
2
Volts
50ms/div
VIN
VOUT
10
1
0.1
0.01
IENABLE (nA)
50 25 0 25 50 75 100 125
Temperature (_C)
TPS731xx
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.......................................................................................................................................... SBVS034M SEPTEMBER 2003REVISED AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
TPS73133 TPS73133
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 21. Figure 22.
TPS73133 TPS73133
TURN-ON RESPONSE TURN-OFF RESPONSE
Figure 23. Figure 24.
TPS73133
POWER UP / POWER DOWN IENABLE vs TEMPERATURE
Figure 25. Figure 26.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
60
55
50
45
40
35
30
25
20
VN(rms)
CFB (F)
10p 100p 1n 10n
VOUT = 2.5V
COUT = 0µF
R1= 39.2k
10Hz < Frequency < 100kHz
5µs/div
100mV/div
100mV/div
VOUT
VOUT
VIN
4.5V
3.5V
COUT = 0µF
VOUT = 2.5V
CFB = 10nF
COUT = 10µF
25µs/div
50mV/div
50mV/div
VOUT
VOUT
IOUT
150mA
10mA
COUT = 0µF
CFB = 10nF
R1= 39.2k
COUT = 10µF
TPS731xx
SBVS034M SEPTEMBER 2003REVISED AUGUST 2009..........................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
TPS73101 TPS73101
RMS NOISE VOLTAGE vs CFB IFB vs TEMPERATURE
Figure 27. Figure 28.
TPS73101 TPS73101
LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
Figure 29. Figure 30.
10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
TPS731xx
GNDEN
ON
OFF
NR
IN OUT
VIN VOUT
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalbypass
capacitortoreduce
outputnoise.
VN+32mVRMS (R1)R2)
R2
+32mVRMS VOUT
VREF
TPS73101
GNDEN FB
IN OUT
VIN VOUT
VOUT = x1.204
(R1+ R2)
R2
R1CFB
R2
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalcapacitor
reducesoutputnoise
andimproves
transientresponse.
OFF ON
VN(mVRMS)+27ǒmVRMS
VǓ VOUT(V)
TPS731xx
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.......................................................................................................................................... SBVS034M SEPTEMBER 2003REVISED AUGUST 2009
APPLICATION INFORMATION
For best accuracy, make the parallel combination of
The TPS731xx belongs to a family of new generation R1and R2approximately equal to 19k. This 19k,
LDO regulators that use an NMOS pass transistor to in addition to the internal 8kresistor, presents the
achieve ultra-low-dropout performance, reverse same impedance to the error amp as the 27k
current blockage, and freedom from output capacitor bandgap reference output. This impedance helps
constraints. These features, combined with low noise compensate for leakages into the error amp
and an enable input, make the TPS731xx ideal for terminals.
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an INPUT AND OUTPUT CAPACITOR
adjustable output version. All versions have thermal REQUIREMENTS
and over-current protection, including foldback
current limit. Although an input capacitor is not required for
stability, it is good analog design practice to connect
Figure 31 shows the basic circuit connections for the a 0.1μF to 1μF low ESR capacitor across the input
fixed voltage models. Figure 32 gives the connections supply near the regulator. This counteracts reactive
for the adjustable output version (TPS73101). input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
The TPS731xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing
may occur when the product of COUT and total ESR
drops below 50nF. Total ESR includes all parasitic
resistances, including capacitor ESR and board,
socket, and solder joint resistance. In most
Figure 31. Typical Application Circuit for applications, the sum of capacitor ESR and trace
Fixed-Voltage Versions resistance will meet this requirement.
OUTPUT NOISE
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS731xx and
it generates approximately 32μVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
(1)
Since the value of VREF is 1.2V, this relationship
Figure 32. Typical Application Circuit for reduces to:
Adjustable-Voltage Version
R1and R2can be calculated for any output voltage (2)
using the formula shown in Figure 32. Sample for the case of no CNR.
resistor values for common output voltages are
shown in Figure 2.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
VN(mVRMS)+8.5ǒmVRMS
VǓ VOUT(V)
TPS731xx
SBVS034M SEPTEMBER 2003REVISED AUGUST 2009..........................................................................................................................................
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An internal 27kresistor in series with the noise ENABLE PIN AND SHUTDOWN
reduction pin (NR) forms a low-pass filter for the The enable pin (EN) is active high and is compatible
voltage reference when an external noise reduction with standard TTL-CMOS levels. A VEN below 0.5V
capacitor, CNR, is connected from NR to ground. For (max) turns the regulator off and drops the GND pin
CNR = 10nF, the total noise in the 10Hz to 100kHz current to approximately 10nA. When EN is used to
bandwidth is reduced by a factor of ~3.2, giving the shutdown the regulator, all charge is removed from
approximate relationship: the pass transistor gate, and the output ramps back
up to a regulated VOUT (see Figure 23).
(3) When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
for CNR = 10nF. discharged using this configuration, and the pass
transistor may be left on (enhanced) for a significant
This noise reduction effect is shown as RMS Noise time after VIN has been removed. This scenario can
Voltage vs CNR in the Typical Characteristics section. result in reverse current flow (if the IN pin is low
The TPS73101 adjustable version does not have the impedance) and faster ramp times upon power-up. In
NR pin available. However, connecting a feedback addition, for VIN ramp times slower than a few
capacitor, CFB, from the output to the feedback pin milliseconds, the output may overshoot upon
(FB) reduces output noise and improves load power-up.
transient performance. Note that current limit foldback can prevent device
The TPS731xx uses an internal charge pump to start-up under some conditions. See the Internal
develop an internal supply voltage sufficient to drive Current Limit section.
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250μV of switching noise at DROPOUT VOLTAGE
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most The TPS731xx uses an NMOS pass transistor to
values of IOUT and COUT. achieve extremely low dropout. When (VIN VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
BOARD LAYOUT RECOMMENDATION TO input-to-output resistance is the RDS-ON of the NMOS
IMPROVE PSRR AND NOISE PERFORMANCE pass element.
To improve ac performance such as PSRR, output For large step changes in load current, the TPS731xx
noise, and transient response, it is recommended that requires a larger voltage drop from VIN to VOUT to
the PCB be designed with separate ground planes for avoid degraded transient response. The boundary of
VIN and VOUT, with each ground plane connected only this transient dropout region is approximately twice
at the ground pin (GND) of the device. In addition, the the dc dropout. Values of VIN VOUT above this line
ground connection for the bypass capacitor should insure normal transient response.
connect directly to the GND pin of the device. Operating in the transient dropout region can cause
INTERNAL CURRENT LIMIT an increase in recovery time. The time required to
recover from a load transient is a function of the
The TPS731xx internal current limit helps protect the magnitude of the change in load current rate, the rate
regulator during fault conditions. Foldback current of change in load current, and the available
limit helps to protect the regulator from damage headroom (VIN to VOUT voltage drop). Under
during output short-circuit conditions by reducing worst-case conditions [full-scale instantaneous load
current limit when VOUT drops below 0.5V. See change with (VIN VOUT) close to dc dropout levels],
Figure 12 in the Typical Characteristics section. the TPS731xx can take a couple of hundred
Note from Figure 12 that approximately –0.2V of VOUT microseconds to return to the specified regulation
results in a current limit of 0mA. Therefore, if OUT is accuracy.
forced below –0.2V before EN goes high, the device
may not start up. In applications that work with both a
positive and negative voltage supply, the TPS731xx
should be enabled first.
12 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
dVńdt +VOUT
COUT 80kWøRLOAD
dVńdt +VOUT
COUT 80kWø(R1)R2)øRLOAD
TPS731xx
www.ti.com
.......................................................................................................................................... SBVS034M SEPTEMBER 2003REVISED AUGUST 2009
TRANSIENT RESPONSE After the EN pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
The low open-loop output impedance provided by the that reverse current is specified as the current flowing
NMOS pass element in a voltage follower out of the IN pin due to voltage applied on the OUT
configuration allows operation without an output pin. There will be additional current flowing into the
capacitor for many applications. As with any OUT pin due to the 80kinternal resistor divider to
regulator, the addition of a capacitor (nominal value ground (see Figure 1 and Figure 2).
1μF) from the output pin (OUT) to ground will reduce
undershoot magnitude but increase its duration. In For the TPS73101, reverse current may flow when
the adjustable version, the addition of a capacitor, VFB is more than 1.0V above VIN.
CFB, from the OUT pin to the FB pin will also improve
the transient response. THERMAL PROTECTION
The TPS731xx does not have active pull-down when Thermal protection disables the output when the
the output is over-voltage. This allows applications junction temperature rises to approximately +160°C,
that connect higher voltage sources, such as allowing the device to cool. When the junction
alternate power supplies, to the output. This also temperature cools to approximately +140°C, the
results in an output overshoot of several percent if the output circuitry is again enabled. Depending on power
load current quickly drops to zero when a capacitor is dissipation, thermal resistance, and ambient
connected to the output. The duration of overshoot temperature, the thermal protection circuit may cycle
can be reduced by adding a load resistor. The on and off. This limits the dissipation of the regulator,
overshoot decays at a rate determined by output protecting it from damage due to overheating.
capacitor COUT and the internal/external load Any tendency to activate the thermal protection circuit
resistance. The rate of decay is given by: indicates excessive power dissipation or an
(Fixed voltage version) inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(4) (including heatsink), increase the ambient
temperature until the thermal protection is triggered;
(Adjustable voltage version) use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
(5) condition of your application. This produces a
worst-case junction temperature of +125°C at the
REVERSE CURRENT highest expected ambient temperature and
worst-case load.
The NMOS pass element of the TPS731xx provides
inherent protection against current flow from the The internal protection circuitry of the TPS731xx has
output of the regulator to the input when the gate of been designed to protect against overload conditions.
the pass device is pulled low. To ensure that all It was not intended to replace proper heatsinking.
charge is removed from the gate of the pass element, Continuously running the TPS731xx into thermal
the EN pin must be driven low before the input shutdown degrades device reliability.
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
PD+(VIN *VOUT) IOUT
TPS731xx
SBVS034M SEPTEMBER 2003REVISED AUGUST 2009..........................................................................................................................................
www.ti.com
POWER DISSIPATION (6)
The ability to remove heat from the die is different for Power dissipation can be minimized by using the
each package type, presenting different lowest possible input voltage necessary to assure the
considerations in the PCB layout. The PCB area required output voltage.
around the device that is free of other components
moves the heat from the device to the ambient air. PACKAGE MOUNTING
Performance data for JEDEC low- and high-K boards Solder pad footprint recommendations for the
are shown in the Power Dissipation Ratings table. TPS731xx are presented in Application Bulletin
Using heavier copper will increase the effectiveness Solder Pad Recommendations for Surface-Mount
in removing heat from the device. The addition of Devices (SBFA015), available from the Texas
plated through-holes to heat-dissipating layers also Instruments web site at www.ti.com.
improves the heat-sink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
space REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (May, 2009) to Revision M ..................................................................................................... Page
Changed Figure 12 ............................................................................................................................................................... 7
Added paragraph about recommended start-up sequence to Internal Current Limit section ............................................. 12
Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section ................................ 12
14 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS73101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73101DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73101DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS731125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS731125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS731125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS731125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73115DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73115DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73115DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73115DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73118DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73118DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73118DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73118DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73130DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73130DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73130DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73130DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73131DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS73131DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73131DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73131DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73132DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73132DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73132DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73132DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73133DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73133DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73133DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73133DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73150DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73150DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73150DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73150DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2009
Addendum-Page 2
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73101, TPS731125, TPS73115, TPS73118, TPS73125, TPS73130, TPS73132, TPS73133, TPS73150 :
Enhanced Product: TPS73101-EP,TPS731125-EP,TPS73115-EP,TPS73118-EP,TPS73125-EP,TPS73130-EP,TPS73132-EP,
TPS73133-EP,TPS73150-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2009
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73101DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73101DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS731125DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS731125DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73115DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73115DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73118DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73118DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73125DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73125DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73130DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73130DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73131DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73131DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73132DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73132DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73133DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73133DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Aug-2009
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73150DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73150DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73101DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73101DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS731125DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS731125DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73115DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73115DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73118DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73118DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73125DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73125DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73130DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73130DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73131DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73131DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73132DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Aug-2009
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73132DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73133DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73133DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
TPS73150DBVR SOT-23 DBV 5 3000 195.0 200.0 45.0
TPS73150DBVT SOT-23 DBV 5 250 195.0 200.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Aug-2009
Pack Materials-Page 3
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