FEATURES Delivers true rms or average rectified value of an ac waveform Fast settling at all input levels Accuracy: 10 V 0.5% of reading Wide dynamic input range 100 V rms to 3 V rms (8.5 V p-p) full-scale input range Larger inputs with external scaling Wide bandwidth: 1 MHz for -3 dB (300 mV) 65 kHz for additional 1% error Zero converter dc output offset No residual switching products Specified at 300 mV rms input Accurate conversion with crest factors up to 10 Low power: 300 A typical at 2.4 V High-Z FET separately powered input buffer RIN 1012 , CIN 2 pF Precision dc output buffer Wide power supply voltage range Dual: 2.4 V to 18 V; single: 4.8 V to 36 V 4 mm x 4 mm LFCSP and 8 mm x 6 mm QSOP packages ESD protected FUNCTIONAL BLOCK DIAGRAM CAVG CCF VCC 100k SUM RMS IGND 8k 100k RMS CORE VEE 16k OUT 10pF IBUFGN 10k 10k IBUFIN- - IBUFIN+ + OBUFIN+ OBUFIN- FET OP AMP + 16k OGND DC BUFFER - IBUFOUT OBUFOUT 10033-001 Data Sheet Low Cost, Low Power, True RMS-to-DC Converter AD8436 AD8436 Figure 1. GENERAL DESCRIPTION The AD8436 delivers true rms results at less cost than misleading peak, averaging, or digital solutions. There is no programming expense or processor overhead to consider, and the 4 mm x 4 mm package easily fits into tight applications. On-board buffer amplifiers enable the widest range of options for any rms-to-dc converter available, regardless of cost. For minimal applications, only a single external averaging capacitor is required. The built-in high impedance FET buffer provides an interface for external attenuators, frequency compensation, or driving low impedance loads. A matched pair of internal resistors enables an easily configurable gain-of-two or more, extending the usable input range even lower. The low power, precision input buffer makes the AD8436 attractive for use in portable multi-meters and other battery-powered applications. The precision dc output buffer minimizes errors when driving low impedance loads with extremely low offset voltages, thanks to internal bias current cancellation. Unlike digital solutions, the AD8436 has no switching circuitry limiting performance at high or low amplitudes (see Figure 2). A usable response of <100 V and >3 V extends the dynamic range with no external scaling, accommodating demanding low level signal conditions and allowing ample overrange without clipping. GREATER INPUT DYNAMIC RANGE AD8436 SOLUTION 100V 1mV 10mV 100mV 1V 3V 10033-002 The AD8436 is a new generation, translinear precision, low power, true rms-to-dc converter loaded with options. It computes a precise dc equivalent of the rms value of ac waveforms, including complex patterns such as those generated by switch mode power supplies and triacs. Its accuracy spans a wide range of input levels (see Figure 2) and temperatures. The ensured accuracy of 0.5% and 10 V output offset result from the latest Analog Devices, Inc., technology. The crest factor error is <0.5% for CF values between 1 and 10. Figure 2. Usable Dynamic Range of the AD8436 vs. The AD8436 operates from single or dual supplies of 2.4 V (4.8 V) to 18 V (36 V). A and J grades are available in a compact 4 mm x 4 mm, 20-lead chip-scale package; A grade is available in a 20-lead QSOP package. The operating temperature ranges are -40C to 125C for A grade and 0C to 70C for J grade. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011-2012 Analog Devices, Inc. All rights reserved. AD8436 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits........................................................................................9 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 10 General Description ......................................................................... 1 Overview ..................................................................................... 10 Revision History ............................................................................... 2 Applications Information .............................................................. 12 Specifications..................................................................................... 3 Using the AD8436....................................................................... 12 Absolute Maximum Ratings ............................................................ 4 AD8436 Evaluation Board ......................................................... 16 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 19 Pin Configuration and Function Descriptions ............................. 5 Ordering Guide .......................................................................... 20 Typical Performance Characteristics ............................................. 6 REVISION HISTORY 7/12--Rev. 0 to Rev. A Added 20-Lead QSOP ........................................................ Universal Changes to Features Section and General Description Section . 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Table 3 and added Figure 4 and added Table 4; Renumbered Sequentially................................................................ 5 Changes to Equation 1 and change to Column One Heading in Table 5 .......................................................................................... 10 Changes to Averaging Capacitor Considerations--RMS Accuracy and to Post Conversion Ripple Reduction Filter and changes to Figure 27 Caption ................................................ 12 Changes to Figure 30 to Figure 32................................................ 13 Changes to Using the FET Input Buffer Section and Using the Output Buffer Section .................................................................... 14 Changes to Figure 38 and Figure 41 and added Converting to Rectified Average Value Section .............................................. 15 Changes to Figure 41...................................................................... 16 Changes to Figure 42 to Figure 46................................................ 17 Changes to Figure 47 and Figure 48 ............................................ 18 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 7/11--Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet AD8436 SPECIFICATIONS eIN = 300 mV (rms), frequency = 1 kHz sinusoidal, ac-coupled, VS = 5 V, TA = 25C, CAVG = 10 F, unless otherwise specified. Table 1. Parameter RMS CORE Conversion Error Vs. Temperature Vs. Rail Voltage Input VOS Output VOS Vs. Temperature DC Reversal Error Nonlinearity Crest Factor Error 1 < CF < 10 Peak Input Voltage Input Resistance Response 1% Error 3 dB Bandwidth Settling Time 0.1% 0.01% Output Resistance Supply Current INPUT BUFFER Voltage Swing Input Output Offset Voltage Input Bias Current Input Resistance Response 0.1 dB 3 dB Bandwidth Supply Current Optional Gain Resistor Gain Error OUTPUT BUFFER Offset Voltage Input Current (IB) Output Swing Drive Current Gain Error Supply Current SUPPLY VOLTAGE Dual Single Conditions Min Typ Max Units Default conditions -40C < T < 125 C 2.4 V to 18 V DC-coupled AC-coupled input -40 C < T < 125C DC-coupled, VIN = 300 mV eIN = 2 mV to 500 mV ac (Additional) CCF = 0.1 F 10 - 0.5 0 0 0.006 0.013 0 0 0.3 0 10 + 0.5 +1.5 +0.2 V/% rdg %/C %/V V V V/C % % +0.5 +VS + 0.7 8.08 % V k -500 -1.5 -0.2 -0.5 -VS - 0.7 7.92 VIN = 300 mV rms (Additional) Rising/falling Rising/falling 15.68 No input G=1 AC- or dc-coupled AC-coupled to Pin RMS -VS -VS + 0.2 -1 8 +500 65 1 kHz MHz 148/341 158/350 16 325 ms ms k A 0 16.32 400 +VS +VS - 0.2 +1 50 1012 V mV mV pA (Frequency) 100 -9.9 950 2.1 160 +10 G = x1 RL = Connected to Pin OUT (Voltage) -200 0 2 -VS + 50e-6 -0.5 (sink) 0.003 40 2.4 4.8 1 IB max measured at power up. Settles to typical value in <15 seconds. Rev. A | Page 3 of 20 200 +10.1 0.05 kHz MHz A k % +200 51 +VS - 1 +15 (source) 0.01 70 V nA V mA % A 18 36 V V AD8436 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltage Supply Input Differential Input Power Dissipation CP-20-10 LFCSP Without Thermal Pad CP-20-10 LFCSP With Thermal Pad RQ Package Output Short-Circuit Duration Temperature Operating Range Storage Range Lead Soldering (60 sec) JA CP-20-10 LFCSP Without Thermal Pad CP-20-10 LFCSP With Thermal Pad RQ-20 Package ESD Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating 18 V VS +VS and -VS 1.2 W 2.1 W 1.1 W Indefinite JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. ESD CAUTION -40C to +125C -65C to +125C 300C 86C/W 48C/W 95C/W 2 kV Rev. A | Page 4 of 20 Data Sheet AD8436 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SUM CAVG CCF VCC 20 IBUFV+ 16 1 15 DNC OBUFV+ PIN 1 INDICATOR RMS IBUFOUT SUM 1 20 CAVG DNC 2 19 CCF RMS 3 18 VCC IBUFOUT 4 AD8436 17 IBUFV+ AD8436 IBUFIN- 5 TOP VIEW (Not to Scale) 16 OBUFV+ TOP VIEW (Not to Scale) IBUFIN+ 6 15 OBUFOUT IBUFGN 7 14 OBUFIN- DNC 8 13 OBUFIN+ OGND 9 12 IGND OUT 10 11 VEE OBUFOUT OBUFIN- IBUFIN- OBUFIN+ IBUFIN+ NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 11 5 6 10 DNC OGND OUT VEE NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD SHOULD NOT BE CONNECTED. 10033-003 IBUFGN Figure 4. Pin Configuration, RQ-20 Figure 3. Pin Configuration, Top View, CP-20-10 Table 3. Pin Function Descriptions, CP-20-10 Table 4. Pin Function Descriptions, RQ-20 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 EP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic DNC RMS IBUFOUT IBUFIN- IBUFIN+ IBUFGN DNC OGND OUT VEE IGND OBUFIN+ OBUFIN- OBUFOUT OBUFV+ IBUFV+ VCC CCF CAVG SUM DNC 10033-104 IGND Description Do Not Connect. Used for factory test. AC Input to the RMS Core. FET Input Buffer Output Pin. FET Input Buffer Inverting Input Pin. FET Input Buffer Noninverting Input Pin. Optional 10 k Precision Gain Resistor. Do Not Connect. Used for factory test. Internal 16 k I-to-V Resistor. RMS Core Voltage or Current Output. Negative Supply Rail. Half Supply Node. Output Buffer Noninverting Input Pin. Output Buffer Inverting Input Pin. Output Buffer Output Pin. Power Pin for the Output Buffer. Power Pin for the Input Buffer. Positive Supply Rail for the RMS Core. Connection for Crest Factor Capacitor. Connection for Averaging Capacitor. Summing Amplifier Input Pin. Exposed Pad Connection to Ground Pad Optional. Rev. A | Page 5 of 20 Mnemonic SUM DNC RMS IBUFOUT IBUFIN- IBUFIN+ IBUFGN DNC OGND OUT VEE IGND OBUFIN+ OBUFIN- OBUFOUT OBUFV+ IBUFV+ VCC CCF CAVG Description Summing Amplifier Input Pin. Do Not Connect. Used for factory test. AC Input to the RMS Core. FET Input Buffer Output Pin. FET Input Buffer Inverting Input Pin. FET Input Buffer Noninverting Input Pin. Optional 10 k Precision Gain Resistor. Do Not Connect. Used for factory test. Internal 16 k I-to-V Resistor. RMS Core Voltage or Current Output. Negative Supply Rail. Half Supply Node. Output Buffer Noninverting Input Pin. Output Buffer Inverting Input Pin. Output Buffer Output Pin. Power Pin for the Output Buffer. Power Pin for the Input Buffer. Positive Supply Rail for the RMS Core. Connection for Crest Factor Capacitor. Connection for Averaging Capacitor. AD8436 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 5V 1V 1V 100mV 10mV -3dB BW 100mV 10mV -3dB BW 1mV 1mV 100V 100V 50V 50V 50 100 1k 10k 100k FREQUENCY (Hz) 1M 5M Figure 5. RMS Core Frequency Response (See Figure 21) VS = 4.8V 50 100 1k 10k 100k FREQUENCY (Hz) 1M 10033-007 INPUT LEVEL (V rms) 5V 10033-004 INPUT LEVEL (V rms) TA = 25C, VS = 5 V, CAVG = 10 F, 1 kHz sine wave, unless otherwise indicated. 5M Figure 8. RMS Core Frequency Response with VS = +4.8 V (See Figure 22) 5V 15 eIN = 3.5mV rms 12 1V 6 100mV GAIN (dB) INPUT LEVEL (V rms) 9 10mV -3dB BW 3 0 -3 -6 1mV -9 1k 10k 100k FREQUENCY (Hz) 1M 5M -15 100 10033-005 50 100 1k 10k 100k 1M 5M FREQUENCY (Hz) Figure 6. RMS Core Frequency Response with VS = 2.4 V (See Figure 21) 10033-008 -12 VS = 2.4V 100V 50V Figure 9. Input Buffer, Small Signal Bandwidth at 0 dB and 6 dB Gain 15 5V eIN = 300mV rms 12 1V 6 100mV GAIN (dB) INPUT LEVEL (V rms) 9 10mV -3dB BW 3 0 -3 -6 1mV -9 50 100 1k 10k 100k FREQUENCY (Hz) 1M 5M -15 100 10033-006 50V Figure 7. RMS Core Frequency Response with VS = 15 V (See Figure 21) 1k 10k 100k FREQUENCY (Hz) 1M 5M 10033-009 -12 VS = 15V 100V Figure 10. Input Buffer, Large Signal Bandwidth at 0 dB and 6 dB Gain Rev. A | Page 6 of 20 Data Sheet 10 eIN = 3.5mV rms PW = 100s ADDITIONAL ERROR (% OF READING) 12 9 3 0 -3 -6 -9 -12 1k 10k 100k 1M 5M FREQUENCY (Hz) 0 CAVG = 10F -5 0 4 6 CREST FACTOR RATIO 8 10 1.00 0.5 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 20 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -50 10033-011 -0.5 0.75 -25 0 50 25 TEMPERATURE (C) 75 100 10033-014 ADDITIONAL ERROR (% OF READING) CAVG = 10F 8 SAMPLES 0.4 125 Figure 15. Additional Conversion Error vs. Temperature Figure 12. Additional Error vs. Supply Voltage 2.5 1.6 2.0 SUPPLY CURRENT (mA) 2.0 1.2 0.8 VS = 15V 1.5 VS = 5V VS = 2.4V 1.0 0.5 0.4 0 0 2 4 12 6 8 10 SUPPLY VOLTAGE (V) 14 16 18 Figure 13. Core Input Voltage for 1% Error vs. Supply Voltage 0 10033-012 INPUT LEVEL (V rms) 2 Figure 14. Crest Factor Error vs. Crest Factor for CAVG and CAVG and CCF Capacitor Combinations Figure 11. Output Buffer, Small Signal Bandwidth NORMALIZED ERROR (%) CAVG = 10F CCF = 0.1F -10 10033-010 -15 100 5 0 0.5 1.0 1.5 INPUT VOLTAGE (V rms) 2.0 10033-015 GAIN (dB) 6 10033-013 15 AD8436 Figure 16. RMS Core Supply Current vs. Input for VS = 2.4 V, 5 V, and 15 V Rev. A | Page 7 of 20 Data Sheet 90 250 80 200 70 150 INPUT OFFSET VOLTAGE (V) 60 50 40 30 20 10 50 0 -50 -100 -150 -200 -25 0 50 25 TEMPERATURE (C) 75 100 125 10033-016 0 -10 -50 100 -250 -50 -25 0 25 50 TEMPERATURE (C) 75 100 125 10033-019 BIAS CURRENT (pA) AD8436 Figure 19. Output Buffer VOS vs. Temperature Figure 17. FET Input Buffer Bias Current vs. Temperature 1000 CAVG = 10F 1kHz 300mV rms BURST INPUT 0V 500 250 0 300mV DC OUT -250 0V -500 1kHz 1mV rms BURST INPUT 0V -750 -25 0 50 75 25 TEMPERATURE (C) 100 125 1mV DC OUT 0V TIME (50ms/DIV) Figure 20. Transition Times with 1 kHz Burst at Two Input Levels (See Theory of Operation Section) Figure 18. Input Offset Voltage of FET Buffer vs. Temperature Rev. A | Page 8 of 20 10033-020 -1000 -50 10033-018 INPUT OFFSET VOLTAGE (V) 750 Data Sheet AD8436 TEST CIRCUITS SIGNAL SOURCE +5V 10F CAV RMS VCC 4.7F 100k RMS CORE IGND AC-IN MONITOR 100k 16k PRECISION DMM OUT OGND VEE 10033-021 -5V PRECISION DMM Figure 21. Core Response Test Circuit Using Dual Supplies SIGNAL SOURCE 10F CAV RMS 4.80V VCC 4.7F 100k RMS CORE IGND AC-IN MONITOR 4.7F 100k 16k PRECISION DMM OGND VEE 10033-022 OUT PRECISION DMM Figure 22. Core Response Test Circuit Using a Single Supply 10F +5V FUNCTION GENERATOR CAV RMS VCC 4.7F RMS CORE 100k IGND AC-IN MONITOR 100k 16k PRECISION DMM OGND VEE -5V PRECISION DMM Figure 23. Crest Factor Test Circuit Rev. A | Page 9 of 20 10033-023 OUT AD8436 Data Sheet THEORY OF OPERATION Why RMS? The rms value of an ac voltage waveform is equal to the dc voltage providing the same heating power to a load. A common measurement technique for ac waveforms is to rectify the signal in a straightforward way using a diode array of some sort, resulting in the average value. The average value of various waveforms (sine, square, and triangular, for example) varies widely; true rms is the only metric that achieves equivalency for all ac waveforms. See Table 5 for non-rms-responding circuit errors. For additional information, select Section I of the 2nd edition of the Analog Devices RMS-to-DC Applications Guide. RMS Core The core consists of a voltage-to-current converter (precision resistor), absolute value, and translinear sections. The translinear section exploits the properties of the bipolar transistor junctions for squaring and root extraction (see Figure 24). The external capacitor (CAVG) provides for averaging the product. Figure 20 shows that there is no effect of signal input on the transition times, as seen in the dc output. Although the rms core responds to input voltages, the conversion process is current sensitive. If the rms input is ac-coupled, as recommended, there is no output offset voltage, as reflected in Table 1. If the rms input is dc-coupled, the input offset voltage is reflected in the output and can be calibrated as with any fixed error. V+ + 5k erms = 1 T CAVG AC IN ABSOLUTE VALUE CIRCUIT V-TO-I The acronym "rms" means root-mean-square and reads as follows: "the square root of the average of the sum of the squares" of the peak values of any waveform. RMS is shown in the following equation: OUT 16k V+ 10033-024 The AD8436 is an implicit function rms-to-dc converter that renders a dc voltage dependent on the rms (heating value) of an ac voltage. In addition to the basic converter, this highly integrated functional circuit block includes two fully independent, optional amplifiers, a standalone FET input buffer amplifier and a precision dc output buffer amplifier (see Figure 1). The rms core includes a precision current responding full-wave rectifier and a log-antilog transistor array for current squaring and square rooting to implement the classic expression for rms (see Equation 1). For basic applications, the converter requires only an external capacitor, for averaging (see Figure 31). The optional on-board amplifiers offer utility and flexibility in a variety of applications without incurring additional circuit board footprint. For lowest power, the amplifier supply pins are left unconnected. - OVERVIEW V- T Figure 24. RMS Core Block Diagram 0V(t)2dt (1) Table 5. General AC Parameters Waveform Type (1 V Peak) Sine Square Triangle Noise Rectangular Pulse SCR DC = 50% DC = 25% Crest Factor 1.414 1.00 1.73 3 2 10 RMS Value 0.707 1.00 0.577 0.333 0.5 0.1 Reading of an Average Value Circuit Calibrated to an RMS Sine Wave 0.707 1.11 0.555 0.295 0.278 0.011 2 4.7 0.495 0.212 0.354 0.150 Rev. A | Page 10 of 20 Error (%) 0 11.0 -3.8 -11.4 -44 -89 -28 -30 Data Sheet AD8436 Referring to Figure 1, the input resistance of the AD8436 is 8 k, and a voltage source input is preferred. The optional input buffer is a wideband JFET input amplifier that minimally loads non-0 sources, such as a tapped resistor attenuator or voltage sensor. Although the input buffer consumes only 150 A, the supply is pinned out and left unconnected to reduce power where needed. Optional matched 10 k input and feedback resistors are provided on chip. Consult the Applications Information section to learn how these resistors can be used. The 3 dB bandwidth of the input buffer is 2.7 MHz at 10 mV rms input and approximately 1.5 MHz at 1 V rms. The amplifier gain and bandwidth are sufficient for applications requiring modest gain or response enhancement to a few hundred kilohertz (kHz), if desired. Configurations of the input buffer are discussed in the Applications Information section. Precision Output Buffer The precision output buffer is a bipolar input amplifier, laser trimmed to cancel input offset voltage errors. As with the input buffer, the supply current is very low (<50 A, typically), and the power can be disconnected for power savings if the buffer is not needed. Be sure that the noninverting input is also disconnected from the core output (OUT) if the buffer supply pin is disconnected. Although the input current of the buffer is very low, a laser-trimmed 16 k resistor, connected in series with the inverting input, offsets any self-bias offset voltage. Dynamic Range The AD8436 is a translinear rms-to-dc converter with exceptional dynamic range. Although accuracy varies slightly more at the extreme input values, the device still converts with no spurious noise or dropout. Figure 25 is a plot of the rms/dc transfer function near zero voltage. Unlike processor or other solutions, residual errors at very low input levels can be disregarded for most applications. 30 OR OTHER DIGITAL SOLUTIONS CANNOT WORK AT ZERO VOLTS 20 10 Rev. A | Page 11 of 20 AD8436 SOLUTION 0 -30 -20 -10 0 10 INPUT VOLTAGE (mV DC) Figure 25. DC Transfer Function near Zero 20 30 10033-025 FET Input Buffer The output buffer can be configured as a single or two-pole lowpass filter using circuits shown in the Applications Information section. Residual output ripple is reduced, without affecting the converted dc output. As the response approaches the low frequency end of the bandwidth, the ripple rises, dependent on the value of the averaging capacitor. Figure 27 shows the effects of four combinations of averaging and filter capacitors. Although the filter capacitor reduces the ripple for any given frequency, the dc error is unaffected. Of course, a larger value averaging capacitor can be selected, at a larger cost. The advantage of using a low-pass filter is that a small value of filter capacitor, in conjunction with the 16 k output resistor, reduces ripple and permits a smaller averaging capacitor, effecting a cost savings. The recommended capacitor values for operation to 40 Hz are 10 F for averaging and 3.3 F for filter. OUTPUT VOLTAGE (mV DC) The 16 k resistor in the output converts the output current to a dc voltage that can be connected to the output buffer or to the circuit that follows. The output appears as a voltage source in series with 16 k. If a current output is desired, the resistor connection to ground is left open and the output current is applied to a subsequent circuit, such as the summing node of a current summing amplifier. Thus, the core has both current and voltage outputs, depending on the configuration. For a voltage output with 0 source impedance, use the output buffer. The offset voltage of the buffer is 25 V or 50 V, depending on the grade. AD8436 Data Sheet APPLICATIONS INFORMATION Averaging Capacitor Considerations--RMS Accuracy OUT CORE DC OUTPUT 9 CLPF 16k OGND 8 Figure 26. Simple One-Pole Post Conversion Filter The result of the conversion process is a dc component and a ripple component whose frequency is twice that of the input. The rms conversion accuracy depends on the value of CAVG, so the value selected need only be large enough to average enough periods at the lowest frequency of interest to yield the required rms accuracy. Figure 28 is a plot of rms error vs. frequency for various averaging capacitor values. For Figure 28, the additional error was 0.001% at 40 Hz using a 10 F metalized polyester capacitor. Larger values yield diminished returns because the settling time increases with negligible improvement in rms accuracy. As seen in Figure 27, CAVG alone determines the rms error, and CLPF serves purely to reduce ripple. Figure 27 shows a constant rms error for CLPF values of 0.33 F and 3.3 F; only the ripple is affected. To use Figure 28, determine the minimum operating frequency and accuracy of the application and then find the suggested capacitor value on the chart. For example, for -0.5% rms at 100 Hz, the capacitor value is 1 F. RMS ERROR (%) Typical AD8436 applications require only a single external capacitor (CAVG) connected to the CAVG pin (see Figure 31). The function of the averaging capacitor is to compute the mean (that is, average value) of the sum of the squares. Averaging (that is, integration) follows the rms core, where the input current is squared. The mean value is the average value of the squared input voltage over several input waveform periods. The rms error is directly affected by the number of periods averaged, as is the resultant peak-to-peak ripple. 1 CAVG = 10F CLPF = 0.33F OR 3.3F 0 -1 -2 -3 -4 -5 -6 Post Conversion Ripple Reduction Filter -7 Input rectification included in the AD8436 introduces a residual ripple component that is dependent on the value of CAVG and twice the input signal frequency for symmetrical input waveforms. For sampling applications such as a high resolution ADC, the ripple component may cause one or more LSBs to cycle, and low value display numerals to flash. -8 CAVG = 1F CLPF = 0.33F OR 3.3F -9 -10 10 100 FREQUENCY (Hz) Figure 27. RMS Error vs. Frequency for Two Values of CAVG and CLPF (Note that only CAVG value affects rms error; CLPF has no effect.) 0 22F 47F -0.5 4.7F 0.47F CAVG = 0.22F 2.2F -1.5 1F -2.0 10 100 FREQUENCY (Hz) Figure 28. Conversion Error vs. Frequency for Various Values of CAVG Rev. A | Page 12 of 20 1k 10033-028 CONVERSION ERROR (%) 10F -1.0 1k 10033-027 This section describes the power supply and feature options, as well as the function and selection of averaging and filter capacitor values. Averaging and filtering options are shown graphically and apply to all circuit configurations. Ripple is reduced by increasing the value of the averaging capacitor, or by postconversion filtering. Ripple reduction following conversion is far more efficient because the ripple average value has been converted to its rms value. Capacitor values for postconversion filtering are significantly less than the equivalent averaging capacitor value for the same level of ripple reduction. This approach requires only a single capacitor connected to the OUT pin (see Figure 26). The capacitor value correlates to the simple frequency relation of 1/2 R-C, where R is fixed at 16 k. 10033-026 USING THE AD8436 Data Sheet AD8436 voltage source (0 source impedance). If a non-zero signal source impedance cannot be avoided, be sure to account for any series connected voltage drop. For simplicity, Figure 29 shows ripple vs. frequency for four combinations of CAVG and CLPF RIPPLE ERROR (V p-p) 1 AC INPUT = 300mV rms CAVG = 1F, CLPF = 0.33F CAVG = 1F, CLPF = 3.3F CAVG = 10F, CLPF = 0.33F CAVG = 10F, CLPF = 3.3F 0.1 An input coupling capacitor must be used to realize the near-zero output offset voltage feature of the AD8436. Select a coupling capacitor value that is appropriate for the lowest expected operating frequency of interest. As a rule of thumb, the input coupling capacitor can be the same as or half the value of the averaging capacitor because the time constants are similar. For a 10 F averaging capacitor, a 4.7 F or 10 F tantalum capacitor is a good choice (see Figure 31). 0.01 0.001 +5V 100 INPUT FREQUENCY (Hz) 1k Figure 29. Residual Ripple Voltage for Various Filter Configurations 10F 19 Figure 30 shows the effects of averaging and post-rms filter capacitors on transition and settling times using a 10-cycle, 50 Hz, 1 second period burst signal input to demonstrate timedomain behavior. In this instance, the averaging capacitor value was 10 F, yielding a ripple value of 6 mV rms. A postconversion capacitor (CLPF) of 0.68 F reduced the ripple to 1 mV rms. An averaging capacitor value of 82 F reduced the ripple to 1 mV but extended the transition time (and cost) significantly. 4.7F OR 10F +* 17 CAVG 2 RMS VCC AD8436 OUT 9 IGND VEE OGND 11 10 8 -5V *FOR POLARIZED CAPACITOR STYLES. 10033-131 10 CAVG +* 10033-029 0.0001 Figure 31. Basic Applications Circuit Using a Capacitor for High Crest Factor Applications The AD8436 contains a unique feature to reduce large crest factor errors. Crest factor is often overlooked when considering the requirements of rms-to-dc converters, but it is very important when working with signals with spikes or high peaks. The crest factor is defined as the ratio of peak voltage to rms. See Table 5 for crest factors for some common waveforms. INPUT 50Hz 10 CYCLE BURST 400mv/DIV CAVG = 10F FOR BOTH PLOTS, BUT RED PLOT HAS NO LOW-PASS FILTER, GREEN PLOT HAS CLPF = 0.68F 10mV/DIV +5V CAVG +* CAVG = 82F 10F CCF 4.7F OR 10F +* Figure 30. Effects of Various Filter Options on Transition Times Capacitor Construction Although tolerant of most capacitor styles, rms conversion accuracy can be affected by the type of capacitor that is selected. Capacitors with low dc leakage yield best all around performance, and many sources are available. Metalized polyester or similar film styles are best, as long as the temperature range is appropriate. For practical applications such as the rms-to-dc function in DMMs or power monitoring circuits, surface mount tantalums are the best over-all choice. Basic Core Connections Many applications require only a single external capacitor for averaging. A 10 F capacitor is more than adequate for acceptable rms errors at line frequencies and below. The signal source sees the input 8 k voltage-to-current conversion resistor at Pin RMS; thus, the ideal source impedance is a 2 18 17 CAVG CCF VCC RMS AD8436 OUT 9 IGND VEE OGND 11 10 8 -5V *FOR POLARIZED CAPACITOR STYLES. 10033-132 TIME (100ms/DIV) 10033-130 0.1F 19 Figure 32. Connection for Additional Crest Factor Performance Crest factor performance is mostly applicable for unexpected waveforms such as switching transients in switchmode power supplies. In such applications, most of the energy is in these peaks and can be destructive to the circuitry involved, although the average ac value can be quite low. Figure 14 shows the effects of an additional crest factor capacitor of 0.1 F and an averaging capacitor of 10 F. The larger capacitor serves to average the energy over long spaces between pulses, while the CCF capacitor charges and holds the energy within the relatively narrow pulse. Rev. A | Page 13 of 20 AD8436 Data Sheet Using the FET Input Buffer The on-chip FET input buffer is an uncommitted FET input op amp used for driving the 8 k I-to-V input resistor of the rms core. Pin IBUFOUT, Pin IBUFIN-, and Pin IBUFIN+ are the I/O, Pin IBUFINGN is an optional connection for gain in the input buffer, and Pin IBUFV+ connects power to the buffer. Connecting Pin IBUFV+ to the positive rail is the only power connection required because the negative rail is internally connected. Because the input stage is a FET and the input impedance must be very high to prevent loading of the source, a large value (10 M) resistor is connected from midsupply at Pin IGND to Pin IBUFIN+ to prevent the input gate from floating high. For unity gain, connect the IBUFOUT pin to the IBUFIN- pin. For a gain of 2x, connect the IBUFGN pin to ground. See Figure 9 and Figure 10 for large and small signal responses at the two built-in gain options. The offset voltage of the input buffer is 500 V, depending on grade. A capacitor connected between the buffer output pin (IBUFOUT) and the RMS pin is recommended so that the input buffer offset voltage does not contribute to the overall error. Select the capacitor value for least minimum error at the lowest operating frequency. Figure 33 is a schematic showing internal components and pin connections. 16 IBUFV+ Using the Output Buffer The AD8436 output buffer is a precision op amp optimized for high dc accuracy. Figure 34 shows a block diagram of the basic amplifier and I/O pins. The amplifier is often configured as a unity gain follower but is easily configured for gain, as a Sallen-Key lowpass filter (in conjunction with the built-in 16 k I-to-V resistor). Note that an additional 16 k on-chip precision resistor in series with the inverting input of the amplifier balances output offset voltages resulting from the bias current from the noninverting amplifier. The output buffer is disconnected from Pin OUT for precision core measurements. As with the input FET buffer, the amplifier positive supply is disconnected when not needed. In normal circumstances, the buffers are connected to the same supply as the core. Figure 35 shows the signal connections to the output buffer. Note that the input offset voltage contribution by the bias currents are balanced by equal value series resistors, resulting in near zero offset voltage. 10F 3 OUTPUT BUFFER IBUFOUT OBUFIN+ 4 IBUFIN- - OBUFIN- 0.47F 5 IBUFIN+ + OBUFOUT - Figure 34. Output Buffer Block Diagram 10k 10M + 16k 10033-034 2 RMS The bandwidth diminishes at the typical rate of a decade per 20 dB of gain, and the output voltage range is constrained. The small signal response, as shown in Figure 9, serves as a guide. As an example, suppose one wanted to detect small input signals at power line frequencies? An external 10 resistor connected from IBUFIN- to ground sets the gain to 101 and the 3 dB bandwidth to ~30 kHz, which is more than adequate for amplifying power line frequencies. 10pF 11 IGND 9 16k Figure 33. Connecting the FET Input Buffer Capacitor coupling at the input and output of the FET buffer is recommended to avoid transferring the buffer offset voltage to the output. Although the FET input impedance is extremely high, the 10 M centering resistor connected to IGND must be taken into account when selecting an input capacitor value. This is simply an impedance calculation using the lowest desired frequency, and finding a capacitor value based on the least attenuation desired. Because the 10 k resistors are closely matched and trimmed to a high tolerance, the input buffer gain can be increased to several hundred with an external resistor connected to Pin IBUFIN-. OGND OBUFIN+ 12 13 OBUFOUT + 16k 14 - OBUFIN- 8 10033-035 IBUFGN IBIAS OUT CORE IBIAS 6 10033-033 10k Figure 35. Basic Output Buffer Connections For applications requiring ripple suppression in addition to the single-pole output filter described previously, the output buffer is configurable as a two-pole Sallen-Key filter using two external resistors and two capacitors. At just over 100 kHz, the amplifier has enough bandwidth to function as an active filter for low frequencies such as power line ripple. For a modest savings in cost and complexity, the external 16 k feedback resistor can be omitted, resulting in slightly higher VOS (80 V). Rev. A | Page 14 of 20 Data Sheet AD8436 10F 2C OBUFIN+ + 12 16k C 16k 13 14 - OBUFOUT 10033-036 8 16k 9 13 - 32.4k 8 OBUFOUT Figure 37. Inverting Output Configuration Current Output Option RMS 2 CCF 19 18 8k CORE IBUFIN+ 20 IGND 11 OGND VEE 8 10 4.7F DO NOT CONNECT FOR CURRENT OUTPUT 32.4k 3 4 15k - 0.47F AC IN INVERTED DC VOLTAGE OUTPUT 18 17 CCF 10M 5 16 VCC IBUFV+ 1 DNC OBUFV+ AD8436 RMS OBUFOUT IBUFOUT OBUFIN- IBUFIN- OBUFIN+ IBUFIN+ IGND IBUFGN DNC OGND OUT 6 10033-138 16k 8 0.1F 19 SUM CAVG 2k (OPTIONAL) OUT + OGND 5 10F + 10F 9 IBUFIN- VCC 2 DIRECTION OF DC OUTPUT CURRENT 4 OUT 9 Figure 40 shows a circuit for a typical application for frequencies as low as power line, and above. The recommended averaging, crest factor and LPF capacitor values are 10 F, 0.1 F and 3.3 F. Refer to the Using the Output Buffer section if additional low-pass filtering is required. If a current output is required, connect the current output, OUT, to the destination load. To maximize precision, provide a means for external calibration to replace the internal trimmed resistor, which is bypassed. This configuration is useful for convenient summing of the AD8436 result with another voltage, or for polarity inversion. CAVG IBUFOUT Recommended Application 14 + OBUFIN+ 10033-037 12 3 Figure 39. Connections for Single Supply Operation 16k OBUFIN- 16k OGND RMS 10M Configure the output buffer as shown in Figure 37 to invert the dc output. OUT AD8436 2 0.47F Figure 36. Output Buffer Amplifier Configured as a Two-Pole, Sallen-Key Low-Pass Filter CORE 17 VCC 4.7F OBUFIN- OGND 19 CAV 10033-039 9 7 8 9 Single Supply 14 DC OUT 13 12 11 VEE 10 VEE 3.3F Figure 38. Connections for Current Output Showing Voltage Inversion 15 10033-040 16k OUT CORE Figure 40. Typical Application Circuit Connections for single supply operation are shown in Figure 39 and are similar to those for dual power supply when the device is ac-coupled. The analog inputs are all biased to half the supply voltage, but the output remains referred to ground because the output of the AD8436 is a current source. An additional bypass connection is required at IGND to suppress ambient noise. Converting to Average Rectified Value To configure the AD8436 for converting ac waveforms to their rectified average value, refer to Figure 41. If no capacitor CAVG is connected, a very accurate full-wave rectified waveform appears at the output and is converted to the average rectified value of the ac input if a capacitor is connected to Pin CLPF. In practice, a minimum capacitance of 470 pF must be connected at Pin CAVG to stabilize the internal loop. To enable both modes of operation, insert a switch between capacitor CAVG and Pin CAVG as shown in Figure 41. Rev. A | Page 15 of 20 AD8436 Data Sheet DISCONNECTING CAVG DEFAULTS THE COMPUTED RESULT TO AVERAGE-VALUE. A MINIMUM OF 470pF CAPACITANCE IS REQUIRED TO MAINTAIN STABILITY. + 470pF CAVG 10F 0.1F 20 19 18 SUM CAVG 16 17 CCF VCC IBUFV+ 1 DNC 2 10F 3 4 0.47F 5 AC IN 10M OBUFV+ AD8436 OBUFOUT RMS IBUFOUT OBUFIN- IBUFIN- OBUFIN+ IBUFIN+ IGND IBUFGN DNC OGND OUT 6 7 8 14 DC OUT 13 12 11 VEE 9 CAPACITOR CLPF, IN CONJUNCTION WITH THE INTERNAL 16k OUTPUT RESISTOR FILTERS THE RECTIFIED OUTPUT, YIELDING THE AVERAGE RECTIFIED VALUE. 15 10 VEE CLPF 3.3F 10033-141 CAPACITOR CAVG COMPUTES THE MEAN IN THE IMPLICIT RMS EXPRESSION. FOR SMALL VALUES OF CAVG, THE AC INPUT WAVEFORM WILL STILL BE FULLY RECITIFIED AND APPEAR AT THE OUTPUT. VCC Figure 41. Configuration for Average Rectified Value Table 6. AD8436 EVALUATION BOARD The AD8436-EVALZ provides a platform to evaluate AD8436 performance. The board is fully assembled, tested, and ready to use after the power and signal sources are connected. Figure 47 is a photograph of the board. Signal connections are located on the primary and secondary sides, with power and ground on the inner layers. Figure 42 to Figure 46 illustrate the various design details of the board, including basic layout and copper patterns. These figures are useful for reference for application designs. A Word About Using the AD8436 Evaluation Board The AD8436-EVALZ offers many options, without sacrificing simplicity. The board is tested and shipped with a 10 F averaging capacitor (CAVG), 3.3 F low-pass filter capacitor (C8) and a 0.1 F (COPT) capacitor to optimize crest factor performance. To evaluate minimum cost applications, remove C8 and COPT. The functions of the five switches are listed in Table 6. Switch CORE_BUFFER INCOUP SDCOUT IBUF_VCC OBUF_VCC Function Selects core or input for the input signal Selects ac or dc coupling to the core Selects the output buffer or the core output at the DCOUT BNC. Enable or disables the input buffer Enable or disables the output buffer All the I/Os are provided with test points for easy monitoring with test equipment. The input buffer gain default is unity; for 2x gain, install a 0603 0 resistor at Position R5. For higher IBUF gains, remove the 0 resistor at Position RFBH (there is an internal 10 k resistor from the OBUF_OUT to IBUFIN-) and install a smaller value resistor in Position RFBL. A 100 resistor establishes a gain of 100x. Single supply operation requires removal of Resistor R6 and installing a 0.1 F capacitor in the same position for noise decoupling. Rev. A | Page 16 of 20 AD8436 10033-142 10033-145 Data Sheet 10033-143 10033-146 Figure 45. AD8436-EVALZ Power Plane Figure 42. Assembly of the AD8436-EVALZ Figure 46. AD8436-EVALZ Ground Plane 10033-144 Figure 43. AD8436-EVALZ Primary Side Copper Figure 44. AD8436-EVALZ Secondary Side Copper Rev. A | Page 17 of 20 Data Sheet 10033-147 AD8436 Figure 47. Photograph of the AD8436-EVALZ +V (RED) GND1 GND2 GND3 GND4 GND5 GND6 CAVG 10F + TCAVG TSUM 20 SUM INCOUP AC DC TCCF 19 CAVG C1 10F + 50V -40C TO +125C C2 CCF 0.1F X8R 18 CCF -V (GRN) C4 0.1F 17 VCC 1 DNC + 10F TIBUFV+ EN 50V -40C TO +125C DIS IBUF_VCC 16 IBUFV+ TOBUFV+ EN OBUFV+ 15 VEE VCC DIS CORE_BUF CORE AC_IN CIN 10F OBUF_VCC TRMSIN 2 RMS OBUFOUT TOBFOUT 14 + BUF TIBUFOUT 3 RFBH 0 C5 0.47F AD8436 IBUFOUT OBUFIN- R8 0 C6* 2.2F TDCOUT BUF TIBFIN- 4 DC OUT TOBUFIN+ OBUFIN+ 12 IBUFIN- CORE RFBL DNI SDCOUT TIBFIN+ 5 C7* 1.5F TIGND IGND 11 IBUFIN+ BUF GAIN R1 10M 6 DNC 7 OGND OUT 8 9 VEE 10 TOGND TBUFGN R5 0 R2 0 R7 0** C3 0.1F TOUT R6 0 R3* 8.06k R4* 0 VEE CLPF 3.3F *COMPONENTS IN GRAY ARE SELECTED BY THE USER. ** REMOVE R7 FOR CORE-ONLY TESTS. Figure 48. Evaluation Board Schematic Rev. A | Page 18 of 20 10033-148 TACIN TOBUFIN- 13 Data Sheet AD8436 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 061609-B 0.80 0.75 0.70 6 10 0.50 0.40 0.30 TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 49. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] (CP-20-10) Dimensions shown in inches 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 11 1 10 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8 0 0.050 (1.27) 0.016 (0.41) COMPLIANT TO JEDEC STANDARDS MO-137-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 50. 20-Lead Lead QSOP Package [RQ_20] (RQ-20) Dimensions shown in inches Rev. A | Page 19 of 20 0.020 (0.51) 0.010 (0.25) 0.041 (1.04) REF 08-19-2008-A 20 AD8436 Data Sheet ORDERING GUIDE Model 1 AD8436ACPZ-R7 AD8436ACPZ-RL AD8436ACPZ-WP AD8436JCPZ-R7 AD8436JCPZ-RL AD8436JCPZ-WP AD8436ARQZ-R7 AD8436ARQZ-RL AD8436ARQZ AD8436-EVALZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C 0C to +70C 0C to +70C 0C to +70C -40C to +125C -40C to +125C -40C to +125C Package Description 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead QSOP [RQ_20] 20-Lead QSOP [RQ_20] 20-Lead QSOP [RQ_20] Evaluation Board Z = RoHS Compliant Part. (c)2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10033-0-7/12(A) Rev. A | Page 20 of 20 Package Option CP-20-10 CP-20-10 CP-20-10 CP-20-10 CP-20-10 CP-20-10 RQ-20 RQ-20 RQ-20