PNP Silicon
Epitaxial Transistor
This PNP Silicon Epitaxial transistor is designed for use in linear
and switching applications. The device is housed in the SOT-223
package which is designed for medium power surface mount
applications.
•NPN Complement is PZT2222AT1
•The SOT-223 package can be soldered using wave or reflow
•SOT-223 package ensures level mounting, resulting in improved
thermal conduction, and allows visual inspection of soldered joints.
The formed leads absorb thermal stress during soldering eliminating
the possibility of damage to the die.
•Available in 12 mm tape and reel
Use PZT2907AT1 to order the 7 inch/1000 unit reel.
Use PZT2907AT3 to order the 13 inch/4000 unit reel.
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Collector-Emitter Voltage VCEO –60 Vdc
Collector-Base Voltage VCBO –60 Vdc
Emitter-Base Voltage VEBO –5.0 Vdc
Collector Current IC–600 mAdc
Total Power Dissipation @ TA = 25°C(1)
Derate above 25°CPD1.5
12 Watts
mW/°C
Operating and Storage Temperature Range TJ, Tstg –65 to 150 °C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction-to-Ambient (surface mounted) RθJA 83.3 °C/W
Lead Temperature for Soldering, 0.0625″ from case
Time in Solder Bath TL260
10 °C
Sec
DEVICE MARKING
P2F
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector-Base Breakdown Voltage (IC = –10 µAdc, IE = 0) V(BR)CBO –60 °—°— Vdc
Collector-Emitter Breakdown Voltage (IC = 10 mAdc, IB = 0) V(BR)CEO –60 — — Vdc
Emitter-Base Breakdown Voltage (IE = –10 µAdc, IC = 0) V(BR)EBO –5.0 °—°— Vdc
Collector-Base Cutoff Current (V CB = –50 Vdc, IE = 0) ICBO —°—°–10 nAdc
Collector-Emitter Cutoff Current (VCE = –30 Vdc, VBE = 0.5 Vdc) ICEX — — –50 nAdc
Base-Emitter Cutoff Current (VCE = –30 Vdc, VBE = –0.5 Vdc) IBEX — — –50 nAdc
1. Device mounted on a glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.059 in.; mounting pad for the collector lead min. 0.93 sq. in.
Preferred devices are ON Semiconductor recommended choices for future use and best overall value.
ON Semiconductor
Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 5 1Publication Order Number:
PZT2907AT1/D
PZT2907AT1
SOT-223 PACKAGE
PNP SILICON
TRANSISTOR
SURFACE MOUNT
ON Semiconductor Preferred Device
CASE 318E-04, STYLE 1
TO-261AA
123
4
COLLECTOR
2,4
BASE 1
3
EMITTER
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic Symbol Min Typ Max Unit
ON CHARACTERISTICS(2)
DC Current Gain
(IC = –0.1 mAdc, VCE = –10 Vdc)
(IC = –1.0 mAdc, VCE = –10 Vdc)
(IC = –10 mAdc, VCE = –10 Vdc)
(IC = –150 mAdc, VCE = –10 Vdc)
(IC = –500 mAdc, VCE = –10 Vdc)
hFE 75
100
100
100
50
—
—
—
—
—
—
—
—
300
—
—
Collector-Emitter Saturation Voltages
(IC = –150 mAdc, IB = –15 mAdc)
(IC = –500 mAdc, IB = –50 mAdc)
VCE(sat) —
——
—–0.4
–1.6
Vdc
Base-Emitter Saturation Voltages
(IC = –150 mAdc, IB = –15 mAdc)
(IC = –500 mAdc, IB = –50 mAdc)
VBE(sat) —
——
—–1.3
–2.6
Vdc
DYNAMIC CHARACTERISTICS
Current-Gain — Bandwidth Product (IC = –50 mAdc, VCE = –20 Vdc, f = 100 MHz) fT200 — — MHz
Output Capacitance (VCB = –10 Vdc, IE = 0, f = 1.0 MHz) Cc— — 8.0 pF
Input Capacitance (VEB = –2.0 Vdc, IC = 0, f = 1.0 MHz) Ce— — 30 pF
SWITCHING TIMES
Turn-On Time
(V 30 Vd I 150 Ad
ton — — 45 ns
Delay Time (VCC = –30 Vdc, IC = –150 mAdc,
I
B1
= –15 mAdc
)
td— — 10
Rise Time
I
B1 = –
15
mAdc)
tr— — 40
Turn-Off Time
(V 60Vd I 150 Ad
toff — — 100 ns
Storage Time (VCC = –6.0 Vdc, IC = –150 mAdc,
I
B1
= I
B2
= –15 mAdc
)
ts— — 80
Fall Time
I
B1 =
I
B2 = –
15
mAdc)
tf— — 30
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle = 2.0%.
Figure 1. Delay and Rise
Time Test Circuit Figure 2. Storage and Fall
Time Test Circuit
INPUT
Zo = 50 Ω
PRF = 150 Hz
RISE TIME ≤ 2.0 ns
0
1.0 k
50
-16 V
200 ns
-30 V
200
TO OSCILLOSCOPE
RISE TIME ≤ 5.0 ns 0
1.0 k
50
-30 V
200 ns
-6.0 V
37
TO OSCILLOSCOPE
RISE TIME ≤ 5.0 ns
+15 V
1.0 k
1N916
INPUT
Zo = 50 Ω
PRF = 150 Hz
RISE TIME ≤ 2.0 ns
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TYPICAL ELECTRICAL CHARACTERISTICS
1000
100
10 -1000-100-10-1.0-0.1
IC, COLLECTOR CURRENT (mA)
hFE, CURRENT GAIN
TJ = 125°C
TJ = -55°C
TJ = 25°C
Figure 3. DC Current Gain
1000
100
10 -1000-100-10-1.0
VCE = -20 V
TJ = 25°C
IC, COLLECTOR CURRENT (mA)
Figure 4. Current Gain Bandwidth Product
fT
, CURRENTGAIN BANDWIDTH PRODUCT (MHz)
-1.0
-0.8
-0.6
-0.4
-0.2
0
VOLTAGE (VOLTS)
-500-200-100
-50-20-10-0.1 -0.2 -0.5 -1.0 -2.0 -5.0
IC, COLLECTOR CURRENT (mA)
Figure 5. “ON” Voltage
TJ = 25°C
VBE(sat) @ IC/IB = 10
VBE(on) @ VCE = -10 V
VCE(sat) @ IC/IB = 10
30
20
10
7.0
5.0
3.0
2.0
-0.1 -0.2 -0.3 -0.5 -0.7 -1.0 -2.0 -3.0 -5.0 -7.0 -10 -20 -30
REVERSE VOLTAGE (VOLTS)
Figure 6. Capacitances
CAPACITANCE (pF)
Ceb
Ccb
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INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE
POWER DISSIPATION
The power dissipation of the SOT-223 is a function of the
pad size. These can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature o f the die, RθJA, the thermal resistance from t h e
device junction to ambient; and the operating temperature,
TA. Using the values provided on the data sheet for the
SOT-223 package, PD can be calculated as follows.
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 1.5 watts.
PD = 150°C – 25°C
83.3°C/W = 1.5 watts
The 83.3°C/W for the SOT-223 package assumes the
recommended collector pad area of 965 sq. mils on a glass
epoxy printed circuit board to achieve a power dissipation of
1.5 watts. I f space is at a premium, a more realistic approach
is to use the device at a PD of 833 mW using the footprint
shown. Using a board material such as Thermal Clad, a
power dissipation of 1.6 watts can be achieved using the
same footprint.
MOUNTING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference should be a maximum of 10°C.
•The soldering temperature and time should not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient should be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied
during cooling
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.079
2.0
0.15
3.8
0.248
6.3
0.079
2.0
0.059
1.5
0.059
1.5
0.059
1.5
0.091
2.3
mm
inches
0.091
2.3
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PACKAGE DIMENSIONS
CASE 318E–04
ISSUE K
SOT–223 (TO–261)
H
S
F
A
B
D
G
L
4
123
0.08 (0003)
C
MK
J
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.249 0.263 6.30 6.70
INCHES
B0.130 0.145 3.30 3.70
C0.060 0.068 1.50 1.75
D0.024 0.035 0.60 0.89
F0.115 0.126 2.90 3.20
G0.087 0.094 2.20 2.40
H0.0008 0.0040 0.020 0.100
J0.009 0.014 0.24 0.35
K0.060 0.078 1.50 2.00
L0.033 0.041 0.85 1.05
M0 10 0 10
S0.264 0.287 6.70 7.30
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
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Notes
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Notes
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PZT2907AT1/D
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