PIC32MX3XX/4XX Data Sheet High-Performance, General Purpose and USB 32-bit Flash Microcontrollers (c) 2010 Microchip Technology Inc. DS61143G Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-131-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS61143G-page 2 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX High-Performance, General Purpose and USB 32-bit Flash Microcontrollers High-Performance 32-bit RISC CPU: * MIPS32(R) M4K(R) 32-bit core with 5-stage pipeline * 80 MHz maximum frequency * 1.56 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state Flash access * Single-cycle multiply and high-performance divide unit * MIPS16e(R) mode for up to 40% smaller code size * Two sets of 32 core register files (32-bit) to reduce interrupt latency * Prefetch Cache module to speed execution from Flash Microcontroller Features: * Operating voltage range of 2.3V to 3.6V * 32K to 512K Flash memory (plus an additional 12 KB of boot Flash) * 8K to 32K SRAM memory * Pin-compatible with most PIC24/dsPIC(R) DSC devices * Multiple power management modes * Multiple interrupt vectors with individually programmable priority * Fail-Safe Clock Monitor Mode * Configurable Watchdog Timer with on-chip Low-Power RC Oscillator for reliable operation Peripheral Features: * Atomic SET, CLEAR and INVERT operation on select peripheral registers * Up to 4-channel hardware DMA with automatic data size detection * USB 2.0-compliant full-speed device and On-The-Go (OTG) controller * USB has a dedicated DMA channel * 3 MHz to 25 MHz crystal oscillator * Internal 8 MHz and 32 kHz oscillators (c) 2010 Microchip Technology Inc. * Separate PLLs for CPU and USB clocks * Two I2CTM modules * Two UART modules with: - RS-232, RS-485 and LIN 1.2 support - IrDA(R) with on-chip hardware encoder and decoder * Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data and up to 16 address lines * Hardware Real-Time Clock and Calendar (RTCC) * Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers) * Five capture inputs * Five compare/PWM outputs * Five external interrupt pins * High-Speed I/O pins capable of toggling at up to 80 MHz * High-current sink/source (18 mA/18 mA) on all I/O pins * Configurable open-drain output on digital I/O pins Debug Features: * Two programming and debugging Interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire MIPS(R) standard enhanced JTAG interface * Unintrusive hardware-based instruction trace * IEEE Standard 1149.2-compatible (JTAG) boundary scan Analog Features: * Up to 16-channel 10-bit Analog-to-Digital Converter: - 1000 ksps conversion rate - Conversion available during Sleep, Idle * Two Analog Comparators * 5V tolerant input pins (digital pins only) DS61143G-page 3 PIC32MX3XX/4XX TABLE 1: PIC32MX GENERAL PURPOSE - FEATURES (1) EUART/SPI/I2CTM 10-bit A/D (ch) Comparators PMP/PSP JTAG 8 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes Trace 32 + 12(1) VREG 40 Programmable DMA Channels PT, MR Timers/Capture/Compare Program Memory (KB) 64 Data Memory (KB) MHz PIC32MX320F032H Packages(2) Device Pins GENERAL PURPOSE PIC32MX320F064H 64 PT, MR 80 64 + 12 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PIC32MX320F128H 64 PT, MR 80 128 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PIC32MX340F128H 64 PT, MR 80 128 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes PIC32MX340F256H 64 PT, MR 80 256 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes 80 512 + 12 (1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes 80 128 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes 80 128 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes 80 256 + 12(1) 32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes 80 512 + 12(1) 32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes PIC32MX340F512H PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L 64 PT, MR 100 PT 121 BG 100 PT 121 BG 100 PT 121 BG 100 PT 121 BG Legend: PT = TQFP Note 1: 2: This device features 12 KB Boot Flash memory. See Legend for an explanation of the acronyms. See Section 30.0 "Packaging Information" for details. DS61143G-page 4 MR = QFN BG = XBGA (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 2: PIC32MX USB - FEATURES Timers/Capture/Compare Programmable DMA Channels Dedicated USB DMA Channels VREG Trace EUART/SPI/I2CTM 10-bit A/D (ch) Comparators PMP/PSP JTAG 0 2 Yes No 2/1/2 16 2 Yes Yes 80 128 + 12 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes 80 256 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes 80 512 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes 80 128 + 12(1) 32 5/5/5 4 2 Yes No 2/2/2 16 2 Yes Yes 80 256 + 12(1) 32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes 80 512 + 12(1) 32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes 64 PT, MR 40 32 + 12(1) PIC32MX440F128H 64 PT, MR PIC32MX440F256H 64 PT, MR Device PIC32MX420F032H PIC32MX440F512H PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L Pins Program Memory (KB) 5/5/5 MHz 8 (1) Packages(2) Data Memory (KB) USB 64 PT, MR 100 PT 121 BG 100 PT 121 BG 100 PT 121 BG Legend: PT = TQFP MR = QFN Note 1: 2: This device features 12 KB Boot Flash memory. See Legend for an explanation of the acronyms. See Section 30.0 "Packaging Information" for details. (c) 2010 Microchip Technology Inc. BG = XBGA DS61143G-page 5 PIC32MX3XX/4XX Pin Diagrams = Pins are up to 5V tolerant PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin QFN (General Purpose) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 U1CTS/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 SCL2/U2TX/PMA8/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61143G-page 6 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin TQFP (General Purpose) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 U1CTS/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 SCL2/U2TX/PMA8/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (c) 2010 Microchip Technology Inc. DS61143G-page 7 PIC32MX3XX/4XX Pin Diagrams (Continued) 100-Pin TQFP (General Purpose) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 IC2/RD9 RTCC/IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD U1CTS/CN20/RD14 U1RTS/CN21/RD15 U2RX/PMA9/CN17/RF4 U2TX/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 DS61143G-page 8 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCAP/ VDDCORE RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 RB5 RB4 VSS VDD NC VDD NC RF7 RF6 RG2 RA2 RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note 1: Refer to Table 3 for full pin names. (c) 2010 Microchip Technology Inc. DS61143G-page 9 PIC32MX3XX/4XX TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, AND PIC32MX360F128L, AND PIC32MX360F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 IC2/RD9 A4 PMD0/RE0 E11 INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8 A7 ENVREG F3 SS2/PMA2/CN11/RG9 A8 VSS F4 SDI2/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 VDD B2 RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 INT1/RE8 B6 PMD11/RF0 G2 INT2/RE9 B7 VCAP/VDDCORE G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) C2 VDD G9 TDO/RA5 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 C5 TRCLK/RA6 H1 AN5/C1IN+/CN7/RB5 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 SDI1/RF7 D2 PMD7/RE7 H9 SCK1/INT0/RF6 D3 PMD5/RE5 H10 SCL1/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/SS1/CN4/RB2 D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 PMD13/CN19/RD13 J4 AVDD D9 OC1/RD0 J5 AN11/PMA12/RB11 D10 No Connect (NC) J6 TCK/RA1 D11 IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12 E1 T5CK/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 SCK2/PMA5/CN8/RG6 J10 SDO1/RF8 E4 T3CK/RC2 J11 SDA1/RG3 E5 VDD K1 PGEC1/AN1/CN3/RB1 E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0 DS61143G-page 10 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, AND PIC32MX360F128L, AND PIC32MX360F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name E7 VSS K3 VREF+/CVREF+/PMA6/RA10 K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 U1TX/RF3 L9 CN20/U1CTS/RD14 K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/PMA7/RA9 (c) 2010 Microchip Technology Inc. DS61143G-page 11 PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin QFN (USB) PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 U1TX/OC4/RD3 U1RX/OC3/RD2 U1RTS/OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 Note: SCL2/U2TX/PMA8/CN18/RF5 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12//RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61143G-page 12 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 U1TX/OC4/RD3 U1RX/OC3/RD2 U1RTS/OC2/RD1 64-Pin TQFP (USB) PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12//RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 SCL2/U2TX/PMA8/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (c) 2010 Microchip Technology Inc. DS61143G-page 13 PIC32MX3XX/4XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX/RF8 U1RX/RF2 USBID/RF3 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD U1CTS/CN20/RD14 U1RTS/CN21/RD15 U2RX/PMA9/CN17/RF4 U2TX/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP (USB) DS61143G-page 14 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCAP/ VDDCORE RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 RB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2 RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note 1: Refer to Table 4 for full pin names. (c) 2010 Microchip Technology Inc. DS61143G-page 15 PIC32MX3XX/4XX TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8 A7 ENVREG F3 SS2/PMA2/CN11/RG9 A8 VSS F4 SDI2/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 Vdd B2 RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 INT1/RE8 B6 PMD11/RF0 G2 INT2/RE9 B7 VCAP/VDDCORE G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) C2 VDD G9 TDO/RA5 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 C5 TRCLK/RA6 H1 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 VBUS D2 PMD7/RE7 H9 VUSB D3 PMD5/RE5 H10 D+/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2 D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 CN19/PMD13/RD13 J4 AVDD D9 SDO1/OC1/INT0/RD0 J5 AN11/PMA12/RB11 D10 No Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12 E1 T5CK/SDI1/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 SCK2/PMA5/CN8/RG6 J10 U1TX/RF8 E4 T3CK/RC2 J11 D-/RG3 E5 VDD K1 PGEC1/AN1/CN3/RB1 E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0 DS61143G-page 16 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name E7 VSS K3 VREF+/CVREF+/PMA6/RA10 K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 U1CTS/CN20/RD14 K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/PMA7/RA9 (c) 2010 Microchip Technology Inc. DS61143G-page 17 PIC32MX3XX/4XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 21 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 31 3.0 PIC32MX MCU ........................................................................................................................................................................... 35 4.0 Memory Organization ................................................................................................................................................................. 41 5.0 Flash Program Memory .............................................................................................................................................................. 85 6.0 Resets ........................................................................................................................................................................................ 87 7.0 Interrupt Controller ..................................................................................................................................................................... 89 8.0 Oscillator Configuration .............................................................................................................................................................. 93 9.0 Prefetch Cache........................................................................................................................................................................... 95 10.0 Direct Memory Access (DMA) Controller .................................................................................................................................. 97 11.0 USB On-The-Go (OTG).............................................................................................................................................................. 99 12.0 I/O Ports ................................................................................................................................................................................... 101 13.0 Timer1 ...................................................................................................................................................................................... 103 14.0 Timers 2, 3, 4, 5 ...................................................................................................................................................................... 105 15.0 Input Capture............................................................................................................................................................................ 107 16.0 Output Compare....................................................................................................................................................................... 109 17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 111 18.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 113 19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 115 20.0 Parallel Master Port (PMP) ...................................................................................................................................................... 119 21.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 121 22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 123 23.0 Comparator .............................................................................................................................................................................. 125 24.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 127 25.0 Power-Saving Features ........................................................................................................................................................... 129 26.0 Special Features ...................................................................................................................................................................... 131 27.0 Instruction Set .......................................................................................................................................................................... 143 28.0 Development Support............................................................................................................................................................... 149 29.0 Electrical Characteristics .......................................................................................................................................................... 153 30.0 Packaging Information.............................................................................................................................................................. 191 Index ................................................................................................................................................................................................. 205 DS61143G-page 18 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2010 Microchip Technology Inc. DS61143G-page 19 PIC32MX3XX/4XX NOTES: DS61143G-page 20 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 1.0 DEVICE OVERVIEW This document contains device-specific information for the PIC32MX3XX/4XX devices. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX3XX/4XX families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. BLOCK DIAGRAM(1,2) FIGURE 1-1: VDDCORE/VCAP OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators Power-up Timer FRC/LPRC Oscillators ENVREG Oscillator Start-up Timer Voltage Regulator PLL PLL-USB Watchdog Timer USBCLK SYSCLK Timing Generation MCLR Power-on Reset Precision Band Gap Reference DIVIDERS VDD, VSS Brown-out Reset PBCLK CN1-22 Peripheral Bus Clocked by SYSCLK Timer1-5 PORTA Priority Interrupt Controller PWM OC1-5 USB EJTAG PORTC MIPS32(R) PORTD DMAC M4K(R) 32 32 CPU Core IS DS 32 PORTE ICD INT 32 32 32 32 Bus Matrix PORTF 32 PORTG Prefetch Module 32 32 Peripheral Bus Clocked by PBCLK JTAG BSCAN PORTB IC1-5 SPI1,2 I2C1,2 32 PMP 10-bit ADC Data RAM Peripheral Bridge UART1,2 128 128-bit wide Program Flash Memory Note 1: 2: RTCC Flash Controller Comparators Some features are not available on all device variants. BOR functionality is provided when the on-board voltage regulator is enabled. (c) 2010 Microchip Technology Inc. DS61143G-page 21 PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type AN0 16 25 K2 I Analog AN1 15 24 K1 I Analog AN2 14 23 J2 I Analog AN3 13 22 J1 I Analog AN4 12 21 H2 I Analog AN5 11 20 H1 I Analog AN6 17 26 L1 I Analog AN7 18 27 J3 I Analog AN8 21 32 K4 I Analog AN9 22 33 L4 I Analog AN10 23 34 L5 I Analog AN11 24 35 J5 I Analog AN12 27 41 J7 I Analog AN13 28 42 L7 I Analog AN14 29 43 K7 I Analog AN15 30 44 L8 I Analog CLKI 39 63 F9 I CLKO 40 64 F11 O OSC1 39 63 F9 I OSC2 40 64 F11 I/O SOSCI 47 73 C10 I SOSCO 48 74 B11 O Description Analog input channels. ST/CMOS External clock source input. Always associated with OSC1 pin function. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. -- 32.768 kHz low-power oscillator crystal output. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. DS61143G-page 22 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type CN0 48 74 B11 I ST CN1 47 73 C10 I ST CN2 16 25 K2 I ST CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I ST CN15 54 83 D7 I ST CN16 55 84 C7 I ST CN17 31 49 L10 I ST CN18 32 50 L11 I ST CN19 -- 80 D8 I ST CN20 -- 47 L9 I ST Description Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. CN21 -- 48 K9 I ST IC1 42 68 E9 I ST IC2 43 69 E10 I ST IC3 44 70 D11 I ST IC4 45 71 C11 I ST IC5 52 79 A9 I ST OCFA 17 26 L1 I ST Output Compare Fault A Input. OC1 46 72 D9 O -- Output Compare output 1. OC2 49 76 A11 O -- Output Compare output 2 OC3 50 77 A10 O -- Output Compare output 3. OC4 51 78 B9 O -- Output Compare output 4. OC5 52 81 C8 O -- Output Compare output 5. OCFB 30 44 L8 I ST Output Compare Fault B Input. INT0 35,46 55,72 H9,D9 I ST External interrupt 0. INT1 42 18 61 I ST External interrupt 1. INT2 43 19 62 I ST External interrupt 2. Capture inputs 1-5. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. (c) 2010 Microchip Technology Inc. DS61143G-page 23 PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type Description INT3 44 66 E11 I ST External interrupt 3. INT4 45 67 E8 I ST External interrupt 4. RA0 -- 17 G3 I/O ST PORTA is a bidirectional I/O port. RA1 -- 38 J6 I/O ST RA2 -- 58 H11 I/O ST RA3 -- 59 G10 I/O ST RA4 -- 60 G11 I/O ST RA5 -- 61 G9 I/O ST RA6 -- 91 C5 I/O ST RA7 -- 92 B5 I/O ST RA9 -- 28 L2 I/O ST RA10 -- 29 K3 I/O ST RA14 -- 66 E11 I/O ST RA15 -- 67 E8 I/O ST RB0 16 25 K2 I/O ST RB1 15 24 K1 I/O ST RB2 14 23 J2 I/O ST RB3 13 22 J1 I/O ST RB4 12 21 H2 I/O ST RB5 11 20 H1 I/O ST RB6 17 26 L1 I/O ST RB7 18 27 J3 I/O ST RB8 21 32 K4 I/O ST RB9 22 33 L4 I/O ST RB10 23 34 L5 I/O ST RB11 24 35 J5 I/O ST RB12 27 41 J7 I/O ST RB13 28 42 L7 I/O ST RB14 29 43 K7 I/O ST RB15 30 44 L8 I/O ST RC1 -- 6 D1 I/O ST RC2 -- 7 E4 I/O ST RC3 -- 8 E2 I/O ST RC4 -- 9 E1 I/O ST RC12 39 63 F9 I/O ST RC13 47 73 C10 I/O ST RC14 48 74 B11 I/O ST RC15 40 64 F11 I/O ST PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. DS61143G-page 24 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type RD0 46 72 D9 I/O ST RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 -- 79 A9 I/O ST RD13 -- 80 D8 I/O ST RD14 -- 47 L9 I/O ST RD15 -- 48 K9 I/O ST RE0 60 93 A4 I/O ST RE1 61 94 B4 I/O ST RE2 62 98 B3 I/O ST RE3 63 99 A2 I/O ST RE4 64 100 A1 I/O ST RE5 1 3 D3 I/O ST RE6 2 4 C1 I/O ST RE7 3 5 D2 I/O ST RE8 -- 18 G1 I/O ST RE9 -- 19 G2 I/O ST RF0 58 87 B6 I/O ST RF1 59 88 A6 I/O ST RF2 34 52 K11 I/O ST RF3 33 51 K10 I/O ST RF4 31 49 L10 I/O ST RF5 32 50 L11 I/O ST RF6 35 55 H9 I/O ST RF7 -- 54 H8 I/O ST RF8 -- 53 J10 I/O ST RF12 -- 40 K6 I/O ST RF13 -- 39 L6 I/O ST Description PORTD is a bidirectional I/O port. PORTE is a bidirectional I/O port. PORTF is a bidirectional I/O port. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. (c) 2010 Microchip Technology Inc. DS61143G-page 25 PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type RG0 -- 90 A5 I/O ST RG1 -- 89 E6 I/O ST RG6 4 10 E3 I/O ST RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST Description PORTG is a bidirectional I/O port. RG9 8 14 F3 I/O ST RG12 -- 96 C3 I/O ST RG13 -- 97 A3 I/O ST RG14 -- 95 C4 I/O ST RG15 -- 1 B2 I/O ST RG2 37 57 H10 I ST RG3 36 56 J11 I ST T1CK 48 74 B11 I ST T2CK -- 6 D1 I ST Timer2 external clock input. T3CK -- 7 E4 I ST Timer3 external clock input. T4CK -- 8 E2 I ST Timer4 external clock input. PORTG input pins. Timer1 external clock input. T5CK -- 9 E1 I ST Timer5 external clock input. U1CTS 43 47 L9 I ST UART1 clear to send. U1RTS 35, 49 48 K9 O -- UART1 ready to send. U1RX 34, 50 52 K11 I ST UART1 receive. U1TX 33, 51 51, 53 J10, K10 O -- UART1 transmit. U2CTS 21 40 K6 I ST UART2 clear to send. U2RTS 29 39 L6 O -- UART2 ready to send. U2RX 31 49 L10 I ST UART2 receive. U2TX 32 50 L11 O -- UART2 transmit. SCK1 35 55, 70 D11, H9 I/O ST Synchronous serial clock input/output for SPI1. SDI1 34 9, 54 E1, H8 I ST SPI1 data in. SDO1 33 53, 72 D9, J10 O -- SPI1 data out. SS1 14 23, 69 E10, J2 I/O ST SPI1 slave synchronization or frame pulse I/O. SCK2 4 10 E3 I/O ST Synchronous serial clock input/output for SPI2. SDI2 5 11 F4 I ST SPI2 data in. SDO2 6 12 F2 O -- SPI2 data out. SS2 8 14 F3 I/O ST SPI2 slave synchronization or frame pulse I/O. SCL1 37, 44 57, 66 E11, H10 I/O ST Synchronous serial clock input/output for I2C1. SDA1 36, 43 56, 67 E8, J11 I/O ST Synchronous serial data input/output for I2C1. SCL2 32 58 H11 I/O ST Synchronous serial clock input/output for I2C2. SDA2 31 59 G10 I/O ST Synchronous serial data input/output for I2C2. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. DS61143G-page 26 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type Description TMS 23 17 G3 I ST JTAG Test mode select pin. TCK 27 38 J6 I ST JTAG test clock input pin. TDI 28 60 G11 I ST JTAG test data input pin. TDO 24 61 G9 O -- JTAG test data output pin. RTCC 42 68 E9 O -- Real-Time Clock Alarm Output. CVREF- 15 28 L2 I Analog Comparator Voltage Reference (low). CVREF+ 16 29 K3 I Analog Comparator Voltage Reference (high). CVREFOUT 23 34 L5 O Analog Comparator Voltage Reference Output. C1IN- 12 21 H2 I Analog Comparator 1 Negative Input. C1IN+ 11 20 H1 I Analog Comparator 1 Positive Input. C1OUT 21 32 K4 O -- C2IN- 14 23 J2 I Analog Comparator 2 Negative Input. C2IN+ 13 22 J1 I Analog Comparator 2 Positive Input. Comparator 1 Output. C2OUT 22 33 L4 O -- PMA0 30 44 L8 I/O TTL/ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Comparator 2 Output. PMA1 29 43 K7 I/O TTL/ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 8 14 F3 O -- PMA3 6 12 F2 O -- PMA4 5 11 F4 O -- PMA5 4 10 E3 O -- PMA6 16 29 K3 O -- PMA7 22 28 L2 O -- PMA8 32 50 L11 O -- PMA9 31 49 L10 O -- PMA10 28 42 L7 O -- PMA11 27 41 J7 O -- PMA12 24 35 J5 O -- PMA13 23 34 L5 O -- PMA14 45 71 C11 O -- PMA15 44 70 D11 O -- PMCS1 45 71 C11 O -- Parallel Master Port Chip Select 1 Strobe. PMCS2 44 70 D11 O -- Parallel Master Port Chip Select 2 Strobe. Parallel Master Port Address (De-multiplexed Master Modes). Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. (c) 2010 Microchip Technology Inc. DS61143G-page 27 PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type PMD0 60 93 A4 I/O TTL/ST PMD1 61 94 B4 I/O TTL/ST PMD2 62 98 B3 I/O TTL/ST PMD3 63 99 A2 I/O TTL/ST PMD4 64 100 A1 I/O TTL/ST PMD5 1 3 D3 I/O TTL/ST PMD6 2 4 C1 I/O TTL/ST PMD7 3 5 D2 I/O TTL/ST PMD8 -- 90 A5 I/O TTL/ST PMD9 -- 89 E6 I/O TTL/ST Description Parallel Master Port Data (De-multiplexed Master mode) or Address/Data (Multiplexed Master modes). PMD10 -- 88 A6 I/O TTL/ST PMD11 -- 87 B6 I/O TTL/ST PMD12 -- 79 A9 I/O TTL/ST PMD13 -- 80 D8 I/O TTL/ST PMD14 -- 83 D7 I/O TTL/ST PMD15 -- 84 C7 I/O TTL/ST PMRD 53 82 B8 O -- Parallel Master Port Read Strobe. PMWR 52 81 C8 O -- Parallel Master Port Write Strobe. PMALL 30 44 L8 O -- Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). PMALH 29 43 K7 O -- Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). VBUS 34 54 H8 I Analog VUSB 35 55 H9 P -- USB Internal Transceiver Supply. VBUSON 11 20 H1 O -- USB Host and OTG Bus Power Control Output. D+ 37 57 H10 I/O Analog USB D+. D- 36 56 J11 I/O Analog USB D-. USB Bus Power Monitor. USBID 33 51 K10 I ST USB OTG ID Detect. ENVREG 57 86 A7 I ST Enable for On-Chip Voltage Regulator. TRCLK -- 91 C5 O -- Trace Clock. Trace Data Bits 0-3. TRD0 -- 97 A3 O -- TRD1 -- 96 C3 O -- TRD2 -- 95 C4 O -- TRD3 -- 92 B5 O -- PGED1 16 25 K2 I/O ST Data I/O pin for programming/debugging communication channel 1. PGEC1 15 24 K1 I ST Clock input pin for programming/debugging communication channel 1. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. DS61143G-page 28 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type Description PGED2 18 27 J3 I/O ST Data I/O pin for programming/debugging communication channel 2. PGEC2 17 26 L1 I ST Clock input pin for programming/debugging communication channel 2. MCLR 7 13 F1 I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD 19 30 J4 P P Positive supply for analog modules. This pin must be connected at all times. AVSS 20 31 L3 P P Ground reference for analog modules. C2, C9, E5, F8, G5, H4, H6, K8 P -- Positive supply for peripheral logic and I/O pins. VDD VCAP/ VDDCORE 10, 26, 38 2, 16, 37, 46, 62 56 85 B7 P -- CPU logic filter capacitor connection. 9, 25, 41 15, 36, 45, 65, 75 A8, B10, D4, D5, E7, F10, F5, G6, G7, H3 P -- Ground reference for logic and I/O pins. VREF+ 16 29 K3 I Analog Analog voltage reference (high) input. VREF- 15 28 L2 I Analog Analog voltage reference (low) input. Vss Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. (c) 2010 Microchip Technology Inc. DS61143G-page 29 PIC32MX3XX/4XX NOTES: DS61143G-page 30 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC32MX3XX/4XX family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see Section 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 "Decoupling Capacitors") * VCAP/VDDCORE (see Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)") * MCLR pin (see Section 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSC1 and OSC2 pins when external oscillator source is used (see Section 2.8 "External Oscillator Pins") 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: Recommendation of 0.1 F (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Additionally, the following pins may be required: * VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of ADC use and ADC voltage reference source. (c) 2010 Microchip Technology Inc. DS61143G-page 31 PIC32MX3XX/4XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION VDD 0.1 F Ceramic CBP R R1 MCLR C VSS VCAP/VDDCORE VDD CEFC PIC32MX VSS 10 2.2.1 VDD 0.1 F Ceramic CBP VSS VDD AVSS VDD AVDD 0.1 F Ceramic CBP VSS 0.1 F Ceramic CBP 0.1 F Ceramic CBP BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible. 2.3 2.3.1 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: * Device Reset * Device Programming and Debugging Pulling The MCLR pin low generates a device reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) R R1 INTERNAL REGULATOR MODE A low-ESR (< 1 Ohm) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VDDCORE pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 29.0 "Electrical Characteristics" for additional information on CEFC specifications. This mode is enabled by connecting the ENVREG pin to VDD. 2.3.2 2.4 JP PIC32MX C Note 1: R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 3: The capacitor can be sized to prevent unintentional resets from brief glitches or to extend the device reset period during POR. EXTERNAL REGULATOR MODE In this mode the core voltage is supplied externally through the VDDCORE pin. A low-ESR capacitor of 10 F is recommended on the VDDCORE pin. This mode is enabled by grounding the ENVREG pin. MCLR The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 26.3 "On-Chip Voltage Regulator" for details. DS61143G-page 32 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 2, MPLAB ICD 3 or MPLAB REAL ICETM. For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" DS51331 * "Using MPLAB(R) ICD 2" (poster) DS51265 * "MPLAB(R) ICD 2 Design Advisory" DS51566 * "Using MPLAB(R) ICD 3" (poster) DS51765 * "MPLAB(R) ICD 3 Design Advisory" DS51764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS51616 * "Using MPLAB(R) REAL ICETM" (poster) DS51749 2.6 JTAG The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2.7 Trace The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 Ohm series resistor between the trace pins and the trace connector. 2.8 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Oscillator Secondary Guard Trace Guard Ring Main Oscillator (c) 2010 Microchip Technology Inc. DS61143G-page 33 PIC32MX3XX/4XX 2.9 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins by setting all bits in the ADPCFG register. 2.10 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternately, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic `0', which may affect user application functionality. DS61143G-page 34 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX MCU Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "MCU" (DS61113) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32(R) M4K(R) Processor Core are available at: www.mips.com/products/cores/ 32-bit-cores/mips32-m4k/#. * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. * The MCU module is the heart of the PIC32MX3XX/4XX Family processor. The MCU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. * 3.1 * Features * 5-stage pipeline * 32-bit Address and Data Paths * MIPS32 Enhanced Architecture (Release 2) - Multiply-Accumulate and Multiply-Subtract Instructions - Targeted Multiply Instruction - Zero/One Detect Instructions - WAIT Instruction - Conditional Move Instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base FIGURE 3-1: * * - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions MIPS16e(R) Code Compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Bus Interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency Autonomous Multiply/Divide Unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 34 clock latency (dividend (rs) sign extension-dependent) Power Control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks EJTAG Debug and Instruction Trace - Support for single stepping - Virtual instruction and data address/value - breakpoints - PC tracing with trace compression MCU BLOCK DIAGRAM MCU EJTAG MDU Execution Core (RF/ALU/Shift) System Coprocessor (c) 2010 Microchip Technology Inc. Trace TAP FMT Bus Interface Trace I/F Off-Chip Debug I/F Dual Bus I/F Bus Matrix 3.0 Power Mgmt. DS61143G-page 35 PIC32MX3XX/4XX 3.2 Architecture Overview The PIC32MX3XX/4XX Family core contains several logic blocks working together in parallel, providing an efficient high performance computing engine. The following blocks are included with the core: * Execution Unit * Multiply/Divide Unit (MDU) * System Control Coprocessor (CP0) * Fixed Mapping Translation (FMT) * Dual Internal Bus interfaces * Power Management * MIPS16e Support * Enhanced JTAG (EJTAG) Controller 3.2.1 EXECUTION UNIT The PIC32MX3XX/4XX Family core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit general purpose registers used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions 3.2.2 MULTIPLY/DIVIDE UNIT (MDU) The PIC32MX3XX/4XX Family core includes a multiply/divide unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the integer unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32MX core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16bit-wide rs, 15 iterations are skipped, and for a 24-bitwide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter and Store Aligner DS61143G-page 36 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 3-1: PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, MSUB/MSUBU 16 bits 1 1 32 bits 2 2 MUL 16 bits 2 1 32 bits 3 2 DIV/DIVU 8 bits 12 11 16 bits 19 18 24 bits 26 25 33 32 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the general purpose register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction, required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, multiply-add (MADD) and multiply-subtract (MSUB), are used to perform the multiplyaccumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds TABLE 3-2: the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (kernel, user and debug), and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2. COPROCESSOR 0 REGISTERS Register Register Number Name Function 0-6 Reserved Reserved in the PIC32MX3XX/4XX Family core 7 HWREna Enables access via the RDHWR instruction to selected hardware registers 8 BadVAddr(1) Reports the address for the most recent address-related exception Processor cycle count 9 Count(1) 10 Reserved Reserved in the PIC32MX3XX/4XX Family core 11 Compare(1) Timer interrupt control 12 Status(1) Processor status and control 12 IntCtl(1) Interrupt system status and control 12 SRSCtl(1) Shadow register set status and control 12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set 13 Cause(1) Cause of last general exception 14 EPC(1) Program counter at last exception 15 PRId Processor identification and revision 15 EBASE Exception vector base register 16 Config Configuration register 16 Config1 Configuration register 1 16 Config2 Configuration register 2 16 Config3 Configuration register 3 (c) 2010 Microchip Technology Inc. DS61143G-page 37 PIC32MX3XX/4XX TABLE 3-2: COPROCESSOR 0 REGISTERS (CONTINUED) Register Register Number Name Function 17-22 Reserved Reserved in the PIC32MX3XX/4XX Family core 23 Debug(2) Debug control and exception status 24 DEPC(2) Program counter at last debug exception 25-29 Reserved Reserved in the PIC32MX3XX/4XX Family core 30 ErrorEPC(1) Program counter at last error 31 DESAVE(2) Debug handler scratchpad register Note 1: 2: Registers used in exception processing. Registers used during debug. Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 shows the exception types in order of priority. TABLE 3-3: PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR) DSS EJTAG Debug Single Step DINT EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the EjtagBrk bit in the ECR register NMI Interrupt DIB AdEL IBE Assertion of NMI signal Assertion of unmasked hardware or software interrupt signal EJTAG debug hardware instruction break matched Fetch address alignment error Fetch reference to protected address Instruction fetch bus error DBp EJTAG Breakpoint (execution of SDBBP instruction) Sys Execution of SYSCALL instruction Bp Execution of BREAK instruction RI Execution of a Reserved Instruction CpU Execution of a coprocessor instruction for a coprocessor that is not enabled CEU Execution of a CorExtend instruction when CorExtend is not enabled Ov Execution of an arithmetic instruction that overflowed Tr Execution of a trap (when trap condition is true) DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value) AdEL Load address alignment error Load reference to protected address AdES Store address alignment error Store to protected address DBE Load or store bus error DDBL DS61143G-page 38 EJTAG data hardware breakpoint matched in load data compare (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 3.3 Power Management The PIC32MX3XX/4XX Family core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking power-down mode is through execution of the WAIT instruction. For more information on power management, see Section 25.0 "Power-Saving Features". 3.3.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX3XX/4XX Family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption. (c) 2010 Microchip Technology Inc. 3.4 EJTAG Debug Support The PIC32MX3XX/4XX Family core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard user mode and kernel modes of operation, the PIC32MX3XX/4XX Family core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the PIC32MX3XX/4XX Family core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define what registers are selected and how they are used. DS61143G-page 39 PIC32MX3XX/4XX NOTES: DS61143G-page 40 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 4.0 MEMORY ORGANIZATION Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 3. "Memory Organization" (DS61115) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX3XX/4XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions including program, data memory, SFRs and Configuration registers reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX3XX/4XX to execute from data memory. (c) 2010 Microchip Technology Inc. 4.1 * * * * * * * * Key Features 32-bit native data width Separate User and Kernel mode address space Flexible program Flash memory partitioning Flexible data RAM partitioning for data and program space Separate boot Flash memory for protected code Robust bus exception handling to intercept runaway code Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable and non-cacheable address regions 4.2 PIC32MX3XX/4XX Memory Layout PIC32MX3XX/4XX microcontrollers implement two address spaces: Virtual and Physical. All hardware resources such as program memory, data memory and peripherals are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by peripherals such as DMA and Flash controller that access memory independently of CPU. DS61143G-page 41 PIC32MX3XX/4XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX320F032H AND PIC32MX420F032H DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD008000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD007FFF Program Flash(2) 0xBD000000 0xA0002000 Reserved 0xA0001FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D008000 0x9D007FFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80002000 0x1D008000 Reserved 0x1D007FFF Program Flash(2) 0x1D000000 0x80001FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS61143G-page 42 Reserved Reserved RAM(2) 0x00002000 0x00001FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICE(1) Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 SFRs 0xBF800000 Reserved 0xBD010000 KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 Reserved 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x1FC03000 Device Configuration Registers Reserved 0x9FC03000 0x9FC02FFF Device Configuration Registers 0x9FC02FEF 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D010000 0x9D00FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80004000 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) 0x00004000 0x00003FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2010 Microchip Technology Inc. DS61143G-page 43 PIC32MX3XX/4XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX320F128H AND PIC32MX320F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D020000 0x9D01FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80004000 0x1D020000 Reserved 0x1D01FFFF Program Flash(2) 0x1D000000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS61143G-page 44 Reserved Reserved RAM(2) 0x00004000 0x00003FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H AND PIC32MX440F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 SFRs 0xBF800000 Reserved 0xBD020000 KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC03000 Device Configuration Registers Reserved 0x9FC03000 0x9FC02FFF Device Configuration Registers 0x9FC02FEF 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D020000 0x9D01FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80008000 0x1D020000 Reserved 0x1D01FFFF Program Flash(2) 0x1D000000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) 0x00008000 0x00007FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2010 Microchip Technology Inc. DS61143G-page 45 PIC32MX3XX/4XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H AND PIC32MX460F256L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x1FC03000 Device Configuration Registers Reserved Device Configuration Registers 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D040000 0x9D03FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80008000 0x1D040000 Reserved 0x1D03FFFF Program Flash(2) 0x1D000000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: DS61143G-page 46 Reserved Reserved RAM(2) 0x00008000 0x00007FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H AND PIC32MX460F512L DEVICES(1) Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 SFRs 0xBF800000 Reserved 0xBD080000 KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC03000 Device Configuration Registers Reserved 0x9FC03000 0x9FC02FFF Device Configuration Registers 0x9FC02FEF 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x9D080000 0x9D07FFFF Program Flash(2) KSEG0 0x1F8FFFFF Reserved SFRs 0x1F800000 Reserved 0x9D000000 0x80008000 0x1D080000 Reserved 0x1D07FFFF Program Flash(2) 0x1D000000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) 0x00008000 0x00007FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). (c) 2010 Microchip Technology Inc. DS61143G-page 47 BUS MATRIX REGISTERS MAP Register Name Bit Range 2000 BMX CON(1) 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 -- -- -- -- -- BMXCHEDMA -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 BMX DKPBA(1) 15:0 -- -- -- -- -- -- -- -- 31:16 BMX 2020 DUDBA(1) 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 2010 2030 BMX DUPBA(1) 15:0 2040 31:16 BMX DRMSZ 15:0 2050 2060 31:16 BMX PUPBA(1) 15:0 BMX PFMSZ 31:16 15:0 31:16 20/4 19/3 18/2 17/1 16/0 All Resets Virtual Address (BF88_#) Bits 22/6 21/5 -- -- -- -- BMXWSDRM -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F BMXARB<2:0> 0042 BMXDKPBA<15:0> -- 0000 BMXDUDBA<15:0> -- 0000 BMXDUPBA<15:0> 0000 0000 xxxx BMXDRMSZ<31:0> xxxx -- -- -- -- -- -- -- -- -- BMXPUPBA<15:0> BMXPFMSZ<31:0> -- -- -- BMXPUPBA<19:16> 0000 0000 xxxx xxxx 0000 BMX BMXBOOTSZ<31:0> BOOTSZ 15:0 3000 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET,and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 2070 PIC32MX3XX/4XX DS61143G-page 48 TABLE 4-1: (c) 2010 Microchip Technology Inc. INTCON 1010 INTSTAT 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 IEC1 1090 IPC0 10A0 10B0 10C0 10E0 10F0 1100 1110 DS61143G-page 49 1120 1140 Legend: Note 1: IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11 30/14 29/13 28/12 27/11 26/10 -- 31:16 -- -- -- -- -- 15:0 -- FRZ -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- -- RIPL<2:0> 31:16 20/4 19/3 18/2 17/1 16/0 VEC<5:0> 0000 IPTMR<31:0> 15:0 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF 0000 0000 0000 SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 0000 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 31:16 -- -- -- -- -- -- USBIF FCEIF -- -- -- -- DMA3IF DMA2IF DMA1IF DMA0IF 0000 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 -- -- -- -- -- -- USBIE FCEIE -- -- -- -- DMA3IE DMA2IE DMA1IE DMA0IE 0000 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 -- -- -- INT0IP<2:0> INT0IS<1:0> -- -- -- CS1IP<2:0> CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- SPI1IP<2:0> SPI1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 15:0 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 15:0 -- -- -- I2C1IP<2:0> I2C1IS<1:0> -- -- -- U1IP<2:0> U1IS<1:0> 0000 31:16 -- -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 31:16 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- -- -- -- -- -- 0000 -- -- -- SPI1RXIE SPI1TXIE -- -- -- -- -- 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX 10D0 IPC1 31/15 All Resets 1000 Bit Range Register Name Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. INTERRUPT REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) TABLE 4-2: INTERRUPT REGISTERS MAP FOR PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L, PIC32MX340F256L AND PIC32MX340F512L DEVICES ONLY(1) INTCON 1010 INTSTAT 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 IEC1 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1140 IPC11 Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 -- 31:16 -- -- -- -- -- 15:0 -- FRZ -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- -- RIPL<2:0> 31:16 20/4 19/3 18/2 17/1 16/0 All Resets 1000 Bit Range Register Name (c) 2010 Microchip Technology Inc. Virtual Address (BF88_#) Bits VEC<5:0> 0000 IPTMR<31:0> 15:0 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF 0000 0000 0000 SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 0000 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 31:16 -- -- -- -- -- -- -- FCEIF -- -- -- -- DMA3IF DMA2IF DMA1IF DMA0IF 0000 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 -- -- -- -- -- -- -- FCEIE -- -- -- -- DMA3IE DMA2IE DMA1IE DMA0IE 0000 15:0 RTCCIE FSCMIE I2C2MIE -- -- -- -- -- SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 -- -- -- INT0IP<2:0> INT0IS<1:0> -- -- -- CS1IP<2:0> CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- SPI1IP<2:0> SPI1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 15:0 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 15:0 -- -- -- I2C1IP<2:0> I2C1IS<1:0> -- -- -- U1IP<2:0> U1IS<1:0> 0000 31:16 -- -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 31:16 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- -- -- -- -- -- 0000 -- -- -- SPI1RXIE SPI1TXIE -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 50 TABLE 4-3: INTERRUPT REGISTERS MAP FOR PIC32MX320F032H, PIC32MXF064H, PIC32MX320F128H AND PIC32MX320F128L DEVICES ONLY(1) INTCON 1010 INTSTAT 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 1090 10A0 10B0 10D0 10E0 10F0 1100 1110 DS61143G-page 51 1140 Legend: Note 1: IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC11 30/14 29/13 28/12 27/11 26/10 -- 31:16 -- -- -- -- -- 15:0 -- FRZ -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- -- RIPL<2:0> 31:16 20/4 19/3 18/2 17/1 16/0 VEC<5:0> 0000 IPTMR<31:0> 15:0 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF 0000 0000 0000 SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 0000 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 31:16 -- -- -- -- -- -- -- FCEIF -- -- -- -- -- -- -- -- 0000 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 -- -- -- -- -- -- -- FCEIE -- -- -- -- -- -- -- -- 0000 15:0 RTCCIE FSCMIE I2C2MIE -- -- -- -- -- SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 31:16 -- -- -- INT0IS<1:0> -- -- -- INT0IP<2:0> SPI1RXIE SPI1TXIE CS1IP<2:0> 0000 CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- SPI1IP<2:0> SPI1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 15:0 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 15:0 -- -- -- I2C1IP<2:0> I2C1IS<1:0> -- -- -- U1IP<2:0> U1IS<1:0> 0000 31:16 -- -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 31:16 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX 10C0 IEC1 31/15 All Resets 1000 Bit Range Register Name Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-4: INTCON 1010 INTSTAT 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 IEC1 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1140 IPC11 Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 -- 31:16 -- -- -- -- -- 15:0 -- FRZ -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- -- RIPL<2:0> 31:16 20/4 19/3 18/2 17/1 16/0 All Resets 1000 Bit Range Register Name (c) 2010 Microchip Technology Inc. Virtual Address (BF88_#) Bits VEC<5:0> 0000 IPTMR<31:0> 15:0 0000 0000 0000 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF -- -- -- OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 -- -- -- -- -- -- USBIF FCEIF -- -- -- -- DMA3IF DMA2IF DMA1IF DMA0IF 0000 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE -- -- -- OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 -- -- -- -- -- -- USBIE FCEIE -- -- -- -- DMA3IE DMA2IE DMA1IE DMA0IE 0000 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 -- -- -- INT0IP<2:0> INT0IS<1:0> -- -- -- CS1IP<2:0> CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 15:0 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 15:0 -- -- -- I2C1IP<2:0> I2C1IS<1:0> -- -- -- U1IP<2:0> U1IS<1:0> 0000 31:16 -- -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 31:16 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 0000 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 15:0 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 31:16 -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 52 INTERRUPT REGISTERS MAP FOR PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) TABLE 4-5: INTCON 1010 INTSTAT 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 1090 10A0 10B0 10C0 10E0 10F0 1100 1110 DS61143G-page 53 1140 Legend: Note 1: IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC11 30/14 29/13 28/12 27/11 26/10 -- 31:16 -- -- -- -- -- 15:0 -- FRZ -- MVEC -- 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 -- -- -- -- -- -- -- -- -- -- TPC<2:0> -- -- -- RIPL<2:0> 31:16 20/4 19/3 18/2 17/1 16/0 VEC<5:0> 0000 IPTMR<31:0> 15:0 0000 0000 0000 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF -- -- -- OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 -- -- -- -- -- -- USBIF FCEIF -- -- -- -- -- -- -- -- 0000 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE -- -- -- OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 -- -- -- -- -- -- USBIE FCEIE -- -- -- -- -- -- -- -- 0000 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 31:16 -- -- -- INT0IS<1:0> -- -- -- INT0IP<2:0> CS1IP<2:0> 0000 CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 15:0 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 15:0 -- -- -- I2C1IP<2:0> I2C1IS<1:0> -- -- -- U1IP<2:0> U1IS<1:0> 0000 31:16 -- -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 31:16 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX 10D0 IEC1 31/15 All Resets 1000 Bit Range Register Name Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. INTERRUPT REGISTERS MAP FOR THE PIC32MX420F032H DEVICE ONLY(1) TABLE 4-6: T1CON 0610 TMR1 0620 0800 PR1 T2CON 0810 TMR2 0820 0A00 PR2 T3CON 0A10 TMR3 0A20 0C00 PR3 T4CON 0C10 TMR4 0C20 (c) 2010 Microchip Technology Inc. 0E00 PR4 T5CON 0E10 0E20 Legend: Note 1: TMR5 PR5 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Register Name 0600 Bit Range Virtual Address (BF80_#) Bits 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON FRZ SIDL TWDIS TWIP -- -- -- TGATE -- TCKPS<1:0> -- TSYNC TCS -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 TMR1<15:0> -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 T32 -- TCS -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- 15:0 TCKPS<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- TCS -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- TGATE 31:16 -- -- -- -- -- -- -- -- -- 15:0 TCKPS<2:0> -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 T32 -- TCS -- 0000 -- -- -- -- 0000 FFFF TCKPS<2:0> -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- TCS -- 0000 -- -- -- -- 0000 FFFF TCKPS<2:0> -- -- -- TMR5<15:0> -- 0000 FFFF PR4<15:0> 31:16 0000 0000 TMR4<15:0> 15:0 0000 FFFF PR3<15:0> 31:16 31:16 -- TMR3<15:0> 15:0 31:16 -- PR2<15:0> 31:16 31:16 -- TMR2<15:0> 15:0 0000 0000 PR1<15:0> 31:16 31:16 -- 0000 0000 -- -- -- -- -- -- -- 0000 15:0 PR5<15:0> FFFF x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 54 TIMER1-5 REGISTERS MAP(1) TABLE 4-7: 2010 IC1BUF IC2CON(1) 2210 2400 IC2BUF IC3CON(1) 2410 2600 IC3BUF IC4CON(1) 2610 2800 IC4BUF IC5CON(1) 2810 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- FEDGE C32 ICTMR 31:16 ICI<1:0> 20/4 19/3 18/2 -- -- -- ICOV ICBNE 17/1 16/0 -- -- ICM<2:0> xxxx IC1BUF<31:0> 15:0 0000 0000 xxxx 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- FEDGE C32 ICTMR 31:16 -- -- ICI<1:0> -- -- ICOV ICBNE -- -- -- ICM<2:0> xxxx IC2BUF<31:0> 15:0 0000 0000 xxxx 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- FEDGE C32 ICTMR 31:16 -- -- ICI<1:0> -- -- ICOV ICBNE -- -- -- ICM<2:0> xxxx IC3BUF<31:0> 15:0 0000 0000 xxxx 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- FEDGE C32 ICTMR 31:16 -- -- ICI<1:0> -- -- ICOV ICBNE -- -- -- ICM<2:0> xxxx IC4BUF<31:0> 15:0 0000 0000 xxxx 31:16 -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- FEDGE C32 ICTMR -- -- ICI<1:0> -- -- ICOV ICBNE -- -- ICM<2:0> -- 0000 0000 31:16 xxxx IC5BUF<31:0> 15:0 xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. IC5BUF DS61143G-page 55 PIC32MX3XX/4XX Legend: Note 1: 31/15 All Resets IC1CON(1) Bit Range Register Name 2000 2200 INPUT CAPTURE1-5 REGISTERS MAP Bits Virtual Address (BF80_#) (c) 2010 Microchip Technology Inc. TABLE 4-8: 3000 OC1CON 3010 3020 OC1R OC1RS 3200 OC2CON 3210 3220 OC2R OC2RS 3400 OC3CON 3410 3420 OC3R OC3RS 3600 OC4CON 3610 3620 OC4R OC4RS (c) 2010 Microchip Technology Inc. 3800 OC5CON 3810 3820 OC5R 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- 0000 0000 xxxx xxxx OC1RS<31:0> 15:0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- -- -- OCM<2:0> 0000 0000 xxxx OC2R<31:0> 15:0 xxxx 31:16 15:0 xxxx OC2RS<31:0> xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- -- -- OCM<2:0> 0000 0000 xxxx OC3R<31:0> 15:0 xxxx 31:16 15:0 xxxx OC3RS<31:0> xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- -- -- OCM<2:0> 0000 0000 xxxx OC4R<31:0> 15:0 xxxx 31:16 15:0 xxxx OC4RS<31:0> xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL 31:16 -- OCM<2:0> xxxx 31:16 15:0 16/0 OC1R<31:0> 15:0 31:16 17/1 OC5R<31:0> -- -- OCM<2:0> -- 0000 0000 xxxx xxxx xxxx OC5RS<31:0> 15:0 xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. OC5RS Legend: Note 1: 31/15 All Resets Bit Range Register Name Virtual Address (BF80_#) Bits PIC32MX3XX/4XX DS61143G-page 56 OUTPUT COMPARE1-5 REGISTERS MAP(1) TABLE 4-9: I2C1CON 5010 5020 5030 5040 5050 5260 5200 5210 5230 5240 5250 5260 I2C1ADD I2C1MSK I2C1BRG I2C1TRN I2C1RCV I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C2BRG I2C2TRN I2C2RCV DS61143G-page 57 Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- 0000 0000 0000 ADD<9:0> -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- 0000 -- -- -- -- -- 0000 -- -- -- -- -- MSK<9:0> 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 0000 I2C1BRG<11:0> -- -- 0000 I2CT1DATA<7:0> -- -- -- -- -- 0000 0000 -- -- -- I2CR1DATA<7:0> 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- 0000 -- -- -- -- -- ADD<9:0> -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- 0000 MSK<9:0> 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 0000 I2C2BRG<11:0> -- -- 0000 I2CT2DATA<7:0> -- -- -- -- -- 0000 0000 -- -- -- 15:0 -- -- -- -- -- -- -- -- I2CR2DATA<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 0000 0000 PIC32MX3XX/4XX 5220 I2C1STAT 31/15 All Resets 5000 Bit Range Register Name Bits Virtual Address (BF80_#) (c) 2010 Microchip Technology Inc. I2C1-2 REGISTERS MAP(1) TABLE 4-10: 6020 U1STA(1) U1TXREG 6030 U1RXREG 6040 (1) U1BRG 6200 U2MODE(1) 6210 6220 6230 6240 U2STA(1) U2TXREG U2RXREG U2BRG(1) Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 -- -- 31:16 -- -- -- -- -- -- 15:0 ON FRZ SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN 15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 31:16 -- -- -- -- -- -- -- -- UEN<1:0> 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 23/7 22/6 21/5 20/4 19/3 18/2 17/1 -- -- -- -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> 16/0 -- 0000 STSEL 0000 ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA 0110 -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- 0000 WAKE LPBACK ABAUD RXINV BRGH STSEL 0000 Transmit Register -- -- 0000 Receive Register 0000 BRG<15:0> 15:0 ON FRZ SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- UEN<1:0> ADM_EN 15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 6000 U1MODE(1) 6010 UART1-2 REGISTERS MAP 0000 PDSEL<1:0> ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA 0110 -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- -- 0000 15:0 BRG<15:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 58 TABLE 4-11: (c) 2010 Microchip Technology Inc. SPI1CON 5810 SPI1STAT 5820 5830 SPI1BUF SPI1BRG 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG Legend: Note 1: 2: 31/15 30/14 29/13 FRMSYNC FRMPOL 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 5800 Bit Range Register Name Bits Virtual Address (BF80_#) (c) 2010 Microchip Technology Inc. SPI1-2 REGISTERS MAP(1,2) TABLE 4-12: 31:16 FRMEN -- -- -- -- -- -- -- -- -- -- -- SPIFE -- 0000 15:0 ON FRZ SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- SPIBUSY -- -- -- -- SPIROV -- -- SPITBE -- -- SPIRBF 31:16 DATA<31:0> 15:0 31:16 0000 0000 0000 -- 15:0 -- 31:16 FRMEN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FRMSYNC FRMPOL -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- SPIFE -- 0000 BRG<8:0> 0000 15:0 ON FRZ SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- SPIBUSY -- -- -- -- SPIROV -- -- SPITBE -- -- SPIRBF 31:16 DATA<31:0> 15:0 31:16 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- BRG<8:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices. 0000 0000 PIC32MX3XX/4XX DS61143G-page 59 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL(1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 (c) 2010 Microchip Technology Inc. 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 31/15 30/14 29/13 28/12 27/11 26/10 -- 31:16 -- -- -- -- -- 15:0 ON FRZ SIDL -- -- 25/9 24/8 23/7 -- -- -- FORM<2:0> 22/6 21/5 -- -- SSRC<2:0> 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 VCFG2 VCFG1 VCFG0 OFFCAL -- CSCNA -- -- BUFS -- 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 ADRC -- -- 31:16 CH0NB -- -- -- 15:0 -- -- -- -- -- 18/2 -- 17/1 16/0 -- -- -- -- -- 0000 CLRASAM -- ASAM SAMP DONE 0000 -- -- -- -- -- -- -- -- 0000 BUFM ALTS 0000 -- -- 0000 ADCS<7:0> CH0SB<3:0> -- 19/3 SMPI<3:0> SAMC<4:0> -- 20/4 -- -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 9000 AD1CON1(1) CH0NA -- -- -- -- -- -- -- 0000 CH0SA<3:0> -- -- -- 0000 -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 ADC Result Word 0 (ADC1BUF0<31:0>) 0000 0000 ADC Result Word 1 (ADC1BUF1<31:0>) 0000 0000 ADC Result Word 2 (ADC1BUF2<31:0>) 0000 0000 ADC Result Word 3 (ADC1BUF3<31:0>) 0000 0000 ADC Result Word 4 (ADC1BUF4<31:0>) 0000 0000 ADC Result Word 5 (ADC1BUF5<31:0>) 0000 0000 ADC Result Word 6 (ADC1BUF6<31:0>) 0000 0000 ADC Result Word 7 (ADC1BUF7<31:0>) 0000 0000 ADC Result Word 8 (ADC1BUF8<31:0>) 0000 0000 0000 ADC Result Word 9 (ADC1BUF9<31:0>) 15:0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 9100 ADC1BUF9 Legend: Note 1: ADC REGISTERS MAP PIC32MX3XX/4XX DS61143G-page 60 TABLE 4-13: 9110 ADC1BUFA 9120 ADC1BUFB 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 ADC Result Word A (ADC1BUFA<31:0>) 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range 31:16 31/15 0000 0000 ADC Result Word B (ADC1BUFB<31:0>) 0000 0000 ADC Result Word C (ADC1BUFC<31:0>) 0000 0000 ADC Result Word D (ADC1BUFD<31:0>) 0000 0000 ADC Result Word E (ADC1BUFE<31:0>) 0000 0000 31:16 0000 ADC Result Word F (ADC1BUFF<31:0>) 15:0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 9160 ADC1BUFF Legend: Note 1: ADC REGISTERS MAP (CONTINUED) Bits Register Name Virtual Address (BF80_#) (c) 2010 Microchip Technology Inc. TABLE 4-13: PIC32MX3XX/4XX DS61143G-page 61 DMASTAT 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 29/13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON FRZ SIDL SUSPEND -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- -- RDWR -- DMACH<1:0> 0000 31:16 DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) 3030 DCRCCON 3040 DCRCDATA 3050 DCRCXOR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- PLEN<3:0> 15:0 31:16 -- 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- CRCEN CRCAPP -- -- -- -- CRCCH<1:0> 0000 -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- DCRCDATA<15:0> -- All Resets Bit Range Bits Register Name Virtual Address (BF88_#) 30/14 31:16 TABLE 4-15: Legend: Note 1: 31/15 0000 DMAADDR<31:0> 15:0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 3020 DMAADDR Legend: Note 1: Bit Range Register Name Virtual Address (BF88_#) Bits 3000 DMACON(1) 3010 DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY -- 0000 0000 0000 15:0 DCRCXOR<15:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 62 TABLE 4-14: (c) 2010 Microchip Technology Inc. 3070 DCH0ECON 3090 DCH0INT DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 3100 DCH0CPTR 3110 DCH0DAT 3120 DCH1CON 3130 DCH1ECON DS61143G-page 63 3140 3150 DCH1INT 29/13 28/12 27/11 26/10 25/9 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- CHCHNS CHEN CHAED 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- 15:0 24/8 CHSIRQ<7:0> 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- CHCHN CHAEN -- -- -- -- -- CHEDET CHPRI<1:0> CHAIRQ<7:0> All Resets 30/14 0000 0000 00FF FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 CHSSA<31:0> 15:0 0000 31:16 0000 CHDSA<31:0> 15:0 0000 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHSSIZ<7:0> -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- CHDSIZ<7:0> -- -- -- -- -- -- -- -- -- 0000 CHSTR<7:0> -- 0000 CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- CHSIRQ<7:0> 15:0 CHCPTR<7:0> -- -- 0000 0000 CHCSIZ<7:0> -- 0000 0000 0000 CHPDAT<7:0> 0000 0000 -- -- CHPRI<1:0> CHAIRQ<7:0> 0000 0000 00FF FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 CHSSA<31:0> 15:0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DCH1SSA Legend: Note 1: 31/15 PIC32MX3XX/4XX 30F0 DCH0CSIZ Bit Range Register Name 3060 DCH0CON 3080 DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-16: 3170 DCH1SSIZ 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3210 (c) 2010 Microchip Technology Inc. 3220 DCH2INT DCH2SSA DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 CHDSA<31:0> 15:0 All Resets Register Name DCH1DSA Bit Range Virtual Address (BF88_#) Bits 3160 3200 DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) (CONTINUED) 0000 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHSSIZ<7:0> -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- CHDSIZ<7:0> -- -- -- -- -- -- -- -- 0000 CHSPTR<7:0> -- -- 0000 CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- 15:0 CHSIRQ<7:0> CHCPTR<7:0> -- -- 0000 0000 CHCSIZ<7:0> -- 0000 0000 0000 CHPDAT<7:0> 0000 0000 -- -- CHPRI<1:0> CHAIRQ<7:0> 0000 0000 00FF FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 CHSSA<31:0> 15:0 0000 31:16 0000 CHDSA<31:0> 15:0 0000 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHSSIZ<7:0> -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 CHDSIZ<7:0> -- -- -- -- -- 0000 0000 0000 -- -- -- -- -- -- -- -- CHSPTR<7:0> 0000 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 64 TABLE 4-16: 3270 DCH2CSIZ 3280 DCH2CPTR DCH2DAT 32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ DS61143G-page 65 3340 DCH3CPTR 3350 DCH3DAT Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET 31:16 -- -- -- -- -- -- -- -- CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- 15:0 CHSIRQ<7:0> CHCPTR<7:0> -- -- 0000 0000 CHCSIZ<7:0> -- All Resets 31/15 0000 CHPDAT<7:0> 0000 0000 -- -- CHPRI<1:0> CHAIRQ<7:0> 0000 0000 00FF FF00 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 CHSSA<31:0> 15:0 0000 31:16 0000 CHDSA<31:0> 15:0 0000 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- CHSSIZ<7:0> -- 0000 CHDSIZ<7:0> -- -- -- -- -- -- -- -- -- 0000 CHSTR<7:0> -- 0000 CHDPTR<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- 0000 -- -- -- 0000 CHCPTR<7:0> -- -- 0000 0000 CHCSIZ<7:0> -- 0000 0000 0000 15:0 -- -- -- -- -- -- -- -- CHPDAT<7:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX 32F0 DCH3SSIZ Bit Range Register Name 3260 DCH2DPTR 3290 DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) (CONTINUED) Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-16: CM1CON A060 CM2CON CMSTAT Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 -- 31:16 -- -- -- -- -- -- -- -- 15:0 ON COE CPOL -- -- -- -- COUT 31:16 -- -- -- -- -- -- -- -- 15:0 ON COE CPOL -- -- -- -- COUT 31:16 -- -- -- -- -- -- -- -- 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- EVPOL<1:0> -- CREF -- -- -- -- -- -- -- -- EVPOL<1:0> -- CREF -- -- -- -- -- -- -- -- CCH<1:0> -- -- CCH<1:0> -- -- 0000 0000 0000 0000 0000 15:0 -- FRZ SIDL -- -- -- -- -- -- -- -- -- -- -- C2OUT C1OUT 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. COMPARATOR VOLTAGE REFERENCE REGISTERS MAP(1) TABLE 4-18: Register Name 9800 CVRCON Legend: Note 1: Bit Range Virtual Address (BF80_#) Bits 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Resets A010 31/15 All Resets Register Name A000 Bit Range Virtual Address (BF80_#) Bits 0000 15:0 ON -- -- -- -- -- -- -- -- CVROE CVRR CVRSS CVR<3:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 66 COMPARATOR REGISTERS MAP(1) TABLE 4-17: (c) 2010 Microchip Technology Inc. NVMKEY F420 NVMADDR(1) F430 NVMDATA F440 NVMSRC ADDR Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 WR WREN WRERR LVDERR LVDSTAT -- -- -- -- -- -- -- 31:16 15:0 31:16 15:0 31:16 15:0 NVMKEY<31:0> NVMOP<3:0> All Resets Bit Range Register Name F400 NVMCON(1) F410 FLASH CONTROLLER REGISTERS MAP Bits Virtual Address (BF80_#) (c) 2010 Microchip Technology Inc. TABLE 4-19: 0000 0000 0000 0000 NVMADDR<31:0> 0000 0000 NVMDATA<31:0> 0000 0000 31:16 0000 NVMSRCADDR<31:0> 15:0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 67 F000 OSCCON F010 OSCTUN 0000 WDTCON F600 RCON F610 RSWRST Legend: Note 1: 2: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- 31:16 -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- PLLODIV<2:0> COSC<2:0> -- 25/9 24/8 21/5 20/4 19/3 18/2 23/7 22/6 RCDIV<2:0> -- SOSCRDY -- NOSC<2:0> CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN 0000 -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- 0000 PBDIV<1:0> 17/1 16/0 All Resets Bit Range Register Name Virtual Address (BF80_#) Bits PLLMULT<2:0> 0000 TUN<5:0> -- -- -- 0000 15:0 ON -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- CMR VREGS EXTR SWR -- WDTO SLEEP IDLE BOR POR 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 SWDTPS<4:0> -- WDTCLR 0000 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SWRST 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. PIC32MX3XX/4XX DS61143G-page 68 SYSTEM CONTROL REGISTERS MAP(1,2) TABLE 4-20: (c) 2010 Microchip Technology Inc. PORTA 6020 LATA 6030 ODCA Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISA15 TRISA14 -- -- -- TRISA10 TRISA9 -- TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RA15 RA14 -- -- -- RA10 RA9 -- RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATA15 LATA14 -- -- -- LATA10 LATA9 -- LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCA15 ODCA14 -- -- -- ODCA10 ODCA9 -- ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-22: PORT B REGISTERS MAP(1) PORTB 6060 6070 Legend: Note 1: LATB ODCB 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name TRISB 31/15 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DS61143G-page 69 PIC32MX3XX/4XX Virtual Address (BF88_#) Bits 6040 6050 31/15 All Resets TRISA Bit Range Register Name 6000 6010 PORT A REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-21: PORTC 60A0 LATC 60B0 ODCC Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 -- -- -- -- -- -- -- TRISC4 TRISC3 TRISC2 TRISC1 -- F01E 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RC15 RC14 RC13 RC12 -- -- -- -- -- -- -- RC4 RC3 RC2 RC1 -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATC15 LATC14 LATC13 LATC12 -- -- -- -- -- -- -- LATC4 LATC3 LATC2 LATC1 -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCC15 ODCC14 ODCC13 ODCC12 -- -- -- -- -- -- -- ODCC4 ODCC3 ODCC2 ODCC1 -- 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-24: PORT C REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) PORTC (c) 2010 Microchip Technology Inc. 60A0 60B0 Legend: Note 1: LATC ODCC 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Register Name TRISC Bit Range Virtual Address (BF88_#) Bits 6080 6090 31/15 All Resets Register Name TRISC Bit Range Virtual Address (BF88_#) Bits 6080 6090 PORT C REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 -- -- -- -- -- -- -- -- -- -- -- -- F000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RC15 RC14 RC13 RC12 -- -- -- -- -- -- -- -- -- -- -- -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATC15 LATC14 LATC13 LATC12 -- -- -- -- -- -- -- -- -- -- -- -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCC15 ODCC14 ODCC13 ODCC12 -- -- -- -- -- -- -- -- -- -- -- -- 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 70 TABLE 4-23: PORTD 60E0 LATD 60F0 ODCD Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-26: PORT D REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) PORTD 60E0 60F0 DS61143G-page 71 Legend: Note 1: LATD ODCD 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name TRISD 31/15 30/14 29/13 28/12 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX Virtual Address (BF88_#) Bits 60C0 60D0 31/15 All Resets TRISD Bit Range Register Name 60C0 60D0 PORT D REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-25: PORTE 6120 LATE 6130 ODCE Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 15:0 -- -- -- -- -- -- RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- ODCE9 ODCE8 ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-28: PORT E REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) PORTE (c) 2010 Microchip Technology Inc. 6120 6130 Legend: Note 1: LATE ODCE 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Register Name TRISE Bit Range Virtual Address (BF88_#) Bits 6100 6110 25/9 All Resets Register Name TRISE Bit Range Virtual Address (BF88_#) Bits 6100 6110 PORT E REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- -- -- -- -- -- -- RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 72 TABLE 4-27: PORTF 6160 LATF 6170 ODCF 31/15 30/14 28/12 27/11 26/10 25/9 31:16 -- -- 15:0 -- -- 31:16 -- -- 15:0 -- -- 31:16 -- -- 15:0 -- -- 31:16 -- -- -- 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 TRISF13 TRISF12 -- -- -- TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 RF13 RF12 -- -- -- RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 LATF13 LATF12 -- -- -- LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- ODCF13 ODCF12 -- -- -- ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Legend: Note 1: TABLE 4-30: PORT F REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) PORTF 6160 6170 Legend: Note 1: LATF ODCF 30/14 31:16 -- -- 15:0 -- -- 31:16 -- -- 29/13 28/12 27/11 26/10 25/9 -- -- -- -- TRISF13 TRISF12 -- -- -- -- -- 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name TRISF 31/15 24/8 23/7 22/6 -- -- -- -- -- -- -- -- -- -- -- TRISF8 -- -- TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- RF13 RF12 -- -- -- RF8 -- -- RF5 RF4 RF3 RF2 RF1 RF0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- LATF13 LATF12 -- -- -- LATF8 -- -- LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- ODCF13 ODCF12 -- -- -- ODCF8 -- -- ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. DS61143G-page 73 PIC32MX3XX/4XX Virtual Address (BF88_#) Bits 6140 6150 29/13 All Resets TRISF Bit Range Register Name 6140 6150 PORT F REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES ONLY(1) Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-29: PORTF 6160 LATF 6170 ODCF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 07FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Legend: Note 1: TABLE 4-32: PORT F REGISTERS MAP FOR PIC32MX420F032H, PIC32MX440F128H AND PIC2MX440F256H DEVICES ONLY(1) PORTF 6160 (c) 2010 Microchip Technology Inc. 6170 Legend: Note 1: LATF ODCF 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Register Name TRISF Bit Range Virtual Address (BF88_#) Bits 6140 6150 22/6 All Resets Register Name TRISF Bit Range Virtual Address (BF88_#) Bits 6140 6150 PORT F REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H AND PIC32MX340F512H DEVICES ONLY(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 03FF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 -- -- -- -- -- -- -- -- -- -- RF5 RF4 RF3 RF2 RF1 RF0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- -- -- ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 74 TABLE 4-31: PORTG 61A0 LATG 61B0 ODCG Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 TRISG15 TRISG14 TRISG13 TRISG12 -- -- TRISG9 TRISG8 TRISG7 TRISG6 -- -- TRISG3 TRISG2 TRISG1 TRISG0 F3CF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 15:0 RG15 RG14 RG13 RG12 -- -- RG9 RG8 RG7 RG6 -- -- RG3 RG2 RG1 RG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATG15 LATG14 LATG13 LATG12 -- -- LATG9 LATG8 LATG7 LATG6 -- -- LATG3 LATG2 LATG1 LATG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ODCG15 ODCG14 ODCG13 ODCG12 -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- ODCG3 ODCG2 ODCG1 ODCG0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-34: PORT G REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) PORTG 61A0 61B0 DS61143G-page 75 Legend: Note 1: LATG ODCG 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- TRISG9 TRISG8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- RG9 31:16 -- -- -- -- -- -- 15:0 -- -- -- -- -- 31:16 -- -- -- -- -- 23/7 22/6 21/5 20/4 -- -- -- -- TRISG7 TRISG6 -- -- -- -- -- -- RG8 RG7 RG6 -- -- -- -- -- -- LATG9 LATG8 LATG7 -- -- -- -- 19/3 All Resets Bit Range Register Name TRISG 31/15 18/2 17/1 16/0 -- -- -- -- 0000 TRISG3 TRISG2 -- -- 03cc -- -- -- -- 0000 -- RG3 RG2 -- -- xxxx -- -- -- -- -- -- 0000 LATG6 -- -- LATG3 LATG2 -- -- xxxx -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- ODCG3 ODCG2 -- -- 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX Virtual Address (BF88_#) Bits 6180 6190 31/15 All Resets TRISG Bit Range Register Name 6180 6190 PORT G REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-33: 61D0 CNEN CNPUE 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON FRZ SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000 31:16 -- -- -- -- -- -- -- -- -- -- CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000 15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Legend: Note 1: TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) 61D0 CNEN CNPUE (c) 2010 Microchip Technology Inc. Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Register Name CNCON Bit Range Virtual Address (BF88_#) Bits 61C0 61E0 31/15 All Resets Register Name CNCON Bit Range Virtual Address (BF88_#) Bits 61C0 61E0 CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON FRZ SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- CNEN18 CNEN17 CNEN16 0000 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUE18 CNPUE17 CNPUE16 0000 15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PIC32MX3XX/4XX DS61143G-page 76 TABLE 4-35: PMCON 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 7060 PMAEN PMSTAT Legend: Note 1: 29/13 31:16 -- -- -- 15:0 ON FRZ SIDL 31:16 -- -- -- 15:0 BUSY 31:16 -- IRQM<1:0> -- 28/12 27/11 -- -- ADRMUX<1:0> -- -- INCM<1:0> -- -- 26/10 24/8 23/7 22/6 -- -- -- -- -- PMPTTL PTWREN PTRDEN -- -- -- MODE16 -- 25/9 -- CSF<1:0> -- MODE<1:0> -- -- 21/5 -- -- 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- ALP CS2P CS1P -- WRSP RDSP 0000 -- -- -- -- -- -- 0000 -- -- -- -- WAITB<1:0> -- 15:0 CS2EN/A15 CS1EN/A14 WAITM<3:0> -- WAITE<1:0> -- ADDR<13:0> 31:16 0000 0000 0000 0000 0000 DATAOUT<31:0> 15:0 0000 31:16 0000 DATAIN<31:0> 15:0 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PTEN<15:0> 31:16 -- 0000 0000 0000 15:0 IBF IBOV -- -- IB3F IB2F IB1F IB0F OBE OBUF -- -- OB3E OB2E OB1E OB0E 0080 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. PROGRAMMING AND DIAGNOSTICS REGISTERS MAP Register Name F200 DDPCON Bit Range Virtual Address (BF80_#) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. -- -- -- -- 31:16 19/3 18/2 17/1 16/0 -- -- -- -- 0000 JTAGEN TROEN -- -- 0008 DS61143G-page 77 PIC32MX3XX/4XX TABLE 4-38: Legend: 30/14 All Resets 7050 PMDIN 31/15 All Resets 7000 Bit Range Register Name Bits Virtual Address (BF80_#) (c) 2010 Microchip Technology Inc. PARALLEL MASTER PORT REGISTERS MAP(1) TABLE 4-37: 31/15 30/14 29/13 28/12 27/11 26/10 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 CHEWEN -- -- -- -- (1) -- 31:16 LTAGBOOT -- -- -- -- -- -- -- -- (1) 31:16 -- -- -- -- -- LMASK<15:5> 4010 CHEACC(1) 4020 CHETAG 4030 CHEMSK 4040 CHEW1 4060 CHEW2 4070 CHEW3 CHELRU 4090 40A0 CHEHIT CHEMIS 15:0 23/7 22/6 -- -- DCSZ<1:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 31:16 31:16 31:16 15:0 31:16 -- -- PREFEN<1:0> -- -- -- -- -- -- -- -- CHEIDX<3:0> -- -- -- -- -- -- -- -- -- 17/1 16/0 -- CHECOH 0000 PFMWS<2:0> 0000 -- 0000 00xx LTAG<23:16> -- -- -- -- -- -- CHEHIT<31:0> CHEMIS<31:0> LLOCK LTYPE -- -- -- -- -- -- -- 0000 -- -- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx CHELRU<24:16> CHELRU<15:0> LVALID xxx0 0000 xxxx CHEW3<31:0> 15:0 31:16 18/2 CHEW2<31:0> 15:0 15:0 19/3 CHEW1<31:0> 15:0 31:16 20/4 CHEW0<31:0> 15:0 15:0 21/5 LTAG<15:4> -- 15:0 31:16 24/8 0000 0000 xxxx xxxx xxxx xxxx xxxx CHEPFABT<31:0> 15:0 xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 40C0 CHEPFABT Legend: Note 1: 15:0 15:0 CHEW0 4050 31:16 25/9 All Resets Bit Range Register Name Virtual Address (BF88_#) Bits 4000 CHECON(1) 4080 PREFETCH REGISTERS MAP PIC32MX3XX/4XX DS61143G-page 78 TABLE 4-39: (c) 2010 Microchip Technology Inc. RTCCON 0220 0230 RTCALRM RTCTIME RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- 15:0 ON FRZ SIDL -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- 15:0 ALRMEN CHIME PIV ALRMSYNC HR01<3:0> 15:0 SEC10<3:0> SEC01<3:0> 31:16 YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 MIN10<3:0> MIN01<3:0> 15:0 SEC10<3:0> SEC01<3:0> -- -- -- -- 22/6 21/5 20/4 RTSECSEL RTCCLKON -- 19/3 18/2 17/1 16/0 -- -- -- 0000 -- -- -- -- AMASK<3:0> HR10<3:0> 31:16 23/7 CAL<11:0> 31:16 RTCWREN RTCSYNC HALFSEC -- -- RTCOE 0000 -- 0000 -- ARPT<7:0> MIN10<3:0> -- -- -- -- -- MONTH10<3:0> -- -- -- -- -- -- MIN10<3:0> -- -- 0000 MIN01<3:0> -- xxxx -- -- MONTH01<3:0> xxxx WDAY01<3:0> xx0x MIN01<3:0> -- -- -- MONTH10<3:0> xx00 -- xxxx -- -- MONTH01<3:0> xx00 00xx 15:0 DAY10<3:0> DAY01<3:0> -- -- -- -- WDAY01<3:0> xx0x x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. TABLE 4-41: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY 2FF4 DEVCFG2 DEVCFG1 2FFC DEVCFG0 DS61143G-page 79 Legend: Note 1: Bit Range Register Name DEVCFG3 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- 15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 31:16 -- -- -- -- 15:0 FUPLLEN(1) -- -- -- -- -- 31:16 -- -- -- -- -- -- 15:0 FCKSM<1:0> FPBDIV<1:0> -- OSCIOFNC 31:16 -- -- -- -- -- CP -- 24/8 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 -- -- -- -- -- -- FPLLODIV<2:0> xxxx -- FPLLIDIV<2:0> xxxx -- -- -- POSCMOD<1:0> -- 22/6 USERID8 FUPLLIDIV<2:0>(1) -- 23/7 BWP 15:0 PWP15 PWP14 PWP13 PWP12 -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. These bits are only available on PIC32MX4XX devices. FPLLMULT<2:0> FWDTEN -- -- IESO -- FSOSCEN -- -- -- -- -- PWP19 PWP18 -- -- -- -- ICESEL -- -- WDTPS<4:0> -- xxxx USERID0 xxxx xxxx FNOSC<2:0> PWP17 xxxx PWP16 DEBUG<1:0> xxxx xxxx PIC32MX3XX/4XX Virtual Address (BFC0_#) Bits 2FF0 2FF8 30/14 All Resets 0210 31/15 All Resets 0200 Bit Range Register Name Bits Virtual Address (BF80_#) (c) 2010 Microchip Technology Inc. RTCC REGISTERS MAP(1) TABLE 4-40: 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 VER<3:0> 15:0 DEVID<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 22/6 21/5 DEVID<27:16> 20/4 19/3 18/2 17/1 16/0 All Resets Register Name DEVID Bit Range Virtual Address (BF80_#) Bits F220 Legend: DEVICE AND REVISION ID SUMMARY xxxx xxxx PIC32MX3XX/4XX DS61143G-page 80 TABLE 4-42: (c) 2010 Microchip Technology Inc. 5050 U1OTGIE 5060 U1OTG STAT 5070 U1OTGCON 5080 U1PWRC 5200 U1IR 5210 U1IE 5220 U1EIR U1EIE 5240 U1STAT 5250 U1CON 5260 U1ADDR DS61143G-page 81 U1BDTP1 5280 5290 Legend: U1FRML U1FRMH 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 -- -- 20/4 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- IDIF 18/2 17/1 -- -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- IDIE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- ID -- LSTATE -- SESVD SESEND -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- UACTPND -- -- USLPGRD -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T1MSECIF LSTATEIF -- 19/3 ACTVIF -- SESVDIF SESENDIF -- T1MSECIE LSTATEIE -- ACTVIE -- SESVDIE SESENDIE -- DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON 15:0 -- -- -- -- -- -- -- -- STALLIF 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- STALLIE 31:16 -- -- -- -- -- -- -- -- -- ATTACHIF RESUMEIF -- -- ATTACHIE RESUMEIE -- -- OTGEN -- -- -- -- -- -- SOFIF UERRIF -- -- -- -- SOFIE -- -- -- 15:0 -- -- -- -- -- -- -- -- BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 VBUSVDIE 0000 -- 0000 VBUSVD 0000 -- 0000 -- 0000 USUSPEND USBPWR 0000 TRNIF TRNIE -- VBUSVDIF 0000 VBUSCHG VBUSDIS 0000 IDLEIF IDLEIE 16/0 UERRIE -- CRC5EF EOFEF -- CRC5EE -- 0000 URSTIF 0000 DETACHIF 0000 -- 0000 URSTIE 0000 DETACHIE 0000 -- PIDEF 0000 0000 0000 -- 15:0 -- -- -- -- -- -- -- -- BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- DIR PPBI -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 0000 USBEN 0000 ENDPT<3:0> -- -- -- PKTDIS 15:0 -- -- -- -- -- -- -- -- JSTATE SE0 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- LSPDEN 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TOKBUSY -- -- EOFEE PIDEE 0000 0000 0000 USBRST HOSTEN RESUME PPBRST SOFEN 0000 -- -- -- -- -- 0000 -- -- -- -- 0000 -- 0000 -- -- -- -- 0000 -- -- -- 0000 DEVADDR<6:0> -- 0000 BDTPTRL<7:1> -- FRML<7:0> 0000 -- -- -- -- -- -- -- -- -- -- FRMH<10:8> 0000 PIC32MX3XX/4XX 5230 31/15 All Resets U1OTGIR Bit Range Register Name 5040 5270 USB REGISTERS MAP Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-43: 52B0 52D0 52E0 U1SOF U1BDTP2 U1BDTP3 U1CNFG1 (c) 2010 Microchip Technology Inc. 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 5350 U1EP5 5360 U1EP6 5370 U1EP7 5380 U1EP8 5390 U1EP9 53A0 U1EP10 53B0 U1EP11 Legend: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- All Resets Register Name U1TOK Bit Range Virtual Address (BF88_#) Bits 52A0 52C0 USB REGISTERS MAP (CONTINUED) 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- 0000 PID<3:0> EP<3:0> -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- 0000 -- -- -- -- 0000 -- -- -- 0000 CNT<7:0> 0000 BDTPTRH<7:0> -- -- 0000 15:0 -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 BDTPTRU<7:0> 0000 15:0 -- -- -- -- -- -- -- -- UTEYE UOEMON USBFRZ USBSIDL -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- LSPD RETRYDIS -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 15:0 -- -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 PIC32MX3XX/4XX DS61143G-page 82 TABLE 4-43: 53D0 U1EP13 53E0 U1EP14 53F0 U1EP15 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL 15:0 -- -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 20/4 19/3 18/2 17/1 16/0 -- All Resets U1EP12 Bit Range Register Name 53C0 Legend: USB REGISTERS MAP (CONTINUED) Bits Virtual Address (BF88_#) (c) 2010 Microchip Technology Inc. TABLE 4-43: 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 -- 0000 EPHSHK 0000 PIC32MX3XX/4XX DS61143G-page 83 PIC32MX3XX/4XX NOTES: DS61143G-page 84 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. "Flash Program Memory" (DS61121) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX devices contain an internal program Flash memory for executing user code. There are three methods by which the user can program this memory: * Run-Time Self Programming (RTSP) * In-Circuit Serial ProgrammingTM (ICSPTM) * EJTAG Programming RTSP is performed by software executing from either Flash or RAM memory. EJTAG is performed using the EJTAG port of the device and a EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. RTSP techniques are described in this chapter. The ICSP and EJTAG methods are described in the "PIC32MX3XX/4XX Programming Specification" (DS61145), which may be downloaded from the Microchip web site. DS61143G-page 85 PIC32MX3XX/4XX NOTES: DS61143G-page 86 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS61118) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 6-1: The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * POR: Power-on Reset MCLR: Master Clear Reset Pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset A simplified block diagram of the Reset module is illustrated in Figure 6-1. SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter Sleep or Idle MCLR WDTR WDT Time-out Voltage Regulator Enabled Power-up Timer POR SYSRST VDD VDD Rise Detect Configuration Mismatch Reset Software Reset (c) 2010 Microchip Technology Inc. Brown-out Reset BOR CMR SWR DS61143G-page 87 PIC32MX3XX/4XX NOTES: DS61143G-page 88 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupt Controller" (DS61108) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. PIC32MX3XX/4XX devices generate interrupt requests in response to interrupt events from peripheral modules. The Interrupt Control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. The PIC32MX3XX/4XX interrupts module includes the following features: * * * * * * * * * * * * Interrupt Requests FIGURE 7-1: Up to 96 interrupt sources Up to 64 interrupt vectors Single and Multi-Vector mode operations Five external interrupts with edge polarity control Interrupt proximity timer Module Freeze in Debug mode Seven user-selectable priority levels for each vector Four user-selectable subpriority levels within each priority Dedicated shadow set for highest priority level Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing INTERRUPT CONTROLLER MODULE Vector Number Interrupt Controller Priority Level CPU Core Shadow Set Number Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and bits) are associated with the CPU. Details about them are available in Section 3.0 "PIC32MX MCU". To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this section, and all other sections of this manual, are signified by uppercase letters only. The CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. (c) 2010 Microchip Technology Inc. DS61143G-page 89 PIC32MX3XX/4XX TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION Interrupt Source(1) IRQ Vector Number Highest Natural Order Priority Interrupt Bit Location Flag Enable Priority Subpriority CT - Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> CS0 - Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 - Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 - External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> T1 - Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> IC1 - Input Capture 1 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> OC1 - Output Compare 1 6 6 IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16> INT1 - External Interrupt 1 7 7 IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24> T2 - Timer2 8 8 IFS0<8> IEC0<8> IPC2<4:2> IPC2<1:0> IC2 - Input Capture 2 9 9 IFS0<9> IEC0<9> IPC2<12:10> IPC2<9:8> OC2 - Output Compare 2 10 10 IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16> INT2 - External Interrupt 2 11 11 IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24> T3 - Timer3 12 12 IFS0<12> IEC0<12> IPC3<4:2> IPC3<1:0> IC3 - Input Capture 3 13 13 IFS0<13> IEC0<13> IPC3<12:10> IPC3<9:8> OC3 - Output Compare 3 14 14 IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16> INT3 - External Interrupt 3 15 15 IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24> T4 - Timer4 16 16 IFS0<16> IEC0<16> IPC4<4:2> IPC4<1:0> IC4 - Input Capture 4 17 17 IFS0<17> IEC0<17> IPC4<12:10> IPC4<9:8> OC4 - Output Compare 4 18 18 IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16> INT4 - External Interrupt 4 19 19 IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24> T5 - Timer5 20 20 IFS0<20> IEC0<20> IPC5<4:2> IPC5<1:0> IC5 - Input Capture 5 21 21 IFS0<21> IEC0<21> IPC5<12:10> IPC5<9:8> OC5 - Output Compare 5 22 22 IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16> SPI1E - SPI1 Fault 23 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24> SPI1TX - SPI1 Transfer Done 24 23 IFS0<24> IEC0<24> IPC5<28:26> IPC5<25:24> SPI1RX - SPI1 Receive Done 25 23 IFS0<25> IEC0<25> IPC5<28:26> IPC5<25:24> U1E - UART1 Error 26 24 IFS0<26> IEC0<26> IPC6<4:2> IPC6<1:0> U1RX - UART1 Receiver 27 24 IFS0<27> IEC0<27> IPC6<4:2> IPC6<1:0> U1TX - UART1 Transmitter 28 24 IFS0<28> IEC0<28> IPC6<4:2> IPC6<1:0> I2C1B - I2C1 Bus Collision Event 29 25 IFS0<29> IEC0<29> IPC6<12:10> IPC6<9:8> I2C1S - I2C1 Slave Event 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> I2C1M - I2C1 Master Event 31 25 IFS0<31> IEC0<31> IPC6<12:10> IPC6<9:8> CN - Input Change Interrupt 32 26 IFS1<0> IEC1<0> IPC6<20:18> IPC6<17:16> AD1 - ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24> PMP - Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0> CMP1 - Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8> CMP2 - Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX General Purpose - Features" and TABLE 2: "PIC32MX USB - Features" for available peripherals. DS61143G-page 90 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED) Interrupt Source(1) IRQ Vector Number Highest Natural Order Priority SPI2E - SPI2 Fault 37 31 Interrupt Bit Location Flag Enable Priority Subpriority IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24> SPI2TX - SPI2 Transfer Done 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> SPI2RX - SPI2 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> U2E - UART2 Error 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0> U2RX - UART2 Receiver 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> U2TX - UART2 Transmitter 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0> I2C2B - I2C2 Bus Collision Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8> I2C2S - I2C2 Slave Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> I2C2M - I2C2 Master Event 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> FSCM - Fail-Safe Clock Monitor 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16> RTCC - Real-Time Clock and Calendar 47 35 IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24> DMA0 - DMA Channel 0 48 36 IFS1<16> IEC1<16> IPC9<4:2> IPC9<1:0> DMA1 - DMA Channel 1 49 37 IFS1<17> IEC1<17> IPC9<12:10> IPC9<9:8> DMA2 - DMA Channel 2 50 38 IFS1<18> IEC1<18> IPC9<20:18> IPC9<17:16> DMA3 - DMA Channel 3 51 39 IFS1<19> IEC1<19> IPC9<28:26> IPC9<25:24> FCE - Flash Control Event 56 44 IFS1<24> IEC1<24> IPC11<4:2> IPC11<1:0> USB 57 45 IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8> Lowest Natural Order Priority Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX General Purpose - Features" and TABLE 2: "PIC32MX USB - Features" for available peripherals. (c) 2010 Microchip Technology Inc. DS61143G-page 91 PIC32MX3XX/4XX NOTES: DS61143G-page 92 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 8.0 OSCILLATOR CONFIGURATION The PIC32MX oscillator system has the following modules and features: * A total of four external and internal oscillator options as clock sources * On-chip PLL (phase-locked loop) with userselectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources * On-chip user-selectable divisor postscaler on select oscillator sources * Software-controllable switching between various clock sources * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shut down * Dedicated on-chip PLL for USB peripheral Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "PIC32MX Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112), which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 8-1: PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM USB PLL UFIN div x div 2 UFRCEN FUPLLEN UFIN = 4 MHz FUPLLDIV<2:0> Primary Oscillator (POSC) OSC1 C1(3) XT, HS, EC RF(2) XTAL C2(3) USB Clock (48 MHz) PLL x24 To Internal Logic 4 MHz FIN 5 MHz XTPLL, HSPLL, FIN ECPLL, FRCPLL div x div y PLL Enable RS(1) PLL Input Divider FPLLIDIV<2:0> OSC2(4) FRC Oscillator 8 MHz typical COSC<2:0> PLL Output Divider PLLODIV<2:0> PLL Multiplier PLLMULT<2:0> div 16 TUN<5:0> Postscaler Postscaler Peripherals div x PBCLK PBDIV<2:0> FRC FRC/16 FRCDIV CPU and Select Peripherals FRCDIV<2:0> LPRC Oscillator LPRC 31.25 kHz typical Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSCEN and FSOSCEN 1. 2. 3. 4. Clock Control Logic Fail-Safe Clock Monitor SOSCI Notes: SOSC A series resistor, RS, may be required for AT strip-cut crystals. The internal feedback resistor, RF, is typically in the range of 2 to 10 M. Refer to the "PIC32MX Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112) for help determining the best oscillator components. PBCLK out is available on the OSC2 pin in certain clock modes. (c) 2010 Microchip Technology Inc. FSCM INT FSCM Event NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT Timer1, RTCC DS61143G-page 93 PIC32MX3XX/4XX NOTES: DS61143G-page 94 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 9.0 PREFETCH CACHE Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. "Prefetch Cache" (DS61119) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 9-1: 9.1 * * * * * * * * Features 16 Fully Associative Lockable Cache Lines 16-byte Cache Lines Up to four Cache Lines Allocated to Data Two Cache Lines with Address Mask to hold repeated instructions Pseudo LRU replacement policy All Cache Lines are software writable 16-byte parallel memory fetch Predictive Instruction Prefetch PREFETCH MODULE BLOCK DIAGRAM CTRL FSM Cache Line Tag Logic CTRL BMX/CPU BMX/CPU Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. Bus Control Cache Control Prefetch Control Cache Line Address Encode Hit LRU Miss LRU RDATA Hit Logic Prefetch Prefetch CTRL RDATA PFM (c) 2010 Microchip Technology Inc. DS61143G-page 95 PIC32MX3XX/4XX NOTES: DS61143G-page 96 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS61117) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32MX (such as Peripheral Bus (PBUS) devices: SPI, UART, I2CTM, etc.) or memory itself. Following are some of the key features of the DMA controller module: * Four Identical Channels, each featuring: - Auto-Increment Source and Destination Address Registers - Source and Destination Pointers - Memory to Memory and Memory to Peripheral Transfers FIGURE 10-1: DMA BLOCK DIAGRAM INT Controller Peripheral Bus * Automatic Word-Size Detection: - Transfer Granularity, down to byte level - Bytes need not be word-aligned at source and destination * Fixed Priority Channel Arbitration * Flexible DMA Channel Operating Modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA Requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA Channel Status Interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half-full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA Debug Support Features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation Module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable System IRQ Address Decoder SE Channel 0 Control I0 Channel 1 Control I1 L Y Bus Interface Device Bus + Bus Arbitration I2 Global Control (DMACON) Channel n Control In SE L Channel Priority Arbitration (c) 2010 Microchip Technology Inc. DS61143G-page 97 PIC32MX3XX/4XX NOTES: DS61143G-page 98 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 11.0 USB ON-THE-GO (OTG) The PIC32MX USB module includes the following features: Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. "USB On-The-Go (OTG)" (DS61126) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. * * The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 fullspeed and low-speed embedded host, full-speed device, or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. * * USB Full-Speed Support for Host and Device Low-Speed Host Support USB OTG Support Integrated Signaling Resistors Integrated Analog Comparators for VBUS Monitoring Integrated USB Transceiver Transaction Handshaking Performed by Hardware Endpoint Buffering Anywhere in System RAM Integrated DMA to Access System RAM and Flash Note: The implementation and use of the USB specifications, as well as other third-party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32MX USB OTG module is presented in Figure 11-1. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. (c) 2010 Microchip Technology Inc. DS61143G-page 99 PIC32MX3XX/4XX FIGURE 11-1: PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) Div x OSC1 UFIN(5) PLL Div 2 FUPLLEN(6) FUPLLIDIV(6) To Clock Generator for Core and Peripherals USB Suspend OSC2 (PB out)(1) UFRCEN(3) Sleep or Idle USB Module SRP Charge VBUS SRP Discharge USB Voltage Comparators 48 MHz USB Clock(7) Full Speed Pull-up D+(2) Registers and Control Interface Host Pull-down Low Speed Pull-up SIE Transceiver D-(2) DMA System RAM Host Pull-down ID Pull-up ID(8) VBUSON(8) Transceiver Power 3.3V VUSB Note 1: 2: 3: 4: 5: 6: 7: 8: PB clock is only available on this pin for select EC modes. Pins can be used as digital inputs when USB is not enabled. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled. DS61143G-page 100 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 12.0 I/O PORTS General purpose I/O pins are the simplest of peripherals. They allow the PIC(R) MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "I/O Ports" (DS61120) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Following are some of the key features of this module: * Individual Output Pin Open-drain Enable/Disable * Individual Input Pin Weak Pull-up Enable/Disable * Monitor Selective Inputs and Generate Interrupt when Change in Pin State is Detected * Operation during CPU Sleep and Idle modes * Fast Bit Manipulation using CLR, SET and INV Registers Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus SYSCLK D Q ODC CK EN Q WR ODC 1 RD TRIS 0 I/O Cell 0 1 D Q 1 TRIS CK EN Q WR TRIS Output Multiplexers D WR LAT WR PORT 0 Q I/O Pin LAT CK EN Q RD LAT 1 RD PORT 0 Sleep Q Q D CK Q Q D CK SYSCLK Synchronization Peripheral Input Legend: Note: R Peripheral Input Buffer R = Peripheral input buffer types may vary. Refer to Table 1-1 "Pinout I/O Descriptions" for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. (c) 2010 Microchip Technology Inc. DS61143G - page 101 PIC32MX3XX/4XX 12.1 Parallel I/O (PIO) Ports All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a data direction or tri-state control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset. Certain I/O pins are shared with analog peripherals and default to analog inputs after a device Reset. PORT is a register used to read the current state of the signal applied to the port I/O pins. Writing to a PORTx register performs a write to the port's latch, LATx register, latching the data to the port's I/O pins. LAT is a register used to write data to the port I/O pins. The LATx latch register holds the data written to either the LATx or PORTx registers. Reading the LATx latch register reads the last value written to the corresponding port or latch register. Not all port I/O pins are implemented on some devices, therefore, the corresponding PORTx, LATx and TRISx register bits will read as zeros. 12.1.1 CLR, SET AND INV REGISTERS Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. The maximum input voltage allowed on the input pins is the same as the maximum VIH specification. Refer to Section 29.0 "Electrical Characteristics" for VIH specification details. Note: 12.1.3 12.1.2 Using a PORTxINV register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions as compared to the traditional read-modify-write method shown below: PORTC ^= 0x0001; DIGITAL INPUTS Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are either TTL buffers or Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at POR. Setting the corresponding bit in the AD1PCFG register = 1 enables the pin as a digital pin. DS61143G - page 102 ANALOG INPUTS Certain pins can be configured as analog inputs used by the ADC and Comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is cleared = 0 (output), the digital output level (VOH or VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read `0'. The AD1PCFG Register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default. 12.1.4 DIGITAL OUTPUTS Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration register. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the "Pin Diagrams" section for the available pins and their functionality. 12.1.5 Note: Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. ANALOG OUTPUTS Certain pins can be configured as analog outputs, such as the CVREF output voltage used by the comparator module. Configuring the Comparator Reference module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin. 12.1.6 INPUT CHANGE NOTIFICATION The input change notification function of the I/O ports (CNx) allows devices to generate interrupt requests in response to change of state on selected pin. Each CNx pin also has a weak pull-up, which acts as a current source connected to the pin. The pull-ups are enabled by setting corresponding bit in CNPUE register. (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 13.0 TIMER1 This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Secondary Oscillator (SOSC) for real-time clock applications. The following modes are supported: Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS61105) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 13-1: Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer 13.1 Additional Supported Features * Selectable clock prescaler * Timer operation during CPU Idle and Sleep mode * Fast bit manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) TIMER1 BLOCK DIAGRAM(1) PR1 Equal 16-bit Comparator TSYNC (T1CON<2>) 1 Reset T1IF Event Flag Sync TMR1 0 0 Q 1 TGATE (T1CON<7>) TGATE (T1CON<7>) D Q TCS (T1CON<1>) ON (T1CON<15>) SOSCO/T1CK x1 SOSCEN SOSCI Gate Sync PBCLK 10 00 Prescaler 1, 8, 64, 256 2 TCKPS<1:0> (T1CON<5:4>) Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1. (c) 2010 Microchip Technology Inc. DS61143G-page 103 PIC32MX3XX/4XX NOTES: DS61143G-page 104 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 14.0 TIMERS 2, 3, 4, 5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS61105) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * Synchronous Internal 32-bit Timer * Synchronous Internal 32-bit Gated Timer * Synchronous External 32-bit Timer Note: 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 14.1 Throughout this chapter, references to registers TxCON, TMRx and PRx use `x' to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or 4; `y' represents Timer3 or 5. Additional Supported Features * Selectable clock prescaler * Timers operational during CPU Idle * Time base for input capture and output compare modules (Timer2 and Timer3 only) * ADC event trigger (Timer3 only) * Fast bit manipulation using CLR, SET and INV registers This family of PIC32MX devices features four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported: * Synchronous Internal 16-bit Timer * Synchronous Internal 16-bit Gated Timer * Synchronous External 16-bit Timer FIGURE 14-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) Sync TMRx ADC Event Trigger(1) Equal Comparator x 16 PRx Reset TxIF Event Flag 0 1 TGATE (TxCON<7>) Q TGATE (TxCON<7>) D Q TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK Note 1: ADC event trigger is available on Timer3 only. 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) 2: TxCK pins not available on 64-pin devices. (c) 2010 Microchip Technology Inc. DS61143G-page 105 PIC32MX3XX/4XX FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy MSHalfWord ADC Event Trigger(3) Equal Sync LSHalfWord 32-bit Comparator PRy TyIF Event Flag TMRx PRx 0 1 TGATE (TxCON<7>) Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of `x' in registers TxCON, TMRx, PRx and TxCK refers to either Timer2 or Timer4; the use of `y' in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5. 2: TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on Timer2/3 pair. DS61143G-page 106 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 15.0 INPUT CAPTURE 2. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Input Capture" (DS61122) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC32MX3XX/4XX devices support up to five input capture channels. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler Capture Event modes - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Input capture can also be used to provide additional sources of external interrupts Simple Capture Event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM ICx Input Timer3 Timer2 ICTMR 0 1 C32 FIFO Control ICxBUF<31:16> Prescaler 1, 4, 16 ICM<2:0> ICxBUF<15:0> Edge Detect ICM<2:0> FEDGE ICxCON ICBNE ICOV ICI<1:0> Interrupt Event Generation Data Space Interface Interrupt (c) 2010 Microchip Technology Inc. Peripheral Data Bus DS61143G-page 107 PIC32MX3XX/4XX NOTES: DS61143G-page 108 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 16.0 OUTPUT COMPARE The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. "Output Capture" (DS61111) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). The following are some of the key features: * Multiple output compare modules in a device * Programmable interrupt generation on compare event * Single and Dual Compare modes * Single and continuous output pulse generation * Pulse-Width Modulation (PWM) mode * Hardware-based PWM Fault detection and automatic output disable * Programmable selection of 16-bit or 32-bit time bases. * Can operate from either of two available 16-bit time bases or a single 32-bit time base 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) Output Logic OCxR(1) 3 OCM<2:0> Mode Select Comparator 0 16 OCTSEL 1 0 S R Q OCx(1) Output Enable OCFA or OCFB (see Note 2) 1 16 TMR register inputs from time bases (see Note 3) Period match signals from time bases (see Note 3) Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. (c) 2010 Microchip Technology Inc. DS61143G-page 109 PIC32MX3XX/4XX NOTES: DS61143G-page 110 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The PIC32MX SPI module is compatible with Motorola(R) SPI and SIOP interfaces. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. "Serial Peripheral Interface (SPI)" (DS61106) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Following are some of the key features of this module: * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 17-1: Master and Slave Modes Support Four Different Clock Formats Framed SPI Protocol Support User Configurable 8-bit, 16-bit and 32-bit Data Width Separate SPI Data Registers for Receive and Transmit Programmable Interrupt Event on every 8-bit, 16-bit and 32-bit Data Transfer Operation during CPU Sleep and Idle Mode Fast Bit Manipulation using CLR, SET and INV Registers * * * * SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write SPIxRXB Registers share address SPIxBUF SPIxTXB Transmit Receive SPIxSR SDIx bit 0 SDOx SSx/FSYNC Shift Control Slave Select and Frame Sync Control Clock Control Edge Select Baud Rate Generator PBCLK SCKx Enable Master Clock Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register. (c) 2010 Microchip Technology Inc. DS61143G-page 111 PIC32MX3XX/4XX NOTES: DS61143G-page 112 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 18.0 INTER-INTEGRATED CIRCUIT (I2CTM) Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. "Inter-Integrated Circuit (I2CTM)" (DS61116) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX3XX/4XX devices have up to two I2C interface modules, denoted as I2C1 and I2C2. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module, `I2Cx' (x = 1 or 2), offers the following key features: * I2C Interface Supporting both Master and Slave Operation. * I2C Slave Mode Supports 7 and 10-bit Address. * I2C Master Mode Supports 7 and 10-bit Address. * I2C Port allows Bidirectional Transfers between Master and Slaves. * Serial Clock Synchronization for I2C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control). * I2C Supports Multi-master Operation; Detects Bus Collision and Arbitrates Accordingly. * Provides Support for Address Bit Masking. The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 18-1 illustrates the I2C module block diagram. (c) 2010 Microchip Technology Inc. DS61143G-page 113 PIC32MX3XX/4XX FIGURE 18-1: I2CTM BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS61143G-page 114 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 19.0 Note UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS61107) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The UART module is one of the serial I/O modules available in PIC32MX3XX/4XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols such as RS232, RS-485, LIN 1.2 and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. FIGURE 19-1: The primary features of the UART module are: * * * * * * * * * * * * * Full-duplex, 8-bit or 9-bit data transmission Even, odd or no parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 76 bps to 20 Mbps at 80 MHz 4-level-deep First-In-First-Out (FIFO) Transmit Data Buffer 4-level-deep FIFO Receive Data Buffer Parity, framing and buffer overrun error detection Support for interrupt only on address detect (9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support * LIN 1.2 protocol support * IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 19-1 illustrates a simplified block diagram of the UART. UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) Hardware Flow Control (c) 2010 Microchip Technology Inc. BCLKx UxRTS UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX DS61143G-page 115 PIC32MX3XX/4XX FIGURE 19-2: Write to UxTXREG BCLK/16 (Shift Clock) UxTX TRANSMISSION (8-BIT OR 9-BIT DATA) Character 1 Start bit bit 0 bit 1 Character 1 bit 7/8 Stop bit UxTXIF Cleared by User UxTXIF Character 1 to Transmit Shift Register TRMT bit FIGURE 19-3: Write to UxTXREG BCLK/16 (Shift Clock) UxTX UxTXIF (UTXISEL0 = 0) UxTXIF (UTXISEL0 = 1) TRMT bit DS61143G-page 116 TWO CONSECUTIVE TRANSMISSIONS Character 1 Character 2 Start bit bit 0 bit 1 Character 1 bit 7/8 Stop bit Start bit bit 0 Character 2 UxTXIF Cleared by User in Software Character 1 to Transmit Shift Register Character 2 to Transmit Shift Register (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 19-4: UART RECEPTION UxRX Start bit bit 0 bit1 bit 7 Stop bit Start bit bit 0 bit 7 Stop bit UxRXIF (RXISEL = 0x) Character 2 to UxRXREG Character 1 to UxRXREG RIDLE bit Note: This timing diagram shows 2 characters received on the UxRX input. FIGURE 19-5: UART RECEPTION WITH RECEIVE OVERRUN Character 1 UxRX Start bit bit 0 bit 1 Characters 2, 3, 4, 5 bit 7/8 Stop bit Start bit bit 0 Character 1, 2, 3, 4 Stored in Receive FIFO bit 7/8 Stop bit Character 6 Start bit bit 7/8 Stop bit Character 5 Held in UxRSR OERR Cleared by User OERR bit RIDLE bit Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character. (c) 2010 Microchip Technology Inc. DS61143G-page 117 PIC32MX3XX/4XX NOTES: DS61143G-page 118 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 20.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Parallel Master Port (PMP)" (DS61128) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. FIGURE 20-1: Key features of the PMP module include: * * * * * * * * * * * * 8-bit,16-bit interface Up to 16 programmable address lines Up to two Chip Select lines Programmable strobe options - Individual read and write strobes, or - Read/write strobe with enable strobe Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Slave Port support - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable Wait states Operate during CPU Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Freeze option for in-circuit debugging Note: On 64-pin devices, data pins PMD<15:8> are not available. PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus PIC32MX3XX/4XX Parallel Master Port Control Lines PMA<0> PMALL PMA<1> PMALH FLASH EEPROM SRAM Up to 16-bit Address PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2 PMRD PMRD/PMWR PMWR PMENB PMD<7:0> PMD<15:8>(1) Note 1: Microcontroller LCD FIFO buffer 16/8-bit Data (with or without multiplexed addressing) On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes. (c) 2010 Microchip Technology Inc. DS61143G-page 119 PIC32MX3XX/4XX NOTES: DS61143G-page 120 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) The following are some of the key features of this module: * * * * Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. "Real-Time Clock and Calendar (RTCC)" (DS61125) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). * * * * * * * * * 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. FIGURE 21-1: * * * * Time: Hours, Minutes and Seconds 24-Hour Format (Military Time) Visibility of One-Half-Second Period Provides Calendar: Weekday, Date, Month and Year Alarm Intervals are configurable for Half of a Second, One Second, 10 Seconds, One Minute, 10 Minutes, One Hour, One Day, One Week, One Month and One Year Alarm Repeat with Decrementing Counter Alarm with Indefinite Repeat: Chime Year Range: 2000 to 2099 Leap Year Correction BCD Format for Smaller Firmware Overhead Optimized for Long-Term Battery Operation Fractional Second Synchronization User Calibration of the Clock Crystal Frequency with Auto-Adjust Calibration Range: 0.66 Seconds Error per Month Calibrates up to 260 ppm of Crystal Error Requirements: External 32.768 kHz Clock Crystal Alarm Pulse or Seconds Clock Output on RTCC pin RTCC BLOCK DIAGRAM 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC Prescalers 0.5s YEAR, MTH, DAY RTCVAL RTCC Timer Alarm Event WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks ALRMVAL WKDAY HR, MIN, SEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse RTCC Pin RTCOE (c) 2010 Microchip Technology Inc. DS61143G-page 121 PIC32MX3XX/4XX NOTES: DS61143G-page 122 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS61104) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX3XX/4XX 10-bit Analog-to-Digital Converter (ADC) includes the following features: * Successive Approximation Register (SAR) conversion * Up to 1000 kilo samples per second (ksps) conversion speed * Up to 16 analog input pins * External voltage reference input pins * One unipolar, differential Sample-and-Hold Amplifier (SHA) FIGURE 22-1: * * * * * * Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Eight conversion result format options Operation during CPU Sleep and Idle modes A block diagram of the 10-bit ADC is illustrated in Figure 22-1. The 10-bit ADC has 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 22-1). The Analog Input Scan mode sequentially converts user-specified channels. A control register specifies which analog input channels will be included in the scanning sequence. The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight, 32-bit output formats when it is read from the result buffer. ADC1 MODULE BLOCK DIAGRAM VREF+(1) AVDD VCFG<2:0> AN0 ADC1BUF0 ADC1BUF1 AN15 CHANNEL SCAN S/H + CH0SB<4:0> CH0SA<4:0> VREF-(1) AVSS - ADC1BUF2 VREFH VREFL SAR ADC CSCNA AN1 ADC1BUFE VREFL ADC1BUFF CH0NA CH0NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. (c) 2010 Microchip Technology Inc. DS61143G-page 121 PIC32MX3XX/4XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC ADC Internal RC Clock(1) 0 TAD ADCS<7:0> 1 8 ADC Conversion Clock Multiplier TPB 2,4,..., 512 Note 1: See the ADC electrical characteristics for the exact RC clock value. DS61143G-page 122 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 23.0 COMPARATOR Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 19. "Comparator" (DS61110) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 23-1: The PIC32MX3XX/4XX Analog Comparator module contains one or more comparator(s) that can be configured in a variety of ways. Following are some of the key features of this module: * Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) * Outputs can be inverted * Selectable interrupt generation A block diagram of the comparator module is illustrated in Figure 23-1. COMPARATOR BLOCK DIAGRAM Comparator 1 CREF ON C1IN+(1) CPOL COUT (CM1CON) C1OUT (CMSTAT) CVREF(2) C1OUT CCH<1:0> C1 C1IN- COE C1IN+ C2IN+ IVREF(2) Comparator 2 CREF ON C2IN+ CPOL COUT (CM2CON) C2OUT (CMSTAT) CVREF(2) C2OUT CCH<1:0> C2IN- C2 COE C2IN+ C1IN+ IVREF(2) Note 1: 2: On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. Internally connected. (c) 2010 Microchip Technology Inc. DS61143G-page 125 PIC32MX3XX/4XX NOTES: DS61143G-page 126 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 24.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 20. "Comparator Voltage Reference (CVREF)" (DS61109) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). A block diagram of the module is illustrated in Figure 24-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 24-1: VREF+ AVDD The comparator voltage reference has the following features: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN CVREF R R 16-to-1 MUX R 16 Steps R CVREFOUT CVRCON<CVROE> R R CVRR VREFAVSS (c) 2010 Microchip Technology Inc. 8R CVRSS = 1 CVRSS = 0 DS61143G-page 127 PIC32MX3XX/4XX NOTES: DS61143G-page 128 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 25.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. "Power-Saving Features" (DS61130) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. This section describes power-saving for the PIC32MX3XX/4XX. The PIC32MX devices offer a total of nine methods and modes that are organized into two categories that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power-saving is controlled by software. 25.1 Power-Saving with CPU Running When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK, and by individually disabling modules. These methods are grouped into the following modes: * FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC Run mode: the CPU is clocked from the LPRC clock source. * SOSC Run mode: the CPU is clocked from the SOSC clock source. * Peripheral Bus Scaling mode: peripherals are clocked at programmable fraction of the CPU clock (SYSCLK). 25.2 CPU Halted Methods The device supports two power-saving modes, Sleep and Idle, both of which halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC Idle Mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC Idle Mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. * SOSC Idle Mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. (c) 2010 Microchip Technology Inc. * LPRC Idle Mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. * Sleep Mode: the CPU, the system clock source, and any peripherals that operate from the system clock source, are halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. 25.3 Power-Saving Operation The purpose of all power-saving is to reduce power consumption by reducing the device clock frequency. To achieve this, low-frequency clock sources can be selected. In addition, the peripherals and CPU can be halted or disabled to further reduce power consumption. 25.3.1 SLEEP MODE Sleep mode has the lowest power consumption of the device Power-Saving operating modes. The CPU and most peripherals are halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep mode. Sleep mode includes the following characteristics: * The CPU is halted. * The system clock source is typically shut down. See Section 25.3.2 "Idle Mode" for specific information. * There can be a wake-up delay based on the oscillator selection. * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. * The BOR circuit, if enabled, remains operative during Sleep mode. * The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. * Some peripherals can continue to operate in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator, e.g., RTCC and Timer 1. * I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. * The USB module can override the disabling of the POSC or FRC. Refer to Section 11.0 "USB OnThe-Go (OTG)" for specific details. * Some modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption. DS61143G-page 129 PIC32MX3XX/4XX The processor will exit, or `wake-up', from Sleep on one of the following events: The processor will wake or exit from Idle mode on the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset. * On a WDT time-out. See Section 26.2 "Watchdog Timer (WDT)". * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of CPU. If the priority of the interrupt event is lower than or equal to current priority of CPU, the CPU will remain halted and the device will remain in Idle mode. * On any source of device Reset. * On a WDT time-out interrupt. See Section 26.2 "Watchdog Timer (WDT)". If the interrupt priority is lower than or equal to current priority, the CPU will remain halted, but the PBCLK will start running and the device will enter into Idle mode. Note: 25.3.2 There is no FRZ mode for this module. IDLE MODE In the Idle mode, the CPU is halted but the System clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is halted. Peripherals can be individually configured to halt when entering Idle by setting their respective SIDL bit. Latency when exiting Idle mode is very low due to the CPU oscillator source remaining active. Note: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in PB divisor ratio. Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator start-up delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator startup/lock delays would be applied. 25.3.3 PERIPHERAL BUS SCALING METHOD Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, Interrupt Controller, DMA, Bus Matrix and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements such as baud rate accuracy should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. The device enters Idle mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed. DS61143G-page 130 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 26.0 SPECIAL FEATURES Note: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the "PIC32MX Family Reference Manual" (DS61132), which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX3XX/4XX devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. These are: * * * * Flexible Device Configuration Watchdog Timer JTAG Interface In-Circuit Serial ProgrammingTM (ICSPTM) 26.1 Configuration Bits The Configuration bits can be programmed to select various device configurations. REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P -- -- -- CP -- -- -- BWP bit 31 bit 24 r-1 r-1 r-1 r-1 -- -- -- -- R/P R/P R/P R/P PWP<7:4> bit 23 bit 16 R/P R/P R/P R/P PWP<3:0> r-1 r-1 r-1 r-1 -- -- -- -- bit 15 bit 8 r-1 r-1 r-1 r-1 R/P r-1 -- -- -- -- ICESEL -- R/P R/P DEBUG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (`0', `1', x = Unknown) P = Programmable bit r = Reserved bit bit 31 Reserved: Write `0' bit 30-29 Reserved: Write `1' bit 28 CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection disabled 0 = Protection enabled bit 27-25 Reserved: Write `1' bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write `1' (c) 2010 Microchip Technology Inc. DS61143G-page 131 PIC32MX3XX/4XX REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one's compliment of the number of write protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF . . . 01111111 = 0xBD07_FFFF bit 11-4 Reserved: Write `1' bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used bit 2 Reserved: Write `1' bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 11 = Debugger disabled 10 = Debugger enabled 01 = Reserved (same as `11' setting) 00 = Reserved (same as `11' setting) DS61143G-page 132 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- bit 31 bit 24 R/P r-1 r-1 FWDTEN -- -- R/P R/P R/P R/P R/P WDTPS<4:0> bit 23 bit 16 R/P R/P R/P FCKSM<1:0> R/P FPBDIV<1:0> r-1 R/P -- OSCIOFNC R/P R/P POSCMOD<1:0> bit 15 bit 8 R/P r-1 R/P r-1 r-1 IESO -- FSOSCEN -- -- R/P R/P R/P FNOSC<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable bit U = Unimplemented bit -n = Bit Value at POR: (`0', `1', x = Unknown) bit 31-24 Reserved: Write `1' bit 23 FWDTEN: Watchdog Timer Enable bit 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled; it can be enabled in software bit 22-21 Reserved: Write `1' bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = `10100' (c) 2010 Microchip Technology Inc. r = Reserved bit DS61143G-page 133 PIC32MX3XX/4XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write `1' bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 OR 00) 0 = CLKO output disabled bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS oscillator mode selected 01 = XT oscillator mode selected 00 = External clock mode selected bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) bit 6 Reserved: Write `1' bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 4-3 Reserved: Write `1' bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable POSC (POSCMOD = 00) when using this oscillator source. DS61143G-page 134 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- R/P R/P R/P FPLLODIV<2:0> bit 23 bit 16 R/P r-1 r-1 r-1 r-1 FUPLLEN -- -- -- -- R/P R/P R/P FUPLLIDIV<2:0> bit 15 bit 8 r-1 R/P -- R/P R/P r-1 FPLLMULT<2:0> R/P -- R/P R/P FPLLIDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable bit U = Unimplemented bit -n = Bit Value at POR: (`0', `1', x = Unknown) bit 31-19 Reserved: Write `1' bit 18-16 FPLLODIV<2:0>: Default Postscaler for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 FUPLLEN: USB PLL Enable bit 1 = Enable USB PLL 0 = Disable and bypass USB PLL bit 14-11 Reserved: Write `1' bit 10-8 FUPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 Reserved: Write `1' (c) 2010 Microchip Technology Inc. r = Reserved bit DS61143G-page 135 PIC32MX3XX/4XX REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 6-4 FPLLMULT<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write `1' bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider REGISTER 26-4: DEVCFG3: DEVICE CONFIGURATION WORD 3 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- bit 23 bit 16 R/P R/P R/P R/P R/P R/P R/P R/P USERID<15:8> bit 15 bit 8 R/P R/P R/P R/P R/P R/P R/P R/P USERID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable bit U = Unimplemented bit -n = Bit Value at POR: (`0', `1', x = Unknown) r = Reserved bit bit 31-16 Reserved: Write `1' bit 15-0 USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSPTM and JTAG DS61143G-page 136 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-5: R DEVID: DEVICE AND REVISION ID REGISTER R R R R VER<3:0>(1) R R R (1) DEVID<27:24> bit 31 bit 24 R R R R R DEVID<23:16> R R R (1) bit 23 bit 16 R R R R R R R R DEVID<15:8>(1) bit 15 bit 8 R R R R R DEVID<7:0> R R R (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (`0', `1', x = Unknown) bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID(1) Note 1: P = Programmable bit r = Reserved bit See the "PIC32MX Flash Programming Specification" (DS61145) for a list of Revision and Device ID values. (c) 2010 Microchip Technology Inc. DS61143G-page 137 PIC32MX3XX/4XX 26.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-Up Timer of the PIC32MX3XX/4XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM PWRT Enable WDT Enable LPRC Control PWRT Enable 1:64 Output LPRC Oscillator PWRT 1 Clock 25-bit Counter WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event 25 0 1 WDT Counter Reset Device Reset NMI (Wake-up) Power Save Decoder FWDTPS<4:0>(DEVCFG1<20:16>) DS61143G-page 138 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 26.3 On-Chip Voltage Regulator 26.3.1 ON-CHIP REGULATOR AND POR All PIC32MX3XX/4XX device's core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX3XX/4XX incorporate an on-chip regulator providing the required core logic voltage from VDD. When the voltage regulator is enabled, it takes fixed delay for it to generate output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. The internal 1.8V regulator is controlled by the ENVREG pin. Tying this pin to VDD enables the regulator, which in turn provides power to the core. A low ESR capacitor (such as tantalum) must be connected to the VDDCORE/VCAP pin (Figure 26-2). This helps to maintain the stability of the regulator. The recommended value for the filer capacitor is provided in Section 29.1 "DC Characteristics". If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of TPWRT at device start-up. See Section 29.0 "Electrical Characteristics" for more information on TPU AND TPWRT. Note: It is important that the low ESR capacitor is placed as close as possible to the VDDCORE/VCAP pin. Tying the ENVREG pin to VSS disables the regulator. In this case, separate power for the core logic at a nominal 1.8V must be supplied to the device on the VDDCORE/VCAP pin. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 26-2 for possible configurations. FIGURE 26-2: ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC32MX3XX/4XX devices also have a simple brownout capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 29.1 "DC Characteristics". 26.3.3 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): 3.3V PIC32MX VDD ENVREG VDDCORE/VCAP CEFC (10 F typ) Note 1: 26.3.2 VSS Regulator Disabled (ENVREG tied to ground): 1.8V(1) 3.3V(1) PIC32MX VDD ENVREG VDDCORE/VCAP VSS These are typical operating voltages. Refer to Section 31.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE. (c) 2010 Microchip Technology Inc. DS61143G-page 139 PIC32MX3XX/4XX 26.4 Programming and Diagnostics PIC32MX3XX/4XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: * Simplified field programmability using two-wire InCircuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32MX devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. FIGURE 26-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS PGEC1 PGED1 ICSPTM Controller PGEC2 PGED2 ICESEL TDI TDO JTAG Controller TCK Core TMS JTAGEN DEBUG<1:0> TRCLK TRD0 TRD1 Instruction Trace Controller TRD2 TRD3 DEBUG<1:0> DS61143G-page 140 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 26-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER r-x r-x r-x r-x r-x r-x r-x r-x -- -- -- -- -- -- -- -- bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x -- -- -- -- -- -- -- -- bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 r-x r-x DDPUSB DDPU1 DDPU2 DDPSPI1 JTAGEN TROEN -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (`0', `1', x = Unknown) P = Programmable bit bit 31-8 Reserved: Write `0'; ignore read bit 7 DDPUSB: Debug Data Port Enable for USB bit 1 = USB peripheral ignores USBFRZ (U1CNFG1<5>) setting 0 = USB peripheral follows USBFRZ setting bit 6 DDPU1: Debug Data Port Enable for UART1 bit 1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting 0 = UART1 peripheral follows FRZ setting bit 5 DDPU2: Debug Data Port Enable for UART2 bit 1 = UART2 peripheral ignores FRZ (U2MODE<14>) setting 0 = UART2 peripheral follows FRZ setting bit 4 DDPSPI1: Debug Data Port Enable for SPI1 bit 1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting 0 = SPI1 peripheral follows FRZ setting bit 3 JTAGEN: JTAG Port Enable bit 1 = Enable JTAG Port 0 = Disable JTAG Port bit 2 TROEN: Trace Output Enable bit 1 = Enable Trace Port 0 = Disable Trace Port bit 1-0 Reserved: Write `1'; ignore read (c) 2010 Microchip Technology Inc. r = Reserved bit DS61143G-page 141 PIC32MX3XX/4XX NOTES: DS61143G-page 142 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 27.0 INSTRUCTION SET The PIC32MX3XX/4XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features: Table 27-1 provides a summary of the instructions that are implemented by the PIC32MX3XX/4XX family core. Note: * CoreExtend instructions * Coprocessor 1 instructions * Coprocessor 2 instructions TABLE 27-1: MIPS32(R) INSTRUCTION SET Instruction Description Refer to "MIPS32(R) Architecture for Programmers Volume II: The MIPS32(R) Instruction Set" at www.mips.com for more information. Function ADD Integer Add Rd = Rs + Rt ADDI Integer Add Immediate Rt = Rs + Immed ADDIU Unsigned Integer Add Immediate Rt = Rs +U Immed ADDU Unsigned Integer Add AND Logical AND Rd = Rs +U Rt Rd = Rs & Rt ANDI Logical AND Immediate Rt = Rs & (016 || Immed) B Unconditional Branch (Assembler idiom for: BEQ r0, r0, offset) PC += (int)offset BAL Branch and Link (Assembler idiom for: BGEZAL r0, offset) GPR[31] = PC + 8 PC += (int)offset BEQ Branch on Equal if Rs == Rt PC += (int)offset BEQL Branch on Equal Likely(1) if Rs == Rt PC += (int)offset else Ignore Next Instruction BGEZ Branch on Greater Than or Equal to Zero if !Rs[31] PC += (int)offset BGEZAL Branch on Greater Than or Equal to Zero and Link GPR[31] = PC + 8 if !Rs[31] PC += (int)offset BGEZALL Branch on Greater Than or Equal to Zero and Link Likely(1) GPR[31] = PC + 8 if !Rs[31] PC += (int)offset else Ignore Next Instruction BGEZL Branch on Greater Than or Equal to Zero Likely(1) if !Rs[31] PC += (int)offset else Ignore Next Instruction BGTZ Branch on Greater Than Zero if !Rs[31] && Rs != 0 PC += (int)offset BGTZL Branch on Greater Than Zero Likely(1) if !Rs[31] && Rs != 0 PC += (int)offset else Ignore Next Instruction BLEZ Branch on Less Than or Equal to Zero if Rs[31] || Rs == 0 PC += (int)offset Note 1: This instruction is deprecated and should not be used. (c) 2010 Microchip Technology Inc. DS61143G-page 143 PIC32MX3XX/4XX TABLE 27-1: MIPS32(R) INSTRUCTION SET (CONTINUED) Instruction Description Function (1) BLEZL Branch on Less Than or Equal to Zero Likely BLTZ Branch on Less Than Zero if Rs[31] PC += (int)offset BLTZAL Branch on Less Than Zero and Link GPR[31] = PC + 8 if Rs[31] PC += (int)offset BLTZALL Branch on Less Than Zero and Link Likely(1) GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction BLTZL Branch on Less Than Zero Likely(1) if Rs[31] PC += (int)offset else Ignore Next Instruction BNE Branch on Not Equal if Rs != Rt PC += (int)offset BNEL Branch on Not Equal Likely(1) if Rs != Rt PC += (int)offset else Ignore Next Instruction BREAK Breakpoint Break Exception CLO Count Leading Ones Rd = NumLeadingOnes(Rs) CLZ Count Leading Zeroes Rd = NumLeadingZeroes(Rs) DERET Return from Debug Exception PC = DEPC Exit Debug Mode if Rs[31] || Rs == 0 PC += (int)offset else Ignore Next Instruction DI Atomically Disable Interrupts Rt = Status; StatusIE = 0 DIV Divide LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt DIVU Unsigned Divide LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt EHB Execution Hazard Barrier Stop instruction execution until execution hazards are cleared EI Atomically Enable Interrupts ERET Return from Exception Rt = Status; StatusIE = 1 if StatusERL PC = ErrorEPC else PC = EPC StatusEXL = 0 StatusERL = 0 LL = 0 EXT Extract Bit Field Rt = ExtractField(Rs, pos, size) INS Insert Bit Field Rt = InsertField(Rs, Rt, pos, size) J Unconditional Jump PC = PC[31:28] || offset<<2 Note 1: This instruction is deprecated and should not be used. DS61143G-page 144 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 27-1: MIPS32(R) INSTRUCTION SET (CONTINUED) Instruction Description Function JAL Jump and Link GPR[31] = PC + 8 PC = PC[31:28] || offset<<2 JALR Jump and Link Register Rd = PC + 8 PC = Rs JALR.HB Jump and Link Register with Hazard Barrier Like JALR, but also clears execution and instruction hazards JR Jump Register PC = Rs JR.HB Jump Register with Hazard Barrier Like JR, but also clears execution and instruction hazards LB Load Byte Rt = (byte)Mem[Rs+offset] LBU Unsigned Load Byte Rt = (ubyte))Mem[Rs+offset] LH Load Halfword Rt = (half)Mem[Rs+offset] LHU Unsigned Load Halfword Rt = (uhalf)Mem[Rs+offset] LL Load Linked Word Rt = Mem[Rs+offset> LLbit = 1 LLAdr = Rs + offset LUI Load Upper Immediate Rt = immediate << 16 LW Load Word Rt = Mem[Rs+offset] LWPC Load Word, PC relative Rt = Mem[PC+offset] LWL Load Word Left Re = Re MERGE Mem[Rs+offset] LWR Load Word Right Re = Re MERGE Mem[Rs+offset] MADD Multiply-Add HI | LO += (int)Rs * (int)Rt MADDU Multiply-Add Unsigned HI | LO += (uns)Rs * (uns)Rt MFC0 Move from Coprocessor 0 Rt = CPR[0, Rd, sel] MFHI Move from HI Rd = HI MFLO Move from LO Rd = LO MOVN Move Conditional on Not Zero if Rt 1/4 0 then Rd = Rs MOVZ Move Conditional on Zero if Rt = 0 then Rd = Rs MSUB Multiply-Subtract HI | LO -= (int)Rs * (int)Rt MSUBU Multiply-Subtract Unsigned HI | LO -= (uns)Rs * (uns)Rt MTC0 Move to Coprocessor 0 CPR[0, n, Sel] = Rt MTHI Move to HI HI = Rs MTLO Move to LO LO = Rs MUL Multiply with register write HI | LO =Unpredictable Rd = ((int)Rs * (int)Rt)31..0 MULT Integer Multiply HI | LO = (int)Rs * (int)Rd MULTU Unsigned Multiply HI | LO = (uns)Rs * (uns)Rd NOP No Operation (Assembler idiom for: SLL r0, r0, r0) NOR Logical NOR Rd = ~(Rs | Rt) OR Logical OR Rd = Rs | Rt ORI Logical OR Immediate Rt = Rs | Immed RDHWR Read Hardware Register (if enabled by HWREna Register) Re = HWR[Rd] Note 1: This instruction is deprecated and should not be used. (c) 2010 Microchip Technology Inc. DS61143G-page 145 PIC32MX3XX/4XX TABLE 27-1: MIPS32(R) INSTRUCTION SET (CONTINUED) Instruction Description Function RDPGPR Read GPR from Previous Shadow Set Rt = SGPR[SRSCtlPSS, Rd] ROTR Rotate Word Right ROTRV Rotate Word Right Variable SB Store Byte Rd = Rtsa-1..0 || Rt31..sa Rd = RtRs-1..0 || Rt31..Rs (byte)Mem[Rs+offset] = Rt SC Store Conditional Word if LLbit = 1 mem[Rs+offset> = Rt Rt = LLbit SDBBP Software Debug Break Point Trap to SW Debug Handler SEB Sign-Extend Byte Rd = SignExtend (Rs-7...0) SEH Sign-Extend Half Rd = SignExtend (Rs-15...0) SH Store Half (half)Mem[Rs+offset> = Rt SLL Shift Left Logical Rd = Rt << sa SLLV Shift Left Logical Variable Rd = Rt << Rs[4:0] SLT Set on Less Than if (int)Rs < (int)Rt Rd = 1 else Rd = 0 SLTI Set on Less Than Immediate if (int)Rs < (int)Immed Rt = 1 else Rt = 0 SLTIU Set on Less Than Immediate Unsigned if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0 SLTU Set on Less Than Unsigned if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0 SRA Shift Right Arithmetic Rd = (int)Rt >> sa SRAV Shift Right Arithmetic Variable Rd = (int)Rt >> Rs[4:0] SRL Shift Right Logical Rd = (uns)Rt >> sa SRLV Shift Right Logical Variable Rd = (uns)Rt >> Rs[4:0] SSNOP Superscalar Inhibit No Operation NOP SUB Integer Subtract Rt = (int)Rs - (int)Rd SUBU Unsigned Subtract Rt = (uns)Rs - (uns)Rd SW Store Word Mem[Rs+offset] = Rt SWL Store Word Left Mem[Rs+offset] = Rt SWR Store Word Right Mem[Rs+offset] = Rt SYNC Synchronize Orders the cached coherent and uncached loads and stores for access to the shared memory SYSCALL System Call SystemCallException TEQ Trap if Equal if Rs == Rt TrapException TEQI Trap if Equal Immediate if Rs == (int)Immed TrapException Note 1: This instruction is deprecated and should not be used. DS61143G-page 146 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 27-1: MIPS32(R) INSTRUCTION SET (CONTINUED) Instruction Description Function TGE Trap if Greater Than or Equal if (int)Rs >= (int)Rt TrapException TGEI Trap if Greater Than or Equal Immediate if (int)Rs >= (int)Immed TrapException TGEIU Trap if Greater Than or Equal Immediate Unsigned if (uns)Rs >= (uns)Immed TrapException TGEU Trap if Greater Than or Equal Unsigned if (uns)Rs >= (uns)Rt TrapException TLT Trap if Less Than if (int)Rs < (int)Rt TrapException TLTI Trap if Less Than Immediate if (int)Rs < (int)Immed TrapException TLTIU Trap if Less Than Immediate Unsigned if (uns)Rs < (uns)Immed TrapException TLTU Trap if Less Than Unsigned if (uns)Rs < (uns)Rt TrapException TNE Trap if Not Equal if Rs != Rt TrapException TNEI Trap if Not Equal Immediate if Rs != (int)Immed TrapException WAIT Wait for Interrupt Go to a low power mode and stall until interrupt occurs WRPGPR Write to GPR in Previous Shadow Set SGPR[SRSCtlPSS, Rd> = Rt WSBH Word Swap Bytes Within Halfwords XOR Exclusive OR Rd = Rt23..16 || Rt31..24 || Rt7..0 || Rt15..8 Rd = Rs ^ Rt XORI Exclusive OR Immediate Rt = Rs ^ (uns)Immed Note 1: This instruction is deprecated and should not be used. (c) 2010 Microchip Technology Inc. DS61143G-page 147 PIC32MX3XX/4XX NOTES: DS61143G-page 148 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 28.0 DEVELOPMENT SUPPORT The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits 28.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2010 Microchip Technology Inc. DS61143G-page 149 PIC32MX3XX/4XX 28.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 28.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 28.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 28.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process DS61143G-page 150 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 28.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 28.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2010 Microchip Technology Inc. 28.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and Microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 28.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement In-Circuit Debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. DS61143G-page 151 PIC32MX3XX/4XX 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 28.13 Demonstration/Development Boards, Evaluation Kits and Starter Kits The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-CircuitDebugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 28.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS61143G-page 152 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings (Note 1) Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS WHEN VDD 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS WHEN VDD < 2.3V (Note 3) ............................ -0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2). 3: See the "Pin Diagrams" section for the 5V tolerant pins. (c) 2010 Microchip Technology Inc. DS61143G-page 153 PIC32MX3XX/4XX 29.1 DC Characteristics TABLE 29-1: OPERATING MIPS VS. VOLTAGE Characteristic DC5 Note 1: Max. Frequency VDD Range (in Volts) Temp. Range (in C) PIC32MX3XX/4XX 2.3-3.6V -40C to +85C 80 MHz (Note 1) 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. TABLE 29-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit Operating Junction Temperature Range TJ -40 -- +125 C Operating Ambient Temperature Range TA -40 -- +85 C PIC32MX3XX/4XX Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) PD PINT + PI/O W PDMAX (TJ - TA)/JA W I/O Pin Power Dissipation: I/O = S ({VDD - VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical JA JA JA JA Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm) Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) Note 1: Max. Unit Notes 40 -- C/W 1 43 -- C/W 1 47 -- C/W 1 28 -- C/W 1 Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Conditions 2.3 -- 3.6 V -- Operating Voltage DC10 Supply Voltage VDD DC12 VDR RAM Data Retention Voltage (Note 1) 1.75 -- -- V -- DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal 1.75 -- 1.95 V -- DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.05 -- -- V/ms -- Note 1: This is the limit to which VDD can be lowered without losing RAM data. DS61143G-page 154 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(3) Max. Units Conditions Operating Current (IDD)(1,2) DC20 8.5 13 mA Code executing from Flash -- DC20c 4.0 -- mA Code executing from SRAM -- DC21 23.5 32 mA Code executing from Flash -- DC21c 16.4 -- mA Code executing from SRAM -- DC22 48 61 mA Code executing from Flash -- DC22c 45 -- mA Code executing from SRAM -- DC23 55 75 mA Code executing from Flash 2.3V DC23c 55 -- mA Code executing from SRAM -- DC24 -- 100 A -40C DC24a -- 130 A +25C DC24b -- 670 A +85C DC25 94 -- A -40C DC25a 125 -- A +25C DC25b 302 -- A +85C DC25c 71 -- A DC26 -- 110 A -40C DC26a -- 180 A +25C DC26b -- 700 A +85C Note 1: 2: 3: 4: 4 MHz 20 MHz (Note 4) 60 MHz (Note 4) 80 MHz 2.3V 3.3V LPRC (31 kHz) (Note 4) Code executing from SRAM 3.6V A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type as well as temperature can have an impact on the current consumption. The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. (c) 2010 Microchip Technology Inc. DS61143G-page 155 PIC32MX3XX/4XX TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1) DC30 -- 5 mA -- 2.3V DC30a 1.4 -- mA -- -- DC30b -- 5 mA -- 3.6V DC31 -- 15 mA -- 2.3V DC31a 13 -- mA -- -- DC31b -- 17 mA -- 3.6V DC32 -- 22 mA -- 2.3V DC32a 20 -- mA -- -- DC32b -- 25 mA -- 3.6V DC33 -- 29 mA -- 2.3V DC33a 24 -- mA -- -- DC33b -- 32 mA -- 3.6V DC34 -- 36 A -40C DC34a -- 62 A +25C DC34b -- 392 A +85C DC35 35 -- A -40C DC35a 65 -- A +25C DC35b 242 -- A +85C DC36 -- 43 A -40C DC36a -- 106 A +25C -- 414 A +85C DC36b Note 1: 2: 3: 4 MHz 20 MHz (Note 3) 60 MHz (Note 3) 80 MHz 2.3V 3.3V LPRC (31 kHz) (Note 3) 3.6V The test conditions for base IDLE current measurements are as follows: System clock is enabled and PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled (ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. DS61143G-page 156 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Power-Down Current (IPD) (Note 1) DC40 7 30 A -40C DC40a 24 30 A +25C DC40b 205 300 A +85C DC40c 25 -- A +25C DC40d 9 70 A -40C DC40e 25 70 A +25C DC40g 115 200 (Note 5) A +70C DC40f 200 400 A +85C 10 A -40C 2.3V Base Power-Down Current (Note 6) 3.3V Base Power-Down Current 3.6V Base Power-Down Current 2.3V Watchdog Timer Current: IWDT (Notes 3,6) 3.3V Watchdog Timer Current: IWDT (Note 3) 3.6V Watchdog Timer Current: IWDT (Note 3) 2.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6) Module Differential Current DC41 -- DC41a -- 10 A +25C DC41b -- 10 A +85C DC41c 5 -- A +25C DC41d -- 10 A -40C DC41e -- 10 A +25C DC41f -- 12 A +85C DC42 -- 10 A -40C DC42a -- 17 A +25C DC42b -- 37 A +85C DC42c 23 -- A +25C DC42e -- 10 A -40C DC42f -- 30 A +25C DC42g -- 44 A +85C DC42 -- 1100 A -40C DC42a -- 1100 A +25C DC42b -- 1000 A +85C DC42c 880 -- A -- DC42e -- 1100 A -40C DC42f -- 1100 A +25C DC42g -- 1000 A +85C Note 1: 2: 3: 4: 5: 6: 3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) 2.5V ADC: IADC (Notes 3,4,6) -- ADC: IADC (Notes 3,4) 3.6V ADC: IADC (Notes 3,4) Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. Data is characterized at +70C and not tested. Parameter is for design guidance only. This parameter is characterized, but not tested in manufacturing. (c) 2010 Microchip Technology Inc. DS61143G-page 157 PIC32MX3XX/4XX TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. VIL DI10 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units with TTL Buffer VSS -- 0.15 VDD V (Note 4) with Schmitt Trigger Buffer VSS -- 0.2 VDD V (Note 4) Characteristics Conditions Input Low Voltage I/O pins: DI15 MCLR VSS -- 0.2 VDD V (Note 4) DI16 OSC1 (XT mode) VSS -- 0.2 VDD V (Note 4) DI17 OSC1 (HS mode) VSS -- 0.2 VDD V (Note 4) DI18 SDAx, SCLx VSS -- 0.3 VDD V SMBus disabled (Note 4) DI19 SDAx, SCLx VSS -- 0.8 V SMBus enabled (Note 4) I/O pins: with Analog Functions 0.8 VDD -- VDD V (Note 4) Digital Only 0.8 VDD -- V (Note 4) 0.25VDD + 0.8V -- 5.5 V (Note 4) 0.8 VDD -- 5.5 V (Note 4) VIH DI20 Input High Voltage with TTL Buffer with Schmitt Trigger Buffer DI25 MCLR 0.8 VDD -- VDD V (Note 4) DI26 OSC1 (XT mode) 0.7 VDD -- VDD V (Note 4) DI27 OSC1 (HS mode) 0.7 VDD -- VDD V (Note 4) DI28 SDAx, SCLx 0.7 VDD -- 5.5 V SMBus disabled (Note 4) DI29 SDAx, SCLx 2.1 -- 5.5 V SMBus enabled, 2.3V VPIN 5.5 (Note 4) ICNPU CNxx Pull up Current 50 250 400 A VDD = 3.3V, VPIN = VSS IIL Input Leakage Current (Note 3) DI30 DI50 I/O Ports -- -- +1 A VSS VPIN VDD, Pin at high-impedance DI51 Analog Input Pins -- -- +1 A VSS VPIN VDD, Pin at high-impedance DI55 MCLR -- -- +1 A VSS VPIN VDD DI56 OSC1 -- -- +1 A VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. This parameter is characterized, but not tested in manufacturing. DS61143G-page 158 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Param. Symbol No. VOL DO10 Characteristics OSC2/CLKO VOH Typical Max. Units Conditions -- -- 0.4 V IOL = 7 mA, VDD = 3.6V -- -- 0.4 V IOL = 6 mA, VDD = 2.3V -- -- 0.4 V IOL = 3.5 mA, VDD = 3.6V -- -- 0.4 V IOL = 2.5 mA, VDD = 2.3V 2.4 -- -- V IOH = -12 mA, VDD = 3.6V 1.4 -- -- V IOH = -12 mA, VDD = 2.3V 2.4 -- -- V IOH = -12 mA, VDD = 3.6V 1.4 -- -- V IOH = -12 mA, VDD = 2.3V Output Low Voltage I/O Ports DO16 Min. Output High Voltage DO20 I/O Ports DO26 OSC2/CLKO TABLE 29-10: DC CHARACTERISTICS: PROGRAM MEMORY(3) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Programming temperature 0C TA +70C (25C recommended) DC CHARACTERISTICS Param. No. Symbol Characteristics Min. Typical(1) Max. Units Conditions Program Flash Memory D130 EP Cell Endurance 1000 -- -- E/W D131 VPR VDD for Read VMIN -- 3.6 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase or Write 3.0 -- 3.6 V 0C to +40C D134 TRETD Characteristic Retention 20 -- -- Year Provided no other specifications are violated D135 IDDP Supply Current during Programming -- 10 -- mA 0C to +40C TWW Word Write Cycle Time 20 -- 40 s 0C to +40C D136 TRW Row Write Cycle Time (Note 2) (128 words per row) 3 4.5 -- ms 0C to +40C D137 TPE Page Erase Cycle Time 20 -- -- ms 0C to +40C TCE Chip Erase Cycle Time 80 -- -- ms 0C to +40C D138 LVDstartup Flash LVD Delay -- -- 6 s Flash LVD comparator delay from enable to output valid. Note 1: 2: 3: -40C to +85C Data in "Typical" column is at 3.3V, 25C unless otherwise stated. The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to "PIC32MX Flash Programming Specification" (DS61145) for operating conditions during programming and erase cycles. (c) 2010 Microchip Technology Inc. DS61143G-page 159 PIC32MX3XX/4XX TABLE 29-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Required Flash wait states SYSCLK Units 0 Wait State 0 to 30 MHz 1 Wait State 31 to 60 2 Wait States 61 to 80 Note 1: Comments -- 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. TABLE 29-12: COMPARATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40C TA +85C for Industrial DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Comments D300 VIOFF Input Offset Voltage -- 7.5 25 mV AVDD = VDD, AVSS = VSS D301 VICM Input Common Mode Voltage 0 -- VDD V AVDD = VDD, AVSS = VSS (Note 2) D302 CMRR Common Mode Rejection Ratio 55 -- -- dB Max VICM = (VDD - 1)V (Note 2) D303 TRESP Response Time -- 150 400 nsec AVDD = VDD, AVSS = VSS (Notes 1,2) D304 ON2OV Comparator Enabled to Output Valid -- -- 10 s Comparator module is configured before setting the comparator ON bit. (Note 2) D305 IVREF Internal Voltage Reference 1.14 1.2 1.26 V -- Note 1: 2: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. These parameters are characterized but not tested. TABLE 29-13: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40C TA +85C for Industrial DC CHARACTERISTICS Param. No. Symbol Characteristics D310 VRES Resolution D311 VRAA Absolute Accuracy D312 Note 1: TSET Settling Time(1) Min. Typical Max. Units Comments VDD/24 -- -- -- VDD/32 LSb -- 1/2 LSb -- -- -- 10 s -- Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from `0000' to `1111'. This parameter is characterized, but not tested in manufacturing. DS61143G-page 160 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40C TA +85C for Industrial DC CHARACTERISTICS Param. No. Symbol Characteristics Min. Typical Max. Units Comments 1.62 1.80 1.98 V -- D320 VDDCORE Regulator Output Voltage D321 CEFC External Filter Capacitor Value 8 10 -- F Capacitor must be low series resistance (< 1 Ohm) D322 TPWRT Power-up Timer Period -- 64 -- ms ENVREG = 0 (c) 2010 Microchip Technology Inc. DS61143G-page 161 PIC32MX3XX/4XX 29.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX3XX/4XX AC characteristics and timing parameters. TABLE 29-15: AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range. AC CHARACTERISTICS FIGURE 29-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode) VSS TABLE 29-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Param. Symbol No. Min. Typical(1) Characteristics Max. Units Conditions DO56 CIO All I/O pins and OSC2 -- -- 50 pF EC mode DO58 CB SCLx, SDAx -- -- 400 pF In I2CTM mode Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 DS61143G-page 162 OS31 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max. Units Conditions External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) DC 4 -- -- 50 (Note 3) 50 (Note 5) MHz MHz EC (Note 5) ECPLL (Note 4) Oscillator Crystal Frequency 3 -- 10 MHz XT (Note 5) OS12 4 -- 10 MHz XTPLL (Notes 4,5) OS10 FOSC OS11 Characteristics OS13 10 -- 25 MHz HS (Note 5) OS14 10 -- 25 MHz HSPLL (Notes 4,5) OS15 32 32.768 100 kHz SOSC (Note 5) -- -- -- -- See parameter OS10 for FOSC value OS20 TOSC TOSC = 1/FOSC = TCY (Note 2) OS30 TOSL, TOSH External Clock In (OSC1) High or Low Time 0.45 x TOSC -- -- nsec EC (Note 5) OS31 TOSR, TOSF External Clock In (OSC1) Rise or Fall Time -- -- 0.05 x TOSC nsec EC (Note 5) OS40 TOST Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) -- 1024 -- TOSC (Note 5) OS41 TFSCM Primary Clock Fail Safe Time-out Period -- 2 -- ms (Note 5) OS42 GM External Oscillator Transconductance -- 12 -- Note 1: 2: 3: 4: 5: mA/V VDD = 3.3V TA = +25C (Note 5) Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing. (c) 2010 Microchip Technology Inc. DS61143G-page 163 PIC32MX3XX/4XX TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 4 -- 5 MHz OS51 FSYS On-Chip VCO System Frequency 60 -- 120 MHz -- OS52 TLOCK PLL Start-up Time (Lock Time) -- -- 2 ms -- OS53 DCLK CLKO Stability (Period Jitter or Cumulative) -0.25 -- +0.25 % Note 1: 2: ECPLL, HSPLL, XTPLL, FRCPLL modes Measured over 100 ms period These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-19: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min. Typical Max. Units Conditions +2 % -- Internal FRC Accuracy @ 8.00 MHz (Note 1) F20 Note 1: FRC -2 -- Frequency calibrated at 25C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 29-20: INTERNAL RC ACCURACY AC CHARACTERISTICS Param. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions -15 -- +15 % -- LPRC @ 31.25 kHz (Note 1) F21 Note 1: LPRC Change of LPRC frequency as VDD changes. DS61143G-page 164 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 29-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 29-1 for load conditions. DO31 DO32 TABLE 29-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol DO31 TIOR DO32 TIOF Characteristics(2) Port Output Rise Time Port Output Fall Time Min. Typical(1) Max. Units Conditions -- 5 15 nsec VDD < 2.5V -- 5 10 nsec VDD > 2.5V -- 5 15 nsec VDD < 2.5V -- 5 10 nsec VDD > 2.5V DI35 TINP INTx Pin High or Low Time 10 -- -- nsec -- DI40 TRBP CNx High or Low Time (input) 2 -- -- TSYSCLK -- Note 1: 2: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. This parameter is characterized, but not tested in manufacturing. (c) 2010 Microchip Technology Inc. DS61143G-page 165 PIC32MX3XX/4XX FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) CPU starts fetching code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) SY00 (TPU) (Note 1) CPU starts fetching code SY10 (TOST) External VDDCORE Provided Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VDDCORE VPOR (TSYSDLY) SY02 Power Up Sequence (Note 3) SY01 (TPWRT) (Note 1) CPU starts fetching code Note 1: The Power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2: Includes interval voltage regulator stabilization delay. 3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled DS61143G-page 166 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 29-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU starts fetching code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU starts fetching code TOST (SY10) TABLE 29-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions SY00 TPU Power-up Period Internal Voltage Regulator Enabled -- 400 600 s -40C to +85C SY01 TPWRT Power-up Period External VDDCORE Applied (Power-Up-Timer Active) 48 64 80 ms -40C to +85C SY02 TSYSDLY System Delay Period: Time required to reload Device Configuration Fuses plus SYSCLK delay before first instruction is fetched. -- 1 s + -- -- -40C to +85C TMCLR MCLR Pulse Width (low) -- 2 -- s -40C to +85C BOR Pulse Width (low) -- 1 -- s -40C to +85C SY20 SY30 Note 1: 2: TBOR 8 SYSCLK cycles These parameters are characterized, but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested. (c) 2010 Microchip Technology Inc. DS61143G-page 167 PIC32MX3XX/4XX FIGURE 29-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 29-1 for load conditions. TABLE 29-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. TA10 TA11 TA15 TTXH TTXL TTXP Characteristics(2) TxCK High Time TxCK Low Time Min. [(12.5 nsec or 1TPB)/N] + 25 nsec -- -- nsec Must also meet parameter TA15. Asynchronous, with prescaler 10 -- -- nsec Synchronous, with prescaler [(12.5 nsec or 1TPB)/N] + 25 nsec -- -- nsec Must also meet parameter TA15. Asynchronous, with prescaler 10 -- -- nsec -- [(Greater of 25 nsec or 2TPB)/N] + 30 nsec -- -- nsec VDD > 2.7V [(Greater of 25 nsec or 2TPB)/N] + 50 nsec -- -- nsec VDD < 2.7V 20 -- -- nsec VDD > 2.7V (Note 3) 50 -- -- nsec VDD < 2.7V (Note 3) -- 100 kHz -- 1 TPB -- TxCK Synchronous, Input Period with prescaler OS60 FT1 SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) 32 TA20 TCKEXT- Delay from External TxCK Clock Edge to Timer Increment -- Note 1: 2: 3: Conditions Synchronous, with prescaler Asynchronous, with prescaler MRL Typical Max. Units Timer1 is a Type A. This parameter is characterized, but not tested in manufacturing. N = prescale value (1, 8, 64, 256) DS61143G-page 168 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Max. Units Conditions Must also meet N = prescale value parameter (1, 2, 4, 8, 16, TB15. Must also meet 32, 64, 256) TB10 TTXH TxCK High Time Synchronous, with prescaler [(12.5 nsec or 1TPB)/N] + 25 nsec -- nsec TB11 TTXL TxCK Low Time Synchronous, with prescaler [(12.5 nsec or 1TPB)/N] + 25 nsec -- nsec TxCK Synchronous, [(Greater of 25 nsec or 2 Input Period with prescaler TPB)/N] + 30 nsec -- nsec VDD > 2.7V [(Greater of 25 nsec or 2 TPB)/N] + 50 nsec -- nsec VDD < 2.7V -- 1 TPB TB15 TB20 Note 1: TTXP TCKEXT- Delay from External TxCK MRL Clock Edge to Timer Increment parameter TB15. -- -- These parameters are characterized, but not tested in manufacturing. FIGURE 29-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 29-1 for load conditions. TABLE 29-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [(12.5 nsec or 1TPB)/N] + 25 nsec -- nsec Must also meet parameter IC15. IC11 TCCH ICx Input High Time [(12.5 nsec or 1TPB)/N] + 25 nsec -- nsec Must also meet parameter IC15. IC15 TCCP ICx Input Period [(25 nsec or 2TPB)/N] + 50 nsec -- nsec Note 1: These parameters are characterized, but not tested in manufacturing. (c) 2010 Microchip Technology Inc. N = prescale value (1, 4, 16) -- DS61143G-page 169 PIC32MX3XX/4XX FIGURE 29-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC10 OC11 Note: Refer to Figure 29-1 for load conditions. TABLE 29-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions OC10 TCCF OCx Output Fall Time -- -- -- nsec See parameter DO32. OC11 TCCR OCx Output Rise Time -- -- -- nsec See parameter DO31. Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx Note: Refer to Figure 29-1 for load conditions. TABLE 29-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristics(1) Min Typical(2) Max Units Conditions OC15 TFD Fault Input to PWM I/O Change -- -- 25 nsec -- OC20 TFLT Fault Input Pulse Width 50 -- -- nsec -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. DS61143G-page 170 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 29-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx MSb In LSb SP30 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 -- -- nsec -- SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 -- -- nsec -- SP20 TSCF SCKx Output Fall Time (Note 4) -- -- -- nsec See parameter DO32. SP21 TSCR SCKx Output Rise Time (Note 4) -- -- -- nsec See parameter DO31. SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- nsec See parameter DO32. SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- nsec See parameter DO31. SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 nsec VDD > 2.7V -- -- 20 nsec VDD < 2.7V SP40 TDIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 10 -- -- nsec -- SP41 TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 10 -- -- nsec -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. (c) 2010 Microchip Technology Inc. DS61143G-page 171 PIC32MX3XX/4XX FIGURE 29-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 Bit 14 - - - - - -1 MSb SDOX LSb SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85Cfor Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 -- -- nsec -- SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 -- -- nsec -- SP20 TSCF SCKx Output Fall Time (Note 4) -- -- -- nsec See parameter DO32. SP21 TSCR SCKx Output Rise Time (Note 4) -- -- -- nsec See parameter DO31. SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- nsec See parameter DO32. SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- nsec See parameter DO31. SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 nsec VDD > 2.7V -- -- 20 nsec VDD < 2.7V SP36 TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge 15 -- -- nsec -- SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 15 -- -- nsec VDD > 2.7V 20 -- -- nsec VDD < 2.7V Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS61143G-page 172 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85Cfor Industrial AC CHARACTERISTICS Param. No. SP41 Symbol TSCH2DIL, TSCL2DIL Note 1: 2: 3: 4: Characteristics(1) Hold Time of SDIx Data Input to SCKx Edge Min. Typical(2) Max. Units Conditions 15 -- -- nsec VDD > 2.7V 20 -- -- nsec VDD < 2.7V These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. FIGURE 29-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. (c) 2010 Microchip Technology Inc. DS61143G-page 173 PIC32MX3XX/4XX TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 -- -- nsec -- SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 -- -- nsec -- SP72 TSCF SCKx Input Fall Time -- -- -- nsec See parameter DO32. SP73 TSCR SCKx Input Rise Time -- -- -- nsec See parameter DO31. SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- nsec See parameter DO32. SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- nsec See parameter DO31. SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 nsec VDD > 2.7V -- -- 20 nsec VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 10 -- -- nsec -- SP41 TSCH2DIL, TSCL2DIL 10 -- -- nsec -- SP50 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL 175 -- -- nsec -- SP51 TSSH2DOZ SSx to SDOx Output High-Impedance (Note 3) 5 -- 25 nsec -- SP52 TSCH2SSH SSx after SCKx Edge TSCL2SSH TSCK + 20 -- -- nsec -- Note 1: 2: 3: 4: Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Assumes 50 pF load on all SPIx pins. DS61143G-page 174 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 29-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 -- -- nsec -- SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 -- -- nsec -- SP72 TSCF SCKx Input Fall Time -- 5 10 nsec -- SP73 TSCR SCKx Input Rise Time -- 5 10 nsec -- SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- nsec See parameter DO32. SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- nsec See parameter DO31. SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 20 nsec VDD > 2.7V -- -- 30 nsec VDD < 2.7V 10 -- -- nsec -- SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Assumes 50 pF load on all SPIx pins. (c) 2010 Microchip Technology Inc. DS61143G-page 175 PIC32MX3XX/4XX TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Characteristics(1) Symbol Hold Time of SDIx Data Input to SCKx Edge Min. Typical(2) Max. Units Conditions 10 -- -- nsec -- 175 -- -- nsec -- SP41 TSCH2DIL, TSCL2DIL SP50 TSSL2SCH, SSx to SCKx or SCKx TSSL2SCL Input SP51 TSSH2DOZ SSx to SDOX Output High-Impedance (Note 4) 5 -- 25 nsec -- SP52 TSCH2SSH SSx after SCKx Edge TSCL2SSH TSCK + 20 -- -- nsec -- SP60 TSSL2DOV SDOx Data Output Valid after SSx Edge -- -- 25 nsec -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 nsec. Assumes 50 pF load on all SPIx pins. FIGURE 29-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-1 for load conditions. FIGURE 29-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 29-1 for load conditions. DS61143G-page 176 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. IM10 IM11 IM20 Min.(1) Max. Units Conditions TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- 1 MHz mode (Note 2) TPB * (BRG + 2) -- s -- Clock High Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- 1 MHz mode (Note 2) TPB * (BRG + 2) -- s -- -- 300 nsec 20 + 0.1 CB 300 nsec -- 100 nsec -- 1000 nsec 20 + 0.1 CB 300 nsec -- 300 nsec 100 kHz mode 250 -- nsec 400 kHz mode 100 -- nsec 1 MHz mode (Note 2) 100 -- nsec THI:SCL TF:SCL Characteristics SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode (Note 2) IM21 TR:SCL SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode (Note 2) IM25 IM26 IM30 IM31 IM33 IM34 TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time Note 1: 2: 100 kHz mode 0 -- s 400 kHz mode 0 0.9 s 1 MHz mode (Note 2) 0 0.3 s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- nsec 400 kHz mode TPB * (BRG + 2) -- nsec 1 MHz mode (Note 2) TPB * (BRG + 2) -- nsec CB is specified to be from 10 to 400 pF. CB is specified to be from 10 to 400 pF. -- -- Only relevant for Repeated Start condition. After this period, the first clock pulse is generated. -- -- BRG is the value of the I2CTM Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). (c) 2010 Microchip Technology Inc. DS61143G-page 177 PIC32MX3XX/4XX TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. IM40 TAA:SCL IM45 Output Valid from Clock TBF:SDA Bus Free Time IM50 CB Note 1: 2: Min.(1) Max. Units Conditions 100 kHz mode -- 3500 nsec -- 400 kHz mode -- 1000 nsec -- 1 MHz mode (Note 2) -- 350 nsec -- Characteristics 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode (Note 2) 0.5 -- s The amount of time the bus must be free before a new transmission can start. -- 400 pF -- Bus Capacitive Loading 2CTM Baud Rate Generator. BRG is the value of the I Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). FIGURE 29-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-1 for load conditions. FIGURE 29-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 29-1 for load conditions. DS61143G-page 178 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. IS10 IS11 IS20 Symbol TLO:SCL THI:SCL TF:SCL Characteristics Clock Low Time Clock High Time SDAx and SCLx Fall Time Min. Max. Units 100 kHz mode 4.7 -- s PBCLK must operate at a minimum of 800 KHz. 400 kHz mode 1.3 -- s PBCLK must operate at a minimum of 3.2 MHz. 1 MHz mode (Note 1) 0.5 -- s 100 kHz mode 4.0 -- s PBCLK must operate at a minimum of 800 KHz. 400 kHz mode 0.6 -- s PBCLK must operate at a minimum of 3.2 MHz. 1 MHz mode (Note 1) 0.5 -- s 100 kHz mode -- 300 nsec 400 kHz mode 20 + 0.1 CB 300 nsec -- 100 nsec 100 kHz mode -- 1000 nsec 400 kHz mode 20 + 0.1 CB 300 nsec -- 300 nsec 100 kHz mode 250 -- nsec 400 kHz mode 100 -- nsec 1 MHz mode (Note 1) 100 -- nsec 100 kHz mode 0 -- nsec 400 kHz mode 0 0.9 s 1 MHz mode (Note 1) 0 0.3 s 100 kHz mode 4700 -- s 400 kHz mode 600 -- s 1 MHz mode (Note 1) 250 -- s 100 kHz mode 4000 -- s 400 kHz mode 600 -- s 1 MHz mode (Note 1) 250 -- s 100 kHz mode 4000 -- s 400 kHz mode 600 -- s 1 MHz mode (Note 1) 600 -- s 1 MHz mode (Note 1) IS21 TR:SCL SDAx and SCLx Rise Time 1 MHz mode (Note 1) IS25 IS26 IS30 IS31 IS33 Note 1: TSU:DAT THD:DAT TSU:STA THD:STA TSU:STO Data Input Setup Time Data Input Hold Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Conditions -- -- CB is specified to be from 10 to 400 pF. CB is specified to be from 10 to 400 pF. -- -- Only relevant for Repeated Start condition. After this period, the first clock pulse is generated. -- Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). (c) 2010 Microchip Technology Inc. DS61143G-page 179 PIC32MX3XX/4XX TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. IS34 IS40 Symbol THD:STO TAA:SCL Characteristics Stop Condition Hold Time Min. IS50 Note 1: TBF:SDA 4000 -- nsec 400 kHz mode 600 -- nsec 1 MHz mode (Note 1) 250 Output Valid from 100 kHz mode Clock 400 kHz mode CB Bus Free Time Units 100 kHz mode 3500 nsec 0 1000 nsec 0 350 nsec 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode (Note 1) 0.5 -- s -- 400 pF Bus Capacitive Loading Conditions -- nsec 0 1 MHz mode (Note 1) IS45 Max. -- The amount of time the bus must be free before a new transmission can start. -- Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). TABLE 29-34: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions Greater of VDD - 0.3 or 2.5 -- Lesser of VDD + 0.3 or 3.6 V VSS -- VSS + 0.3 V AVDD V (Note 1) Device Supply AD01 AD02 AVDD AVSS Module VDD Supply Module VSS Supply -- -- Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.0 -- 2.5 -- 3.6 V VREFH = AVDD (Note 3) AD06 VREFL Reference Voltage Low AVSS -- VREFH - 2.0 V (Note 1) AD07 VREF Absolute Reference Voltage (VREFH - VREFL) 2.0 -- AVDD V (Note 3) AD08 IREF Current Drain -- 250 -- 400 3 A A ADC operating ADC off VREFL -- VREFH V -- AD05a Analog Input AD12 Note 1: 2: 3: 4: VINH-VINL Full-Scale Input Span These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with 1 kHz sinewave. DS61143G-page 180 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-34: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. No. AD17 Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions VINL Absolute VINL Input Voltage AVSS - 0.3 -- AVDD/2 V -- VIN Absolute Input Voltage AVSS - 0.3 -- AVDD + 0.3 V -- Leakage Current -- 0.001 0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10K Recommended Impedance of Analog Voltage Source -- -- 5K (Note 1) RIN ADC Accuracy - Measurements with External VREF+/VREFAD20c Nr Resolution AD21c INL Integral Nonlinearity -- 10 data bits -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V bits -- AD22c DNL Differential Nonlinearity -- -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) AD23c GERR Gain Error -- -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD24n EOFF Offset Error -- -- <1 LSb VINL = AVSS = 0V, AVDD = 3.3V AD25c -- Monotonicity -- -- -- -- Guaranteed bits (Note 3) ADC Accuracy - Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Nonlinearity -- -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD22d DNL Differential Nonlinearity -- -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) AD23d GERR Gain Error -- -- <4 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD24d EOFF Offset Error -- -- <2 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD25d Monotonicity -- -- -- -- Guaranteed -- 10 data bits Dynamic Performance AD31b SINAD Signal to Noise and Distortion 55 58.5 -- dB (Notes 3,4) AD34b ENOB Effective Number of Bits 9.0 9.5 -- bits (Notes 3,4) Note 1: 2: 3: 4: These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with 1 kHz sinewave. (c) 2010 Microchip Technology Inc. DS61143G-page 181 PIC32MX3XX/4XX TABLE 29-35: 10-BIT CONVERSION RATE PARAMETERS PIC32MX 10-bit A/D Converter Conversion Rates (Note 2) ADC Speed 1 MIPS to 400 ksps (Note 1) TAD Sampling RS Max Minimum Time Min 65 ns 132 ns 500 VDD Temperature 3.0V to 3.6V -40C to +85C ADC Channels Configuration VREF- VREF+ CHX ANx Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V SHA ADC -40C to +85C VREF- VREF+ or or AVSS AVDD CHX ANx SHA ADC ANx or VREF- Up to 300 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V -40C to +85C VREF- VREF+ or or AVSS AVDD CHX ANx SHA ADC ANx or VREF- Note 1: 2: External VREF- and VREF+ pins must be used for correct operation. These parameters are characterized, but not tested in manufacturing. DS61143G-page 182 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-36: A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max. Units Conditions Clock Parameters AD50 TAD A/D Clock Period (Note 2) 65 -- -- nsec See Table 29-35. AD51 TRC A/D Internal RC Oscillator Period -- 250 -- nsec (Note 3) Conversion Rate AD55 TCONV Conversion Time -- 12 TAD -- -- -- AD56 FCNV Throughput Rate (Sampling Speed) -- -- 1000 KSPS AVDD = 3.0V to 3.6V -- -- 400 KSPS AVDD = 2.5V to 3.6V Sample Time 1 -- 31 TAD TSAMP must be 132 nsec. -- 1.0 TAD -- -- Auto-Convert Trigger (SSRC<2:0> = 111) not selected. AD57 TSAMP Timing Parameters AD60 TPCS Conversion Start from Sample Trigger(3) AD61 TPSS Sample Start from Setting Sample (SAMP) bit 0.5 TAD -- 1.5 TAD -- -- AD62 TCSS Conversion Completion to Sample Start (ASAM = 1) (Note 3) -- 0.5 TAD -- -- -- AD63 TDPU Time to Stabilize Analog Stage from A/D OFF to A/D ON (Note 3) -- -- 2 s -- Note 1: 2: 3: These parameters are characterized, but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested. (c) 2010 Microchip Technology Inc. DS61143G-page 183 PIC32MX3XX/4XX FIGURE 29-18: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in the "PIC32MX Family Reference Manual" (DS61132). 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion. DS61143G-page 184 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 29-19: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADxCON. ADON to start AD operation. 5 - Convert bit 0. 2 - Sampling starts after discharge period. TSAMP is described in the "PIC32MX Family Reference Manual" (DS61132). 6 - One TAD for end of conversion. 3 - Convert bit 9. 8 - Sample for time specified by SAMC<4:0>. 7 - Begin conversion of next channel. 4 - Convert bit 8. (c) 2010 Microchip Technology Inc. DS61143G-page 185 PIC32MX3XX/4XX FIGURE 29-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 29-37: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical Max. Units Conditions 20 -- -- nsec -- PS1 TdtV2wrH Data In Valid before WR or CS Inactive (setup time) PS2 TwrH2dtI WR or CS Inactive to Data - In Invalid (hold time) 40 -- -- nsec -- PS3 TrdL2dtV RD and CS Active to Data - Out Valid -- -- 60 nsec -- PS4 TrdH2dtI RD Active or CS Inactive to Data - Out Invalid 0 -- 10 nsec -- PS5 Tcs CS Active Time TPB + 40 -- -- nsec -- PS6 TWR WR Active Time TPB + 25 -- -- nsec -- PS7 TRD RD Active Time TPB + 25 -- -- nsec -- Note 1: These parameters are characterized, but not tested in manufacturing. DS61143G-page 186 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX FIGURE 29-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 29-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions PM1 TLAT PMALL/PMALH Pulse Width -- 1 TPB -- -- -- PM2 TADSU Address Out Valid to PMALL/PMALH Invalid (address setup time) -- 2 TPB -- -- -- PM3 TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) -- 1 TPB -- -- -- PM4 TAHOLD PMRD Inactive to Address Out Invalid (address hold time) 5 -- -- nsec -- PM5 TRD PMRD Pulse Width -- 1 TPB -- -- -- PM6 TDSU PMRD or PMENB Active to Data In Valid (data setup time) 15 -- -- nsec -- PM7 TDHOLD PMRD or PMENB Inactive to Data In Invalid (data hold time) -- 80 -- nsec -- Note 1: These parameters are characterized, but not tested in manufacturing. (c) 2010 Microchip Technology Inc. DS61143G-page 187 PIC32MX3XX/4XX FIGURE 29-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 29-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions PM11 TWR PMWR Pulse Width -- 1 TPB -- -- -- PM12 TDVSU Data Out Valid before PMWR or PMENB goes Inactive (data setup time) -- 2 TPB -- -- -- PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time) -- 1 TPB -- -- -- Note 1: These parameters are characterized, but not tested in manufacturing. DS61143G-page 188 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX TABLE 29-40: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ Max. Units Conditions 3.0 -- 3.6 V Voltage on bus must be in this range for proper USB operation. USB313 VUSB USB Voltage USB315 VILUSB Input Low Voltage for USB Buffer -- -- 0.8 V -- USB316 VIHUSB Input High Voltage for USB Buffer 2.0 -- -- V -- USB318 VDIFS Differential Input Sensitivity -- -- 0.2 V -- USB319 VCM Differential Common Mode Range 0.8 -- 2.5 V The difference between D+ and Dmust exceed this value while VCM is met. USB320 ZOUT Driver Output Impedance 28.0 -- 44.0 -- USB321 VOL Voltage Output Low 0.0 -- 0.3 V 1.5 k load connected to 3.6V. USB322 VOH Voltage Output High 2.8 -- 3.6 V 1.5 k load connected to ground. Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 29-23: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low Trf (c) 2010 Microchip Technology Inc. TTDOout TTDOzstate Defined Undefined DS61143G-page 189 PIC32MX3XX/4XX TABLE 29-41: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max. Units Conditions EJ1 TTCKCYC TCK Cycle Time 25 -- nsec -- EJ2 TTCKHIGH TCK High Time 10 -- nsec -- EJ3 TTCKLOW TCK Low Time 10 -- nsec -- EJ4 TTSETUP TAP Signals Setup Time Before Rising TCK 5 -- nsec -- EJ5 TTHOLD TAP Signals Hold Time After Rising TCK 3 -- nsec -- EJ6 TTDOOUT TDO Output Delay Time from Falling TCK -- 5 nsec -- EJ7 TTDOZSTATE TDO 3-State Delay Time from Falling TCK -- 5 nsec -- EJ8 TTRSTLOW TRST Low Time 25 -- nsec -- EJ9 TRF TAP Signals Rise/Fall Time, All Input and Output -- -- nsec -- Note 1: These parameters are characterized, but not tested in manufacturing. DS61143G-page 190 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX360F 512H-80I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: Example PIC32MX360F 256L-80I/PT e3 0510017 Example PIC32MX360F 512H-80I/MR e3 0510017 121-Lead XBGA (10x10x1.1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Example Example PIC32MX460F 512L-80I/BG e3 0510017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2010 Microchip Technology Inc. DS61143G-page 191 PIC32MX3XX/4XX 30.2 Package Details The following sections give the technical details of the packages. ' ( !" #$ % & 3& '!&" & 4 && 255***' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b 123 NOTE 1 NOTE 2 A c A2 A1 L L1 6&! ' !7'&! 8"') %7 7 #& 9 < & #! 8 89 : ; /1+ = = / / / = / 3&7 & 7 / ; / 3& & 7 # # 4 4 !! & #%% ' 77.. 8 .3 3& 9 ?#& . > 1+ /> 9 7 & 1+ # # 4 ?#& . 1+ # # 4 7 & 1+ > 7 #4 !! = 7 #?#& ) # %& > > > # %& 1&&' > > > ( !" # $% &" ' ()"&'"!&) & #*&& & # + '% ! & ! & ,!- ' ' !! #.#&"# '#% ! &"!!#% ! &"!!! & $ #/'' !# ' ! #& .0/ 1+2 1 !' ! & $ & " !**&"&& ! .32 % ' !("!" *&"&& (%%' & " ! ! * + @/1 DS61143G-page 192 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX ' ( !" #$ % & 3& '!&" & 4 && 255***' '5 (c) 2010 Microchip Technology Inc. # * !( 4 ! ! & 4 % & & # & DS61143G-page 193 PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143G-page 194 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2010 Microchip Technology Inc. DS61143G-page 195 PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143G-page 196 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX ' ( ## !" #$ % & 3& '!&" & 4 && 255***' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E E1 N b NOTE 1 1 23 NOTE 2 c A L A1 6&! ' !7'&! 8"') %7 7 #& 9 < & #! 77.. 8 8 89 : 1+ = = / / / = / 3&7 & 7 / ; / 3& & 7 # # 4 4 !! & #%% ' A2 L1 .3 3& 9 ?#& . > 1+ /> 9 7 & 1+ # # 4 ?#& . 1+ # # 4 7 & 1+ > 7 #4 !! = 7 #?#& ) @ # %& > > > # %& 1&&' > > > ( !" # $% &" ' ()"&'"!&) & #*&& & # + '% ! & ! & ,!- ' ' !! #.#&"# '#% ! &"!!#% ! &"!!! & $ ' ! #& .0/ 1+2 1 !' ! & $ & " !**&"&& ! .32 % ' !("!" *&"&& (%%' & " ! ! #/'' !# * + 1 (c) 2010 Microchip Technology Inc. DS61143G-page 197 PIC32MX3XX/4XX ' ( ## !" #$ % & 3& '!&" & 4 && 255***' '5 DS61143G-page 198 # * !( 4 ! ! & 4 % & & # & (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2010 Microchip Technology Inc. DS61143G-page 199 PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143G-page 200 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX APPENDIX A: REVISION HISTORY Revision F (June 2009) Revision E (July 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. * Updated the PIC32MX340F128H features in Table 1 to include 4 programmable DMA channels. Global changes include: * Changed all instances of OSCI to OSC1 and OSCO to OSC2 * Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE * Deleted registers in most sections, refer to the related section of the "PIC32MX Family Reference Manual" (DS61132). The other changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name "High-Performance, General Purpose and USB 32-bit Flash Microcontrollers" Update Description Added a "Packages" column to Table 1 and Table 2. Corrected all pin diagrams to update the following pin names. * Changed PGC1/EMUC1 to PGEC1 * Changed PGD1/EMUD1 to PGED1 * Changed PGC2/EMUC2 to PGEC2 * Changed PGD2/EMUD2 to PGED2 Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant. Added 64-Lead QFN package pin diagrams, one for General Purpose and one for USB. Section 1.0 "Device Overview" Reconstructed Figure 1-1 to include Timers, ADC and RTCC in the block diagram. Section 2.0 "Guidelines for Getting Started with 32-bit Microcontrollers" Added a new section to the data sheet that provides the following information: * Basic Connection Requirements * Capacitors * Master Clear Pin * ICSPTM Pins * External Oscillator Pins * Configuration of Analog and Digital Pins * Unused I/Os Section 4.0 "Memory Organization" Updated the memory maps, Figure 4-1 through Figure 4-6. Section 7.0 "Interrupt Controller" Removed the "Address" column from Table 7-1. Section 12.0 "I/O Ports" Added a second paragraph in Section 12.1.3 "Analog Inputs" to clarify that all pins that share ANx functions are analog by default, because the AD1PCFG register has a default value of 0x0000. (c) 2010 Microchip Technology Inc. All summary peripheral register maps were relocated to Section 4.0 "Memory Organization". DS61143G-page 201 PIC32MX3XX/4XX TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 26.0 "Special Features" Modified bit names and locations in Register 26-5 "DEVID: Device and Revision ID Register". Replaced "TSTARTUP" with "TPU", and "64-ms nominal delay" with "TPWRT", in Section 26.3.1 "On-Chip Regulator and POR". The information that appeared in the Watchdog Timer and the Programming and Diagnostics sections of 61143E version of this data sheet has been incorporated into the Special Features section: * Section 26.2 "Watchdog Timer (WDT)" * Section 26.4 "Programming and Diagnostics" Section 29.0 "Electrical Characteristics" Added the 64-Lead QFN package to Table 29-3. Updated data in Table 29-5. Updated data in Table 29-7. Updated data in Table 29-4, Table 29-5, Table 29-7 and Table 29-8. Updated data in Table 29-10. Added OS42 parameter to Table 29-17. Replaced Table 29-23. Replaced Table 29-24. Replaced Table 29-25. Updated Table 29-36. Section 30.0 "Packaging Information" Added 64-Lead QFN package marking information to Section 30.1 "Package Marking Information". Added the 64-Lead QFN (MR) package drawing and land pattern to Section 30.2 "Package Details". "Product Identification System" Added the MR package designator for the 64-Lead (9x9x0.9) QFN. DS61143G-page 202 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Revision G (April 2010) The revision includes the following global update: * Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. TABLE A-2: This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table. MAJOR SECTION UPDATES Section Name Update Description "High-Performance, General Purpose Updated the crystal oscillator range to 3 MHz to 25 MHz (see Peripheral and USB 32-bit Flash Features:) Microcontrollers" Added the 121-pin Ball Grid Array (XBGA) pin diagram. Updated Table 1: "PIC32MX General Purpose - Features" and Table 2: "PIC32MX USB - Features" Added the following tables: - Table 3: "Pin Names: PIC32MX320F128L, PIC32MX340F128L, and PIC32MX360F128L, and PIC32MX360F512L Devices", - Table 4: "Pin Names: PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices" Updated the following pins as 5V tolerant: - 64-pin QFN (USB): Pin 34 (VBUS), Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 64-pin TQFP (USB): Pin 34 (Vbus), Pin 36 (D-/RG3), Pin 37 (D+/RG2) and Pin 42 (IC1/RTCC/INT1/RD8) - 100-pin TQFP (USB): Pin 54 (VBUS), Pin 56 (D-/RG3) and Pin 57 (D+/RG2) Section 1.0 "Device Overview" Updated the Pinout I/O Descriptions table to include the device pin numbers (see Table 1-1) Section 2.0 "Guidelines for Getting Started with 32-bit Microcontrollers" Updated the Ohm value for the low-ESR capacitor from less than 5 to less than 1 (see Section 2.3.1 "Internal Regulator Mode"). Labeled the capacitor on the VCAP/VDDCORE pin as CEFC in Figure 2-1. Changed 10 F capacitor to CEFC capacitor in Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)". Section 4.0 "Memory Organization" Updated all register map tables to include the "All Resets" column. Separated the PORT register maps into individual tables (see Table 4-21 through Table 4-34). In addition, formatting changes were made to improve readability. Section 12.0 "I/O Ports" Updated the second paragraph of Section 12.1.2 "Digital Inputs" and removed Table 12-1. Section 22.0 "10-bit Analog-to-Digital Converter (ADC)" Updated the ADC Conversion Clock Period Block Diagram (see Figure 222). Section 26.0 "Special Features" Extensive updates were made to Section 26.2 "Watchdog Timer (WDT)" and Section 26.3 "On-Chip Voltage Regulator". (c) 2010 Microchip Technology Inc. DS61143G-page 203 PIC32MX3XX/4XX TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 29.0 "Electrical Characteristics" Update Description Updated the Absolute Maximum Ratings and added Note 3. Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table 29-3). Updated the conditions for parameters DC20, DC21, DC22 and DC23 in Table 29-5. Updated the comments for parameter D321 (CEFC) in Table 29-14. Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics, changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure 29-13). Section 30.0 "Packaging Information" Added the 121-pin XBGA package marking information and package details. "Product Identification System" Added the definition for BG (121-lead 10x10x1.1 mm, XBGA). Added the definition for Speed. DS61143G-page 204 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX INDEX A M AC Characteristics ............................................................ 162 Internal RC Accuracy ................................................ 164 AC Electrical Specifications Parallel Master Port Read Requirements ................. 187 Parallel Master Port Write Requirements.................. 188 Parallel Slave Port Requirements ............................. 186 Assembler MPASM Assembler................................................... 150 MPLAB ASM30 Assembler, Linker, Librarian ................... 150 MPLAB ICD 3 In-Circuit Debugger System ...................... 151 MPLAB Integrated Development Environment Software.. 149 MPLAB PM3 Device Programmer .................................... 152 MPLAB REAL ICE In-Circuit Emulator System ................ 151 MPLINK Object Linker/MPLIB Object Librarian ................ 150 B Block Diagrams A/D Module ............................................................... 123 Comparator I/O Operating Modes............................. 125 Comparator Voltage Reference ................................ 127 Connections for On-Chip Voltage Regulator............. 139 Input Capture ............................................................ 107 JTAG Compliant Application Showing Daisy-Chaining of Components ........................ 140 Output Compare Module........................................... 109 Reset System.............................................................. 87 RTCC ........................................................................ 121 Type B Timer ................................................ 35, 95, 105 UART ........................................................................ 115 WDT.......................................................................... 138 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 139 C C Compilers Hi-Tech C.................................................................. 150 MPLAB C .................................................................. 150 Comparator Operation .................................................................. 126 Comparator Voltage Reference Configuring................................................................ 128 CPU Module.................................................................. 31, 35 D DC Characteristics ............................................................ 154 I/O Pin Input Specifications....................................... 158 I/O Pin Output Specifications .................................... 159 Idle Current (IIDLE) .................................................... 156 Operating Current (IDD)............................................. 155 Power-Down Current (IPD) ........................................ 157 Program Memory ...................................................... 159 Temperature and Voltage Specifications .................. 154 Demonstration/Development Boards, Evaluation Kits, and Starter Kits ......................................................... 152 Development Support ....................................................... 149 E Electrical Characteristics................................................... 153 AC ............................................................................. 162 Errata .................................................................................. 19 F Flash Program Memory ...................................................... 85 RTSP Operation.......................................................... 85 I I/O Ports .................................................................... 101, 115 Parallel I/O (PIO)....................................................... 102 (c) 2010 Microchip Technology Inc. P Packaging ......................................................................... 191 Details....................................................................... 192 Marking..................................................................... 191 PIC32 Family USB Interface Diagram .............................. 100 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express ........................................... 152 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express ........................................... 151 Pinout I/O Descriptions (table)............................................ 22 Power-on Reset (POR) and On-Chip Voltage Regulator ............................... 139 S Serial Peripheral Interface (SPI) ... 87, 97, 111, 119, 121, 130 Software Simulator (MPLAB SIM) .................................... 151 Special Features............................................................... 131 T Timer1 Module.............................................. 89, 95, 103, 105 Timing Diagrams 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) .................................. 184 I2Cx Bus Data (Master Mode) .................................. 176 I2Cx Bus Data (Slave Mode) .................................... 178 I2Cx Bus Start/Stop Bits (Master Mode)................... 176 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 178 Input Capture (CAPx) ............................................... 169 OC/PWM .................................................................. 170 Output Compare (OCx) ............................................ 170 Parallel Master Port Write................................. 187, 188 Parallel Slave Port .................................................... 186 SPIx Master Mode (CKE = 0) ................................... 171 SPIx Master Mode (CKE = 1) ................................... 172 SPIx Slave Mode (CKE = 0) ..................................... 173 SPIx Slave Mode (CKE = 1) ..................................... 175 Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 168 Transmission (8-bit or 9-bit Data) ............................. 116 UART Reception with Receive Overrun ................... 117 Timing Requirements CLKO and I/O ........................................................... 165 Timing Specifications I2Cx Bus Data Requirements (Master Mode)........... 176 I2Cx Bus Data Requirements (Slave Mode)............. 178 Output Compare Requirements................................ 170 Simple OC/PWM Mode Requirements ..................... 170 SPIx Master Mode (CKE = 0) Requirements............ 171 SPIx Master Mode (CKE = 1) Requirements............ 172 SPIx Slave Mode (CKE = 1) Requirements.............. 175 V VDDCORE/VCAP Pin ........................................................... 139 Voltage Reference Specifications..................................... 160 Voltage Regulator (On-Chip) ............................................ 139 DS61143G-page 205 PIC32MX3XX/4XX W Watchdog Timer Operation .................................................................. 138 WWW, On-Line Support...................................................... 19 DS61143G-page 206 (c) 2010 Microchip Technology Inc. PIC32MX3XX/4XX Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 3XX F 512 H T - 80 I / PT - XXX Examples: PIC32MX320F032H-40I/PT: General purpose PIC32MX, 32 KB program memory, 64-pin, Industrial temperature, TQFP package. Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed PIC32MX360F256L-80I/PT: General purpose PIC32MX, 256 KB program memory, 100-pin, Industrial temperature, TQFP package. Temperature Range Package Pattern Flash Memory Family Architecture MX = 32-bit RISC MCU core Product Groups 3XX = General purpose microcontroller family Flash Memory Family F = Flash program memory Program Memory Size 32 64 128 256 512 = 32K = 64K = 128K = 256K = 512K Speed 40 = 40 MHz 80 = 80 MHz Pin Count H L = 64-pin = 100-pin Temperature Range I = -40C to +85C (Industrial) Package PT PT MR BG = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) = 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample 4XX = USB (c) 2010 Microchip Technology Inc. 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