Januar y 2001
2001 Fairc hild S emi c onduc tor International FDC640P Rev E(W)
FDC640P
P-Channel 2.5V PowerTrench
Specified MOSFET
General Description
This P-Channel 2.5V specif ied MOSFET uses a rugged
gate version of Fairchild’s advanced PowerTrench
process. It has been optimized for power management
applications with a wide range of gate drive voltage
(2.5V – 12V).
Applications
Battery management
Load switch
Battery protection
Features
–4.5 A, –20 V RDS(ON) = 0.053 @ VGS = –4.5 V
RDS(ON) = 0.080 @ VGS = –2.5 V
Rugged gate rating (±12V)
Fast switching speed
High performanc e trenc h technology for extremely
low RDS(ON)
D
D
D
S
D
G
SuperSOT -6
TM
6
5
4
1
2
3
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain-Sourc e V oltage –20 V
VGSS Gate-Source Voltage ±12 V
IDDrain Current – Continuous (Note 1a) –4.5 A
– Pulsed –20
Maximum Power Dissipation (Note 1a) 1.6 WPD
(Note 1b) 0.8
TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Am bient (Note 1a) 78 °C/W
RθJC Thermal Resistance, Junction-to-Cas e (Note 1) 30 °C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
.640 FDC640P 7’’ 8mm 3000 units
FDC640P
FDC640P Rev E(W)
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS Drain–Source B reakdown Volt age VGS = 0 V, ID = –250 µA–20 V
BVDSS
TJ
Breakdown Voltage Temperature
Coefficient ID = –250 µA, Referenced to 25°C–14 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1 µA
IGSSF Gate–Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
IGSSR Gate–Body Leak age, Reverse VGS = –12 V, VDS = 0 V –100 nA
On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = –250 µA–0.6 –1.0 –1.5 V
VGS(th)
TJ
Gate Threshold Voltage
Temperature Coeffic i ent ID = –250 µA, Referenced to 25°C3mV/°C
RDS(on) Static Drain–S ource
On–Resistance VGS = –4.5 V, ID = –4.5 A
VGS = –2.5 V, ID = –3.6 A
VGS = –4.5 V, ID = –4.5A,TJ=125°C
0.039
0.062
0.053
0.053
0.080
0.077
ID(on) On–Stat e Drain Current VGS = –4.5 V, VDS = –5 V –20 A
gFS Forward Transconductance VDS = –5 V, ID = –4.5 A 16 S
Dynam ic Ch ara cteristics
Ciss Input Capacitance 890 pF
Coss Output Capacitance 244 pF
Crss Reverse Transfer Capaci t ance
VDS = –10 V, V GS = 0 V,
f = 1.0 MHz 123 pF
Switching Characteristics (Note 2)
td(on) Turn–On Delay Time 12 22 ns
trTurn–On Rise Time 9 18 ns
td(off) Turn–Of f Delay Time 24 38 ns
tfTurn–Off Fall Time
VDD = –10 V, ID = –1 A,
VGS = –4.5 V, RGEN = 6
13 23 ns
QgTotal Gate Charge 9 13 nC
Qgs Gate–Source Charge 2 nC
Qgd Gate–Drain Charge
VDS = –10 V, ID = –4.5 A,
VGS = –4.5 V
3nC
Drain–Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drai n–S ource Diode Forward Current –1.3 A
VSD Drain–Source Di ode Forward
Voltage VGS = 0 V, IS = –1.3 A (Note 2) –0.7 –1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the drain
pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a. 78°C/W when mounted on a 1in2 pad of 2oz copper on FR-4 board.
b. 156°C/W when mounted on a minimum pad.
2. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%
FDC640P
FDC640P Rev E(W)
Typical Characteristics
0
3
6
9
12
15
00.511.522.5
-VDS, DRAIN -S O URCE VO LTAGE (V)
-I
D
, DRAIN CURRENT (A)
-3.0V -2.5V
-2.0V
VGS = -4.5V
-3.5V
0.5
1
1.5
2
2.5
3
03691215
-ID, DRAIN CURRE NT (A)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
VGS = -2.0V
-3.5V
-3.0V -4.0V -4.5V
-2.5V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = -4.5 A
VGS = -4.5 V
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
1.522.533.544.55
-VGS, GATE TO SOURCE VOLTAGE (V)
R
DS(ON)
, ON-RESISTANCE (OHM)
ID = -2.25 A
TA = 125oC
TA = 25oC
Figure 3. On-Resistance Variation with
Temperature. Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
2
4
6
8
10
12
0.511.522.53
-VGS, GATE TO SOURCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A)
TA = -55oC
125oC
VDS = -5V 25oC
0.0001
0.001
0.01
0.1
1
10
0 0.2 0.4 0.6 0.8 1 1.2
-VSD, BODY DIO DE FORWARD V O LTAGE (V)
-I
S
, REVERSE DRAIN CURRENT (A
)
TA = 125oC
25oC
-55oC
VGS = 0V
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDC640P
FDC640P Rev E(W)
Typical Characteristics
0
1
2
3
4
5
024681012
Qg, GATE CHARGE (nC)
-V
GS
, GATE-SOURCE VOLTAGE (V)
ID = -4.5A VDS = -5V
-15V
-10V
0
200
400
600
800
1000
1200
0 5 10 15 20
-VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
CISS
CRSS
COSS
f = 1MHz
VGS = 0 V
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.1 1 10 100
-VDS, DRAIN-SOUR CE V O LTAGE (V)
-I
D
, DRAIN CURRENT (A)
DC
10s1s
100ms
100
µ
s
RDS(ON) LIMIT
VGS = -4.5V
SINGLE PULSE
RθJA = 156oC/W
TA = 25oC
10ms1ms
0
1
2
3
4
5
0.1 1 10 100 1000
t1, TIME (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJA = 156°C/W
TA = 25°C
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
r(t), NORMAL IZED EFF ECTIVE
TRANSIENT THERMAL RESISTANCE
RθJA(t) = r(t) + RθJA
RθJA = 156°C/W
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
P
(p
k
)
t1t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b
Transient thermal response will change depending on the circuit board design.
FDC640P
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN T O IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PA TENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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