1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R
RE
D
GND1
NC
VCC2
B
A
NC
GND2
DE
DW PACKAGE
(TOP VIEW)
VCC1
GND1 GND2
ISODEPV
ISO1176
functiondiagram
DE
6
D
5
R3
4
RE
ISODE
10
B
A
13
12
PV 7
GALVANICISOLATION
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
ISOLATED RS-485 PROFIBUS TRANSCEIVER
Check for Samples: ISO1176
1FEATURES • Low Bus Capacitance – 10 pF (MAX)
• 4000-VPEAK Isolation, 560-Vpeak VIORM • 50 kV/ms Typical Transient Immunity
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2), • Failsafe Receiver for Bus Open, Short, Idle
IEC 61010-1, IEC 60950-1 and CSA • 3.3-V Inputs are 5-V Tolerant
Approved APPLICATIONS
• Bus-Pin ESD Protection • Profibus
– 16 kV HBM Between Bus Pins and GND2 • Factory Automation
– 6 kV HBM Between Bus Pins and GND1 • Networked Sensors
• Meets or Exceeds the Requirements of • Motor/Motion Control
EN 50170 and TIA/EIA-485 • HVA and Building Automation Networks
• Signaling Rates up to 40 Mbps • Networked Security Stations
• Differential Output Exceeds 2.1 V (54 ΩLoad)
DESCRIPTION
The ISO1176 is an isolated differential line transceiver designed for use in PROFIBUS applications. The device
is ideal for long transmission lines since the ground loop is broken to provide for operation with a much larger
common mode voltage range. The symmetrical isolation barrier of each device is tested to provide 2500 Vrms of
isolation between the line transceiver and the logic level interface.
The galvanically isolated differential bus transceiver is an integrated circuit designed for bi-directional data
communication on multipoint bus-transmission lines. The transceiver combines a galvanically isolated differential
line driver and differential input line receiver. The driver has an active-high enable with isolated enable-state
output on the ISODE pin (pin 10) to facilitate direction control. The driver differential outputs and the receiver
differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer
minimum loading to the bus allowing up to 160 nodes.
The PV pin (pin 7) is provided as a full-chip enable option. All device outputs become high impedance when a
logic low is applied to the PV pin. For more information, see the function tables in the device information section.
Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can
cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and
duration. The ISO1176 can significantly reduce the risk of data corruption and damage to expensive control
circuits.
The device is characterized for operation over the ambient temperature range of –40°C to 85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
VALUE UNIT
VCC1,Supply voltage(2) –0.5 to 7 V
VCC2
VOVoltage at any bus I/O terminal –9 to 14 V
VIVoltage input at any D, DE or RE terminal –0.5 to 7 V
IOReceiver output current ±10 mA
Bus pins to GND1 ±6
Human Body JEDEC Standard 22, Test Method A114-C.01 Bus pins to GND2 ±16
Model kV
Electrostatic All pins ±4
ESD discharge Charged Device JEDEC Standard 22, Test Method C101 All pins ±1
Model
Machine model ANSI/ESDS5.2-1996 All pins ±200 V
TJMaximum junction temperature 170 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) All voltage values except differential I/O bus voltages are with respect to the referenced network ground terminal and are peak voltage
values.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
Logic side supply voltage, VCC1 (with respect to GND1) 3.15 5.5
VCC V
Bus side supply voltage, VCC2 (with respect to GND2) 4.75 5.25
VCM Voltage at either bus I/O terminal A, B –7 12 V
PV, RE 2 VCC1
VIH High-level input voltage V
D, DE 0.7 VCC1
PV, RE 0 0.8
VIL Low-level input voltage V
D, DE 0.3 VCC1
VID Differential input voltage A with respect to B –12 12 V
Driver –70 70
IOOutput current mA
Receiver –8 8
Input pulse width 10 ns
TJOperating junction temperature –40 150 °C
SUPPLY CURRENT
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DE at 0 V 4 6
3 V DE at VCC1, 2 Mbps 5 mA
DE at VCC1, 25 Mbps 6
ICC1 Logic side RMS supply current DE at 0 V 7 10
5.5 V DE at VCC1, 2 Mbps 8 mA
DE at VCC1, 25 Mbps 11
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ISO1176
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SLLS897D –MARCH 2008–REVISED MARCH 2010
SUPPLY CURRENT (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DE at 0 V 15 18
ICC2 Bus side RMS supply current 5.25 V DE at VCC1, 2 Mbps, 54 Ωload 70 mA
DE at VCC1, 25 Mbps, 54 Ωload 75
ISODE-PIN ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –8 mA VCC2 – 0.8 4.6
VOH High-level output voltage V
IOH = –20 mA VCC2 – 0.1 5
IOL = 8 mA 0.2 0.4
VOL Low-level output voltage V
IOL = 20 mA 0 0.1
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOD Open-circuit differential output voltage |VA– VB|, Figure 1 1.5 VCC2 V
See Figure 2 and Figure 6 2.1
Steady-state differential output voltage
|VOD(SS)| V
Common-mode loading with Vtest from –7
magnitude 2.1
V to 12 V, See Figure 3
Change in steady-state differential output
|ΔVOD(SS)| RL= 54 Ω, See Figure 4 andFigure 5 –0.2 0.2 V
voltage between logic states
VOC(SS) Steady-state common-mode output voltage 2 3
Change in steady-state common-mode output
ΔVOC(SS) RL= 54 Ω, See Figure 4 and Figure 5 –0.2 0.2 V
voltage
VOC(PP) Peak-to-peak common-mode output voltage 0.5
Differential output voltage over and under
VOD(RING) See Figure 6 and Figure 10 10% VOD(pp)
shoot
VI(HYS) Input voltage hysteresis See Figure 7 150 mV
D, DE at 0 V or VCC1 –10 10
IIInput current mA
PV(1) at 0 V or VCC1 120
IO(OFF) Output current with power off VCC ≤2.5 V See Receiver input
current
IOZ High impedance state output current DE at 0 V
IOS(P) Peak short-circuit output current VOS = –7 V to 12 V –250 250
DE at VCC, See VOS = 12 V, D at 135
Figure 8 and GND1 mA
IOS(SS) Steady-state short-circuit output current Figure 9 VOS = –7 V, D at –135
VCC1
COD Differential output capacitance See Receiver CIN
CMTI Common-mode transient immunity See Figure 20 25 kV/ms
(1) The PV pin has a 50 kΩpull-up resistor and leakage current depends on supply voltage.
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ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH, tpHL Propagation delay time 35 ns
VCC1 at 5 V
VCC2 at 5 V
tsk(p) Pulse skew (|tp HL – tpLH|) 2 5 ns
tpLH, tpHL Propagation delay time 40 ns
VCC1 at 3.3 V See Figure 10
VCC2 at 5 V
tsk(p) Pulse skew (|tp HL – tp LH|) 2 5 ns
trDifferential output signal rise time 2 3 7.5 ns
tfDifferential output signal fall time 2 3 7.5 ns
tpDE DE to ISODE prop delay See Figure 14 30 ns
tt(MLH), tt(MHL) Output transition skew See Figure 11 1 ns
tp(AZH), tp(BZH) Propagation delay time, high-impedance-to-active output 80 ns
tp(AZL), tp(BZL) CL= 50 pF,
tp(AHZ), tp(BHZ) RE at 0 V,
Propagation delay time, active-to- high-impedance output 80 ns
tp(ALZ), tp(BLZ) See Figure 12 and
Figure 13
|tp(AZL) – tp(BZH)|Enable skew time 0.55 1.5 ns
|tp(AZH) – tp(BZL)|
t(CFB) Time from application of short-circuit to current foldback See Figure 9 0.5 ms
t(TSD) Time from application of short-circuit to thermal shutdown TA= 25°C, See Figure 9 100 ms
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT(+) Positive-going differential input voltage threshold IO= –8 mA –80 –10 mV
SeeFigure 15
VIT(–) Negative-going differential input voltage threshold IO= 8 mA –200 –120 mV
Vhys Hysteresis voltage (VIT+ – VIT-) 40 mV
IOH = –8 mA VCC1 –0.4 3
VID = 200 mV,
VOH High-level output voltage V
See Figure 15 IO H = –20 mA VCC1 –0.1 3.3
VCC1 at 3.3 V and VCC2 at
5 V IO L = 8 mA 0.2 0.4
VID = –200 mV,
VOL Low-level output voltage V
See Figure 15 IOL = 20 mA 0 0.1
IOH = –8 mA VCC1 –0.8 4.6
VID = 200 mV,
VOH High-level output voltage V
See Figure 15 IO H = –20 mA VCC1 –0.1 5
VCC1 at 5 V and VCC2 at 5
VIO L = 8 mA 0.2 0.4
VID = –200 mV,
VOL Low-level output voltage V
See Figure 15 IOL = –20 mA 0 0.1
IA, IBVCC = 4.75 V or 5.25 V
VI= –7 V or 12 V,
Bus pin input current –160 200 mA
IA(OFF) Other input = 0 V VCC2 = 0 V
IB(OFF)
IIReceiver enable input current RE = 0 V –50 50 mA
IOZ High-impedance state output current RE = VCC1 –1 1 mA
RID Differential input resistance A, B 48 kΩ
Test input signal is a 1.5 MHz sine wave with
1 Vpp amplitude , CDis measured across
CID Differential input capacitance 7 10 pF
A and B
CMR Common mode rejection See Figure 19 4 V
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Product Folder Link(s) :ISO1176
I
VI
D
DE
A
B
VOB VOA
VOD
IOA
IOB
GND1
GND2
VCC1
0or
VCC1
GND1
GND2
II
VI
D
DE
A
B
VOB VOA
VOD
IOA
IOB
GND1
GND1 GND2
54 W
VCC1
0or
VCC1
GND2
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH, tpHL Propagation delay time 50
VCC1 at 5 V, VCC2 at 5 V ns
tsk(p) Pulse skew (|tp HL – tpLH|) 2 5
tpLH, tpHL Propagation delay time 55
VCC1 at 3.3 V, VCC2 at 5 V See Figure 16 ns
tsk(p) Pulse skew (|tp HL – tp LH|) 2 5
trOutput signal rise time 2 4 ns
tfOutput signal fall time 2 4
tpZH Propagation delay time, high-impedance-to-high-level output 13 25
DE at VCC1,ns
See Figure 17
tpHZ Propagation delay time, high-level-to-high-impedance output 13 25
tpZL Propagation delay time, high-impedance-to-low-level output 13 25
DE at VCC,ns
See Figure 18
tpLZ Propagation delay time, low-level-to-high-impedance output 13 25
PARAMETER MEASUREMENT INFORMATION
Figure 1. Open Circuit Voltage Test Circuit
Figure 2. VOD Test Circuit
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s) :ISO1176
375 W
60 W
+
V
OD
-
D
DE
GND2
A
B
0or3V
VCC2
375 W
-7V
to
12V
II
VI
D
DE
A
B
V
OB VOA
V
OD
IOA
IOB
GND1
GND1 GND2
VOC
RL
2
RL
2
VCC1
0or
VCC1
GND2
GeneratorPRR=500kHz,
50%dutycycle,t <6ns,
t <6ns,Z =50
r
t O Ω
II
VI
D
DE
A
B
VOB VOA
VOD
IOA
IOB
GND1
VOC
RL
2
RL
2VOC
BVB
VA
A
OC(p-p)
V
VOC(SS)
VCC1
GND1 GND2
GND2
Input
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Driver VOD with Common-mode Loading Test Circuit
Figure 4. Driver VOD and VOC Without Common-Mode Loading Test Circuit
Figure 5. Steady-State Output Voltage Test Circuit and Voltage Waveforms
6Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
0VDifferential
VOD(pp)
VDO(RING)
VDO(SS)
II
VI
D
DE
A
B
VOB VOA
VOD
IOA
IOB
GND1
54 W
VCC1
0or
VCC1
GND1
GND2
GND2
IOS
D
A
B
Vos
IOS
time
60
250
120
GND1
DE
GND2
GND2
0.5 W
t(CFB)
t(TSD)
OutputCurrent-mA
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. VOD(RING) Waveform and Definitions
Figure 7. Input Voltage Hysteresis Test Circuit
Figure 8. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0)
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s) :ISO1176
IOS
D
A
B
Vos
IOS
time
60
250
120
GND2GND1
DE
GND2 t(CFB)
t(TSD)
OutputCurrent-mA
VOD
50 W
D
A
B
DE
VI
Input
Generator
90%
GND1
VCC1
R =54
±1%
LWC =50pF
±20%
L
C IncludesFixtureand
InstrumentationCapacitance
L
GeneratorPRR=500kHz,50%Duty
Cycle,t <6ns,Z =50
r O W
VI
VOD
3V
1.5V 1.5V
tPLH tPHL
VOD(H)
VOD(L)
90%
0V 0V
10% 10%
trtf
50 W
D
A
B
DE
VI
Input
Generator
GND1 VOA VOB
50%
VO
A
B
VCC1
GND2
R =54
±1%
LWC =50pF
±20%
Ltt(MHL) tt(MLH)
50%
50% 50%
C IncludesFixtureand
InstrumentationCapacitance
L
GeneratorPRR=500kHz,50%Duty
Cycle,t <6ns,t <6ns,Z =50
r f O W
DE
A
B
50 %
50 %
0V
Signal
Generator 50 W
DE
B
A
D
GND 1 GND 2
VOA VOB
V =0V
IN
R =110
LW
C =50pF
L
R =110
LW
C =50pF
L
VCC2
t(AZL)
t(BZH)
1.5V
t(ALZ)
t(BHZ)
V +0.5V
OL
V -0.5V
O
GeneratorPRR=500kHz,50%Duty
Cycle,t <6ns,t <6ns,Z =50
r f O W
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. IOS(SS) Steady State Short Circuit Output Current Test Circuit
Figure 10. Driver Switching Test Circuit and Waveforms
Figure 11. Driver Output Transition Skew Test Circuit and Waveforms
Figure 12. Driver Enable/Disable Test, D at Logic Low Test Circuit and Waveforms
8Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
Signal
Generator
DE
B
A
D
VOA VOB
DE
A
B
50%
0V
50 W
GND1 GND2
R =110
LW
C =50pF
L
R =110
LW
C =50pF
L
VCC2
t(AZH)
t(BZL)
1.5V
V +0.5V
OL
V -0.5V
OH
V =3V
IN t(AHZ)
50%
t(BLZ)
GeneratorPRR=500kHz,50%Duty
Cycle,t <6ns,t <6ns,Z =50
r f O W
Signal
Generator 50 W
DE
D
GND1
ISODE
ISODE
DE 50%
VCC1 VCC2
V =V
IN CC1
GND2
C =15pF
±20%
L
50%
t DE_LH
Pt DE_HL
P
50%
50%
GeneratorPRR=500kHz,50%Duty
Cycle,t <6ns,t <6ns,Z =50
r f O W
VID
IO
VO
Input A
Output
50%
V
OH
V
OL
tf
tr
tpLH tpHL
10%
90%
1.5V
1.5V
0V
InputB
Signal
Generator 50 W
CL=15pF
R
A
B
VID
VO
IO
(IncludesProbeand
JigCapacitance)
PRR=100kHz,50%DutyCycle,
t <6ns,t <6ns,Z =50
r f O W
Signal
Generator 50 W
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 13. Driver Enable/Disable Test, D at Logic High Test Circuit and Waveforms
Figure 14. DE to ISODE Prop Delay Test Circuit and Waveforms
Figure 15. Receiver DC Parameter Definitions
Figure 16. Receiver Switching Test Circuit and Waveforms
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s) :ISO1176
1.5V
VO
GND
tpZH tpHZ
1.5V
3V
0V
1.5V
RE
R
Signal
Generator 50 W
CL=15pF
R
A
B
1kW
RE
PRR=100kHz,50%dutycycle,
t <6ns,t <6ns,Z =50
r f O W
(IncludesProbeand
JigCapacitance)
DE
D
54 W
0V
VCC
VCC
V -0.5V
OH
1.5V
OH
V
V
OL
tpZL tpLZ
1.5V
3V
0V
RE
R
1.5V
0V
Signal
Generator
R
A
B
RE
DE
D
54 W
50 W
1kW
PRR=100kHz,50%dutycycle,
t <6ns,t <6ns,Z =50
r f O W
CL=15pF
(IncludesProbeand
JigCapacitance)
VCC
VCC1
V +0.5V
OL
50 W
470nF
100nF
2.2kW
Scope
Scope
V
R
100nF
GND
A
B
R
D
RE
DE
V
f=1to50MHz
Ampl.=±5V
INPUT
V
=-2Vto7V
OFFSET
VCC
50 W
2.2kW
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 17. Receiver Enable Test Circuit and Waveforms, Data Output High
Figure 18. Receiver Enable Test Circuit and Waveforms, Data Output Low
Figure 19. Common-Mode Rejection Test Circuit
10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
D
R
DE
1kWRE
54 W
GND 1
VTEST
GND 2
(IncludesProbeand
JigCapacitance)
A
B
GND1
S1
2V C=0.1 F
±1%
mVCC1 VCC2
0.8V
V orV
OH OL
C =15pF
L
Success/FailCriterion:
StableV orV Outputs
OH OL
V orV
OH OL
C=0.1 F±1%m
ISO1176
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SLLS897D –MARCH 2008–REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 20. Common-Mode Transient Immunity Test Circuit
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0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 20 40 60 80
VCC =4.75V
VCC =5V
VCC =5.25V
VOD − DifferentialOutputV
oltage − V
IL− LoadCurrent − mA
100 Ω
50 Ω
TA=25 C
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20
SignallingRate-Mbps
I -SupplyCurrent-mA
CC
ICC1
ICC2
5VVCC1
3.3VVCC1
NoLoad
T =25°C
A
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
−40 −15 10 35 60 85
VCC =4.75V
VCC =5V
VCC =5.25V
DriverOutputT
ransitionSkew − ns
TA− Free-AirTemperature −°C
RL=54 Ω,
CL=50pF
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
−40 −15 10 35 60 85
VCC =4.75V
VCC =5.25V
VCC =5V
DriverRise,FallT
ime − ns
TA− Free-AirTemperature −°C
RL=54 Ω,
CL=50pF
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE RMS SUPPLY CURRENT
vs vs
LOAD CURRENT SIGNALING RATE
Figure 21. Figure 22.
DRIVER OUTPUT TRANSITION SKEW DRIVER RISE, FALL TIME
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 23. Figure 24.
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Product Folder Link(s) :ISO1176
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
−40 −15 10 35 60 85
VCC =4.75V
VCC =5.25V
TA− Free-AirTemperature −°C
DriverEnableSkew − ns
RL=110 Ω,
CL=50pF
VCC =5V
-99
-89
-79
-69
-59
-49
-39
-29
-19
-9
1
0 1 2 3 4 5
V -OutputVoltage-V
O
I -OutputCurrent-mA
O
15pFLoad
T =25°C
A
0
10
20
30
40
50
60
70
80
90
100
110
0 1 2 3 4 5
V -OutputVoltage-V
O
I -OutputCurrent-mA
O
15pFLoad
T =25°C
A
ISO1176
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SLLS897D –MARCH 2008–REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
DRIVER ENABLE SKEW HIGH-LEVEL OUTPUT VOLTAGE
vs vs
FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT
Figure 25. Figure 26.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
Figure 27.
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Product Folder Link(s) :ISO1176
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R
RE
D
GND1
NC
VCC2
B
A
NC
GND2
DE
DW PACKAGE
(TOP VIEW)
VCC1
GND1 GND2
ISODEPV
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
DEVICE INFORMATION
PACKAGE PIN FUNCTION DESCRIPTION
NAME PIN NO. FUNCTION
Vcc1 1 logic side power supply
GND1 2, 8 logic side ground, internally connected
R 3 receiver output
RE 4 receiver logic-low enable
DE 5 driver logic-high enable input
D 6 driver input
ISO1176 chip enable, logic high applied immediately after power-up for device operation.
PV 7 A logic low 3-states all outputs.
GND2 9, 15 bus side ground, internally connected
ISODE 10 bus-side driver enable output
nc 11, 14 not connected internally, may be left floating
A 12 non-inverting bus output
B 13 inverting bus output
Vcc2 16 bus side power supply
14 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
DRIVER FUNCTION TABLE
VCC1 VCC2 POWER INPUT ENABLE ENABLE OUTPUTS
VALID INPUT OUTPUT
(D) A B
(ISODE)
(PV) (DE)
(ISO1176)
PU PU H or open H H H H L
PU PU H or open L H H L H
PU PU H or open X L L Z Z
PU PU H or open X open L Z Z
PU PU H or open open H H H L
PD PU X X X L Z Z
PU PD X X X L Z Z
PD PD X X X L Z Z
X X L X X L Z Z
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
RECEIVER FUNCTION TABLE
VCC1 VCC2 POWER VALID DIFFERENTIAL INPUT ENABLE OUTPUT
(PV) (ISO1176) VID = (VA– VB) (RE) ®)
PU PU H or open –0.01 V ≤VID L H
PU PU H or open –0.2 V < VID < –0.01 V L ?
PU PU H or open VID ≤–0.2 V L L
PU PU H or open X H Z
PU PU H or open X open Z
PU PU H or open Open circuit L H
PU PU H or open Short Circuit L H
PU PU H or open Idle (terminated) bus L H
PD PU X X X Z
PU PD H or open X L H
PD PD X X X Z
X X L X X Z
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s) :ISO1176
500 W
D,REInput DEInput
PVInput
11 W
ISODEOutput
4W
3.3VROutput 5VROutput
VCC1 VCC1 VCC1
500 W
VCC1
1MW
1MW
VCC1
VCC2
5.5 W
5.5 W
11 W
VCC1
VCC1
VCC1
500 W
VCC1
6.4 W
VCC1
50kW
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
EQUIVALENT CIRCUIT SCHEMATICS
16 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
Input
BInput
90kW
Input
A Input
18kW
16V
VCC2
16V 18kW
16V
16V
18kW
18kW
VCC2
Output
A andBOutputs
VCC2
16V
16V
90kW
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A Failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
qJA = 212°C/W, VI= 5.5 V, TJ= 170°C,
ISSafety input, output, or supply current DW-16 128 mA
TA= 25°C
TSMaximum case temperature DW-16 150 °C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :ISO1176
0
25
50
75
100
125
150
0 50 100 150 200
T -CaseTemperature-°C
C
SafetyLimitingCurrent-mA
V at5.5V
CC1,2
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-K thermal resistance(1) 168
qJA Junction-to-air °C/W
High-K board(1) 96.1
qJB Junction-to-board thermal resistance 61 °C/W
qJC Junction-to-case thermal resistance 48 °C/W
VCC1 = VCC2 = 5.25 V, TJ= 150°C, CL= 15 pF,
PDDevice power dissipation 220 mW
Input a 20 MHz 50% duty cycle square wave
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
Figure 28. DW-16 qJC Thermal Derating Curve per IEC 60747-5-2
PACKAGE CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance) Shortest terminal to terminal distance 8.34 mm
through air
L(I02) Minimum external tracking (Creepage)(1) Shortest terminal to terminal distance 8.1 mm
across the package surface
CTI Tracking resistance (Comparative Tracking DIN IEC 60112 / VDE 0303 Part 1 ≥175 V
Index)
Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm
RIO Isolation resistance Input to output, VIO = 500 V, all pins on
each side of the barrier tied together >1012 Ω
creating a two-terminal device
CIO Barrier capacitance Input to output VI= 0.4 sin (4E6pt) 2 pF
CIInput capacitance to ground VI= 0.4 sin (4E6pt) 2 pF
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
18 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
REGULATORY INFORMATION
VDE CSA UL
Recognized under 1577
Certified according to IEC Approved under CSA Component Component Recognition
60747-5-2 Acceptance Notice Program(1)
File Number: 40014131 File Number: 1698195 File Number: E181974
(1) Production tested ≥3000 Vrms for 1 second in accordance with UL 1577.
IEC 60554-1 RATINGS TABLE
PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group IIIa
Rated mains voltage < 150 VRMS I-IV
Installation classification Rated mains voltage < 300 VRMS I-III
Rated mains voltage < 400 VRMS I-II
IEC 60747-5-2 INSULATION CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIORM Maximum working insulation voltage 560 V
Method b1, VPR = VIORM × 1.875, 100% Production
VPR Input to output test voltage 1050 V
test with t = 1 s, Partial discharge <5 pC
VIOTM Transient overvoltage t = 60 s 4000 V
RSInsulation resistance VIO = 500 V at TS>109Ω
Pollution degree 2
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s) :ISO1176
INISO
ISO
N2GND ZZ
Z
vv
+
=
VN
RIN
CIN
RISO
CISO
SystemGround (GND1)
BusReturn (GND2)
16V
A orB
49
9
INISO
ISO
N
2GND
10x610
10
RR
R
v
v
+
=
+
=
94.0
16
1
1
1
C
C
1
1
C
1
C
1
C
1
v
v
IN
ISO
INISO
ISO
N
2GND =
+
=
+
=
+
=
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
APPLICATION INFORMATION
Transient Voltages
Isolating of a circuit insulates it from other circuits and earth, so that noise voltage develops across the insulation
rather than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical
fast transients that occur after installation. The transient ratings of the ISO1176 standard are sufficient for all but
the most severe installations. However, some equipment manufacturers use ESD generators to test equipment
transient susceptibility. This practice can exceed insulation ratings. ESD generators simulate static discharges
that may occur during device or equipment handling with low-energy but high-voltage transients.
Figure 29 models the ISO1176 bus IO connected to a noise generator. CIN and RIN is the device, and any other
stray or added capacitance or resistance across the A or B pin to GND2. CISO and RISO is the capacitance and
resistance between GND1 and GND2 of the ISO1176, plus those of any other insulation (transformer, etc.). Stray
inductance is assumed to be negligible.
From this model, the voltage at the isolated bus return
is
(1)
and is always less than 16 V from VN. If the ISO1176
is tested as a stand-alone device,
• RIN=6x104Ω,
• CIN= 16 x 10–12 F,
• RISO= 109Ωand
• CISO= 10–12 F.
Notice from Figure 29 that the resistor ratio determines
the voltage ratio at low frequencies, and that the
inverse capacitance ratio determines the voltage ration
at high frequencies. In the stand-alone case and for
low frequencies,
(2) Figure 29. Device Model For Static Discharge
Testing
or essentially all of the noise appears across the
barrier.
At high frequencies,
(3)
and 94% of VNappears across the barrier. As long as
RISO is greater than RIN and CISO is less than CIN, most
of the transient noise appears across the isolation
barrier, as it should.
Using ESD generators to test equipment transient susceptibility, or considering product claims of ESD ratings
above the barrier transient ratings of an isolated interface is not recommended. ESD is best managed through
recessing or covering connector pins in a conductive connector shell, and by proper installer training.
20 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
EFFECTIVEPULSEWIDTH
REFRESHTIME
ACTIVEDRIVERSTATE
BUSDIFFERENTIAL VOLTAGE
ISO1176 RECEIVEROUTPUT
RECEIVERPOSITIVETHRESHOLD
RECEIVERNEGATIVETHRESHOLD
DISABLED
EFFECTIVEPULSEWIDTH
REFRESHTIME
ACTIVEDRIVERSTATE
BUSDIFFERENTIAL VOLTAGE
ISO1176 RECEIVEROUTPUT
RECEIVERPOSITIVETHRESHOLD
RECEIVERNEGATIVETHRESHOLD
ISO1176
www.ti.com
SLLS897D –MARCH 2008–REVISED MARCH 2010
ISO1176 “Sticky Bit” Issue (Under Certain Conditions)
Summary: In applications with sufficient differential noise on the bus, the output of the ISO1176 receiver may
“stick” at an incorrect state for up to 30 µs.
Description: The ISO1176 isolated Profibus (RS-485) transceiver is rated for signaling up to 40 Mbps on
twisted-pair bus lines. The receiver thresholds comply with RS-485 and Profibus specifications; an input
differential voltage VID = VA- VB> 200 mV causes a logic High on the R output, and VID < -200 mV causes a
logic Low on the R output. To assure a known receiver output when the bus is shorted or idle, the upper
threshold is set below zero, such that VID = 0 mV causes a logic High on the R output. The data sheet specifies a
typical upper threshold (VIT+) of -80 mV and a typical lower threshold (VIT-) of -120 mV.
At a signaling rate of 40 Mbps, each valid data bit has a duration of 25 ns. At typical Profibus signaling rates of
12 Mbps or lower, each valid data bit has a duration of 83 ns or more. The ISO1176 correctly sets the R output
for each of these valid data bits.
In applications with a high degree of differential noise on the bus lines, it is possible to get short periods when an
invalid bus voltage triggers a change in state of the internal receiver circuits. An issue with the digital isolation
channel in the ISO1176 may cause the invalid receiver state to “stick” rather than immediately transition back to
the correct state. The receiver output will always transition to the correct state, but may stick in the incorrect state
for up to 30 µs. This can cause a temporary loss of data.
Figure 30 shows two cases which could result in temporary loss of data.
Figure 30.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s) :ISO1176
ISO1176
SLLS897D –MARCH 2008–REVISED MARCH 2010
www.ti.com
REVISION HISTORY
Changes from Original (March 2008) to Revision A Page
• Added the Bus-Pin ESD Protection bullet and sub bullets to the Features List ................................................................... 1
• Added 3.3-V Inputs are 5-V Tolerant to the Features List .................................................................................................... 1
• Added Bus pins to GND1 and Bus pins to GND2 to the ESD information of the Abs Max Ratings table ........................... 2
• Added the APPLICATION INFORMATION section ............................................................................................................ 20
Changes from Revision A (May 2008) to Revision B Page
• Changed L(IO1), Minimum air gap (Clearance) in the PACKAGE CHARACTERISTICS table From: MIN = 7.7mm
To: 8.34mm. ........................................................................................................................................................................ 18
Changes from Revision B (June 2008) to Revision C Page
• Changed the text in the second paragraph of the DESCRIPTON From: whenever the driver is disabled or VCC2 = 0
To: allowing up to 160 nodes. ............................................................................................................................................... 1
Changes from Revision C (October 2008) to Revision D Page
• Added 560-Vpeak VIORM to the first Features List ................................................................................................................ 1
• Added UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2), to the Features List .......................................................................... 1
• Added Input pulse width MIN = 10 ns to the RECOMMENDED OPERATING CONDITIONS table .................................... 2
• Added the CSA column to the Regulatory Information table .............................................................................................. 19
• Changed the ISO1176 “Sticky Bit” Issue section ................................................................................................................ 21
22 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :ISO1176
PACKAGE OPTION ADDENDUM
www.ti.com 5-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO1176DW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ISO1176DWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ISO1176DWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ISO1176DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO1176DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO1176DWR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Aug-2012
Pack Materials-Page 2
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