TM TAS5132 www.ti.com SLES190 - DECEMBER 2006 STEREO DIGITAL AMPLIFIER POWER STAGE FEATURES * * * * * * * * * * * * * 2x20 W at 10% THD+N Into 8- BTL 2x25 W at 10% THD+N Into 6- BTL >100-dB SNR (A-Weighted) <0.1% THD+N at 1 W Thermally Enhanced Package: - DDV (44-pin HTSSOP) High-Efficiency Power Stage (>90%) With 140-m Output MOSFETs Power-On Reset for Protection on Power Up Without Any Power-Supply Sequencing Integrated Self-Protection Circuits Including Undervoltage, Overtemperature, Overload, Short Circuit PWM Activity Detector to detect stopped PWM inputs and protect the system Error Reporting EMI Compliant When Used With Recommended System Design Intelligent Gate Drive Pin Compatible With the TAS5142DDV A low-cost, high-fidelity audio system can be built using a TI chipset, comprising a modulator (e.g., TAS5086) and the TAS5132. This system only requires a simple passive LC demodulation filter to deliver high-quality, high-efficiency audio amplification with proven EMI compliance. This device requires two power supplies, at 12 V for GVDD and VDD, and at 18 V for PVDD. The TAS5132 does not require power-up sequencing due to internal power-on reset. The efficiency of this digital amplifier is greater than 90% into 8 , which enables the use of smaller power supplies and heatsinks. The TAS5132 has an innovative protection system integrated on chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and overtemperature protection. The TAS5132 has a new proprietary current-limiting circuit that reduces the possibility of device shutdown during high-level music transients. BTL OUTPUT POWER vs SUPPLY VOLTAGE 30 TC = 75C THD+N @ 10% 25 * * * * Televisions Mini/Micro Audio Systems DVD Receivers Home Theaters DESCRIPTION The TAS5132 is an integrated stereo digital amplifier power stage with an advanced protection system. The TAS5132 is capable of driving a 6- bridge-tied load (BTL) at up to 25 W per channel with low integrated noise at the output, low THD+N performance, and low idle power dissipation. PO - Output Power - W APPLICATIONS 20 6 15 10 8 5 0 0 5 10 15 20 PVDD - Supply Voltage - V G002 PurePath DigitalTM These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital, PowerPAD are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006, Texas Instruments Incorporated TAS5132 www.ti.com SLES190 - DECEMBER 2006 GENERAL INFORMATION Terminal Assignment The TAS5132 is available in a thermally enhanced package: * 44-pin HTSSOP PowerPADTM package (DDV) This package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink. DDV PACKAGE (TOP VIEW) GVDD_B OTW NC NC SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D NC NC VDD GVDD_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GVDD_A BST_A NC PVDD_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D PVDD_D NC BST_D GVDD_D P0016-02 2 Submit Documentation Feedback TAS5132 www.ti.com SLES190 - DECEMBER 2006 GENERAL INFORMATION (continued) MODE Selection Pins MODE PINS PWM INPUT M3 M2 M1 0 0 0 2N 0 0 1 Reserved 0 1 0 1N (1) 0 1 1 1N (1) 1N (1) 1 0 0 1 0 1 2N (1) (2) 1 1 0 1 1 1 (1) (1) OUTPUT CONFIGURATION PROTECTION SCHEME 2 channels BTL output BTL mode (2) AD modulation 2 channels BTL output BTL mode (2) AD modulation 1 channel PBTL output PBTL mode. Only PWM_A input is used. 4 channels SE output Protection works similarly to BTL mode (2). Only difference in SE mode is that OUT_X is Hi-Z instead of a pulldown through internal pulldown resistor. AD/BD modulation AD modulation AD/BD modulation 2 channels BTL output Protection system work similarly to BTL mode (2) (0, 0, 0); however the PWM input protection is disabled. Also, overcurrent detection will be more sensitive and will latch if an error occurs. Reserved The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific mode. An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels. Package Heat Dissipation Ratings (1) (1) (2) PARAMETER TAS5132DDV RJC (C/W)--2 BTL or 4 SE channels (8 transistors) 1.4 RJC (C/W)--1 BTL or 2 SE channel(s) (4 transistors) 2.6 RJC (C/W)--(1 transistor) 8.7 Pad area (2) 15 mm2 JC is junction-to-case, CH is case-to-heatsink. RCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The RCH with this condition is 2.5C/W for the DDV package. Submit Documentation Feedback 3 TAS5132 www.ti.com SLES190 - DECEMBER 2006 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VDD to AGND -0.3 V to 13.2 V GVDD_X to AGND -0.3 V to 13.2 V PVDD_X to GND_X (2) -0.3 V to 30 V OUT_X to GND_X (2) -0.3 V to 30 V BST_X to GND_X (2) -0.3 V to 43.2 V VREG to AGND -0.3 V to 4.2 V GND_X to GND -0.3 V to 0.3 V GND_X to AGND -0.3 V to 0.3 V GND to AGND -0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND -0.3 V to 4.2 V RESET_X, SD, OTW to AGND -0.3 V to 7 V Maximum continuous sink current (SD, OTW) 9 mA Maximum operating junction temperature range, TJ 0C to 150C Storage temperature range -40C to 125C Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260C Minimum pulse duration, low 50 ns (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. ORDERING INFORMATION TA PACKAGE DESCRIPTION 0C to 70C TAS5132DDV 44-pin HTSSOP For the most current specification and package information, see the TI Web site at www.ti.com. 4 Submit Documentation Feedback TAS5132 www.ti.com SLES190 - DECEMBER 2006 Terminal Functions TERMINAL NAME NO. FUNCTION (1) DESCRIPTION AGND 11 P Analog ground BST_A 43 P HS bootstrap supply (BST). External capacitor to OUT_A required. BST_B 34 P HS bootstrap supply (BST). External capacitor to OUT_B required. BST_C 33 P HS bootstrap supply (BST). External capacitor to OUT_C required. BST_D 24 P HS bootstrap supply (BST). External capacitor to OUT_D required. GND 10 P Ground GND_A 38 P Power ground for half-bridge A GND_B 37 P Power ground for half-bridge B GND_C 30 P Power ground for half-bridge C GND_D 29 P Power ground for half-bridge D GVDD_A 44 P Gate-drive voltage supply. Requires 0.1-F capacitor to GND. GVDD_B 1 P Gate-drive voltage supply. Requires 0.1-F capacitor to GND. GVDD_C 22 P Gate-drive voltage supply. Requires 0.1-F capacitor to GND. GVDD_D 23 P Gate-drive voltage supply. Requires 0.1-F capacitor to GND. M1 15 I Mode selection 1 M2 14 I Mode selection 2 M3 13 I Mode selection 3 NC 3, 4, 19, 20, 25, 42 - No connect. Pins may be grounded. OC_ADJ 9 O Analog overcurrent programming. Requires resistor to ground. OTW 2 O Overtemperature warning signal, open drain, active low OUT_A 39 O Output, half-bridge A OUT_B 36 O Output, half-bridge B OUT_C 31 O Output, half-bridge C OUT_D 28 O Output, half-bridge D PVDD_A 40, 41 P Power supply input for half-bridge A. Requires close decoupling of 0.1-F capacitor to GND_A. PVDD_B 35 P Power supply input for half-bridge B. Requires close decoupling of 0.1-F capacitor to GND_B. PVDD_C 32 P Power supply input for half-bridge C. Requires close decoupling of 0.1-F capacitor to GND_C. PVDD_D 26, 27 P Power supply input for half-bridge D. Requires close decoupling of 0.1-F capacitor to GND_D. PWM_A 6 I Input signal for half-bridge A PWM_B 8 I Input signal for half-bridge B PWM_C 16 I Input signal for half-bridge C PWM_D 18 I Input signal for half-bridge D RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active low RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active low SD 5 O Shutdown signal, open-drain, active-low VDD 21 P Power supply for digital voltage regulator. Requires 0.1-F capacitor in parallel with a 10-F capacitor to GND. VREG 12 P Digital regulator supply filter. Requires 0.1-F capacitor to AGND. (1) I = input, O = output, P = power Submit Documentation Feedback 5 TAS5132 www.ti.com SLES190 - DECEMBER 2006 SYSTEM BLOCK DIAGRAM OTW System Microcontroller SD TAS5508 OTW SD BST_A BST_B RESET_AB RESET_CD VALID PWM_A LeftChannel Output OUT_A Output H-Bridge 1 Input H-Bridge 1 PWM_B OUT_B Bootstrap Capacitors 2nd-Order L-C Output Filter for Each Half-Bridge 2-Channel H-Bridge BTL Mode OUT_C PWM_C 4 18 V PVDD System Power Supply GND 12 V 4 PVDD Power Supply Decoupling BST_D Bootstrap Capacitors 4 GVDD VDD VREG Power Supply Decoupling Hardwire OC Limit GND GVDD (12 V)/VDD (12 V) VAC 6 OC_ADJ AGND VDD M3 OUT_D 2nd-Order L-C Output Filter for Each Half-Bridge BST_C VREG M2 GND PVDD_A, B, C, D M1 GVDD_A, B, C, D Input H-Bridge 2 PWM_D Hardwire Mode Control Output H-Bridge 2 GND_A, B, C, D RightChannel Output B0047-01 Submit Documentation Feedback TAS5132 www.ti.com SLES190 - DECEMBER 2006 FUNCTIONAL BLOCK DIAGRAM VDD Undervoltage Protection OTW Internal Pullup Resistors to VREG SD M1 Protection and I/O Logic M2 M3 4 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D BTL/PBTL-Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv . Ctrl. Timing Gate Drive OUT_C BTL/PBTL-Configuration Pulldown Resistor GND_C GVDD_B BST_B PVDD_B PWM_B PWM Rcv . Ctrl. Timing Gate Drive OUT_B BTL/PBTL-Configuration Pulldown Resistor GND_B GVDD_A BST_A PVDD_A PWM_A PWM Rcv . Ctrl. Timing Gate Drive OUT_A BTL/PBTL-Configuration Pulldown Resistor GND_A B0034-02 Submit Documentation Feedback 7 TAS5132 www.ti.com SLES190 - DECEMBER 2006 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply DC supply voltage 0 18 19 V GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator input DC supply voltage 10.8 12 13.2 V RL (BTL) RL (SE) Output filter: L = 10 H, C = 470 nF. Output AD modulation, switching frequency > 350 kHz Load impedance RL (PBTL) LOutput (BTL) LOutput (SE) 6-8 3-4 3-4 10 Minimum output inductance under short-circuit condition Output-filter inductance H 10 LOutput (PBTL) 10 FPWM PWM frame rate TJ Junction temperature 192 384 0 432 kHz 125 C AUDIO SPECIFICATIONS (BTL) PVDD_X = 18 V, GVDD = VDD = 12 V, BTL mode, RL = 8 , ROC = 22 K, CBST = 33-nF, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75C (unless otherwise noted). Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER PO Power output per channel, DDV package MIN TYP 26 RL = 8 , 10% THD, clipped input signal 20 RL = 6 , 0 dBFS, unclipped input signal 20 RL = 8 , 0 dBFS, unclipped input signal 16 0 dBFS MAX UNIT W <0.1% THD+N Total harmonic distortion + noise Vn Output integrated noise A-weighted (1) A-weighted 94 105 dB 94 105 dB .6 W SNR Signal-to-noise ratio 1W DNR Dynamic range A-weighted, input level = -60 dBFS using TAS5086 modulator Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, 4 channels switching (2) (1) (2) 8 TEST CONDITIONS RL = 6 , 10% THD, clipped input signal SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback <0.06% 50 200 V TAS5132 www.ti.com SLES190 - DECEMBER 2006 AUDIO SPECIFICATIONS (Single-Ended Output) PVDD_X = 18 V, GVDD = VDD = 12 V, SE mode, RL = 3 , ROC = 22 K, CBST = 33-nF, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75C (unless otherwise noted). Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER PO TEST CONDITIONS Power output per channel, DDV package TYP RL = 3 , 10% THD, clipped input signal 12.5 RL = 4 , 10% THD, clipped input signal 10.0 RL = 3 , 0 dBFS, unclipped input signal 9.5 RL = 4 , 0 dBFS, unclipped input signal 7.5 0 dBFS, 4 .09 1 W, 4 .05 UNIT W THD+N Total harmonic distortion + noise Vn Output integrated noise A-weighted 18 V SNR Signal-to-noise ratio (1) A-weighted 100 dB DNR Dynamic range A-weighted, input level = -60 dBFS using TAS5086 modulator 100 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, 4 channels switching (2) .6 W (1) (2) % SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. AUDIO SPECIFICATIONS (PBTL) PVDD_X = 18 V, GVDD = VDD = 12 V, PBTL mode, RL = 3 , ROC = 22 K, CBST = 33-nF, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75C (unless otherwise noted). Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER PO TEST CONDITIONS Power output per channel, DDV package TYP RL = 3 , 10% THD, clipped input signal 50 RL = 4 , 10% THD, clipped input signal 40 RL = 3 , 0 dBFS, unclipped input signal 37 RL = 4 , 0 dBFS, unclipped input signal 30 0 dBFS, 3 .14 1 W, 3 .02 UNIT W THD+N Total harmonic distortion + noise Vn Output integrated noise A-weighted 30 V SNR Signal-to-noise ratio (1) A-weighted 105 dB DNR Dynamic range A-weighted, input level = -60 dBFS using TAS5086 modulator 105 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, 1 channel switching (2) .6 W (1) (2) % SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback 9 TAS5132 www.ti.com SLES190 - DECEMBER 2006 ELECTRICAL CHARACTERISTICS RL= 8 , FPWM = 384 kHz (unless otherwise noted). All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX 3 3.3 3.6 UNIT Internal Voltage Regulator and Current Consumption VREG Voltage regulator, only used as a reference node IVDD VDD supply current IGVDD_X Gate supply current per half-bridge IPVDD_X Half-bridge idle current VDD = 12 V Operating, 50% duty cycle V 6 9 Idle, reset mode 5.5 8 50% duty cycle 3.6 5.5 Reset mode 1.0 2.0 50% duty cycle, without output filter or load 9 15 mA Reset mode, no switching .1 .2 mA mA mA Output Stage MOSFETs RDSon,LS Drain-to-source resistance, LS TJ = 25C, includes metallization resistance, GVDD = 12 V 140 155 m RDSon,HS Drain-to-source resistance, HS TJ = 25C, includes metallization resistance, GVDD = 12 V 140 155 m I/O Protection Vuvp,G Undervoltage protection limit, GVDD_X, voltage rising 9.6 V Vuvp,G Undervoltage protection limit, GVDD_X, voltage falling 9.2 V BSTuvpF Puts device into RESET when BST voltage falls below limit 6.2 V BSTuvpR Brings device out of RESET when BST voltage rises above limit 6.6 V OTW (1) Overtemperature warning 125 C OTWHYST (1) Temperature drop needed below OTW temperature for OTW to be inactive after the OTW event 25 C OTE (1) Overtemperature error 155 C OTEOTWdifferential (1) OTE-OTW differential 30 C OTEHYST (1) A reset event must occur for SD to be released following an OTE event. 30 C OLPC Overload protection counter FPWM = 384 kHz 1.25 ms IOC Overcurrent limit protection Resistor--programmable, max. current, ROCP = 22 k IOCT Overcurrent response time ROCP OC programming resistor range Internal pulldown resistor at the output of each half-bridge Connected when RESET is active to provide bootstrap capacitor charge. Not used in SE mode PAD PWM Activity Detector, causes device reset when PWM input signal is stopped. PWM stopped and time measured for device to go into RESET (Output switching stopped) 10 5.0 150 Resistor tolerance = 5% for typical value; the minimum resistance should not be less than 20k. RPD (1) 4.0 Specified by design Submit Documentation Feedback 6.0 A ns k 20 10 22 3.0 k 25 S TAS5132 www.ti.com SLES190 - DECEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) RL= 8 , FPWM = 384 kHz (unless otherwise noted). All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Digital Specifications VIH High-level input voltage VIL Low-level input voltage Ilkg 2 PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD V 0.8 Static, High PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD Input leakage current V 100 A Static, Low PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD -10 10 OTW/Shutdown (SD) RINT_PU Internal pullup resistance, OTW to VREG, SD to VREG VOH High-level output voltage VOL Low-level output voltage Internal pullup resistor 20 26 32 3 3.3 3.6 External pullup of 4.7 k to 5 V 5.5 IO = 4 mA 0.25 0.5 k V V TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 30 TC = 75C THD+N @ 10% TC = 75C PVDD = 18 V One Channel 25 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % 10 1 6 0.1 20 6 15 10 8 5 8 0.01 0 0.1 1 0 10 PO - Output Power - W 5 10 15 20 PVDD - Supply Voltage - V G002 G001 Figure 1. Figure 2. Submit Documentation Feedback 11 TAS5132 www.ti.com SLES190 - DECEMBER 2006 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) UNCLIPPED OUTPUT POWER vs SUPPLY VOLTAGE SYSTEM EFFICIENCY vs OUTPUT POWER 100 25 TC = 75C 95 20 Efficiency - % PO - Output Power - W 90 15 6 10 8 85 6 80 75 70 5 8 65 TC = 25C 60 0 0 5 10 15 0 20 10 20 30 40 50 PO - Output Power - W PVDD - Supply Voltage - V G003 Figure 3. Figure 4. SYSTEM POWER LOSS vs OUTPUT POWER SYSTEM OUTPUT POWER vs CASE TEMPERATURE 60 G004 30 7 TC = 25C 6 25 6 PO - Output Power - W Power Loss - W 5 6 4 3 2 8 20 8 15 10 5 1 THD+N @ 10% 0 0 0 10 20 30 40 PO - Output Power - W 50 60 0 G005 Figure 5. 12 20 40 60 Figure 6. Submit Documentation Feedback 80 TC - Case Temperature - C 100 120 G006 TAS5132 www.ti.com SLES190 - DECEMBER 2006 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) Noise Amplitude - dBr NOISE AMPLITUDE vs FREQUENCY 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 TC = 75C 0 2 4 6 8 10 12 14 16 18 20 22 24 f - Frequency - kHz G007 Figure 7. TYPICAL CHARACTERISTICS, SE CONFIGURATION OUTPUT POWER vs SUPPLY VOLTAGE 15 10 TC = 75C Digital Gain = 3 dB TC = 75C THD+N @ 10% 12 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 1 3 0.1 9 3 6 3 4 4 0.01 0.01 0.1 1 PO - Output Power - W 0 10 0 G008 Figure 8. 5 10 15 20 PVDD - Supply Voltage - V G009 Figure 9. Submit Documentation Feedback 13 TAS5132 www.ti.com SLES190 - DECEMBER 2006 TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued) OUTPUT POWER vs CASE TEMPERATURE 15 12 PO - Output Power - W 3 9 4 6 3 THD+N @ 10% 0 0 20 40 60 80 100 120 TC - Case Temperature - C G010 Figure 10. TYPICAL CHARACTERISTICS, PBTL CONFIGURATION OUTPUT POWER vs SUPPLY VOLTAGE 60 10 TC = 75C Digital Gain = 3 dB TC = 75C THD+N @ 10% 50 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 1 3 0.1 40 3 30 20 4 10 0.01 4 0.1 1 10 PO - Output Power - W 60 0 0 G011 Figure 11. 14 5 10 20 G012 Figure 12. Submit Documentation Feedback 15 PVDD - Supply Voltage - V TAS5132 www.ti.com SLES190 - DECEMBER 2006 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION (continued) SYSTEM OUTPUT POWER vs CASE TEMPERATURE 60 THD+N @ 10% PO - Output Power - W 50 3 40 4 30 20 10 0 0 20 40 60 80 TC - Case Temperature - C 100 120 G013 Figure 13. Submit Documentation Feedback 15 TAS5132 www.ti.com SLES190 - DECEMBER 2006 PVDD 3.3 GVDD 10 mF 220 mF 25 V 10 nF 25 V 10 (A) 10 nF 25 V TAS5132DDV 100 nF(A) 1 2 Microcontroller GVDD_A 4 5 Shutdown BST_A NC NC NC PVDD_A SD 6 PWM1_P PWM_A 7 VALID RESET_AB 8 PWM1_M PWM_B 22 k 9 OC_ADJ PWM2_P 10 GND 11 PWM2_M AGND 12 100 nF TAS5508 VREG 13 1 10 mF 10 (A) 10 nF 25 V PVDD_B 35 BST_B 34 BST_C PVDD 33 nF 33 PWM_C GND_D RESET_CD OUT_D 33 nF 100 nF 25 V 100 nF 25 V 47 mF 25 V 10 nF 25 V 100 nF 25 V 3.3 470 nF 63 V 29 28 10 mH @ 6 A PVDD_D 100 nF 25 V 3.3 26 NC PVDD_D NC NC GVDD_C 47 mF 25 V 10 mH@ 6 A 30 27 22 3.3 OUT_B 36 GND_C VDD 100 nF 25 V GND_B 37 M1 21 100 nF 47 mF 25 V GND_A 38 M2 PWM_D GVDD 100 nF 25 V OUT_A 39 18 20 10 mH @ 6 A PVDD_A 40 OUT_C 31 16 470 nF 63 V 41 PVDD_C 32 15 19 3.3 10 mH @ 6 A 42 M3 14 17 33 nF 43 OTW 3 0 Optional 100 nF 25 V 44 GVDD_B BST_D GVDD_D 100 nF 25 V 25 10 nF 25 V 47 mF 25 V 24 23 PVDD 33 nF 100 nF(A) 3.3 10 nF 25 V 220 mF 25 V S0070-06 A. Optional component, GVDD_A and GVDD_B can potentially share the same decoupling components. Also, GVDD_C and GVDD_D can potentially share the same decoupling components. Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters 16 Submit Documentation Feedback TAS5132 www.ti.com SLES190 - DECEMBER 2006 PVDD 3.3 GVDD 10 mF 220 mF 25 V 10 nF 25 V 10 (A) 10 nF 25 V TAS5132DDV 100 nF(A) 1 2 Microcontroller GVDD_A 43 OTW 4 5 Shutdown NC NC NC PVDD_A SD 6 PWM1_P PWM_A 7 VALID RESET_AB 8 PWM_B 22 k 9 PWM2 OC_ADJ 10 GND 11 AGND 100 nF 12 VREG 13 TAS5508 17 GND_A 38 1 10 mF BST_B 34 BST_C 10 (A) 33 nF 33 PWM_C GND_D RESET_CD OUT_D 33 nF 100 nF 25 V 100 nF 25 V 47 mF 25 V 10 nF 25 V 100 nF 25 V 3.3 470 nF 63 V 29 28 10 mH@ 6 A PVDD_D 100 nF 25 V 3.3 26 NC PVDD_D NC NC GVDD_C 47 mF 25 V 10 mH@ 6 A 30 27 22 10 nF 25 V PVDD_B 35 GND_C VDD 100 nF 3.3 OUT_B 36 M1 21 GVDD 100 nF 25 V 47 mF 25 V GND_B 37 M2 PWM_D 20 100 nF 25 V OUT_A 39 18 19 10 mH @ 6 A PVDD_A 40 OUT_C 31 16 470 nF 63 V 41 PVDD_C 32 15 3.3 10 mH @ 6 A 42 M3 14 33 nF BST_A 3 0 Optional 100 nF 25 V 44 GVDD_B BST_D GVDD_D 100 nF 25 V 25 10 nF 25 V 47 mF 25 V 24 23 PVDD 33 nF 100 nF(A) 3.3 10 nF 25 V 220 mF 25 V S0070-07 A. Optional component, GVDD_A and GVDD_B can potentially share the same decoupling components. Also, GVDD_C and GVDD_D can potentially share the same decoupling components. Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters Submit Documentation Feedback 17 TAS5132 www.ti.com SLES190 - DECEMBER 2006 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5132 needs only a 12-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 192 kHz, the bootstrap capacitor might need to be increased in value. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF 18 ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5132 reference design. For additional information on recommended power supply and required components, see the application diagrams given previously in this data sheet. The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 18-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5132 is fully protected against erroneous power-stage turnon due to parasitic gate charging. SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The TAS5132 does not require a power-up sequence. The outputs of the H-bridges remain in a low-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is recommended to hold RESET_AB and RESET_CD in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. The output impedance is approximately 3K under this condition, unless mode 1, 0, 0 (Single-ended Mode), is used. This means that the TAS5132 should be held in reset for at least 200 S to ensure that the bootstrap capacitors are charged. This also assumes that the recommended 0.033-F bootstrap capacitors are used. Changes to bootstrap capacitor values will change the bootstrap capacitor charge time. When the TAS5132 is being used with TI PWM modulators such as the TAS5086, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended. Powering Down The TAS5132 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down, thus preventing audible artifacts, including pops or clicks. Submit Documentation Feedback TAS5132 www.ti.com SLES190 - DECEMBER 2006 When the TAS5132 is being used with TI PWM modulators such as the TAS5086, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended. ERROR REPORTING The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125C (see the following table). SD OTW DESCRIPTION 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) 0 1 Overload (OLP) or undervoltage (UVP) 1 0 Junction temperature higher than 125C (overtemperature warning) 1 1 Junction temperature lower than 125C and no OLP or UVP faults (normal operation) Note that asserting either RESET_AB or RESET_CD low forces the SD signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device, resulting in device shutdown (OTE). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). DEVICE PROTECTION SYSTEM The TAS5132 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5132 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload and overtemperature, the device automatically recovers when the fault condition has been removed. For highest possible reliability, recovering from an overload fault requires external reset of the device (see the Device Reset section of this data sheet) no sooner than 1 second after the shutdown. PWM inputs that will detect the condition when a PWM input is continuously high or low. This function is named PWM Activity Detector (PAD). Without this protection circuitry, if a PWM input is continuously high or low, the PVDD power supply voltage could appear on the associated output pin. This condition could damage either the output load (loudspeaker) or the device. If a PWM input remains either high or low for over 10 S, the device's outputs will be set into a Hi-Z state. If this error condition occurs, SD will not be asserted low. Use of TAS5132 Capable Systems in High-Modulation-Index This device requires at least 50 ns of low time on the output per 384-kHz PWM frame rate in order to keep the bootstrap capacitors charged. As an example, if the modulation index is set to 99.2% in the TAS5086, this setting allows PWM pulse durations down to 20 ns. This signal, which does not meet the 50-ns requirement, is sent to the PWM_X pin, and this low-state pulse time does not allow the bootstrap capacitor to stay charged. In this situation, the low voltage across the bootstrap capacitor can cause the bootstrap UVP circuitry to avtivate and shutdown the device. The TAS5132 device requires limiting the TAS5086 modulation index to 96.1% to keep the bootstrap capacitor charged under all signals and loads. Therefore, TI strongly recommends using a TI PWM processor, such as TAS5508 or TAS5086, with the modulation index set at 96.1% to interface with TAS5132. This is done by writing 0x04 to the Modulation Limit Register (0x10) in the TAS5086 or 0x04 to the Modulation Limit Register (0x16) in the TAS5508. Overcurrent (OC) Protection Limiting and Overload Detection With Current The device has independent, fast-reacting current detectors with on all high-side and low-side power-stage FETs. See the following table for OC-adjust resistor values. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, i.e., it performs a current-limiting function, rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. The TAS5132 contains circuitry associated with its Submit Documentation Feedback 19 TAS5132 www.ti.com SLES190 - DECEMBER 2006 Current limiting and overload protection are independent for half-bridges A and B and, respectively, C and D. That is, if the bridge-tied load between half-bridges A and B causes an overload fault, only half-bridges A and B are shut down. OC-Adjust Resistor Values (k) Max. Current Before OC Occurs (A) 22 5.2 27 4.6 30 4.2 33 3.8 DEVICE RESET 42 3.2 47 2.9 56 2.5 69.8 2.0 Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high-impedance state. Thus, both reset pins are well suited for hard-muting the power stage if needed. Overtemperature Protection The TAS5132 has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125C (nominal) and, if the device junction temperature exceeds 155C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, both RESET_AB and RESET_CD must be asserted. Thereafter, the device resumes normal operation. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5132 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures 20 that all circuits are fully operational when the GVDD_X and VDD supply voltages reach 9.6 V (typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold. In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs. In the SE mode, the weak pulldowns are not enabled, and it is therefore recommended to ensure bootstrap capacitor charging by providing a low pulse on the PWM inputs when reset is asserted high. Asserting either reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high. A rising-edge transition on either reset input allows the device to resume operation after an overload fault. Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TAS5132DDV ACTIVE HTSSOP DDV 44 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5132DDVG4 ACTIVE HTSSOP DDV 44 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5132DDVR ACTIVE HTSSOP DDV 44 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5132DDVRG4 ACTIVE HTSSOP DDV 44 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5132DDVR Package Package Pins Type Drawing SPQ HTSSOP 2000 DDV 44 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5132DDVR HTSSOP DDV 44 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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