ANALOG DEVICES FEATURES Single Chip Construction Double-Buffered Latch for 8-Bit uP-Compatibility Fast Settling Time: 500ns max to +1/2LSB High Stability Buried Zener Reference on Chip Monotonicity Guaranteed Over Temperature Linearity Guaranteed Over Temperature: 1/2LSB max (AD567K) Guaranteed for Operation with +12V or +15V Supplies Low Power: 300mW Including Reference TTL/SV CMOS Compatible Logic Inputs Low Cost PRODUCT DESCRIPTION The AD567 is a complete high speed 12-bit digital-to-analog converter including a high stability buried zener voltage reference and double-buffered input latch on a single chip. The converter uses 12 precision high speed bipolar current steering switches and a laser trimmed thin film resistor network to provide fast settling time and high accuracy. Microprocessor compatibility is achieved by the on-chip double-buffered latch. The design of the input latch allows direct interface to 4-, 8-, 12-, or 16-bit buses. The 12 bits of data from the first rank of latches can then be transferred to the second rank, avoiding generation of spurious analog out- put values. The latch responds to strobe pulses as short as 100ns, allowing use with the fastest available microprocessors. The functional completeness and high performance in the AD567 results from a combination of advanced switch design, high speed bipolar manufacturing process, and the proven laser wafer-trimming (LWT) technology. The AD567 is trimmed at the wafer level and is specified to +1/4LSB maximum linearity error (K grade) at 25C and +1/2LSB over the full opera- ting temperature range. The subsurface (buried) Zener diode on the chip provides a low-noise voltage reference which has long-term stability and temperature drift characteristics comparable to the best dis- crete reference diodes. The laser trimming process which pro- vides the excellent linearity is also used to trim both the abso- lute value of the reference as well as its temperature coefficient. The AD567 is thus well suited for wide temperature range performance with +1/2LSB maximum linearity error and guaranteed monotonicity over the full temperature range. Typical full scale gain T.C. is 10ppm/C. The AD567 is available in three performance grades. The AD567J and K are specified for use over the 0 to +70C tem- perature range and are available in either a 28-pin hermetically- *Covered by patent numbers: 3,803,590; 3,890,611; 3,932,863; 3,978,473; 4,020,486; and other patents pending. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implica- tion or otherwise under any patent or patent rights of Analog Devices. Microprocessor-Compatible 12-Bit D/A Converter AD367 sealed, ceramic DIP or a 28-pin molded plastic DIP (N package). The AD567S grade is specified for the -55C to +125C range and is available in the ceramic package. PRODUCT HIGHLIGHTS 1, The AD567 is a complete current output DAC with volt- age reference and digital latches on a single IC chip. 2. The double-buffered latch structure permits direct inter- face to 4-, 8-, 12-, or 16-bit data buses. All logic inputs are TTL or 5 volt CMOS compatible. 3. The internal buried zener reference is laser-trimmed to 10.00 volts with a 1% maximum error. The reference volt- age is also available for external application. 4. The chip also contains SiCr thin film application resistors which can be used either with an external op amp to pro- vide a precision voltage output or as input resistors for an A/D converter. The resistors are matched to the internal ladder network to guarantee a low gain temperature coef- ficient and are laser-trimmed for minimum full scale and bipolar offset errors. 5. The precision high speed current switch design* provides high de accuracy and an optimally-damped settling charac- teristic. Output current settling time is 500 nanoseconds maximum to +1/2LSB. 6. The single-chip construction makes the AD567 inherently more reliable than multichip hybrid designs. The AD567S grade with guaranteed linearity and monotonicity over the -55C to +125C range is especially recommended for high reliability needs in harsh environments. The unit is available processed to MIL-STD-883, Level B. Route 1 Industrial Park: P.O. Box 280; Norwood, Mass. 02062 Tel: 617/329-4700 TWX: 710/394-6577 West Coast Texas 714/842-1717 214/231-5094 Mid-West 312/653-5000SPECIFICATIONS (Ta =+25C, Veg =+12V or +15V, VEE = -12V or -15V, unless otherwise specified) MIN DATA INPUTS! (Pins 10-15 and 17-28) TTL or 5 Volt CMOS Input Voltage Bit ON Logic 1 Bit OFF Logic 0 Logic Current (each bit) Bit ON Logic 1 Bit OFF Logic 0 +2.0 -RESOLUTION OUTPUT Current Unipolar (all bits on) -1.6 Bipolar (all bits on or off) +0.8 Resistance (exclusive of span resistors) 6k Offset Unipolar Bipolar (Figure 3, Rz = 50Q fixed) Capacitance Compliance Voltage Tmin to Tmax -1.5 ACCURACY (error relative to full scale) +25C Tmin to Tmax DIFFERENTIAL NONLINEARITY +25C Tmin to Tmax TEMPERATURE COEFFICIENTS With Internal Reference Unipolar Zero Bipolar Zero Gain (Full Scale) Differential Nonlinearity TEMPERATURE RANGE Operating 0 Storage =~65 POWER REQUIREMENTS Vec, +11.4 to +16.5V de VEE> -11.4 to -16.5V de POWER SUPPLY GAIN SENSITIVITY? Vcc = +11.4 to +16.5V de VEE = -11.4 to -16.5V de PROGRAMMABLE OUTPUT RANGE (see Figures 1, 2, 3) EXTERNAL ADJUSTMENTS Gain Error with Fixed 50Q Resistor for R2 (Figure 2) Bipolar Zero Error with Fixed 50Q Resistor for R1 (Figure 3) Gain Adjustment Range (Figure 2) +0.25 Bipolar Zero Adjustment Range 0.15 REFERENCE INPUT _ Input Impedance 15k REFERENCE OUTPUT Voltage 9.90 Current (available for external loads) 0.1 POWER DISSIPATION PRICE (100+) NOTES ADS567) rye +120 +35 2.0 #1,.0. 8k 0.01 0.05 25 +1/4 (0.006) 1/2 (0.012) 21/2 -17 a) Oto +5 -2.5 to +2.5 0 to +10 -5 to +5 -10 to +10 +0.1 0.05 20k 10.00 1.0 300 AD567JN ADS67JD ' The digital input specifications are guaranteed but not tested over the operating temperature range. 2 The power supply gain sensitivity is tested in reference to a Vcc, VEE | of 15V de +10%. Specifications subject to change without notice. MAX 45.5 +0.8 +300 +100 2 al $1.2 10k 0.05 0.15 +10 1/2 (0.012) +3/4 (0.018) 43/4 MONOTONICITY GUARANTEED 10 50 +70 +150 -25 10 25 +0.25 0.15 25k 10.10 495 $12.95 $14.95 MIN +2.0 =1.6 +0.8 6k AD567K TYP +120 +35 -2.0 2:10 8k 0.01 0.05 25 +1/8 (0.003) +1/4 (0.006) 41/4 MAX 559 +0.8 +300 +100 12_ ; -2.4 Hid 10k 0.05 0.1 +10 41/4 (0.006) +1/2 (0.012) 41/2 MONOTONICITY GUARANTEED -65 EQu25 0.15, 15k 9.90 0.1 Oto +5 -2.5 to +2.5 Oto +10 - to+5 0.05 20k 10.00 1.0 300 ADS67KN ADS67KD 10 20 +70 +150 -25 10 25 +0.25 +0.1 25k 10.10 495 $17.95 $22.95 UA BA Bits mA mA Q % of F.S. % of F.S. pk \V LSB % of FS. LSB % of F.S. LSB ppm/C ppm/?c ppm/C ppm/?c C 8 &G mA mA ppm of F.S./% ppm of F.S./% 4<4<= << % of F.S. % of F.S. % ot FS, % of F.S. Q Vv mA mWMODEL DATA INPUTS! (Pins 10-15 and 17-28) ~ TTL or 5 Volt CMOS Input Voltage Bit ON Logic 1 Bit OFF Logic 0 Logic Current (each bit) Bit ON Logic 1 Bit OFF Logic 0 RESOLUTION OUTPUT Current Unipolar (all bits on) Bipolar (all bits on or off) Resistance (exclusive of span resistors) Offset Unipolar Bipolar (Figure 3, Rz = 5022 fixed) Capacitance Compliance Voltage Tmin to Tmax ACCURACY (error relative to full scale) +25C Tmin to Tnvax: DIFFERENTIAL NONLINEARITY 425C Tint Emax TEMPERATURE COEFFICIENTS With Internal Reference Unipolar Zero Bipolar Zero Gain (Full Scale) Differential Nonlinearity TEMPERATURE RANGE Operating Storage POWER REQUIREMENTS Vcc, +11.4 to +16.5V de Veg, -11.4 to -16.5V de POWER SUPPLY GAIN SENSITIVITY? Vcc = +11.4 to +16.5V de VEE = -11.4 to -16.5V de PROGRAMMABLE OUTPUT RANGES (see Figures 1, 2, 3) EXTERNAL ADJUSTMENTS Gain Error with Fixed 50Q Resistor for R2 (Figure 2) Bipolar Zero Error with Fixed 50Q Resistor for R1 (Figure 3) Gain Adjustment Range (Figure 2) Bipolar Zero Adjustment Range REFERENCE INPUT Input Impedance REFERENCE OUTPUT Voltage Current (available for external loads) POWER DISSIPATION PRICE (100+) Specifications subject to change without notice, AD567SD/AD567SD/883B MIN TYP MAX +2.0 +5.5 +0.7 +120 +300 +35 +100 12 -1.6 -2.0 -2.4 +0.8 10 #2 6k 8k 10k 0.01 0.05 0.05 0.15 25 15 +10 +1/4 +1/2 (0.006) (0.012) 2 3/4 (0.012) (0.018) ELS 2: +3/4 MONOTONICITY GUARANTEED 1 2 10 15 30 2 -55 +125 -65 +150 3 5 -17 -25 3 10 15 25 Oto +5 -2.5 to +2.5 Oto +10 -5 to +5 -10 to +10 +0.1 0.25 +0.05 +0.15 0.25 +0.15 15k 20k 25k 9.90 10.00 10.10 0.1 1.0 300 495 i AD567SD $59.00 AD567SD/883B $68.00 UNITS uA LA Bits | mA mA % of F.S. % of F.S. pF LSB % of F.S. LSB % of F.S. LSB ppm/C ppm/C ppm/C ppm/C "6 Cc mA mA ppm of F.S./% ppm of F.S./% Poe de % of F.S. % of F.S. % of F.S. % of F.S. Q Vv mA mWTIMING SPECIFICATIONS (All Models, Ta = 25C, Vcc = +12V or +15V, Veg =-12V or -15V) Symbol Parameter Min Typ Max tpw Data Valid to End of WR 50 os tcw CS Valid to End of WR 100 = taw Address Valid to End of WR. 100 a ns twp Write Pulse Width 100 ns tpy Data Hold Time 0 = ns tseTr Output Current Settling Time 400 500 ns TIMING DIAGRAMS WRITE CYCLE #1 (Load First Rank from Data Bus; A3 = 1) [- DB11-DBO yy | x == wR \ \ \ 7 ABSOLUTE MAXIMUM RATINGS Vcc to Power Ground... 6... eee eee OV to +18V Ver to Power Ground .......50 000002 eee OV to -18V Voltage on DAC Output (Pin 2).......----- -3V to +12V Digital Inputs (Pins 10-15, 17-28) to Power Ground.........--+--+-++055 -1.0V to +7.0V Ref In to Reference Ground .......-.-. ++ see veers EI2V Bipolar Offset to Reference Ground .........++4-. +12V 10V Span R to Reference Ground ......-.-.+40005 #12V 20V Span R to Reference Ground ..........5+055 +24V Ref Out... 2... .... 00054 Indefinite short to power ground Momentary Short to Vcc Power Dissipation... 2... eee ees 1000mW WRITE CYCLE #2 (Load Second Rank from First Rank; Az, Az, Ao = 1) [> tcw cs [- taw _s} A3 C twp | WR OUTPUT OUTLINE DIMENSIONS Dimensions shown in inches and (mm). PARRA RARAARARAA 0.55 (12.97) 0.53 (13.47) VV VV T | 0.16 (4.07) 1.45 (36.83) 0.606 (15.4) 0.14 (3.56) 4d (36. | : AS 1.44 (36.58) - 0.594 (15 aint rey ~ nt mao Nb al. Le 0.175 (4.45) 0.065 0.065 (1.66) 66) 0.02 (0.508) 0.105 (2.67) 0.12 (3.05) 0. 0.045 (1.15) (1.15) 0.015 (0.381) 0.095 (2.42) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 28-Pin Plastic DIP (N Package) AD567 ORDERING GUIDE LINEARITY TEMP ERROR MAX MODEL PACKAGE RANGE @ 25C AD567JN Plastic Com +1/2LSB AD567KN Plastic Com +1/4LSB AD567JD Ceramic Com #1/2LSB AD567KD Ceramic Com +1/4LSB AD567SD Ceramic Mil +1/2LSB AD567SD/883B Ceramic Mil +1/2LSB +1/2LSB 0.598 (15.19) 0.568 (14.43) : ft 7 | Se 0.06 (3.08) (4.32) 1.414 (35.92) max 1.38 (35.06) OA2:0.83) ee 0.012 (0.305) Les Lee 0.606 (15.4) 0.008 (0.203) 0.175 (4.45) 0.58 (14.74) 0.065 (1.66) 0.02 (0.508) 0.105 (2.67) 0.125 (3.18) 0.045 (1.15) 0.015 (0.381) 0.095 (2.42) LEAD NO.1 IDENTIFIED BY DOT OR NOTCH LEADS ARE GOLD OR TIN PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 28-Pin Ceramic DIP (D Package) PIN CONNECTIONS TOP VIEW eH sip orrset [_} 1 ~ 28 {_] 0811 (msB) DAC OUT (-2mA FS.) 2 27 [_] pB10 GAIN T.C. C FUN L) ov sPANR [_] 3 IDENTIFIER 26 [_] ps9 MAX 20V SPAN R Oo 4 25 w pes 50ppm/C REF GND (_] 5 24) 087 O 20ppm/ C VREF OUT CO 6 23 a DB6 oO AD567 50ppm/ C Mec OC 7 22 ) O85 oO 20ppm/ C Vace iw (_] 8 21{_] 084 30ppm/C vee (9 20 [] 08s 30ppm/C Kw 19 082 wR Cc u 18 {_] 081 A3 12 7 ) DBO (LSB) A2 13 16 [~] POWER GROUND ail] 15 [_] aoTHE AD567 OFFERS TRUE 12-BIT PERFORMANCE OVER THE FULL TEMPERATURE RANGE RELATIVE ACCURACY: Analog Devices defines relative accuracy as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from 0 to F.S. 1LSB) for any bit combination. The ADS567 is laser trimmed to 1/4LSB (0.006% of F.S.) maxi- mum error at +25C for the K version and 1/2LSB for the JandS. MONOTONICITY: A DAC is said to be monotonic if the out- put either increases or remains constant for increasing digital inputs such that the output will always be a non-decreasing function of input. All versions of the AD567 are mono- tonic over their full operating temperature range. DIFFERENTIAL NONLINEARITY: Monotonic behavior requires that the differential linearity error be less than 1LSB both at +25C and over the temperature range of inter- est. Differential nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a 1LSB change in digital input code. For example, for a 10 volt full scale output, a change of 1LSB in digital input code should result in a 2.44mV change in the analog output (1LSB = 10V x 1/4096 = 2.44mV). If in actual use, however, a 1LSB change in the input code results in a change of only 0.61mV (1/4LSB) in analog output, the differential linearity error would be 1.83mV, or 3/4LSB. The AD567K has a max differential linearity error of 1/2LSB, which specifies that every step will be at least 1/2LSB and at most 1 1/2LSB. The differential nonlinearity temperature coefficient must also be considered if the device is to remain monotonic over its full operating temperature range. A differential nonlinearity temper- ature coefficient of 1.0ppm/C could, under worst case condi- tions for a temperature change of +25C to +125C, add 0.01% (100C x 1.0ppm/C) of error. The resulting error could then be as much as 0.01% + 0.006% (initial error, 1/4LSB) = 0.016% of F.S. (1/2LSB represents 0.012% of F.S.). To be sure of accurate performance all versions of the AD567 are 100% tested for monotonicity over the full oper- ating temperature range. ANALOG CIRCUIT CONNECTIONS The standard current-to-voltage conversion connections using an operational amplifier are shown here with the preferred trim- ming techniques. If alow offset operational amplifier (AD510L; AD517L; AD741L; AD301AL; AD OP-07) is used, excellent performance can be obtained in many situations without trim- ming (an op amp with less than 0.5mV max offset voltage should be used to keep offset errors below 1/2LSB). Unipolar zero will typically be within +1/2LSB (plus op amp offset), and full scale accuracy will be within 0.1% (0.25% max). Substituting a 50Q2 resistor for the 100Q bipolar offset trim- mer will give a bipolar zero error typically within 2LSB (0.05%). The AD544 is recommended for buffered voltage-output appli- cations which require fast settling time to +1/2LSB. The feed- back capacitor is shown with the optimum value for each application; this capacitor is required to compensate for the 25 picofarad DAC output capacitance. +Vcc 1002 }p, 50kQ +Vec tS WR A3-A0 080-0811 BIPOLAR $1002 OFF -Vee 10)(11){12)-{15 (17 281 REF OUT iS 7S savrePaN + 4 R2 roy LATCHES vov sean 1o0n | 19.95 0.5mA 9.95k 3 8 DAC REF IN 5k J out Ope | OUTPUT DAC -< 2 - 0 TO +10V lout = lb 2 5 4x Irer x Sk "A544 => REF uel + 24k GND AD567 Figure 1. Oto +10V Unipolar Voltage Output FIGURE 1. UNIPOLAR CONFIGURATION This configuration will provide a unipolar 0 to +10 volt output range. In this mode, the bipolar terminal, pin 1, should be grounded if not used for trimming. STEPI...ZERO ADJUST Turn all bits OFF and adjust zero trimmer R1, until the out- put reads 0.000 volts (1LSB = 2.44mV). In most cases this trim is not needed, and pin 1 should be connected to pin 5. STEP II... GAIN ADJ UST Turn all bits ON and adjust 100Q gain trimmer R2, until the output is 9.9976 volts. (Full scale is adjusted to 1LSB less than nominal full scale of 10.000 volts.) If a 10.2375V full scale is desired (exactly 2.5mV/bit), insert a 12092 resistor in series with the gain resistor at pin 3 to the op amp output. BIPOLAR OFF CS WR A3-A0 DBO - 0B11 20V SPAN PT we DAC ok 20nF | OUTPUT Pr} -5v TO +5V O D544 2.4kQ. Figure 2, +5V Bipolar Voltage Output FIGURE 2. BIPOLAR CONFIGURATION This configuration will provide a bipolar output voltage from -5,000 to +4.9976 volts, with positive full scale occurring with all bits ON (all 1s). STEP I...OFFSET ADJUST Turn OFF all bits. Adjust 100Q trimmer R1 to give -5.000 volts output. STEP II... GAIN ADJUST Turn ON All bits. Adjust 100Q gain trimmer R2 to give a reading of +4.9976 volts. Please note that it is not necessary to trim the op amp to ob- tain full accuracy at room temperature. In most bipolar situa- tions, an op amp trim is unnecessary unless the untrimmed off- set drift of the op amp is excessive.FIGURE 3 OTHER VOLTAGE RANGES The AD567 can also be easily configured for a unipolar 0 to +5 volt range or +2.5 volt and +10 volt bipolar ranges by using the additional 5k application resistor provided at the 20 volt span R terminal, pin 4. For a 5 volt span (0 to +5 or 2.5), the two 5k resistors are used in parallel by shorting pin 4 to pin 2 and connecting pin 3 to the op amp output and the bipolar offset either to ground for unipolar or to REF OUT for the bipolar range. For the +10 volt range (20 volt span) use the 5k resistors in series by connecting only pin 4 to the op amp output and the bipolar offset connected as shown. The +10 volt option is shown in Figure 3. R1 1002 +Vcc CS WR A3-AO DB0-0B11 BIPOLAR OFF REF 7 10){11)}(12)(15 H{(17 1 our 6 ee=| jPeee=) 20V SPAN + 4 LATCHES m2 10V 5k 1002 | 19.95k 0.5mA 9.95k 3 )10V SPAN 8 DAC REF IN = 5k J out AOSE OUTPUT ENCE DAC o-< 2 NPP -10v To +10 20k lout = ie Sa n 5 = 4x IReF x . ADS44 REF >= CODE GND AD567 co ans 9 ue POWER -VeE GND Figure 3. +10V Voltage Output The internal resistor values shown in Figures 1, 2, and 3 are nominal values only, as is the output current. These values are subject to an absolute tolerance of approximately +20%. Furthermore, the resistors in the AD567 exhibit a tempera- ture coefficient of approximately -50ppm/*C. While these absolute tolerances may appear excessively wide, the ratios of the resistor values and tracking TC are extremely well- controlled. In applications where the internal feedback resistor determines the output voltage range it is the ratios which determine the accuracy. However, in applications where the desired full scale range requires use of an external resistor, sufficient trim range must be provided to compensate for the tolerance of the internal resistance. INTERNAL/EXTERNAL REFERENCE USE The AD567 has an internal low-noise buried zener diode refer- ence which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a high speed DAC and will give long-term stability equal or superior to the best discrete zener reference diodes. The performance of the AD567 is specified with the internal refer- ence driving the DAC since all trimming and testing (especially for full scale error and bipolar offset) is done in this config- uration. The AD567 can be used with an external reference, but may not have sufficient trim range to accommodate a reference which does not match the internal reference. The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 0.5mA to Ref In and 1.0mA to Bipolar Offset). Output Range Connect Pin 3 to: 0 to +5V Amplifier Output 0 to +10V Amplifier Output -2.5V to +2.5V_ Amplifier Output -5V to +5V Amplifier Output -10V to +10V _ Connect Pin 4 to: A minimum of 0.1mA is available for driving external loads. The AD567 reference output should be buffered with an ex- ternal op amp if it is required to supply additional output current. The reference is typically trimmed to 0.2%, then tested and guaranteed to 1.0% max error. The temperature coefficient is comparable to that of the full scale TC for a particular grade. OUTPUT VOLTAGE COMPLIANCE The AD567 has atypical output compliance range from -1.5 to +10 volts. The current-steering output stages will be unaffected by changes in the output terminal voltage over that range. How- ever, there is an equivalent output impedance of 8k in parallel with 25pF at the output terminal which produces an equivalent error current if the voltage deviates from analog common. This isa linear effect which does not change with input code. Opera- tion beyond the compliance limits may cause either output stage saturation or breakdown which results in nonlinear per- formance. Compliance limits are not affected by the posi- tive power supply, but are a function of output current and negative supply, as shown in Figure 4. lout = -2mA NEGATIVE COMPLIANCE VOLTAGE < 11.4V 13.5V 16.5V NEGATIVE SUPPLY -- Veg Figure 4. Typical Negative Compliance Range vs. Negative Supply GROUNDING RULES The AD567 brings out separate reference and power grounds to allow optimum connections for low noise and high speed performance. These grounds should be tied together at one point, usually the device power ground. The separate ground returns are provided to minimize current flow in low-level signal paths. In this way, logic return currents are not sum- med into the same return path with analog signals. The reference ground at pin 5 is the ground point for the internal reference and is thus the high quality ground for the AD567; it should be connected directly to the analog reference point of the system. The power ground at pin 16 can be connected to the most convenient ground point; analog power return is preferred. If power ground contains high frequency noise beyond 200m\V, this noise may feed through the converter, thus some caution will be required in applying these grounds. It is also important to properly apply decoupling capacitors on the power supplies for the AD567 and the output amp li- fier. The correct method for decoupling is to connect a capac- itor from each power supply pin of both the AD567 and the amplifier directly to the reference ground pin of the AD567. Any load driven by the output amplifier should also be re- ferred to the reference ground pin. Connect Pin 1 to: Pin 2 Pin 5 Amplifier Output Pin 5 Pin 2 Pin 6 (through 5082) Amplifier Output Amplifier Output Pin 6 (through 50Q) Pin 6 (through 5022) Table 1. Connections for Various Output Ranges -6-DIGITAL CIRCUIT DETAILS The double-buffered latch permits data to be loaded into the The bus interface logic of the AD567 consists of four inde- first rank latches of several AD567s and subsequently strobed pendently addressable registers in two ranks. The first rank into the second rank registers of all the DACs. All analog out- consists of three four-bit registers which can be loaded di- puts will then update simultaneously. rectly from a 4-, 8-, 12-, or 16-bit microprocessor bus. Once 4-BIT PROCESSOR INTERFACE the complete 12-bit data word has been assembled in the first rank, it can be loaded into the 12-bit register of the second rank. This double-buffered organization avoids the generation of spurious analog output values. Figure 5 shows the block diagram of the AD567 logic section. Many industrial control applications use four-bit microproces- sors but require 12-bit accurate analog control voltages. The AD567 is well suited to these applications, due to its flexible control structure. The latches are controlled by the address inputs, AO-A3, and = zs 6811, DB7,.0B3 the CS and WR inputs. All control inputs are active low, con- a 2 B10, DBG, DB2 sistent with general practice in microprocessor systems. The aavle CS and WR inputs must both be low for any operation to | 288, 0B4, DBO occur. The four address lines each enable one of the four latches, as indicated in Table 2 below. \ aporess } 1 DECODER All latches in the AD567 are level-triggered. This means that data present during the time when the control signals are valid 7 will enter the latch. When any one of the control signals re- 3 6 turns high, the data is latched. 2 | 1/2 7418139 | 5 DB11 DBs DB7 -- 084 DB3 - DBO 4 28)( 27){26 425 24)423)422)K 21 20){19)4 18) 17, es (10 wrR ai ADDRESS OPERATION OF TI SAB aiboce ars oO tH BURR Suteur 4) 20V SPAN R 2003) Figure 6. Addressing for 4-Bit Microprocessor Interface ~ 032 ee Pp VvsAN Fach AD567 occupies four locations in a 4-bit microprocessor _ 19.950 chet tI L111 Ld. system. A single 74LS139 2-to-4 decoder is used to provide we parmnen wees ir sequential addresses for the four AD567 registers. CS is de- merge oan rived from an address decoder driven from the high order Our REFERENCE ApeST Lhe address bits. The system WR is used for the WR input of the AD567. Figure 5. AD567 Block Diagram 8-BIT MICROPROCESSOR INTERFACE =, . The AD567 interfaces easily to 8-bit microprocessor systems CS WR A3 A2 Al AO Operation. . . of all types. The control logic makes possible the use of right- 1 X X X X X No Operation or left-justified data formats. x 1 x % A Ne Opemann : Whenever a 12-bit DAC is loaded from an 8-bit bus, two bytes 0 0 1 1 1 0 Enable 4 LSBs of First Rank are required. If the program considers the data to be a 12-bit o 0 1 1 0 1 Enable 4 Middle Bits of First Rank binary fraction (between 0 and 4095/4096), the data is left- 0 0 1 0 1 1 Enable 4 MSBs of First Rank justified, with the eight most significant bits in one byte and 0 0 1 1 1 Loads Second Rank from First Rank the remaining bits in the upper half of another byte. Right- 6) 0 0 0 (AD Late: Teengpaent justified data calls for the eight least significant bits to occupy X = Dont Care one byte, with the 4 most significant bits residing in the lower Table 2. AD567 Truth Table half of another byte, simplifying integer arithmetic. MICROPROCESSOR BUS INTERFACING [pB11| B10] DBS | vss | 07 | DBs | ves | vee | The AD567 interface logic is configured with enough flexi- ; bility to allow relatively simple interface to the various micro- processor bus structures. The required control signals, CS and | Bs | DB2 | DBI | oes | x | a | x | x | WR, are easily derived in most systems. Usually a base address is decoded, and this active-low signal is used for CS (Chip Select). Either 1/O Write or Memory Write can be used for WR, | x | x | x | x | pB11| 0B10] DBO | pes | depending on the system design. The relative timing of these signals is not important and they are interchangeable. The address lines determine which of the latches are being | 087 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DBO enabled. It is permissible to enable two or more latches simultaneously, as in the examples of 8-, 12-, and 16-bit 6, Right Justified interfaces. Figure 7. 12-Bit Data Formats for 8-Bit Systems a. Left JustifiedFigure 8 shows an addressing scheme for use with an AD567 AS set up for left-justified data in an 8-bit system. The base ad- | ADONESS To GS INPUT dress is decoded from the high-order address bits and the re- DECODER pono sultant active-low signal is applied to CS. The two LSBs of the address bus are connected as shown to the AD567 address ya Tse inputs. The latches now reside in two consecutive locations, with location X01 loading the four LSBs and location X10 loading the eight MSBs and updating the output. Yo TO AO, Al X DAC A2 EN Yi TO A2 X DAC Al Al 2 TO AO, A1 Y DAC AO AO Y3 TO A2 Y DAC 0B11 DB10 DB9 DB8 TO A3, BOTH DACS wR _ _ TO WR INPUT D3 DB7 (BOTH DACS) D2 DBe a2 | a1] ao OPERATION D1 DBs o | o | 0 | LOAD sLsBx DAC bo 84 0 | 0 | 1 | LOAD 4mse x Dac DB3 o | 1 | 0 | LOAD 8~LsB-Y DAC DB2 o | 1 | 1 | LOAD 4msB - Y DAC DBI 1 |x | x | UPDATE BOTH DACS DBO Figure 10. Addressing for Two DACs (Right-Justified) on 8-Bit Bus ADDRESS DECODER AO USING THE AD567 WITH 12- AND 16-BIT BUSES The AD567 is easily interfaced to 12- and 16-bit data buses. In this operation, all four address lines (AO through A3) are tied to low, and the latch is enabled by CS and WR going low. The AD567 thus occupies a single memory location. Al A2 A3 wR Figure 8. Left-Justified 8-Bit Bus Interface This configuration renders the second rank register trans- Right-justified data can be similarly accommodated. The parent, using the first rank of registers as the data latch. The overlapping of data lines is reversed, and the address con- CS input can be driven from an active-low decoded address, nections are slightly different. The AD567 still occupies and WR can be the system WR signal. [t should be noted that two adjacent locations in the processors memory map. any data bus activity during the period when CS and WR are both active will cause activity at the AD567 output. If data is not guaranteed stable during this period, the second rank register can be used to provide double buffering. 0B11 DB10 OB9 DBB ae D111 D6 DBE D10 : ae o BE Ds Ba ee o D6 5S DBI DS DBO D4 A15 D3 | ADDRESS D2 i DECODER go A2 po _______+J Re A15 at ' ADDRESS ~~ Al ! DECODER AO A2 A2 A3 wa WR wR Figure 9. Right-Justified 8-Bit Bus Interface USING MULTIPLE AD567 DACS IN 8-BIT SYSTEMS . : : Many applications use multiple digital-to-analog converters Figure 11. Connections for 12- and 16-Bit Bus Interface driven from the same data bus. For example, automatic test : : DIGITAL INPUT CONSIDERATIONS equipment systems often require all analog outputs to be produced simultaneously. Vector-scan graphic systems require The threshold of the digital input circuitry is set at 1.4 volts that the X and Y coordinates of the stroke endpoints be up- and does novvaty with supply voltage. The input lines can dated simultaneously. The AD567 can be used with a very thus interface with any type of 5 volt logic. The configuration simple address decoder to perform this function, as shown of the input circuit is shown in Figure 12, The input line can in Figure 10. The 74LS139 two-line to four-line decoder and be modeled asia. 30kQ Tesistance connected to a -0.7V rail, one inverter provide a set of distinct address pulses which in parallel with a SpF capacitance to ground. assign the registers of the two DACs to a block of consecutive memory locations, In this circuit, write operations to addres- DIGITAL ! ses XO00 and X001 load the first rank registers of one DAC (PINS 10-15 t SpF in a right-justified data format. Addresses XO10 and XO11 1 L 30K load the first tank of another DAC, also in a right-justified ON to Losi format. A write to any address from X100 to X111 will load rong A the second rank registers of both DACs simultaneously from - their respective first rank registers. Figure 12. Equivalent Digital Input Circuit C679a41/83 PRINTED IN U.S.A.