REV.
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AD7226
LC
2
MOS
Quad 8-Bit D/A Converter
FUNCTIONAL BLOCK DIAGRAM
CONTROL
LOGIC
DAC A
DAC B
DAC C
DAC D
LATCH A
LATCH B
LATCH C
LATCH D
A
B
C
D
MSB
DATA
(8-BIT)
LSB
WR
A1
A0
VSS AGND AGND
VREF VDD
VOUTA
VOUTB
VOUTC
VOUTD
D
A
T
A
B
U
S
AD7226
GENERAL DESCRIPTION
The AD7226 contains four 8-bit voltage-output digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the four D/A
converters. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS (5 V) compatible input
port. Control inputs A0 and A1 determine which DAC is
loaded when WR goes low. The control logic is speed-compat-
ible with most 8-bit microprocessors.
Each D/A converter includes an output buffer amplifier capable
of driving up to 5 mA of output current. The amplifiers’ offsets
are laser-trimmed during manufacture, thereby eliminating any
requirement for offset nulling.
Specified performance is guaranteed for input reference voltages
from 2 V to 12.5 V with dual supplies. The part is also specified
for single supply operation at a reference of 10 V.
The AD7226 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC
2
MOS) process, which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching
Since all four DACs are fabricated on the same chip at the
same time, precise matching and tracking between the DACs
is inherent.
2. Single-Supply Operation
The voltage mode configuration of the DACs allows the
AD7226 to be operated from a single power supply rail.
3. Microprocessor Compatibility
The AD7226 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered.
4. Small Size
Combining four DACs and four op amps plus interface logic
into a 20-pin package allows a dramatic reduction in board
space requirements and offers increased reliability in systems
using multiple converters. Its pinout is aimed at optimizing
board layout with all the analog inputs and outputs at one
end of the package and all the digital inputs at the other.
FEATURES
Four 8-Bit DACs with Output Amplifiers
Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages
Microprocessor-Compatible
TTL/CMOS-Compatible
No User Trims
Extended Temperature Range Operation
Single Supply Operation Possible
APPLICATIONS
Process Control
Automatic Test Equipment
Automatic Calibration of Large System Parameters,
e.g., Gain/Offset
D
11
781-461-3113
AD7226* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
•AN-317: Circuit Applications of the AD7226 Quad CMOS
DAC
•AN-321: 3-Phase Sine Wave Generation Using the AD7226
Quad DAC
Data Sheet
•AD7226: Military Data Sheet
•AD7226: LC2MOS Quad 8-Bit D/A Converter Data Sheet
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•Digital to Analog Converters ICs Solutions Bulletin
DESIGN RESOURCES
•AD7226 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all AD7226 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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REV.–2–
AD7226–SPECIFICATIONS
(VDD = 11.4 V to 16.5 V, VSS = –5 V 10%, AGND = DGND = 0 V; VREF = +2 V to (VDD – 4 V)1,
unless otherwise noted. All Specifications TMIN to TMAX unless otherwise noted.)
DUAL SUPPLY
Parameter K, B Versions
2
Unit Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Total Unadjusted Error ±1LSB maxV
DD
= 15 V ± 5%, V
REF
= 10 V
Relative Accuracy ±0.5 LSB max
Differential Nonlinearity ±1LSB max Guaranteed Monotonic
Full-Scale Error ±0.5 LSB max
Full-Scale Temperature Coefficient ±20 ppm/∞C typ V
DD
= 14 V to 16.5 V, V
REF
= +10 V
Zero Code Error ±20 mV max
Zero Code Error Temperature Coefficient ±50 mV/∞C typ
REFERENCE INPUT
Voltage Range 2 to (V
DD
– 4) V min to V max
Input Resistance 2 kW min
Input Capacitance
3
50 pF min Occurs when each DAC is loaded with all 0s.
200 pF max Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Leakage Current ±1mA max V
IN
= 0 V or V
DD
Input Capacitance 8 pF max
Input Coding Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
2.5 V/ms min
Voltage Output Settling Time
4
4ms max V
REF
= 10 V; Settling Time to ±1/2 LSB
Digital Crosstalk 10 nV secs typ
Minimum Load Resistance 2 kW min V
OUT
= 10 V
POWER SUPPLIES
V
DD
Range 11.4/16.5 V min/V max For Specified Performance
I
DD
13 mA max Outputs Unloaded; V
IN
= V
INL
or V
INH
I
SS
11 mA max Outputs Unloaded; V
IN
= V
INL
or V
INH
SWITCHING CHARACTERISTICS
4, 5
Address to Write Setup Time, t
AS
0ns min
Address to Write Hold Time, t
AH
0ns min
Data Valid to Write Setup Time, t
DS
50 ns min
Data Valid to Write Hold Time, t
DH
0ns min
Write Pulsewidth, t
WR
50 ns min
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K Version: –40∞C to +85∞C
B Version: –40∞C to +85∞C
3
Guaranteed by design. Not production tested.
4
Sample Tested at 25∞C to ensure compliance.
5
Switching Characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
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REV.
AD7226
–3–
SINGLE SUPPLY
Parameter K, B Versions
2
Unit Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Total Unadjusted Error ±2LSB max
Differential Nonlinearity ±1LSB max Guaranteed Monotonic
REFERENCE INPUT
Input Resistance 2 kW min
Input Capacitance
3
50 pF min Occurs when each DAC is loaded with all 0s.
200 pF max Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Leakage Current ±1mA max V
IN
= 0 V or V
DD
Input Capacitance 8 pF max
Input Coding Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
2V/ms min
Voltage Output Settling Time
4
4ms max Settling Time to ±1/2 LSB
Digital Crosstalk 10 nV secs typ
Minimum Load Resistance 2 kW min V
OUT
= +10 V
POWER SUPPLIES
V
DD
Range 14.25/15.75 V min/V max For Specified Performance
I
DD
13 mA max Outputs Unloaded; V
IN
= V
INL
or V
INH
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K Version: –40∞C to +85∞C
B Version: –40∞C to +85∞C
3
Guaranteed by design. Not production tested.
4
Sample Tested at 25∞C to ensure compliance.
Specifications subject to change without notice.
(VDD = 15 V 5%, VSS = AGND = DGND = O V; VREF = 10 V1 unless otherwise noted.
All specifications TMIN to TMAX unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, V
DD
V
SS
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, V
DD
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
OUT
to AGND
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
Power Dissipation (Any Package) to 75∞C . . . . . . . . . . 500 mW
Derates above 75∞C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/∞C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40∞C to +85∞C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. Typically short circuit current to AGND is 50 mA.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
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REV.–4–
AD7226
PIN CONFIGURATIONS
DIP and SOIC/SSOP
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD7226
V
REF
AGND
DGND
DB7 (MSB)
DB6
A0
A1
WR
DB0(LSB)
DB5
DB4 DB3
DB2
DB1
V
SS
V
OUT
A
V
OUT
BV
OUT
C
V
OUT
D
V
DD
PLCC
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
V
REF
AGND
DGND
DB7 (MSB)
DB8
AD7226
V
DD
A0
A1
WR
DB0(LSB)
DB5
DB4
DB3
DB2
DB1
V
SS
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
TERMINOLOGY
TOTAL UNADJUSTED ERROR
This is a comprehensive specification that includes full-scale
error, relative accuracy and zero code error. Maximum output
voltage is V
REF
– 1 LSB (ideal), where 1 LSB (ideal) is V
REF
/
256. The LSB size will vary over the V
REF
range. Hence the zero
code error will, relative to the LSB size, increase as V
REF
decreases.
Accordingly, the total unadjusted error, which includes the zero
code error, will also vary in terms of LSB’s over the V
REF
range.
As a result, total unadjusted error is specified for a fixed refer-
ence voltage of 10 V.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
allowing for zero and full-scale error and is normally expressed
in LSB’s or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL CROSSTALK
The glitch impulse transferred to the output of one converter
due to a change in the digital input code to another of the con-
verters. It is specified in nV secs and is measured at V
REF
= 0 V.
FULL SCALE ERROR
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
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D
REV.
AD7226
–5–
CIRCUIT INFORMATION
D/A SECTION
The AD7226 contains four identical, 8-bit, voltage mode digital-to-
analog converters. The output voltages from the converters have the
same polarity as the reference voltage allowing single supply opera-
tion. A novel DAC switch pair arrangement on the AD7226 allows a
reference voltage range from 2 V to 12.5 V.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. The simplified circuit diagram for one channel is
shown in Figure 1. Note that V
REF
(Pin 4) and AGND (Pin 5)
are common to all four DACs.
RRR
2R 2R 2R 2R 2R
DB0 DB5 DB6 DB7
VREF
AGND
SHOWN FOR ALL 1s ON DAC
VOUT
Figure 1. D/A Simplified Circuit Diagram
The input impedance at the V
REF
pin of the AD7226 is the
parallel combination of the four individual DAC reference input
impedances. It is code dependent and can vary from 2 kW to
infinity. The lowest input impedance (i.e., 2 KW) occurs when
all four DACs are loaded with the digital code 01010101.
Therefore, it is important that the reference presents a low
output impedance under changing load conditions. The nodal
capacitance at the reference terminals is also code dependent
and typically varies from 100 pF to 250 pF.
Each V
OUT
pin can be considered as a digitally programmable
voltage source with an output voltage of:
VDV
OUTX X REF
=
(1)
where D
X
is fractional representation of the digital input code
and can vary from 0 to 255/256.
The source impedance is the output resistance of the buffer
amplifier.
OP AMP SECTION
Each voltage-mode D/A converter output is buffered by a unity
gain, noninverting CMOS amplifier. This buffer amplifier is
capable of developing 10 V across a 2 kW load and can drive
capacitive loads of 3300 pF. The output stage of this amplifier
consists of a bipolar transistor from the V
DD
line and a current
load to the V
SS
, the negative supply for the output amplifiers.
This output stage is shown in Figure 2.
The NPN transistor supplies the required output current drive
(up to 5 mA). The current load consists of NMOS transistors
which normally act as a constant current sink of 400 mA to V
SS
,
giving each output a current sink capability of approximately
400 mA if required.
The AD7226 can be operated single or dual supply resulting
in different performance in some parameters from the output
amplifiers.
In single supply operation (V
SS
= 0 V = AGND), with the out-
put approaching AGND (i.e., digital code approaching all 0s)
VDD
VSS
I/P
O/P
400A
Figure 2. Amplifier Output Stage
the current load ceases to act as a current sink and begins to act
as a resistive load of approximately 2 kW to AGND. This occurs
as the NMOS transistors come out of saturation. This means
that, in single supply operation, the sink capability of the ampli-
fiers is reduced when the output voltage is at or near AGND. A
typical plot of the variation of current sink capability with out-
put voltage is shown in Figure 3.
V
OUT
(V)
500
0102
I
SINK
(A)
468
400
300
200
100
0
V
SS
= –5V
V
SS
= 0 V
DD
= +15V
Figure 3. Variation of I
SINK
with V
OUT
If the full sink capability is required with output voltages at or
near AGND (= 0 V), then V
SS
can be brought below 0 V by 5 V
and thereby maintain the 400 mA current sink as indicated in
Figure 3. Biasing V
SS
below 0 V also gives additional headroom
in the output amplifier which allows for better zero code error
performance on each output. Also improved is the slew rate and
negative-going settling time of the amplifiers (discussed later).
Each amplifier offset is laser trimmed during manufacture to
eliminate any requirement for offset nulling.
DIGITAL SECTION
The digital inputs of the AD7226 are both TTL and CMOS
(5 V) compatible from V
DD
= 11.4 V to 16.5 V. All logic inputs
are static protected MOS gates with typical input currents of
less than 1 nA. Internal input protection is achieved by an
on-chip distributed diode from DGND to each MOS gate. To
minimize power supply currents, it is recommended that the
digital input voltages be driven as close to the supply rails (V
DD
and DGND) as practically possible.
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D
REV. –6–
AD7226
INTERFACE LOGIC INFORMATION
Address lines A0 and A1 select which DAC will accept data
from the input port. Table I shows the selection table for the
four DACs with Figure 4 showing the input control logic. When
the WR signal is LOW, the input latches of the selected DAC
are transparent and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high the analog outputs remain
at the value corresponding to the data held in their respective latches.
Table I. AD7226 Truth Table
AD7226 Control Inputs AD7226
WR A1 A0 Operation
HXXNo Operation Device Not Selected
LLLDAC A Transparent
LLDAC A Latched
LLHDAC B Transparent
LHDAC B Latched
LHLDAC C Transparent
HLDAC C Latched
LHHDAC D Transparent
HHDAC D Latched
L = Low State, H = High State, X = Don’t Care
A0
A1
W
R
TO LATCH A
TO LATCH B
TO LATCH C
TO LATCH D
Figure 4. Input Control Logic
t
DS
t
DH
t
AH
t
AS
VINL
VINH
VINH
VINL
VDD
VDD
VDD
DATA
ADDRESS
WR
0
0
0
t
WR
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 10% TO 90% OF VDD.
t
r =
t
f = 20ns OVER VDD RANGE.
2. TIMING MEASUREMENT REFERENCE LEVEL IS
3. SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS
LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE
SPURIOUS OUTPUTS.
VINH + VINL
2
Figure 5. Write Cycle Timing Diagram
D
REV.
Typical Performance Characteristics–AD7226
–7–
(TA = 25C, VDD = 15 V, VSS = –5 V)
INPUT CODE (DECIMAL EQUIVALENT)
2.0
0 16
TOTA L UNADJUSTED ERROR (LSBs)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
V
REF
= 10V
TPC 1. Channel-to-Channel Matching
V
REF
(V)
01424681012
4
RELATIVE ACCURACY (LSBs)
3
2
1
0
–1
–2
–3
–4
AD7226K, B
TPC 2. Relative Accuracy vs. V
REF
V
REF
(V)
01424681012
4
DIFFERENTIAL NONLINEARITY (LSBs)
3
2
1
0
–1
–2
–3
–4
AD7226K, B
TPC 3. Differential Nonlinearity vs. V
REF
TEMPERATURE (C)
2.0
010
ZERO CODE ERROR (LSBs)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0 20 30 40 50 60 70 80 90 100 110 120 130
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
TPC 4. Zero Code Error vs. Temperature
D
REV. –8–
AD7226
SPECIFICATION RANGES
In order for the DACs to operate to their specifications, the
reference voltage must be at least 4 V below the V
DD
power
supply voltage. This voltage differential is required for correct
generation of bias voltages for the DAC switches.
The AD7226 is specified to operate over a V
DD
range from
+12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to +16.5 V)
with a V
SS
of –5 V ± 10%. Operation is also specified for a single
+15 V ± 5% V
DD
supply. Applying a V
SS
of –5 V results in
improved zero code error, improved output sink capability with
outputs near AGND and improved negative-going settling time.
Performance is specified over a wide range of reference voltages
from 2 V to (V
DD
– 4 V) with dual supplies. This allows a range
of standard reference generators to be used such as the AD780,
a 2.5 V band gap reference and the AD584, a precision 10 V
reference. Note that in order to achieve an output voltage range
of 0 V to 10 V a nominal 15 V ± 5% power supply voltage is
required by the AD7226.
SETTLING TIME
The output stage of the buffer amplifiers consists of a bipolar
NPN transistor from the V
DD
line and a constant current load to
V
SS
. V
SS
is the negative power supply for the output buffer ampli-
fiers. As mentioned in the op amp section, in single supply
operation the NMOS transistor will come out of saturation as the
output voltage approaches AGND and will act as a resistive load
of approximately 2 kW to AGND. As a result, the settling time for
negative-going signals approaching AGND in single supply opera-
tion will be longer than for dual supply operation where the
current load of 400 mA is maintained all the way down to AGND.
Positive-going settling-time is not affected by V
SS
.
The settling-time for the AD7226 is limited by the slew-rate of
the output buffer amplifiers. This can be seen from Figure 6
which shows the dynamic response for the AD7226 for a full
scale change. Figures 7a and 7b show expanded settling-time
photographs with the output waveforms derived from a differen-
tial input to an oscilloscope. Figure 7a shows the settling time
for a positive-going step and Figure 7b shows the settling time
for a negative-going output step.
DATA
V
OUT
Figure 6. Dynamic Response (V
SS
= –5 V)
DATA
O/P
+1/2 LSB
–1/2 LSB
Figure 7a. Positive Step Settling Time (V
SS
= –5 V)
DATA
O/P
+1/2 LSB
–1/2 LSB
Figure 7b. Negative Step Settling Time (V
SS
= –5 V)
GROUND MANAGEMENT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. This is especially true in micropro-
cessor systems where digital noise is prevalent. The simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7226. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7226 AGND and
DGND pins (IN914 or equivalent).
Unipolar Output Operation
This is the basic mode of operation for each channel of the
AD7226, with the output voltage having the same positive
polarity as +V
REF
. The AD7226 can be operated single supply
(V
SS
= AGND) or with positive/negative supplies (see op amp
section which outlines the advantages of having negative V
SS
).
The code table for unipolar output operation is shown in Table
II. Note that the voltage at V
REF
must never be negative with
respect to DGND in order to prevent parasitic transistor turn-on.
Connections for the unipolar output operation are shown in
Figure 8.
D
REV.
AD7226
–9–
DAC A
DAC B
DAC C
DAC D
MSB
VREF VDD
DGND
AGND
VSS
VOUTA
WR
A1
A0
LSB
VOUTB
VOUTC
VOUTD
DB7
DB0
Figure 8. AD7226 Unipolar Output Circuit
Table II. Unipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1 1 1 1 1 1 1 1
+Ê
Ë
Áˆ
¯
˜
V
REF
255
256
1 0 0 0 0 0 0 1
+Ê
Ë
Áˆ
¯
˜
V
REF
129
256
1 0 0 0 0 0 0 0
+Ê
Ë
Áˆ
¯
˜=+VV
REF
REF
128
256 2
0 1 1 1 1 1 1 1
+Ê
Ë
Áˆ
¯
˜
V
REF
127
256
0 0 0 0 0 0 0 1
+Ê
Ë
Áˆ
¯
˜
V
REF
1
256
0 0 0 0 0 0 0 0 0 V
Note LSB V V
REF REF
:
–
=
()
()
=Ê
Ë
Áˆ
¯
˜
21
256
8
(2)
Bipolar Output Operation
Each of the DACs of the AD7226 can be individually config-
ured to provide bipolar output operation. This is possible using
one external amplifier and two resistors per channel. Figure 9
shows a circuit used to implement offset binary coding (bipolar
operation) with DAC A of the AD7226. In this case
VR
RDV R
RV
OUT A REF REF
=+
Ê
Ë
Áˆ
¯
˜¥
()
Ê
Ë
Áˆ
¯
˜¥
()
12
1
2
1
–
(3)
With R1 = R2
VDV
OUT A REF
=
()
¥21–(4)
where D
A
is a fractional representation of the digital word in latch A.
Mismatch between R1 and R2 causes gain and offset errors and
therefore these resistors must match and track over tempera-
ture. Once again the AD7226 can be operated in single supply
or from positive/negative supplies. Table III shows the digital
code versus output voltage relationship for the circuit of Figure 9
with R1 = R2.
DAC A
VREF VDD
DGND
AGND
VSS
VOUTAVOUT
VREF
AD7226
*
R2
R1
+15V
–15V
R1, R2 = 10k 0.1%
*DIGITAL INPUTS OMITTED
FOR CLARITY
Figure 9. AD7226 Bipolar Output Circuit
Table III. Bipolar (Offset Binary) Code Table
DAC Latch Contents
MSB LSB Analog Output
1 1 1 1 1 1 1 1
+Ê
Ë
Áˆ
¯
˜
V
REF
127
128
1 0 0 0 0 0 0 1
+Ê
Ë
Áˆ
¯
˜
V
REF
1
128
1 0 0 0 0 0 0 0 0 V
0 1 1 1 1 1 1 1
–V REF
1
128
Ê
Ë
Áˆ
¯
˜
0 0 0 0 0 0 0 1
–V REF
127
128
Ê
Ë
Áˆ
¯
˜
0 0 0 0 0 0 0 0
––VV
REF REF
128
128
Ê
Ë
Áˆ
¯
˜=
AGND BIAS
The AD7226 AGND pin can be biased above system GND
(AD7226 DGND) to provide an offset “zero” analog output
voltage level. Figure 10 shows a circuit configuration to achieve
this for channel A of the AD7226. The output voltage, V
OUT
A,
can be expressed as:
VAV DV
OUT BIAS A IN
=+
()
(5)
where D
A
is a fractional representation of the digital input word
(0 £ D £ 255/256).
D
REV. –10–
AD7226
DAC A
VREF VDD
DGND
AGND
VSS
VOUTA
AD7226
*
*DIGITAL INPUTS OMITTED FOR CLARITY
5
VBIAS
Figure 10. AGND Bias Circuit
For a given V
IN
, increasing AGND above system GND will
reduce the effective V
DD
–V
REF
which must be at least 4 V to
ensure specified operation. Note that because the AGND pin is
common to all four DACs, this method biases up the output
voltages of all the DACs in the AD7226. Note that V
DD
and V
SS
of the AD7226 should be referenced to DGND.
3-PHASE SINE WAVE
The circuit of Figure 11 shows an application of the AD7226 in
the generation of 3-phase sine waves which can be used to con-
trol small 3-phase motors. The proper codes for synthesizing a
full sine wave are stored in EPROM, with the required phase-
shift of 120∞ between the three D/A converter outputs being
generated in software.
Data is loaded into the three D/A converters from the sine
EPROM via the microprocessor or control logic. Three loops are
generated in software with each D/A converter being loaded
from a separate loop. The loops run through the look-up table
producing successive triads of sinusoidal values with 120∞
separation which are loaded to the D/A converters producing
three sine wave voltages 120∞ apart. A complete sine wave
cycle is generated by stepping through the full look-up table.
If a 256-element sine wave table is used then the resolution of
the circuit will be 1.4∞ (360∞/256). Figure 13 shows typical
resulting waveforms. The sine waves can be smoothed by filter-
ing the D/A converter outputs.
The fourth D/A converter of the AD7226, DAC D, may be
used in a feedback configuration to provide a programmable
reference voltage for itself and the other three converters. This
configuration is shown in Figure 11. The relationship of V
REF
to
V
IN
is dependent upon digital code and upon the ratio of R
F
to
R and is given by the formula.
V
G
GD
V
REF
D
IN
=+
()
+¥
()
¥
1
1
(6)
where G = R
F
/R
and D
D
is a fractional representation of the digital word in latch D.
Alternatively, for a given V
IN
and resistance ratio, the required
value of D
D
for a given value of V
REF
can be determined from
the expression
DRR
V
V
R
R
DF
IN
REF F
=+
()
¥1/–
(7)
Figure 12 shows typical plots of V
REF
versus digital code for
three different values of R
F
. With V
IN
= 2.5 V and R
F
= 3 R the
peak-to-peak sine wave voltage from the converter outputs will
vary between 2.5 V and 10 V over the digital input code range
of 0 to 255.
DIGITAL CODE (Decimal Equivalent)
4.0 V
IN
0 16
V
REF
32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
3.5 V
IN
3.0 V
IN
2.5 V
IN
2.0 V
IN
1.5 V
IN
V
IN
R
F
= 3R
R
F
= 2R
R
F
= R
V
DD
= +15 V
V
SS
= –5 V
Figure 12. Variation of V
REF
with Feedback Configuration
V
REF
V
OUT
A
WR
A1
A0 V
OUT
B
V
OUT
C
V
OUT
D
AD7226
DATA
BUS
ADDRESS
BUS
MICROPROCESSOR
OR
CONTROL LOGIC SINE
EPROM
ADDRESS
DECODE
V
IN
R
F
R
Figure 11. 3-Phase Sine Wave Generation Circuit
V
OUT
A
V
OUT
B
V
OUT
C
Figure 13. 3-Phase Sine Wave Output
D
REV.
AD7226
–11–
STAIRCASE WINDOW COMPARATOR
In many test systems, it is important to be able to determine
whether some parameter lies within defined limits. The staircase
window comparator of Figure 14a is a circuit that can be used,
for example, to measure the V
OH
and V
OL
thresholds of a TTL
device under test. Upper and lower limits on both V
OH
and V
OL
can be programmably set using the AD7226. Each adjacent pair
of comparators forms a window of programmable size. If V
TEST
lies within a window, then the output for that window will be
high. With a reference of 2.56 V applied to the V
REF
input, the
minimum window size is 10 mV.
V
REF
V
DD
AGND
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
OH
(HIGH)
V
OL
(HIGH)
V
OH
(LOW)
V
OL
(LOW)
V
TEST
FROM D.U.T.
1/4 CA339
10k
5V
10k
5V
5V
5V
10k
10k
5V 10kWINDOW 5
WINDOW 4
WINDOW 3
WINDOW 2
WINDOW 1
AD7226
Figure 14a. Logic Level Measurement
VREF
AGND
VOUTA
VOUTB
VOUTC
VOUTD
WINDOW 5
WINDOW 4
WINDOW 3
WINDOW 2
WINDOW 1
Figure 14b. Window Structure
The circuit can easily be adapted to allow for overlapping of
windows as shown in Figure 15a. If the three outputs from this
circuit are decoded then five different nonoverlapping program-
mable windows can again be defined.
VREF VDD
AGND 5V 10kWINDOW 3
VOUTA
VOUTB
VOUTC
VOUTD
VTEST
FROM D.U.T.
10k
5V
10k
5V WINDOW 2
WINDOW 1
AD7226
Figure 15a. Overlapping Windows
V
REF
AGND
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
WINDOW 3
WINDOW 2
WINDOW 1
Figure 15b. Window Structure
DAC A
VREF VDD
DGND
AGND
VSS
VOUTA
AD7226
*
*DIGITAL INPUTS OMITTED
FOR CLARITY
+4V
–4V
+15V
15k
10k
Figure 16. Varying Reference Signal
VARYING REFERENCE SIGNAL
In some applications, it may be desirable to have a varying signal
applied to the reference input of the AD7226. The AD7226 has
multiplying capability within upper and lower limits of reference
voltage when operated with dual supplies. The upper and lower
limits are those required by the AD7226 to achieve its linearity
specification. Figure 16 shows a sine wave signal applied to the
reference input of the AD7226. For input signal frequencies up
to 50 kHz, the output distortion typically remains less than 0.1%.
Typical 3 dB bandwidth figure is 700 kHz.
D
REV. –12–
AD7226
OFFSET ADJUST
Figure 17 shows how the AD7226 can be used to provide pro-
grammable input offset voltage adjustment for the AD544 op
amp. Each output of the AD7226 can be used to trim the input
offset voltage on one AD544. The 620 kW resistor tied to 10 V
provides a fixed bias current to one offset node. For symmetri-
cal adjustment, this bias current should equal the current in the
other offset node with the half-full scale code (i.e., 10000000)
on the DAC. Changing the code on the DAC varies the bias
current and hence provides offset adjust for the AD544. For
example, the input offset voltage on the AD544J, which has a
maximum of ±2 mV, can be programmably trimmed to ±10 mV.
DAC A
VREF VDD
DGND
AGND
VSS
VOUTA
AD7226
*
*DIGITAL INPUTS OMITTED
FOR CLARITY
620k
500k
+15V
–15V
145
7
+10V
Figure 17. Offset Adjust for AD544
WR
A1
A0
AD7226*
ADDRESS/DATA BUS
ADDRESS BUS
ADDRESS
DECODE
WR EN
DB7
DB0
8212DS2
ALE
D7
D0
A8
A15
*LINEAR CIRCUITRY OMITTED FOR CLARITY
8085A
Figure 18. AD7226 to 8085A Interface
WR
A1
A0
AD7226
*
DATA BUS
ADDRESS BUS
ADDRESS
DECODE
R/WEN
DB7
DB0
D7
D0
A0
A15
*LINEAR CIRCUITRY OMITTED FOR CLARITY
EN
E
6809
Figure 19. AD7226 to 6809 Interface
WR
A1
A0
AD7226
*
DATA BUS
ADDRESS BUS
ADDRESS
DECODE
R/WEN
DB7
DB0
D7
D0
A0
A15
*LINEAR CIRCUITRY OMITTED FOR CLARITY
EN
2
6502
Figure 20. AD7226 to 6502 Interface
WR
A1
A0
AD7226
*
DATA BUS
ADDRESS BUS
ADDRESS
DECODE
WR EN
DB7
DB0
D7
D0
A0
A15
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Z-80
Figure 21. AD7226 to Z-80 Interface
D
AD7226
Rev. D | Page 1
OUTLINE DIMENSIONS
CONT ROLLING DIM E NS IONS ARE IN INCHES; MILLIM E TER DI M E NSIO NS
(IN PARENT HES E S ) ARE ROUNDED-OFF INCH EQ UIVALENT S FOR
REFERENCE O N LYAND ARE NOT AP P ROPRIAT E FO R USE IN DE SIG N.
CORNER LEADS MAY BE CONFI GURED AS WHOLE OR HALF L E ADS .
COMP LIANT TO JEDEC STANDARDS M S - 001
070706-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2. 92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
20
110
11
0.100 ( 2 .54)
BSC
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)
0.210 ( 5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2. 92)
Figure 1. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-20)
Dimensions shown in inches and (millimeters)
20
110
11
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005
(0.13)
MIN
0.098 (2.49)
MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX 1.060 (26.92) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 2. 20-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-20)
Dimensions shown in inches and (millimeters)
AD7226
Rev. D | Page
COM PLI ANT TO JEDEC S TANDARDS MO-150-AE
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 M IN
0.65 BSC
2.00 M A X
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 3. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
20 11
10
1
1.27
(0.0500)
BSC
06-07-2006-A
Figure 4. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
14
AD7226
Rev. D | Page
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.020 (0.50)
R
BOTTOM
VIEW
(PI NS U P )
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.056 (1.42)
0.042 (1.07) 0.20 ( 0. 5 1)
MIN
0.120 (3.04)
0.090 (2.29)
3
4
1918
8914
13
TOP VIEW
(PINS DOWN)
0.395 (10.03)
0.385 (9.78) SQ
0.356 (9.04)
0.350 (8.89)SQ
0.048 (1.22 )
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.020
(0.51)
R
0.050
(1.27)
BSC
0.180 (4.57)
0.165 (4.19)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
Figure 5. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20A)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Total Unadjusted Error2 Package Description Package Option3
AD7226BQ −40°C to +85°C ±1 LSB 20 Lead CERDIP Q-20
AD7226BRSZ −40°C to +85°C ±1 LSB 20 Lead SSOP RS-20
AD7226KN −40°C to +85°C ±1 LSB 20 Lead PDIP N-20
AD7226KNZ −40°C to +85°C ±1 LSB 20 Lead PDIP N-20
AD7226KP −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A
AD7226KP-REEL −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A
AD7226KPZ −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A
AD7226KPZ-REEL −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A
AD7226KR −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20
AD7226KR-REEL −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20
AD7226KRZ −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20
AD7226KRZ-REEL −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20
AD7226BCHIPS −40°C to +85°C ±1 LSB Chips or Die
1 Z = ROHS Compliant Part.
2 Dual supply operation.
3 N = plastic DIP; P = plastic leaded chip carrier; Q = CERDIP; RW = SPIC; RS = SSOP.
REVISION HISTORY
1/11—Rev. C to Rev. D
Changes to Ordering Guide ........................................................... 15
3/03—Rev. B to Rev. C
Title Revision ..................................................................................... 1
3/03—Rev. A to Rev. B
Edits to Features ................................................................................ 1
Edits to Specifications ....................................................................... 2
Edits to Ordering Guide ................................................................... 3
Edits to Absolute Maximum Ratings .............................................. 3
Edits to Pin Configurations ............................................................. 4
Edits to Specifications Ranges ......................................................... 8
Outline Dimensions Updated ........................................................ 13
RS-20 Package Added ..................................................................... 13
Updated RS-20 Package Outline Dimensions ............................. 13
AD7226
Rev. D | Page
NOTES
©2003-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00987-0-1/11(D)
