M74VHC1GT126DT1G - ON SEMICONDUCTOR

May, 2012 − Rev. 15

1Publication Order Number:

MC74VHC1GT126/D

MC74VHC1GT126

Noninverting Buffer /

CMOS Logic Level Shifter

with LSTTL−Compatible Inputs

The MC74VHC1GT126 is a single gate noninverting 3−state buffer

fabricated with silicon gate CMOS technology. It achieves high speed

operation similar to equivalent Bipolar Schottky TTL while maintaining

CMOS low power dissipation.

The MC74VHC1GT126 requires the 3−state control input (OE) to be

set Low to place the output into the high impedance state.

The device input is compatible with TTL−type input thresholds and

the output has a full 5 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the

input, allowing the device to be used as a logic−level translator from

3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to

3 V CMOS Logic while operating at the high−voltage power supply.

The MC74VHC1GT126 input structure provides protection when

voltages up to 7 V are applied, regardless of the supply voltage. This

allows the MC74VHC1GT126 to be used to interface 5 V circuits to

3 V circuits. The output structures also provide protection when

VCC = 0 V. These input and output structures help prevent device

destruction caused by supply voltage − input/output voltage mismatch,

battery backup, hot insertion, etc.

Features

•High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V

•Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C

•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V

•CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load

•Power Down Protection Provided on Inputs and Outputs

•Balanced Propagation Delays

•Pin and Function Compatible with Other Standard Logic Families

•Chip Complexity: FETs = 62; Equivalent Gates = 16

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free and are RoHS Compliant

Figure 1. Pinout (Top View)

IN A OUT Y

VCC

IN A

OUT YGND

Figure 2. Logic Symbol

PIN ASSIGNMENT

3 GND

IN A

OUT Y

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

FUNCTION TABLE

A Input Y Output

OE Input

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SC−88A / SOT−353 / SC−70

DF SUFFIX

CASE 419A

TSOP−5 / SOT−23 / SC−59

DT SUFFIX

CASE 483

MARKING

DIAGRAMS

W3 M G

W3 = Device Code

M = Date Code*

G= Pb−Free Package

W3 M G

*Date Code orientation and/or position may vary

depending upon manufacturing location.

(Note: Microdot may be in either location)

MC74VHC1GT126

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MAXIMUM RATINGS

Symbol Characteristics Value Unit

VCC DC Supply Voltage −0.5 to +7.0 V

VIN DC Input Voltage −0.5 to +7.0 V

VOUT DC Output Voltage −0.5 to VCC + 0.5 V

IIK Input Diode Current −20 mA

IOK Output Diode Current VOUT < GND; VOUT > VCC +20 mA

IOUT DC Output Current, per Pin +25 mA

ICC DC Supply Current, VCC and GND +50 mA

PDPower Dissipation in Still Air SC−88A, TSOP−5 200 mW

qJA Thermal Resistance SC−88A, TSOP−5 333 °C/W

TLLead Temperature, 1 mm from Case for 10 s 260 °C

TJJunction Temperature Under Bias +150 °C

Tstg Storage Temperature −65 to +150 °C

VESD ESD Withstand Voltage Human Body Model (Note 1)

Machine Model (Note 2)

Charged Device Model (Note 3)

> 2000

> 200

N/A

ILatchup Latchup Performance Above VCC and Below GND at 125°C (Note 4) ±500 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Tested to EIA/JESD22−A114−A

2. Tested to EIA/JESD22−A115−A

3. Tested to JESD22−C101−A

4. Tested to EIA/JESD78

RECOMMENDED OPERATING CONDITIONS

Symbol Characteristics Min Max Unit

VCC DC Supply Voltage 3.0 5.5 V

VIN DC Input Voltage 0.0 5.5 V

VOUT DC Output Voltage 0.0 VCC V

TAOperating Temperature Range −55 +125 °C

tr, tfInput Rise and Fall Time VCC = 5.0 V ± 0.5 V 0 20 ns/V

Device Junction Temperature versus

Time to 0.1% Bond Failures

Junction

Temperature °CTime, Hours Time, Years

80 1,032,200 117.8

90 419,300 47.9

100 178,700 20.4

110 79,600 9.4

120 37,000 4.2

130 17,800 2.0

140 8,900 1.0

1 10 100 1000

TIME, YEARS

NORMALIZED FAILURE RATE

TJ= 80 C°

TJ= 90 C°

TJ= 100 C°

TJ= 110 C°

TJ= 130 C°

TJ= 120 C°

FAILURE RATE OF PLASTIC = CERAMIC

UNTIL INTERMETALLICS OCCUR

Figure 3. Failure Rate vs. Time Junction Temperature

MC74VHC1GT126

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

(V)

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎ

TA ≤ 85°C

ÎÎÎÎÎÎ

−55 ≤ TA ≤ 125°C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎ

Minimum High−Level

Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

3.0

4.5

5.5

ÎÎÎ

1.4

2.0

ÎÎ

ÎÎÎ

1.4

2.0

ÎÎÎ

1.4

2.0

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

3.0

4.5

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

0.53

0.8

ÎÎÎ

0.53

0.8

ÎÎÎ

ÎÎÎÎ

0.53

0.8

ÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎ

Minimum High−Level

Output Voltage

VIN = VIH or VIL

ÎÎÎÎÎÎÎ

VIN = VIH or VIL

IOH = − 50 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

2.9

4.4

ÎÎ

3.0

4.5

ÎÎÎ

2.9

4.4

ÎÎÎ

2.9

4.4

ÎÎÎÎ

ÎÎ

ÎÎÎÎÎÎÎ

VIN = VIH or VIL

IOH = − 4 mA

IOH = − 8 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

2.58

3.94

ÎÎ

ÎÎÎ

2.48

3.80

ÎÎÎ

2.34

3.66

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Output Voltage

VIN = VIH or VIL

ÎÎÎÎÎÎÎ

VIN = VIH or VIL

IOL = 50 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

ÎÎ

0.0

ÎÎÎ

0.1

ÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

0.1

ÎÎ

ÎÎÎÎÎÎÎ

VIN = VIH or VIL

IOL = 4 mA

IOL = 8 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

ÎÎ

ÎÎÎ

0.36

ÎÎÎ

0.44

ÎÎÎ

ÎÎÎÎ

0.52

ÎÎÎÎ

IIN

ÎÎÎÎÎÎÎ

Maximum Input Leak-

age Current

ÎÎÎÎÎÎÎ

VIN = 5.5 V or GND

ÎÎÎ

0 to

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

±0.1

ÎÎÎ

±1.0

ÎÎÎ

ÎÎÎÎ

±1.0

ÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎ

Maximum Quiescent

Supply Current

ÎÎÎÎÎÎÎ

VIN = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

1.0

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ICCT

ÎÎÎÎÎÎÎ

Quiescent Supply

Current

ÎÎÎÎÎÎÎ

Input: VIN = 3.4 V

Other Input: VCC or GND

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

1.35

ÎÎÎ

1.50

ÎÎÎ

ÎÎÎÎ

1.65

ÎÎ

ÎÎÎÎ

IOPD

ÎÎÎÎÎÎÎ

Output Leakage

Current

ÎÎÎÎÎÎÎ

VOUT = 5.5 V

ÎÎÎ

0.0

ÎÎÎ

ÎÎ

ÎÎÎ

0.5

ÎÎÎ

5.0

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎ

Maximum 3−State

Leakage Current

ÎÎÎÎÎÎÎ

VIN = VIH or VIL

VOUT = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

±0.25

ÎÎÎ

±2.5

ÎÎÎ

ÎÎÎÎ

±2.5

ÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎ

TA ≤ 85°C

ÎÎÎÎÎÎ

−55 ≤ TA ≤ 125°C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎ

Maximum Propagation

Delay, A to Y

(Figures 3 and 5)

ÎÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15pF

CL = 50pF

ÎÎÎ

5.6

8.1

ÎÎ

8.0

11.5

ÎÎÎ

1.0

ÎÎÎ

9.5

13.0

ÎÎÎ

ÎÎÎÎ

12.0

16.0

ÎÎ

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15pF

CL = 50pF

ÎÎÎ

3.8

5.3

ÎÎ

5.5

7.5

ÎÎÎ

1.0

ÎÎÎ

6.5

8.5

ÎÎÎ

ÎÎÎÎ

8.5

10.5

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎ

Maximum Output

Enable TIme,OE to Y

(Figures 4 and 5)

ÎÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15pF

RL = RI = 500 WCL = 50pF

ÎÎÎ

5.4

7.9

ÎÎ

8.0

11.5

ÎÎÎ

1.0

ÎÎÎ

9.5

13.0

ÎÎÎ

ÎÎÎÎ

11.5

15.0

ÎÎ

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15pF

RL = RI = 500 WCL = 50pF

ÎÎÎ

3.6

5.1

ÎÎ

5.1

7.1

ÎÎÎ

1.0

ÎÎÎ

6.0

8.0

ÎÎÎ

ÎÎÎÎ

7.5

9.5

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎ

Maximum Output

Disable Time,OE to Y

(Figures 4 and 5)

ÎÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15pF

RL = RI = 500 WCL = 50pF

ÎÎÎ

6.5

8.0

ÎÎ

9.7

13.2

ÎÎÎ

1.0

ÎÎÎ

11.5

15.0

ÎÎÎ

ÎÎÎÎ

14.5

18.0

ÎÎ

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15pF

RL = RI = 500 WCL = 50pF

ÎÎÎ

4.8

7.0

ÎÎ

6.8

8.8

ÎÎÎ

1.0

ÎÎÎ

8.0

10.0

ÎÎÎ

ÎÎÎÎ

10.0

12.0

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎ

Maximum Input

Capacitance

ÎÎÎÎÎÎÎÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎ

Maximum Three−State

Output Capacitance

(Output in High

Impedance State)

ÎÎÎÎÎÎÎÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

CPD Power Dissipation Capacitance (Note 5)

Typical @ 25°C, VCC = 5.0 V

5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC /4 (per buffer). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

MC74VHC1GT126

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SWITCHING WAVEFORMS

Figure 4. Switching Waveforms Figure 5.

50%

50% VCC

VCC

GND

HIGH

IMPEDANCE

VOL + 0.3V

VOH - 0.3V

tPZL tPLZ

tPZH tPHZ

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 6. Test Circuit

*Includes all probe and jig capacitance

Figure 7. Test Circuit

OUTPUT

TEST POINT

CL *

1 kWCONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

DEVICE

UNDER

TEST

HIGH

IMPEDANCE

50%

50% VCC

VCC

GND

tPLH tPHL

Figure 8. Input Equivalent Circuit

INPUT

ORDERING INFORMATION

Device Package Shipping†

M74VHC1GT126DF1G SC−88A / SOT−353 / SC−70

(Pb−Free)

3000 / Tape & Reel

M74VHC1GT126DF2G SC−88A / SOT−353 / SC−70

(Pb−Free)

M74VHC1GT126DT1G TSOP−5 / SOT−23 / SC−59

(Pb−Free)

NLVVHC1GT126DF1G* SC−88A / SOT−353 / SC−70

(Pb−Free)

NLVVHC1GT126DF2G* SC−88A / SOT−353 / SC−70

(Pb−Free)

NLVVHC1GT126DT1G* TSOP−5 / SOT−23 / SC−59

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

MC74VHC1GT126

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PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 419A−01 OBSOLETE. NEW STANDARD

419A−02.

4. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

DIM

MIN MAX MIN MAX

MILLIMETERS

1.80 2.200.071 0.087

INCHES

B1.15 1.350.045 0.053

C0.80 1.100.031 0.043

D0.10 0.300.004 0.012

G0.65 BSC0.026 BSC

H--- 0.10---0.004

J0.10 0.250.004 0.010

K0.10 0.300.004 0.012

N0.20 REF0.008 REF

S2.00 2.200.079 0.087

B0.2 (0.008) MM

12 3

D 5 PL

−B−

SC−88A (SC−70−5/SOT−353)

CASE 419A−02

ISSUE K

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PACKAGE DIMENSIONS

TSOP−5

CASE 483−02

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS

OF BASE MATERIAL.

4. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

5. OPTIONAL CONSTRUCTION: AN

ADDITIONAL TRIMMED LEAD IS ALLOWED

IN THIS LOCATION. TRIMMED LEAD NOT TO

EXTEND MORE THAN 0.2 FROM BODY.

DIM MIN MAX

MILLIMETERS

A3.00 BSC

B1.50 BSC

C0.90 1.10

D0.25 0.50

G0.95 BSC

H0.01 0.10

J0.10 0.26

K0.20 0.60

L1.25 1.55

M0 10

S2.50 3.00

123

54 S

0.7

0.028

1.0

0.039

ǒmm

inchesǓ

SCALE 10:1

0.95

0.037

2.4

0.094

1.9

0.074

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.20

CAB

T0.10

2X T0.20

NOTE 5

SEATING

PLANE

0.05

DETAIL Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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MC74VHC1GT126/D

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