MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 D Low Supply-Voltage Range: 1.8 V to 3.6 V D Ultralow Power Consumption D D D D D D D D D D D D D D - Active Mode: 330 A at 1 MHz, 2.2 V - Standby Mode: 1.1 A - Off Mode (RAM Retention): 0.2 A Five Power-Saving Modes Wake-Up From Standby Mode in Less Than 6 s 16-Bit RISC Architecture, 125-ns Instruction Cycle Time Three-Channel Internal DMA 12-Bit Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan Feature Dual 12-Bit Digital-to-Analog (D/A) Converters With Synchronization 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers On-Chip Comparator Serial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface Serial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface Supply Voltage Supervisor/Monitor With Programmable Level Detection Brownout Detector Bootstrap Loader I2C is a registered trademark of Philips Incorporated. D Serial Onboard Programming, D D D No External Programming Voltage Needed, Programmable Code Protection by Security Fuse Family Members Include - MSP430F155 16KB+256B Flash Memory 512B RAM - MSP430F156 24KB+256B Flash Memory 1KB RAM - MSP430F157 32KB+256B Flash Memory, 1KB RAM - MSP430F167 32KB+256B Flash Memory, 1KB RAM - MSP430F168 48KB+256B Flash Memory, 2KB RAM - MSP430F169 60KB+256B Flash Memory, 2KB RAM - MSP430F1610 32KB+256B Flash Memory 5KB RAM - MSP430F1611 48KB+256B Flash Memory 10KB RAM - MSP430F1612 55KB+256B Flash Memory 5KB RAM Available in 64-Pin QFP Package (PM) and 64-Pin QFN Package (RTD) For Complete Module Descriptions, See the MSP430x1xx Family User's Guide, Literature Number SLAU049 description The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2011, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 description (continued) The MSP430F15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430F161x series offers extended RAM addressing for memory-intensive applications and large C-stack requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc. AVAILABLE OPTIONS PACKAGED DEVICES TA -40C to 85C PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RTD) MSP430F155IPM MSP430F156IPM MSP430F157IPM MSP430F167IPM MSP430F168IPM MSP430F169IPM MSP430F1610IPM MSP430F1611IPM MSP430F1612IPM MSP430F155IRTD MSP430F156IRTD MSP430F157IRTD MSP430F167IRTD MSP430F168IRTD MSP430F169IRTD MSP430F1610IRTD MSP430F1611IRTD MSP430F1612IRTD For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DEVELOPMENT TOOL SUPPORT All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following: D Debugging and Programming Interface - MSP-FET430UIF (USB) - MSP-FET430PIF (Parallel Port) D Debugging and Programming Interface with Target Board - MSP-FET430U64 (PM package) D Standalone Target Board - MSP-TS430PM64 (PM package) D Production Programmer - 2 MSP-GANG430 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 pin designation, MSP430F155, MSP430F156, and MSP430F157 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK PM, RTD PACKAGE (TOP VIEW) 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/URXD0 P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 P3.1/SIMO0/SDA P3.2/SOMI0 P3.3/UCLK0/SCL P3.4/UTXD0 DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+ VREF-/VeREF- P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 pin designation, MSP430F167, MSP430F168, MSP430F169 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK PM, RTD PACKAGE (TOP VIEW) 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 P3.1/SIMO0/SDA P3.2/SOMI0 P3.3/UCLK0/SCL P3.4/UTXD0 DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+ VREF-/VeREF- P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 pin designation, MSP430F1610, MSP430F1611, MSP430F1612 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK PM, RTD PACKAGE (TOP VIEW) 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0 P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 P3.1/SIMO0/SDA P3.2/SOMI0 P3.3/UCLK0/SCL P3.4/UTXD0 DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+ VREF-/VeREF- P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 functional block diagram, MSP430F15x XIN XOUT DVCC DVSS AVCC AVSS P1 RST/NMI P2 8 ROSC Oscillator XT2IN System Clock XT2OUT ACLK 32KB Flash 1KB RAM ADC12 DAC12 SMCLK 24KB Flash 1KB RAM 16KB Flash 512B RAM 12-Bit 8 Channels <10s Conv. 12-Bit 2 Channels Voltage out P3 8 I/O Port 1/2 16 I/Os, with Interrupt Capability P4 8 P5 8 P6 8 I/O Port 3/4 16 I/Os 8 I/O Port 5/6 16 I/Os MCLK Test MAB, 4 Bit MAB,MAB, 16 Bit16-Bit JTAG CPU MCB Emulation Module Incl. 16 Reg. Bus Conv MDB, 16-Bit MDB, 16 Bit MDB, 8 Bit 4 TMS DMA Controller TCK TDI/TCLK 3 Channels Watchdog Timer 15/16-Bit TDO/TDI Timer_B3 Timer_A3 3 CC Reg Shadow Reg 3 CC Reg POR SVS Brownout Comparator A USART0 UART Mode SPI Mode I2C Mode functional block diagram, MSP430F16x XIN XOUT DVCC DVSS AVCC AVSS P1 RST/NMI P2 8 ROSC Oscillator XT2IN System Clock XT2OUT ACLK 60KB Flash 2KB RAM ADC12 DAC12 SMCLK 48KB Flash 2KB RAM 32KB Flash 1KB RAM 12-Bit 8 Channels <10s Conv. 12-Bit 2 Channels Voltage out P3 8 I/O Port 1/2 16 I/Os, with Interrupt Capability P4 8 P5 8 P6 8 I/O Port 3/4 16 I/Os 8 I/O Port 5/6 16 I/Os MCLK Test MAB, 4 Bit MAB,MAB, 16 Bit16-Bit JTAG CPU MCB Emulation Module Incl. 16 Reg. Bus Conv MDB, 16-Bit MDB, 16 Bit MDB, 8 Bit 4 TMS TCK TDI/TCLK TDO/TDI 6 Hardware Multiplier MPY, MPYS MAC,MACS DMA Controller 3 Channels Watchdog Timer 15/16-Bit Timer_B7 Timer_A3 7 CC Reg Shadow Reg 3 CC Reg POST OFFICE BOX 655303 POR SVS Brownout * DALLAS, TEXAS 75265 Comparator A USART0 USART1 UART Mode SPI Mode I2C Mode UART Mode SPI Mode MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 functional block diagram, MSP430F161x XIN XOUT DVCC DVSS AVCC AVSS P1 RST/NMI P2 8 ROSC Oscillator XT2IN System Clock XT2OUT ACLK 55KB Flash 5KB RAM ADC12 DAC12 SMCLK 48KB Flash 10KB RAM 32KB Flash 5KB RAM 12-Bit 8 Channels <10s Conv. 12-Bit 2 Channels Voltage out P3 8 I/O Port 1/2 16 I/Os, with Interrupt Capability P4 8 P5 8 P6 8 I/O Port 3/4 16 I/Os 8 I/O Port 5/6 16 I/Os MCLK Test MAB, 4 Bit MAB,MAB, 16 Bit16-Bit JTAG CPU MCB Emulation Module Incl. 16 Reg. Bus Conv MDB, 16-Bit MDB, 16 Bit MDB, 8 Bit 4 TMS TCK TDI/TCLK TDO/TDI Hardware Multiplier MPY, MPYS MAC,MACS DMA Controller 3 Channels Watchdog Timer 15/16-Bit Timer_B7 Timer_A3 7 CC Reg Shadow Reg 3 CC Reg POST OFFICE BOX 655303 POR SVS Brownout * DALLAS, TEXAS 75265 Comparator A USART0 USART1 UART Mode SPI Mode I2C Mode UART Mode SPI Mode 7 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12. AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12. DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts. DVSS 63 P1.0/TACLK 12 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 13 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O pin/SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output P2.0/ACLK 20 I/O General-purpose digital I/O pin/ACLK output P2.1/TAINCLK 21 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive P2.3/CA0/TA1 23 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input P2.5/Rosc 25 I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency P2.6/ADC12CLK/ DMAE0 26 I/O General-purpose digital I/O pin/conversion clock - 12-bit ADC/DMA channel 0 external trigger P2.7/TA0 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output P3.0/STE0 28 I/O General-purpose digital I/O pin/slave transmit enable - USART0/SPI mode P3.1/SIMO0/SDA 29 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode, I2C data - USART0/I2C mode P3.2/SOMI0 30 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode P3.3/UCLK0/SCL 31 I/O General-purpose digital I/O pin/external clock input - USART0/UART or SPI mode, clock output - USART0/SPI mode, I2C clock - USART0/I2C mode P3.4/UTXD0 32 I/O General-purpose digital I/O pin/transmit data out - USART0/UART mode P3.5/URXD0 33 I/O General-purpose digital I/O pin/receive data in - USART0/UART mode P3.6/UTXD1 34 I/O General-purpose digital I/O pin/transmit data out - USART1/UART mode P3.7/URXD1 35 I/O General-purpose digital I/O pin/receive data in - USART1/UART mode P4.0/TB0 36 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output P4.2/TB2 38 I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3/TB3 39 I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output P4.4/TB4 40 I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output P4.5/TB5 41 I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output P4.6/TB6 42 I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output P4.7/TBCLK 43 I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input P5.0/STE1 44 I/O General-purpose digital I/O pin/slave transmit enable - USART1/SPI mode P5.1/SIMO1 45 I/O General-purpose digital I/O pin/slave in/master out of USART1/SPI mode P5.2/SOMI1 46 I/O General-purpose digital I/O pin/slave out/master in of USART1/SPI mode P5.3/UCLK1 47 I/O General-purpose digital I/O pin/external clock input - USART1/UART or SPI mode, clock output - USART1/SPI mode 8 Digital supply voltage, negative terminal. Supplies all digital parts. 16x, 161x devices only POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION P5.4/MCLK 48 I/O General-purpose digital I/O pin/main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O pin/auxiliary clock ACLK output P5.7/TBOUTH/ SVSOUT 51 I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance - Timer_B TB0 to TB6/SVS comparator output P6.0/A0 59 I/O General-purpose digital I/O pin/analog input a0 - 12-bit ADC P6.1/A1 60 I/O General-purpose digital I/O pin/analog input a1 - 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O pin/analog input a2 - 12-bit ADC P6.3/A3 2 I/O General-purpose digital I/O pin/analog input a3 - 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O pin/analog input a4 - 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O pin/analog input a5 - 12-bit ADC P6.6/A6/DAC0 5 I/O General-purpose digital I/O pin/analog input a6 - 12-bit ADC/DAC12.0 output P6.7/A7/DAC1/ SVSIN 6 I/O General-purpose digital I/O pin/analog input a7 - 12-bit ADC/DAC12.1 output/SVS input RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). TCK 57 I Test clock. TCK is the clock input port for device programming test and bootstrap loader start TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ 10 I Input for an external reference voltage VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12 VREF-/VeREF- 11 I Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1 XT2IN 53 I Input port for crystal oscillator XT2. Only standard crystals can be connected. XT2OUT 52 O Output terminal of crystal oscillator XT2 QFN Pad NA NA Test data output port. TDO/TDI data output or programming data input terminal QFN package pad connection to DVSS recommended (RTD package only) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 shows the address modes. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ---> R5 Single operands, destination only e.g., CALL PC -->(TOS), R8--> PC Relative jump, un/conditional e.g., JNE R8 Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE Indirect D D D D D Indirect autoincrement Register Indexed Symbolic (PC relative) Absolute Immediate NOTE: S = source 10 S D D D D D SYNTAX EXAMPLE MOV Rs,Rd MOV R10,R11 MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) MOV EDE,TONI OPERATION R10 --> R11 M(2+R5)--> M(6+R6) M(EDE) --> M(TONI) MOV &MEM,&TCDAT M(MEM) --> M(TCDAT) MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) --> M(Tab+R6) D MOV @Rn+,Rm MOV @R10+,R11 M(R10) --> R11 R10 + 2--> R10 D MOV #X,TONI MOV #45,TONI D = destination POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 #45 --> M(TONI) MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM - All clocks are active D Low-power mode 0 (LPM0) - CPU is disabled - ACLK and SMCLK remain active. MCLK is disabled D Low-power mode 1 (LPM1) - CPU is disabled - ACLK and SMCLK remain active. MCLK is disabled - DCO's dc generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2) - CPU is disabled - MCLK and SMCLK are disabled - DCO's dc generator remains enabled - ACLK remains active D Low-power mode 3 (LPM3) - CPU is disabled - MCLK and SMCLK are disabled - DCO's dc generator is disabled - ACLK remains active D Low-power mode 4 (LPM4) - CPU is disabled - ACLK is disabled - MCLK and SMCLK are disabled - DCO's dc generator is disabled - Crystal oscillator is stopped POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External Reset Watchdog Flash memory WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator Fault Flash memory access violation NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 3) ACCVIFG (see Notes 1 and 3) (Non)maskable (Non)maskable (Non)maskable 0FFFCh 14 Timer_B7 (see Note 5) TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13 TBCCR1 to TBCCR6 CCIFGs, TBIFG (see Notes 1 and 2) Maskable 0FFF8h 12 Timer_B7 (see Note 5) Comparator_A CAIFG Maskable 0FFF6h 11 Watchdog timer WDTIFG Maskable 0FFF4h 10 USART0 receive URXIFG0 Maskable 0FFF2h 9 USART0 transmit I2C transmit/receive/others UTXIFG0 I2CIFG (see Note 4) Maskable 0FFF0h 8 ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 7 Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6 Timer_A3 TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4 USART1 receive URXIFG1 Maskable 0FFE6h 3 USART1 transmit UTXIFG1 Maskable 0FFE4h 2 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1 Maskable 0FFE0h 0, lowest DAC12 DMA NOTES: 1. 2. 3. 4. 5. 12 DAC12_0IFG, DAC12_1IFG DMA0IFG, DMA1IFG, DMA2IFG (see Notes 1 and 2) Multiple source flags Interrupt flags are located in the module. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. I2C interrupt flags located in the module Timer_B7 in MSP430F16x/161x family has 7 CCRs; Timer_B3 in MSP430F15x family has 3 CCRs; in Timer_B3 there are only interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 7 Address 0h 6 UTXIE0 rw-0 URXIE0 rw-0 5 4 ACCVIE NMIIE rw-0 3 2 1 OFIE rw-0 rw-0 Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as general-purpose timer. OFIE: Oscillator fault interrupt enable NMIIE: Nonmaskable interrupt enable ACCVIE: Flash memory access violation interrupt enable URXIE0: USART0: UART and SPI receive-interrupt enable UTXIE0: USART0: UART and SPI transmit-interrupt enable 7 6 01h 5 4 UTXIE1 URXIE1 rw-0 3 2 1 0 2 1 0 rw-0 URXIE1: USART1: UART and SPI receive interrupt enable UTXIE1: USART1: UART and SPI transmit interrupt enable WDTIE rw-0 WDTIE: Address 0 URXIE1 and UTXIE1 are not present in MSP430F15x devices. interrupt flag register 1 and 2 7 Address 02h 6 UTXIFG0 rw-1 5 URXIFG0 4 3 NMIIFG rw-0 OFIFG rw-0 rw-1 WDTIFG rw-(0) WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin URXIFG0: USART0: UART and SPI receive flag UTXIFG0: USART0: UART and SPI transmit flag Address 7 03h 6 5 4 UTXIFG1 URXIFG1 rw-1 URXIFG1: 3 2 1 0 rw-0 USART1: UART and SPI receive flag UTXIFG1: USART1: UART and SPI transmit flag URXIFG1 and UTXIFG1 are not present in MSP430F15x devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 module enable registers 1 and 2 7 UTXE0 Address 04h rw-0 6 URXE0 USPIE0 5 3 USART0: UART mode receive enable UTXE0: USART0: UART mode transmit enable USPIE0: USART0: SPI mode transmit and receive enable 05h 7 6 5 UTXE1 rw-0 4 URXE1 USPIE1 3 rw-0 URXE1: USART1: UART mode receive enable UTXE1: USART1: UART mode transmit enable USPIE1: USART1: SPI mode transmit and receive enable URXE1, UTXE1, and USPIE1 are not present in MSP430F15x devices. Legend: rw: rw-0: 2 1 0 2 1 0 rw-0 URXE0: Address 14 4 Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 memory organization, MSP430F15x MSP430F155 MSP430F156 MSP430F157 Memory Main: interrupt vector Main: code memory Size Flash Flash 16KB 0FFFFh - 0FFE0h 0FFFFh - 0C000h 24KB 0FFFFh - 0FFE0h 0FFFFh - 0A000h 32KB 0FFFFh - 0FFE0h 0FFFFh - 08000h Information memory Size Flash 256 Byte 010FFh - 01000h 256 Byte 010FFh - 01000h 256 Byte 010FFh - 01000h Boot memory Size ROM 1KB 0FFFh - 0C00h 1KB 0FFFh - 0C00h 1KB 0FFFh - 0C00h Size 512B 03FFh - 0200h 1KB 05FFh - 0200h 1KB 05FFh - 0200h 16-bit 8-bit 8-bit SFR 01FFh - 0100h 0FFh - 010h 0Fh - 00h 01FFh - 0100h 0FFh - 010h 0Fh - 00h 01FFh - 0100h 0FFh - 010h 0Fh - 00h RAM Peripherals memory organization, MSP430F16x MSP430F167 MSP430F168 MSP430F169 Memory Main: interrupt vector Main: code memory Size Flash Flash 32KB 0FFFFh - 0FFE0h 0FFFFh - 08000h 48KB 0FFFFh - 0FFE0h 0FFFFh - 04000h 60KB 0FFFFh - 0FFE0h 0FFFFh - 01100h Information memory Size Flash 256 Byte 010FFh - 01000h 256 Byte 010FFh - 01000h 256 Byte 010FFh - 01000h Boot memory Size ROM 1KB 0FFFh - 0C00h 1KB 0FFFh - 0C00h 1KB 0FFFh - 0C00h Size 1KB 05FFh - 0200h 2KB 09FFh - 0200h 2KB 09FFh - 0200h 16-bit 8-bit 8-bit SFR 01FFh - 0100h 0FFh - 010h 0Fh - 00h 01FFh - 0100h 0FFh - 010h 0Fh - 00h 01FFh - 0100h 0FFh - 010h 0Fh - 00h RAM Peripherals memory organization, MSP430F161x MSP430F1610 MSP430F1611 MSP430F1612 Size Flash Flash 32KB 0FFFFh - 0FFE0h 0FFFFh - 08000h 48KB 0FFFFh - 0FFE0h 0FFFFh - 04000h 55KB 0FFFFh - 0FFE0h 0FFFFh - 02500h Size 5KB 024FFh - 01100h 10KB 038FFh - 01100h 5KB 024FFh - 01100h Extended Size 3KB 024FFh - 01900h 8KB 038FFh - 01900h 3KB 024FFh - 01900h Mirrored Size 2KB 018FFh - 01100h 2KB 018FFh - 01100h 2KB 018FFh - 01100h Information memory Size Flash 256 Byte 010FFh - 01000h 256 Byte 010FFh - 01000h 256 Byte 010FFh - 01000h Boot memory Size ROM 1KB 0FFFh - 0C00h 1KB 0FFFh - 0C00h 1KB 0FFFh - 0C00h Size 2KB 09FFh - 0200h 2KB 09FFh - 0200h 2KB 09FFh - 0200h 16-bit 8-bit 8-bit SFR 01FFh - 0100h 0FFh - 010h 0Fh - 00h 01FFh - 0100h 0FFh - 010h 0Fh - 00h 01FFh - 0100h 0FFh - 010h 0Fh - 00h Memory Main: interrupt vector Main: code memory RAM (Total) RAM (mirrored at 018FFh - 01100h) Peripherals POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL FUNCTION PM, RTD PACKAGE PINS Data Transmit 13 - P1.1 Data Receive 22 - P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B are also called information memory. D New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. MSP430F161x MSP430F15x and MSP430F16x 16KB 24KB 32KB 48KB 60KB 32KB 48KB 55KB 0FFFFh 0FFFFh 0FFFFh 0FFFFh 0FFFFh 0FFFFh 0FFFFh 0FFFFh 0FE00h 0FDFFh 0FE00h 0FDFFh 0FE00h 0FDFFh 0FE00h 0FDFFh 0FE00h 0FDFFh 0FE00h 0FDFFh 0FE00h 0FDFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FC00h 0FBFFh 0FC00h 0FBFFh 0FC00h 0FBFFh 0FC00h 0FBFFh 0FC00h 0FBFFh 0FC00h 0FBFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0FA00h 0F9FFh 0FA00h 0F9FFh 0FA00h 0F9FFh 0FA00h 0F9FFh 0FA00h 0F9FFh 0FA00h 0F9FFh 0FA00h 0F9FFh 0C400h 0C3FFh 0A400h 0A3FFh 08400h 083FFh 04400h 043FFh 01400h 013FFh 08400h 083FFh 04400h 043FFh 02800h 027FFh 0C200h 0C1FFh 0A200h 0A1FFh 08200h 081FFh 04200h 041FFh 01200h 011FFh 08200h 081FFh 04200h 041FFh 02600h 025FFh 0C000h 0A000h 08000h 04000h 01100h 08000h 024FFh 04000h 038FFh 02500h 024FFh Segment 0 w/ Interrupt Vectors Segment 1 Segment 2 Main Memory Segment n-1 010FFh 010FFh 010FFh 010FFh 010FFh 01100h 010FFh 01100h 010FFh 01100h 010FFh 01080h 0107Fh 01080h 0107Fh 01080h 0107Fh 01080h 0107Fh 01080h 0107Fh 01080h 0107Fh 01080h 0107Fh 01080h 0107Fh 01000h 01000h 01000h 01000h 01000h 01000h 01000h 01000h Segment n RAM ('F161x only) Segment A Info Memory Segment B 16 MSP430F169 and MSP430F1612 flash segment n = 256 bytes. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User's Guide, literature number SLAU049. DMA controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral. oscillator and system clock The clock system in the MSP430F15x and MSP430F16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. brownout, supply voltage supervisor (SVS) The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min). digital I/O There are six 8-bit I/O ports implemented--ports P1 through P6: D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. hardware multiplier (MSP430F16x/161x only) The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16, 16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 USART0 The MSP430F15x and the MSP430F16x(x) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels. The I2C support is compliant with the Philips I2C specification version 2.1 and supports standard mode (up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported, as well as master and slave modes. The USART0 also supports 16-bit-wide I2C data transfers and has two dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C mode. USART1 (MSP430F16x/161x only) The MSP430F16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. With the exception of I2C support, operation of USART1 is identical to USART0. Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A3 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 12 - P1.0 TACLK TACLK ACLK ACLK SMCLK SMCLK 21 - P2.1 TAINCLK INCLK 13 - P1.1 TA0 CCI0A 22 - P2.2 14 - P1.2 15 - P1.3 TA0 CCI0B DVSS GND DVCC VCC TA1 CCI1A CAOUT (internal) CCI1B DVSS GND MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER 13 - P1.1 17 - P1.5 CCR0 TA0 27 - P2.7 14 - P1.2 18 - P1.6 CCR1 TA1 23 - P2.3 DVCC VCC ADC12 (internal) TA2 CCI2A 15 - P1.3 ACLK (internal) CCI2B DVSS GND DVCC VCC 19 - P1.7 CCR2 TA2 24 - P2.4 Timer_B3 (MSP430F15x only) Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 Timer_B7 (MSP430F16x/161x only) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_B3/B7 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 43 - P4.7 TBCLK TBCLK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER ACLK ACLK SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A 36 - P4.0 36 - P4.0 TB0 CCI0B ADC12 (internal) DVSS GND 37 - P4.1 37 - P4.1 DVCC VCC TB1 CCI1A TB1 CCI1B DVSS GND DVCC VCC 38 - P4.2 TB2 CCI2A 38 - P4.2 TB2 CCI2B DVSS GND 39 - P4.3 39 - P4.3 DVCC VCC TB3 CCI3A TB3 CCI3B DVSS GND DVCC VCC 40 - P4.4 TB4 CCI4A 40 - P4.4 TB4 CCI4B DVSS GND 41 - P4.5 41 - P4.5 42 - P4.6 MODULE BLOCK DVCC VCC TB5 CCI5A TB5 CCI5B DVSS GND DVCC VCC TB6 CCI6A ACLK (internal) CCI6B DVSS GND DVCC VCC CCR0 TB0 37 - P4.1 ADC12 (internal) CCR1 TB1 38 - P4.2 CCR2 TB2 39 - P4.3 CCR3 TB3 40 - P4.4 CCR4 TB4 41 - P4.5 CCR5 TB5 42 - P4.6 CCR6 TB6 Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 Comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. ADC12 The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. DAC12 The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation. 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 peripheral file map PERIPHERAL FILE MAP DMA DAC12 ADC12 DMA channel 2 transfer size DMA2SZ 01F6h DMA channel 2 destination address DMA2DA 01F4h DMA channel 2 source address DMA2SA 01F2h DMA channel 2 control DMA2CTL 01F0h DMA channel 1 transfer size DMA1SZ 01EEh DMA channel 1 destination address DMA1DA 01ECh DMA channel 1 source address DMA1SA 01EAh DMA channel 1 control DMA1CTL 01E8h DMA channel 0 transfer size DMA0SZ 01E6h DMA channel 0 destination address DMA0DA 01E4h DMA channel 0 source address DMA0SA 01E2h DMA channel 0 control DMA0CTL 01E0h DMA module control 1 DMACTL1 0124h DMA module control 0 DMACTL0 0122h DAC12_1 data DAC12_1DAT 01CAh DAC12_1 control DAC12_1CTL 01C2h DAC12_0 data DAC12_0DAT 01C8h DAC12_0 control DAC12_0CTL 01C0h Interrupt-vector-word register ADC12IV 01A8h Inerrupt-enable register ADC12IE 01A6h Inerrupt-flag register ADC12IFG 01A4h Control register 1 ADC12CTL1 01A2h Control register 0 ADC12CTL0 01A0h Conversion memory 15 ADC12MEM15 015Eh Conversion memory 14 ADC12MEM14 015Ch Conversion memory 13 ADC12MEM13 015Ah Conversion memory 12 ADC12MEM12 0158h Conversion memory 11 ADC12MEM11 0156h Conversion memory 10 ADC12MEM10 0154h Conversion memory 9 ADC12MEM9 0152h Conversion memory 8 ADC12MEM8 0150h Conversion memory 7 ADC12MEM7 014Eh Conversion memory 6 ADC12MEM6 014Ch Conversion memory 5 ADC12MEM5 014Ah Conversion memory 4 ADC12MEM4 0148h Conversion memory 3 ADC12MEM3 0146h Conversion memory 2 ADC12MEM2 0144h Conversion memory 1 ADC12MEM1 0142h Conversion memory 0 ADC12MEM0 0140h POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) ADC12 (continued) Timer_B7/ _ Timer_B3 (see Note 1) Timer_A3 _ ADC memory-control register15 ADC12MCTL15 08Fh ADC memory-control register14 ADC12MCTL14 08Eh ADC memory-control register13 ADC12MCTL13 08Dh ADC memory-control register12 ADC12MCTL12 08Ch ADC memory-control register11 ADC12MCTL11 08Bh ADC memory-control register10 ADC12MCTL10 08Ah ADC memory-control register9 ADC12MCTL9 089h ADC memory-control register8 ADC12MCTL8 088h ADC memory-control register7 ADC12MCTL7 087h ADC memory-control register6 ADC12MCTL6 086h ADC memory-control register5 ADC12MCTL5 085h ADC memory-control register4 ADC12MCTL4 084h ADC memory-control register3 ADC12MCTL3 083h ADC memory-control register2 ADC12MCTL2 082h ADC memory-control register1 ADC12MCTL1 081h ADC memory-control register0 ADC12MCTL0 080h Capture/compare register 6 TBCCR6 019Eh Capture/compare register 5 TBCCR5 019Ch Capture/compare register 4 TBCCR4 019Ah Capture/compare register 3 TBCCR3 0198h Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control 6 TBCCTL6 018Eh Capture/compare control 5 TBCCTL5 018Ch Capture/compare control 4 TBCCTL4 018Ah Capture/compare control 3 TBCCTL3 0188h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh Reserved 017Eh Reserved 017Ch Reserved 017Ah Reserved 0178h Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Reserved 016Eh Reserved 016Ch Reserved 016Ah Reserved 0168h NOTE 1: Timer_B7 in MSP430F16x/161x family has seven CCRs, Timer_B3 in MSP430F15x family has three CCRs. 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Timer_A3 _ (continued) Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Sum extend SUMEXT 013Eh Result high word RESHI 013Ch Result low word RESLO 013Ah Second operand OP2 0138h Multiply signed +accumulate/operand1 MACS 0136h Multiply+accumulate/operand1 MAC 0134h Multiply signed/operand1 MPYS 0132h Multiply unsigned/operand1 MPY 0130h Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h Watchdog Watchdog Timer control WDTCTL 0120h USART1 (MSP430F16x and MSP430F161x only) Transmit buffer U1TXBUF 07Fh Receive buffer U1RXBUF 07Eh Baud rate U1BR1 07Dh Baud rate U1BR0 07Ch Modulation control U1MCTL 07Bh Receive control U1RCTL 07Ah Transmit control U1TCTL 079h USART control U1CTL 078h Transmit buffer U0TXBUF 077h Receive buffer U0RXBUF 076h Baud rate U0BR1 075h Baud rate U0BR0 074h Modulation control U0MCTL 073h Receive control U0RCTL 072h Transmit control U0TCTL 071h USART control U0CTL 070h I2C interrupt vector I2CIV 011Ch I2C slave address I2CSA 011Ah I2C own address I2COA 0118h I2C data I2CDR 076h I2C SCLL I2CSCLL 075h I2C SCLH I2CSCLH 074h I2C PSC I2CPSC 073h I2C data control I2CDCTL 072h I2C transfer control I2CTCTL 071h USART control U0CTL 070h I2C data count I2CNDAT 052h I2C interrupt flag I2CIFG 051h I2C interrupt enable I2CIE 050h Hardware Multiplier (MSP430F16x and MSP430F161x only) Flash USART0 (UART or SPI mode) USART0 (I2C mode) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Comparator_A p _ Comparator_A port disable CAPD 05Bh Comparator_A control2 CACTL2 05Ah Comparator_A control1 CACTL1 059h Basic clock system control2 BCSCTL2 058h Basic clock system control1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 055h Port P6 Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag2 IFG2 003h SFR interrupt flag1 IFG1 002h SFR interrupt enable2 IE2 001h SFR interrupt enable1 IE1 000h Basic Clock Port P5 Port P4 Port P3 Port P2 Port P1 Special p Functions 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature, Tstg: Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 85C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. recommended operating conditions MIN NOM MAX UNIT Supply voltage during program execution, VCC (AVCC = DVCC = VCC) MSP430F15x/16x/161x 1.8 3.6 V Supply voltage during flash memory programming, VCC (AVCC = DVCC = VCC) MSP430F15x/16x/161x 2.7 3.6 V Supply voltage during program execution, SVS enabled (see Note 1), VCC (AVCC = DVCC = VCC) MSP430F15x/16x/161x 2 3.6 V 0 0 V MSP430F15x/16x/161x -40 85 C Supply voltage, VSS (AVSS = DVSS = VSS) Operating free-air temperature range, TA t l frequency, f f(LFXT1) LFXT1 crystal (see Notes 2 and 3) LF selected, XTS=0 Watch crystal 32.768 XT1 selected, XTS=1 Ceramic resonator XT1 selected, XTS=1 Crystal 450 8000 kHz 1000 8000 kHz 450 8000 1000 8000 VCC = 1.8 V DC 4.15 VCC = 3.6 V DC 8 Ceramic resonator XT2 crystal frequency, frequency f(XT2) Crystal MCLK) f(System) Processor frequency (signal MCLK), kHz kHz MHz NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the VCC is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1-M resistor from XOUT to VSS is recommended when VCC < 2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15 MHz at VCC 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8 MHz at VCC 2.8 V. 3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. f (MHz) 8.0 MHz IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII Supply voltage range, 'F15x/16x/161x, during program execution 4.15 MHz 1.8 V 2.7 V 3 V Supply Voltage - V Supply voltage range, 'F15x/16x/161x, during flash memory programming 3.6 V Figure 1. Frequency vs Supply Voltage, MSP430F15x/16x/161x POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP430F15x/16x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC) PARAMETER I(AM) I(LPM0) I(LPM2) TEST CONDITIONS Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) 40C to 85C TA = -40C Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 4,096 Hz, f(ACLK) = 4,096 Hz XTS=0, SELM=3 TA = -40C 40C to 85C Low-power mode, (LPM0) f((MCLK)) = 0 MHz, f(SMCLK) ( ) = 1 MHz, f(ACLK) = 32,768 32 768 Hz XTS=0, SELM=(0,1) (see Note 1) TA = -40C 40C to 85C Low-power mode, (LPM2), f(MCLK) = f(SMCLK) = 0 MHz, MHz f(ACLK) = 32.768 Hz, SCG0 = 0 TA = -40C 40C to 85C VCC TYP MAX 2.2 V 330 400 3V 500 600 2.2 V 2.5 7 3V 9 20 2.2 V 50 60 I(LPM3) I(LPM4) Low-power mode, mode (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 ( (see N Note t 2) A A A A 3V 75 90 2.2 V 11 14 3V 17 22 1.1 1.6 1.1 1.6 TA = 85C 2.2 3.0 TA = -40C 2.2 2.8 TA = 25C Low-power mode, (LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 2.2 V 2.0 2.6 TA = 85C 3.0 4.3 TA = -40C 0.1 0.5 0.2 0.5 1.3 2.5 TA = 25C TA = 85C UNIT A A TA = -40C TA = 25C MIN 3V 2.2V / 3 V A A A A A NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. WDT is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected. Current consumption of active mode versus system frequency I(AM) = I(AM) [1 MHz] x f(System) [MHz] Current consumption of active mode versus supply voltage I(AM) = I(AM) [3 V] + 210 A/V x (VCC - 3 V) 26 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP430F161x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC) PARAMETER I(AM) I(LPM0) I(LPM2) TEST CONDITIONS Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) 40C to 85C TA = -40C Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 4,096 Hz, f(ACLK) = 4,096 Hz XTS=0, SELM=3 TA = -40C 40C to 85C Low-power mode, (LPM0) f((MCLK)) = 0 MHz, f(SMCLK) ( ) = 1 MHz, f(ACLK) = 32,768 32 768 Hz XTS=0, SELM=(0,1) (see Note 1) TA = -40C 40C to 85C Low-power mode, (LPM2), f(MCLK) = f(SMCLK) = 0 MHz, MHz f(ACLK) = 32.768 Hz, SCG0 = 0 TA = -40C 40C to 85C VCC TYP MAX 2.2 V 330 400 3V 500 600 2.2 V 2.5 7 3V 9 20 2.2 V 50 60 I(LPM3) I(LPM4) Low-power mode, mode (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 ( (see N Note t 2) A A A A 3V 75 95 2.2 V 11 14 3V 17 22 1.3 1.6 1.3 1.6 TA = 85C 3.0 6.0 TA = -40C 2.6 3.0 TA = 25C Low-power mode, (LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 2.2 V 2.6 3.0 TA = 85C 4.4 8.0 TA = -40C 0.2 0.5 0.2 0.5 2.0 5.0 TA = 25C TA = 85C UNIT A A TA = -40C TA = 25C MIN 3V 2.2V / 3 V A A A A A NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. WDT is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected. Current consumption of active mode versus system frequency I(AM) = I(AM) [1 MHz] x f(System) [MHz] Current consumption of active mode versus supply voltage I(AM) = I(AM) [3 V] + 210 A/V x (VCC - 3 V) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI) PARAMETER VIT+ Positive going input threshold voltage Positive-going VIT- Negative going input threshold voltage Negative-going Vhys Input voltage hysteresis (VIT+ - VIT-) VCC MIN TYP MAX 2.2 V 1.1 1.5 3V 1.5 1.98 2.2 V 0.4 0.9 3V 0.9 1.3 2.2 V 0.3 1.1 3V 0.5 1 UNIT V V V inputs Px.x, TAx, TBx PARAMETER TEST CONDITIONS VCC MIN Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag (see Note 1) 2.2 V 62 3V 50 TA0, TA1, TA2 2.2 V 62 3V 50 t(int) External interrupt timing t(cap) Timer_A, Timer_B capture timing f(TAext) Timer_A, Timer_B clock frequency externally applied to pin TACLK TBCLK TACLK, TBCLK, INCLK: t(H) = t(L) Timer A Timer Timer_A, Timer_B B clock frequency SMCLK or ACLK signal selected f(TBext) f(TAint) f(TBint) TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see Note 2) TYP MAX UNIT ns ns 2.2 V 8 3V 10 2.2 V 8 3V 10 MHz MHz NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter than t(int). 2. Seven capture/compare registers in 'F16x/161x and three capture/compare registers in 'F15x. leakage current - ports P1, P2, P3, P4, P5, P6 (see Note 1) PARAMETER Ilkg(Px.y) Leakage current TEST CONDITIONS Port Px V(Px.y) (see Note 2) VCC MIN TYP 2.2 V/3 V NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input. 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MAX UNIT 50 nA MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs - ports P1, P2, P3, P4, P5, P6 PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level TEST CONDITIONS MIN TYP MAX IOH(max) = -1.5 mA, VCC = 2.2 V, See Note 1 VCC-0.25 VCC IOH(max) = -6 mA, VCC = 2.2 V, See Note 2 VCC-0.6 VCC IOH(max) = -1.5 mA, VCC = 3 V, See Note 1 VCC-0.25 VCC IOH(max) = -6 mA, VCC = 3 V, See Note 2 VCC-0.6 VCC IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25 IOL(max) = 6 mA, VCC = 2.2 V, See Note 2 VSS VSS+0.6 IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25 IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6 UNIT V V NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to satisfy the maximum specified voltage drop. output frequency PARAMETER TEST CONDITIONS MIN f(Px.y) 6 0 y 7) (1 x 6, CL = 20 pF, IL = 1.5 mA 2V/3V VCC = 2 2.2 f(ACLK) f(MCLK) f(SMCLK) P2.0/ACLK, P5.6/ACLK P5 4/MCLK P5.4/MCLK, P1.4/SMCLK, P5.5/SMCLK CL = 20 pF VCC = 2 2.2 2V/3V P1.0/TACLK CL = 20 pF VCC = 2.2 V / 3 V f(ACLK) = f(LFXT1) = f(XT1) 40% f(ACLK) = f(LFXT1) = f(LF) 30% P1.1/TA0/MCLK, CL = 20 pF, VCC = 2.2 V / 3 V f(MCLK) = f(XT1) P1.4/TBCLK/SMCLK, CL = 20 pF, VCC = 2.2 V / 3 V f(SMCLK) = f(XT2) t(Xdc) Duty cycle of output frequency POST OFFICE BOX 655303 DC f(SMCLK) = f(DCOCLK) * DALLAS, TEXAS 75265 MAX UNIT fSystem MHz fSystem f(ACLK) = f(LFXT1) f(MCLK) = f(DCOCLK) TYP MHz 60% 70% 50% 40% 50%- 15 ns 60% 50% 50%+ 15 ns 40% 60% 50%- 15 ns 50% 50%+ 15 ns 29 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs - ports P1, P2, P3, P4, P5, P6 (continued) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 40 TA = 25C VCC = 2.2 V P3.5 I OL - Low-Level Output Current - mA I OL - Low-Level Output Current - mA 25 20 TA = 85C 15 10 5 0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P3.5 TA = 85C 30 20 10 0 0.0 2.5 TA = 25C 0.5 VOL - Low-Level Output Voltage - V 1.0 1.5 2.0 2.5 3.0 3.5 VOL - Low-Level Output Voltage - V Figure 3 Figure 2 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P3.5 I OH - High-Level Output Current - mA I OH - High-Level Output Current - mA 0 -5 -10 -15 TA = 85C -20 -5 VCC = 3 V P3.5 -15 -25 -35 TA = 85C TA = 25C -25 0.0 0.5 TA = 25C 1.0 1.5 2.0 2.5 -45 0.0 0.5 VOH - High-Level Output Voltage - V 1.5 Figure 5 POST OFFICE BOX 655303 2.0 2.5 3.0 VOH - High-Level Output Voltage - V Figure 4 30 1.0 * DALLAS, TEXAS 75265 3.5 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER t(LPM3) TEST CONDITIONS MIN TYP VCC = 2.2 V/3 V, fDCO fDCO43 Delay time MAX 6 UNIT s RAM PARAMETER VRAMh TEST CONDITIONS See Note 1 CPU HALTED MIN TYP MAX 1.6 UNIT V NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. Comparator_A (see Note 1) PARAMETER TEST CONDITIONS I(DD) CAON=1 CARSEL=0, CAON=1, CARSEL=0 CAREF=0 I(Refladder/Refdiode) CAON=1, CARSEL=0, CAREF 1/2/3 no load at CAREF=1/2/3, P2.3/CA0/TA1 and P2.4/CA1/TA2 V(IC) V(Ref025) Common-mode input voltage Voltage @ 0.25 V V V(Ref050) CC node CC Voltage @ 0.5V V CC node CC VCC TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 CAON =1 2.2 V/3 V 0 PCA0=1, CARSEL=1, CAREF=1, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.23 0.24 0.25 PCA0=1, CARSEL=1, CAREF=2, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.47 0.48 0.5 2.2 V 390 480 540 3V 400 490 550 -30 PCA0=1, CARSEL=1, CAREF=3, no load at P2.3/CA0/TA1 P2 3/CA0/TA1 and P2.4/CA1/TA2 TA = 85C V(RefVT) (see Figure 6 and Figure 7) V(offset) Offset voltage See Note 2 2.2 V/3 V Vhys Input hysteresis CAON=1 2.2 V/3 V t(response LH) t(response HL) MIN VCC-1 UNIT A A V mV 30 mV mV 0 0.7 1.4 TA = 25 25C, C, Overdrive 10 mV, Without filter: CAF=0 2.2 V 130 210 300 3V 80 150 240 TA = 25 25C, C, Overdrive 10 mV, With filter: CAF=1 2.2 V 1.4 1.9 3.4 3V 0.9 1.5 2.6 TA = 25 25C, C, Overdrive 10 mV, Without filter: CAF=0 2.2 V 130 210 300 3V 80 150 240 TA = 25 25C, C, Overdrive 10 mV, With filter: CAF=1 2.2 V 1.4 1.9 3.4 3V 0.9 1.5 2.6 ns s ns s NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 650 650 VCC = 2.2 V V(REFVT) - Reference Volts -mV V(REFVT) - Reference Volts -mV VCC = 3 V 600 Typical 550 500 450 400 -45 -25 -5 15 35 55 75 600 Typical 550 500 450 400 -45 95 -25 TA - Free-Air Temperature - C 0 15 35 55 VCC 1 CAF CAON Low Pass Filter V+ V- + _ 0 0 1 1 To Internal Modules CAOUT Set CAIFG Flag 2.0 s Figure 8. Block Diagram of Comparator_A Module VCAOUT Overdrive V- 400 mV V+ t(response) Figure 9. Overdrive Definition 32 75 95 Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V Figure 6. V(RefVT) vs Temperature, VCC = 3 V 0V -5 TA - Free-Air Temperature - C POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP td(BOR) VCC(Start) dVCC/dt 3 V/s (see Figure 10) V(B_IT-) dVCC/dt 3 V/s (see Figure 10 through Figure 12) Vhys(B_IT-) Brownout t(reset) MAX UNIT 2000 s 0.7 x V(B_IT-) dVCC/dt 3 V/s (see Figure 10) 70 Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V/3 V 2 130 V 1.71 V 180 mV s NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is 1.8 V. 2. During power up, the CPU begins code execution following a period of tBOR(delay) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x1xx Family User's Guide (SLAU049) for more information on the brownout/SVS circuit. typical characteristics VCC Vhys(B_IT-) V(B_IT-) VCC(Start) BOR 1 0 t d(BOR) Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 33 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 typical characteristics (continued) VCC 3V 2 VCC(min)- V Vcc = 3 V typical conditions t pw 1.5 1 VCC(min) 0.5 0 0.001 1 1000 1 ns tpw - Pulse Width - s 1 ns tpw - Pulse Width - s Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC VCC(min)- V 2 1.5 t pw 3V Vcc = 3 V typical conditions 1 VCC(min) 0.5 0 0.001 tf = tr 1 1000 tf tr tpw - Pulse Width - s tpw - Pulse Width - s Figure 12. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal 34 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) SVS (supply voltage supervisor/monitor) PARAMETER t(SVSR) TEST CONDITIONS MIN dVCC/dt > 30 V/ms (see Figure 13) MAX 150 dVCC/dt 30 V/ms 2000 td(SVSon) SVSON, switch from VLD = 0 to VLD 0, VCC = 3 V tsettle VLD 0 V(SVSstart) VLD 0, VCC/dt 3 V/s (see Figure 13) 150 1.55 VLD = 1 VCC/dt 3 V/s (see Figure 13) VLD = 2 to 14 Vhys(SVS_IT-) VCC/dt 3 V/s (see Figure 13), External voltage applied on A7 VCC/dt 3 V/s (see Figure 13 and Figure 14) V(SVS_IT-) (SVS IT ) VCC/dt 3 V/s (see Figure 13 and Figure 14), External voltage applied on A7 ICC(SVS) (see Note 1) NOM 5 VLD = 15 70 120 s 300 s 12 s 1.7 V 155 mV V(SVS_IT-) x 0.004 V(SVS_IT-) x 0.008 4.4 10.4 VLD = 1 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71 VLD = 7 2.46 2.65 2.86 VLD = 8 2.58 2.8 3 VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42 VLD = 12 3.11 3.35 3.61 VLD = 13 3.24 3.5 3.76 VLD = 14 3.43 3.7 3.99 VLD = 15 1.1 1.2 1.3 10 15 VLD 0, VCC = 2.2 V/3 V UNIT mV V A The recommended operating voltage range is limited to 3.6 V. tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 35 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 typical characteristics Software sets VLD >0: SVS is active AVCC V(SVS_IT-) V(SVSstart) Vhys(SVS_IT-) Vhys(B_IT-) V(B_IT-) VCC(start) Brownout Brownout Region Brownout Region 1 0 SVS out td(BOR) t d(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT-) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 13. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(min) VCC(min)- V 1.5 Triangular Drop 1 1 ns 1 ns VCC 0.5 t pw 3V 0 1 10 100 1000 tpw - Pulse Width - s VCC(min) tf = tr tf tr t - Pulse Width - s Figure 14. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1) 36 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) DCO (see Note 1) PARAMETER TEST CONDITIONS VCC f(DCO03) Rsel = 0 0, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO13) Rsel = 1 1, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO23) Rsel = 2 2, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO33) Rsel = 3 3, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO43) Rsel = 4 4, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO53) Rsel = 5 5, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO63) Rsel = 6 6, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO73) Rsel = 7 7, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25C f(DCO47) Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25C f(DCO77) Rsel = 7 7, DCO = 7 7, MOD = 0 0, DCOR = 0 0, TA = 25C SRsel SDCO MIN TYP MAX UNIT 2.2 V 0.08 0.12 0.15 3V 0.08 0.13 0.16 2.2 V 0.14 0.19 0.23 3V 0.14 0.18 0.22 2.2 V 0.22 0.30 0.36 3V 0.22 0.28 0.34 2.2 V 0.37 0.49 0.59 3V 0.37 0.47 0.56 2.2 V 0.61 0.77 0.93 3V 0.61 0.75 0.90 2.2 V 1 1.2 1.5 3V 1 1.3 1.5 2.2 V 1.6 1.9 2.2 3V 1.69 2.0 2.29 2.2 V 2.4 2.9 3.4 3V 2.7 3.2 3.65 fDCO40 x 1.7 fDCO40 x 2.1 fDCO40 x 2.5 2.2 V/3 V 2.2 V 4 4.5 4.9 3V 4.4 4.9 5.4 SR = fRsel+1 / fRsel 2.2 V/3 V 1.35 1.65 2 SDCO = f(DCO+1) / f(DCO) 2.2 V/3 V 1.07 1.12 1.16 2.2 V -0.31 -0.36 -0.40 3V -0.33 -0.38 -0.43 0 5 10 Dt Temperature drift, drift Rsel = 4 4, DCO = 3 3, MOD = 0 (see Note 2) DV Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) 2.2 V/3 V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz %/C %/V Frequency Variance NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System). 2. This parameter is not production tested. Max f DCO_7 Min Max f DCO_0 Min IIIIIII IIIIIII 1 f DCOCLK IIIIIII IIIIIII 2.2 3 VCC - V 0 1 2 3 4 5 6 7 DCO Figure 15. DCO Characteristics POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 37 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7. D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO. D Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to: f average + MOD 32 f (DCO) f (DCO)1) f (DCO))(32*MOD) f (DCO)1) DCO when using ROSC (see Note 1) PARAMETER TEST CONDITIONS VCC fDCO, DCO output frequency Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, TA = 25C 2.2 V Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 MIN TYP MAX UNIT 1.815% MHz 1.9515% MHz 2.2 V/3 V 0.1 %/C 2.2 V/3 V 10 %/V 3V NOTES: 1. ROSC = 100k. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = 50ppm/C. crystal oscillator, LFXT1 oscillator (see Note 1) PARAMETER CXIN Integrated input capacitance CXOUT Integrated output capacitance VIL I t llevels l att XIN Input TEST CONDITIONS MIN XTS=0; LF oscillator selected, VCC = 2.2 V/3 V UNIT pF 2 XTS=0; LF oscillator selected, VCC = 2.2 V/3 V 12 XTS=1; XT1 oscillator selected, VCC = 2.2 V/3 V VIH MAX 12 XTS=1; XT1 oscillator selected, VCC = 2.2 V/3 V VCC = 2.2 V/3 V ( (see N Note 2) TYP pF 2 XTS = 0 or 1 XT1 or LF modes VSS 0.2 x VCC XTS = 0, LF mode 0.9 x VCC VCC XTS = 1, XT1 mode 0.8 x VCC VCC V NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. crystal oscillator, XT2 oscillator (see Note 1) PARAMETER TEST CONDITIONS MIN TYP CXIN Integrated input capacitance VCC = 2.2 V/3 V 2 CXOUT Integrated output capacitance VCC = 2.2 V/3 V 2 VIL VIH Input levels at XIN VCC = 2 2.2 2 V/3 V (see Note 2) MAX UNIT pF pF VSS 0.2 x VCC V 0.8 x VCC VCC V NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. USART0, USART1 (see Note 1) PARAMETER t() ( ) USART0/USART1: deglitch time TEST CONDITIONS MIN TYP MAX VCC = 2.2 V 200 430 800 VCC = 3 V 150 280 500 UNIT ns NOTE 1: The signal applied to the USART0/USART1 receive signal/terminal (URXD0/1) should meet the timing requirements of t() to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0/1 line. 38 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS MIN AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (see Note 2) All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1 0 x 7; V(AVSS) VP6.x/Ax V(AVCC) IADC12 Operating supply current into AVCC terminal (see Note 3) fADC12CLK = 5.0 MHz ADC12ON = 1, 1 REFON = 0 SHT0=0, SHT1=0, ADC12DIV=0 IREF+ Operating supply current i t AVCC tterminal into i l (see Note 4) fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, REF2_5V = 1 fADC12CLK = 5.0 MHz ADC12ON = 0 0, REFON = 1, REF2_5V = 0 TYP MAX UNIT 2.2 3.6 V 0 VAVCC V 2.2 V 0.65 1.3 3V 0.8 1.6 3V 0.5 0.8 2.2 V 0.5 0.8 3V 0.5 0.8 mA mA mA CI Input capacitance Only one terminal can be selected at one time, P6.x/Ax 2.2 V RI Input MUX ON resistance 0V VAx VAVCC 3V 40 pF 2000 Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC12. 4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. 12-bit ADC, external reference (see Note 1) PARAMETER TEST CONDITIONS MAX UNIT 1.4 VAVCC V VeREF+ > VREF-/VeREF- (see Note 3) 0 1.2 V Differential external reference voltage input VeREF+ > VREF-/VeREF- (see Note 4) 1.4 VAVCC V IVeREF+ Static input current 0V VeREF+ VAVCC 2.2 V/3 V 1 A IVREF-/VeREF- Static input current 0V VeREF- VAVCC 2.2 V/3 V 1 A VeREF+ Positive external reference voltage input VeREF+ > VREF-/VeREF- (see Note 2) VREF- /VeREF- Negative external reference voltage input (VeREF+ - VREF-/VeREF-) MIN TYP NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 39 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference PARAMETER Positive built in reference built-in voltage output VREF+ AVCC(min) AVCC minimum voltage, Positive built-in built in reference active IVREF+ Load current out of VREF+ terminal Load current regulation Load-current VREF+ terminal IL(VREF)+ TEST CONDITIONS MIN REF2_5V = 1 for 2.5 V IVREF+max IVREF+ IVREF+min VCC = 3 V REF2_5V = 0 for 1.5 V IVREF+max IVREF+ IVREF+min VCC = 2.2 V/3 V MAX 2.4 2.5 2.6 1.44 1.5 1.56 UNIT V REF2_5V = 0, IVREF+max IVREF+ IVREF+min 2.2 REF2_5V = 1, -0.5mA IVREF+ IVREF+min 2.8 REF2_5V = 1, -1mA IVREF+ IVREF+min IVREF+ = 500 A +/- 100 A 0 75 V, V Analog input voltage ~0.75 REF2_5V = 0 TYP V 2.9 VCC = 2.2 V 0.01 -0.5 VCC = 3 V 0.01 -1 mA VCC = 2.2 V 2 VCC = 3 V 2 IVREF+ = 500 A 100 A Analog input voltage ~1.25 V, REF2_5V = 1 VCC = 3 V 2 LSB 20 ns IDL(VREF) + Load current regulation VREF+ terminal IVREF+ =100 A 900 A, CVREF+=5 5 F F, ax ~0.5 0 5 x VREF+ , Error of conversion result 1 LSB VCC = 3 V CVREF+ Capacitance at pin VREF+ (see Note 1) REFON =1, 0 mA IVREF+ IVREF+max VCC = 2.2 V/3 V TREF+ Temperature coefficient of built-in reference IVREF+ is a constant in the range of 0 mA IVREF+ 1 mA VCC = 2.2 V/3 V tREFON Settle time of internal reference voltage (see Figure 16 and Note 2) IVREF+ = 0.5 mA, CVREF+ = 10 F, VREF+ = 1.5 V, VAVCC = 2.2 V 5 LSB F 10 100 17 ppm/C ms Not production tested, limits characterized Not production tested, limits verified by design NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF-/VeREF- and AVSS: 10 F tantalum and 100 nF ceramic. 2. The condition is that the error in a conversion started after tREFON is less than 0.5 LSB. The settling time depends on the external capacitive load. CVREF+ 100 F tREFON .66 x CVREF+ [ms] with CVREF+ in F 10 F 1 F 0 1 ms 10 ms 100 ms tREFON Figure 16. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+ 40 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 DVCC From Power Supply + - 10 F DVSS 100 nF AVCC + - 10 F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] AVSS 100 nF VREF+ or VeREF+ + - Apply External Reference 10 F 100 nF VREF-/VeREF- + - 10 F MSP430F15x MSP430F16x MSP430F161x 100 nF Figure 17. Supply Voltage and Reference Voltage Design VREF-/VeREF- External Supply From Power Supply DVCC + - 10 F DVSS 100 nF AVCC + - Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 10 F AVSS 100 nF MSP430F161x VREF+ or VeREF+ + - 10 F MSP430F15x MSP430F16x 100 nF Reference Is Internally Switched to AVSS VREF-/VeREF- Figure 18. Supply Voltage and Reference Voltage Design VREF-/VeREF- = AVSS, Internally Connected POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 41 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters 2.2V/3 V 0.45 5 6.3 MHz ADC12DIV=0, fADC12CLK=fADC12OSC 2.2 V/ 3 V 3.7 5 6.3 MHz CVREF+ 5 F, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz 2.2 V/ 3 V 2.06 3.51 s External fADC12CLK from ACLK, MCLK or SMCLK: ADC12SSEL 0 tADC12ON Turn on settling time of the ADC (see Note 1) tSample Sampling time RS = 400 , RI = 1000 , CI = 30 pF = [RS + RI] x CI;(see Note 2) 13xADC12DIVx 1/fADC12CLK s 100 3V 1220 2.2 V 1400 ns ns Not production tested, limits characterized Not production tested, limits verified by design NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than 0.5 LSB. The reference and input signal are already settled. 2. Approximately ten Tau () are needed to get an error of less than 0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance. 12-bit ADC, linearity parameters PARAMETER EI Integral linearity error ED Differential linearity error EO TEST CONDITIONS 1.4 V (VeREF+ - VREF-/VeREF-) min 1.6 V MIN TYP MAX 2 UNIT 2 2 V/3 V 2.2 1.7 LSB (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) 2.2 V/3 V 1 LSB Offset error (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), Internal impedance of source RS < 100 , CVREF+ = 10 F (tantalum) and 100 nF (ceramic) 2.2 V/3 V 2 4 LSB EG Gain error (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) 2.2 V/3 V 1.1 2 LSB ET Total unadjusted error (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) 2.2 V/3 V 2 5 LSB 42 1.6 V < (VeREF+ - VREF-/VeREF-) min [VAVCC] POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID TEST CONDITIONS PARAMETER MIN TYP MAX Operating supply current into AVCC terminal (see Note 1) REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C 2.2 V 40 120 ISENSOR 3V 60 160 VSENSOR ADC12ON = 1, INCH = 0Ah, TA = 0C 2.2 V 986 (see Note 2) 3V 986 2.2 V 3.55 3.553% 3V 3.55 3.553% TCSENSOR ADC12ON = 1 1, INCH = 0Ah Sample time required if channel 10 is selected (see Note 3) ADC12ON = 1, INCH = 0Ah, Error of conversion result 1 LSB IVMID Current into divider at channel 11 (see Note 4) ADC12ON = 1, 1 INCH = 0Bh, 0Bh 1.1 1.10.04 AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh, VMID is ~0.5 x VAVCC 2.2 V VMID 3V 1.5 1.500.04 Sample time required if channel 11 is selected (see Note 5) ADC12ON = 1, INCH = 0Bh, Error of conversion result 1 LSB 2.2 V 1400 tVMID(sample) 3V 1220 30 3V 30 A A mV tSENSOR(sample) 2.2 V UNIT mV/C ss 2.2 V NA 3V NA A A V ns Not production tested, limits characterized NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+. 2. The temperature sensor offset can be as much as 20_C. A single-point calibration is recommended in order to minimize the offset error of the built-in temperature sensor. 3. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on) 4. No additional current is needed. The VMID is used during sampling. 5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. 12-bit DAC, supply specifications PARAMETER AVCC IDD PSRR Analog supply voltage Supply Current: Single DAC Channel (see Notes 1 and 2) Power supply rejection ratio (see Notes 3 and 4) TEST CONDITIONS VCC AVCC = DVCC, AVSS = DVSS =0 V MIN TYP 2.20 MAX UNIT 3.60 V DAC12AMPx=2, DAC12IR=0, DAC12_xDAT=0800h 2.2V/3V 50 110 DAC12AMPx=2, DAC12IR=1, DAC12_xDAT=0800h , VeREF+=VREF+= AVCC 2.2V/3V 50 110 DAC12AMPx=5, DAC12IR=1, DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 200 440 DAC12AMPx=7, DAC12IR=1, DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 700 1500 DAC12_xDAT = 800h, VREF = 1.5 V AVCC = 100mV DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V AVCC = 100mV A A 2.2V 70 dB 3V NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly. 2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. 3. PSRR = 20*log{AVCC/VDAC12_xOUT}. 4. VREF is applied externally. The internal reference is not used. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 43 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (see Figure 19) PARAMETER TEST CONDITIONS Resolution INL DNL EO MIN (12-bit Monotonic) Integral nonlinearity (see Note 1) Differential nonlinearity (see Note 1) Offset voltage w/o calibration (see Notes 1, 2) Offset voltage with calibration (see Notes 1, 2) dE(O)/dT VCC Gain error (see Note 1) dE(G)/dT Gain temperature coefficient (see Note 1) tOffset_Cal Time for offset calibration (see Note 3) MAX 12 Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V UNIT bits 2 0 2.0 8.0 8 0 LSB 0 4 0.4 1.0 1 0 LSB 21 mV 2 5 2.5 Offset error temperature coefficient (see Note 1) EG TYP 2.2V/3V VREF = 1.5 V 2.2V VREF = 2.5 V 3V 30 uV/C 3 50 3.50 2.2V/3V % FSR ppm of FSR/C 10 DAC12AMPx=2 2.2V/3V 100 DAC12AMPx=3,5 2.2V/3V 32 DAC12AMPx=4,6,7 2.2V/3V 6 ms NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1. 2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON 3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx ={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect accuracy and is not recommended. DAC V OUT DAC Output VR+ RLoad = Ideal transfer function AV CC 2 CLoad = 100pF Offset Error Positive Negative Gain Error DAC Code Figure 19. Linearity Test Load Conditions and Gain/Offset Definition 44 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (continued) TYPICAL INL ERROR vs DIGITAL INPUT DATA INL - Integral Nonlinearity Error - LSB 4 VCC = 2.2 V, VREF = 1.5V DAC12AMPx = 7 DAC12IR = 1 3 2 1 0 -1 -2 -3 -4 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT - Digital Code TYPICAL DNL ERROR vs DIGITAL INPUT DATA DNL - Differential Nonlinearity Error - LSB 2.0 VCC = 2.2 V, VREF = 1.5V DAC12AMPx = 7 DAC12IR = 1 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT - Digital Code POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 45 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, output specifications PARAMETER TEST CONDITIONS VCC No Load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 VO Output voltage range (see Note 1, Figure 22) CL(DAC12) Max DAC12 load capacitance IL(DAC12) Max DAC12 load current RO/P(DAC12) MIN 2.2V/3V TYP 0 UNIT 0.005 V No Load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 2.2V/3V AVCC-0.05 AVCC RLoad= 3 k, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 2.2V/3V 0 0.1 V RLoad= 3 k, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 2.2V/3V AVCC-0.13 AVCC V 100 pF 2.2V/3V Output resistance (see Figure 22) MAX 2.2V -0.5 +0.5 mA 3V -1.0 +1.0 mA RLoad= 3 k VO/P(DAC12) = 0 V DAC12AMPx = 7 DAC12_xDAT = 0h 2.2V/3V 150 250 RLoad= 3 k VO/P(DAC12) = AVCC DAC12AMPx = 7 DAC12_xDAT = 0FFFh 2.2V/3V 150 250 RLoad= 3 k 0.3 V < VO/P(DAC12) < AVCC - 0.3 V DAC12AMPx = 7 2.2V/3V 1 4 NOTES: 1. Data is valid after the offset calibration of the output amplifier. ILoad RO/P(DAC12_x) Max RLoad AV CC DAC12 2 O/P(DAC12_x) CLoad= 100pF Min 0.3 AV CC-0.3V VOUT AV CC Figure 22. DAC12_x Output Resistance Tests 46 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit DAC, reference input specifications PARAMETER TEST CONDITIONS Reference input voltage range VeREF+ Ri(VREF+), Ri(VeREF+) NOTES: 1. 2. 3. 4. 5. Reference input p i t resistance VCC MIN TYP MAX DAC12IR=0 (see Notes 1 and 2) 2.2V/3V AVCC/3 AVCC+0.2 DAC12IR=1 (see Notes 3 and 4) 2.2V/3V AVcc AVcc+0.2 DAC12_0 IR = DAC12_1 IR = 0 2.2V/3V DAC12_0 IR = 1, DAC12_1 IR = 0 2.2V/3V DAC12_0 IR = 0, DAC12_1 IR = 1 2.2V/3V DAC12_0 IR = DAC12_1 IR =1, DAC12_0 SREFx = DAC12_1 SREFx (see Note 5) 2.2V/3V 20 UNIT V M 40 48 56 k 20 24 28 k For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / [3*(1 + EG)]. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / (1 + EG). When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance. 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 23 and Figure 24) PARAMETER tON tS(FS) tS(C-C) SR DAC12 on-time S ttli time, ti Settling full-scale Settling S ttli time, ti code to code Slew rate Glitch energy: full-scale full scale TEST CONDITIONS DAC12_xDAT _ = 800h,, ErrorV(O) < 0.5 LSB (see Note 1,Figure 23) DAC12 DAT = DAC12_xDAT 80h F7Fh 80h DAC12_xDAT DAC12 xDAT = 3F8h 408h 3F8h BF8h C08h BF8h DAC12_xDAT DAC12 DAT = 80h F7Fh 80h DAC12 DAT = DAC12_xDAT 80h F7Fh 80h VCC MIN TYP MAX DAC12AMPx = 0 {2, 3, 4} 2.2V/3V 60 120 DAC12AMPx = 0 {5, 6} 2.2V/3V 15 30 DAC12AMPx = 0 7 2.2V/3V 6 12 DAC12AMPx = 2 2.2V/3V 100 200 DAC12AMPx = 3,5 2.2V/3V 40 80 DAC12AMPx = 4,6,7 2.2V/3V 15 30 DAC12AMPx = 2 2.2V/3V 5 DAC12AMPx = 3,5 2.2V/3V 2 DAC12AMPx = 4,6,7 2.2V/3V 1 DAC12AMPx = 2 2.2V/3V 0.05 0.12 DAC12AMPx = 3,5 2.2V/3V 0.35 0.7 DAC12AMPx = 4,6,7 2.2V/3V 1.5 2.7 DAC12AMPx = 2 2.2V/3V 10 DAC12AMPx = 3,5 2.2V/3V 10 DAC12AMPx = 4,6,7 2.2V/3V 10 UNIT s s s V/s nV-ss nV NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 23. 2. Slew rate applies to output voltage steps 200mV. Conversion 1 VOUT DAC Output ILoad RLoad = 3 k Glitch Energy Conversion 2 Conversion 3 +/- 1/2 LSB AV CC 2 RO/P(DAC12.x) +/- 1/2 LSB CLoad = 100pF tsettleLH tsettleHL Figure 23. Settling Time and Glitch Energy Testing POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 47 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure 24. Slew Rate Testing 12-bit DAC, dynamic specifications continued (TA = 25C unless otherwise noted) PARAMETER BW-3dB TEST CONDITIONS 3-dB bandwidth, VDC=1.5V, VAC=0.1VPP (see Figure 25) Channel to channel crosstalk (see Note 1 and Figure 26) VCC MIN DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 40 DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 180 DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 550 DAC12_0DAT = 800h, No Load, DAC12_1DAT = 80h<->F7Fh, RLoad = 3k fDAC12_1OUT = 10kHz @ 50/50 duty cycle 2.2V/3V DAC12_0DAT = 80h<->F7Fh, RLoad = 3k, DAC12_1DAT = 800h, No Load fDAC12_0OUT = 10kHz @ 50/50 duty cycle 2.2V/3V TYP MAX UNIT kHz -80 dB -80 NOTES: 1. RLOAD = 3 k, CLOAD = 100 pF ILoad Ve REF+ RLoad = 3 k AV CC DAC12_x 2 DACx AC CLoad = 100pF DC Figure 25. Test Conditions for 3-dB Bandwidth Specification ILoad RLoad AV CC DAC12_0 DAC12_xDAT 080h 2 DAC0 7F7h 080h V OUT CLoad= 100pF VREF+ ILoad e V DAC12_yOUT RLoad AV CC DAC12_1 V DAC12_xOUT 2 DAC1 fToggle CLoad= 100pF Figure 26. Crosstalk Test Conditions 48 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7F7h 080h MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) flash memory TEST CONDITIONS PARAMETER VCC MIN TYP MAX UNIT VCC(PGM/ ERASE) Program and erase supply voltage 2.7 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 104 Program/Erase endurance TJ = 25C ms 105 tRetention Data retention duration tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 Block program time for each additional byte or word tBlock, End Block program end-sequence wait time tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 cycles 100 years 21 see Note 3 tFTG 6 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). JTAG interface TEST CONDITIONS PARAMETER fTCK TCK input frequency see Note 1 RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 VCC MIN 2.2 V 0 NOM MAX UNIT 5 MHz 3V 0 10 MHz 2.2 V/ 3 V 25 60 90 k MIN NOM MAX NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions. JTAG fuse (see Note 1) TEST CONDITIONS PARAMETER VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TDI/TCLK for fuse-blow: F versions IFB Supply current into TDI/TCLK during fuse blow tFB Time to blow fuse TA = 25C VCC 2.5 6 UNIT V 7 V 100 mA 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 49 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics port P1, P1.0 to P1.7, input/output with Schmitt trigger P1SEL.x 0 P1DIR.x Direction Control From Module 1 Pad Logic P1.0/TACLK ... 0 P1OUT.x Module X OUT 1 P1.7/TA2 P1IN.x EN Module X IN D P1IRQ.x P1IE.x Q P1IFG.x EN Set Interrupt Flag Interrupt Edge Select P1IES.x P1SEL.x PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 DVSS P1IN.0 TACLK P1IE.0 P1IFG.0 P1IES.0 P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.1 Out0 signal P1IN.1 CCI0A P1IE.1 P1IFG.1 P1IES.1 signal P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 P1IN.2 CCI1A P1IE.2 P1IFG.2 P1IES.2 P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal P1IN.3 CCI2A P1IE.3 P1IFG.3 P1IES.3 P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4 signal P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 Out0 P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5 P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out1 signal P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6 P1OUT.7 signal P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7 P1Sel.7 P1DIR.7 P1DIR.7 Out2 Signal from or to Timer_A 50 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt trigger P2SEL.x 0 P2DIR.x Direction Control From Module 0: Input 1: Output 1 0 P2OUT.x Module X OUT 1 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 Pad Logic P2.6/ADC12CLK/DMAE0 P2.7/TA0 P2IN.x EN Module X IN P2IRQ.x Bus Keeper D P2IE.x P2IFG.x EN Q CAPD.X Interrupt Edge Select Set Interrupt Flag P2IES.x P2SEL.x x: Bit Identifier 0 to 2, 6, and 7 for Port P2 PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P2IES.0 P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 DVSS P2IN.1 INCLK P2IE.1 P2IFG.1 P2IES.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT P2IN.2 CCI0B P2IE.2 P2IFG.2 P2IES.2 P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 ADC12CLK P2IN.6 DMAE0# P2IE.6 P2IFG.6 P2IES.6 P2OUT.7 signal P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 P2Sel.7 P2DIR.7 P2DIR.7 Out0 Signal from Comparator_A Signal to Timer_A Signal from Timer_A ADC12CLK signal is output of the 12-bit ADC module # Signal to DMA, channel 0, 1 and 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 51 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.3 to P2.4, input/output with Schmitt trigger P2SEL.3 0: Input 1: Output 0 P2DIR.3 Direction Control From Module 1 Pad Logic P2.3/CA0/TA1 0 P2OUT.3 Module X OUT 1 P2IN.3 EN Module X IN Bus Keeper D P2IRQ.3 P2IE.3 P2IFG.3 EN Set Q Interrupt Flag Interrupt Edge Select CAPD.3 Comparator_A CAEX P2CA P2IES.3 P2SEL.3 CAREF CAF + CCI1B To Timer_A3 - P2SEL.4 P2IES.4 Interrupt Flag P2IFG.4 P2IRQ.4 Set EN Q P2IE.4 CAREF Reference Block Edge Select Interrupt CAPD.4 D Module X IN Bus Keeper EN P2IN.4 Module X OUT P2OUT.4 From Module Direction Control P2DIR.4 1 0 1 P2.4/CA1/TA2 Pad Logic 1: Output 0: Input 0 P2SEL.4 PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal P2IN.3 unused P2IE.3 P2IFG.3 P2IES.3 P2OUT.4 signal P2IN.4 unused P2IE.4 P2IFG.4 P2IES.4 P2Sel.4 P2DIR.4 P2DIR.4 Out2 Signal from Timer_A 52 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.5, input/output with Schmitt trigger and Rosc function for the basic clock module 0: Input 1: Output P2SEL.5 0 P2DIR.5 Direction Control From Module Pad Logic 1 P2.5/Rosc 0 P2OUT.5 Module X OUT 1 Bus Keeper P2IN.5 EN Module X IN P2IRQ.5 D P2IE.5 Q P2IFG.5 EN Set Interrupt Flag VCC Edge Select Interrupt P2IES.5 P2SEL.5 Internal to Basic Clock Module 0 1 to DCOR DC Generator CAPD.5 DCOR: Control Bit From Basic Clock Module If it Is Set, P2.5 Is Disconnected From P2.5 Pad PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 DVSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 53 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt trigger P3SEL.x 0: Input 1: Output 0 P3DIR.x Direction Control From Module 1 Pad Logic P3OUT.x Module X OUT 0 P3.0/STE0 1 P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1 P3.7/URXD1 P3IN.x EN D Module X IN x: Bit Identifier, 0 and 4 to 7 for Port P3 PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P3Sel.0 P3DIR.0 DVSS P3OUT.0 DVSS P3IN.0 STE0 P3Sel.4 P3DIR.4 DVCC P3OUT.4 UTXD0 P3IN.4 Unused P3Sel.5 P3DIR.5 DVSS P3OUT.5 DVSS P3IN.5 URXD0 P3Sel.6 P3DIR.6 DVCC P3OUT.6 UTXD1 P3IN.6 Unused P3Sel.7 P3DIR.7 DVSS P3OUT.7 DVSS P3IN.7 URXD1 Output from USART0 module Output from USART1 module Input to USART0 module Input to USART1 module 54 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.1, input/output with Schmitt trigger P3SEL.1 SYNC MM STC STE 0 P3DIR.1 0: Input 1: Output 1 DCM_SIMO Pad Logic P3.1/SIMO0/SDA 0 P3OUT1 (SI)MO0 or SDAo/p From USART0 1 P3IN.1 EN SI(MO)0 or SDAi/p To USAET0 D POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 55 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.2, input/output with Schmitt trigger P3SEL.2 SYNC MM STC STE 0 P3DIR.2 0: Input 1: Output 1 DCM_SOMI Pad Logic P3.2/SOMI0 0 P3OUT.2 SO(MI)0 From USART0 1 P3IN.2 EN (SO)MI0 To USART0 D port P3, P3.3, input/output with Schmitt-trigger P3SEL.3 SYNC MM STC STE 0 P3DIR.3 0: Input 1: Output 1 DCM_UCLK Pad Logic P3.3/UCLK0/SCL 0 P3OUT.3 UCLK.0 From USART0 1 P3IN.3 EN UCLK0 D To USART0 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode). I2C, slave mode: The clock applied to SCL is used to shift data in and out. The frequency of the clock source of the module must be w 10 times the frequency of the SCL clock. I2C, master mode: To shift data in and out, the clock is supplied via the SCL terminal to all I2C slaves. The frequency of the clock source of the module must be w 10 times the frequency of the SCL clock. 56 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P4, P4.0 to P4.6, input/output with Schmitt trigger Module IN of pin P5.7/TBOUTH/SVSOUT P4DIR.7 P4SEL.7 P4SEL.x 0: Input 1: Output 0 P4DIR.x Direction Control From Module P4OUT.x 1 P4.0/TB0 ... 0 1 Module X OUT Bus Keeper P4.6/TB6 P4IN.x EN Module X IN D x: Bit Identifier, 0 to 6 for Port P4 PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P4Sel.0 P4DIR.0 P4DIR.0 P4OUT.0 Out0 signal P4IN.0 CCI0A / CCI0B P4OUT.1 Out1 signal P4IN.1 CCI1A / CCI1B signal P4IN.2 CCI2A / CCI2B P4Sel.1 P4DIR.1 P4DIR.1 P4Sel.2 P4DIR.2 P4DIR.2 P4OUT.2 Out2 P4Sel.3 P4DIR.3 P4DIR.3 P4OUT.3 Out3 signal P4IN.3 CCI3A / CCI3B P4OUT.4 Out4 signal P4IN.4 CCI4A / CCI4B signal P4IN.5 CCI5A / CCI5B P4IN.6 CCI6A P4Sel.4 P4DIR.4 P4DIR.4 P4Sel.5 P4DIR.5 P4DIR.5 P4OUT.5 Out5 P4Sel.6 P4DIR.6 P4DIR.6 P4OUT.6 Out6 signal Signal from Timer_B Signal to Timer_B POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 57 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P4, P4.7, input/output with Schmitt trigger P4SEL.7 0: Input 1: Output 0 P4DIR.7 1 Pad Logic P4.7/TBCLK 0 P4OUT.7 DVSS 1 P4IN.7 EN Timer_B, D TBCLK port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt trigger P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module 1 Pad Logic P5OUT.x Module X OUT 0 P5.0/STE1 1 P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH/SVSOUT P5IN.x EN Module X IN D x: Bit Identifier, 0 and 4 to 7 for Port P5 PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x P5Sel.0 P5Sel.4 MODULE X OUT PnIN.x P5DIR.0 DVSS P5DIR.4 DVCC P5Sel.5 P5DIR.5 P5Sel.6 P5DIR.6 P5Sel.7 P5DIR.7 MODULE X IN P5OUT.0 DVSS P5IN.0 STE.1 P5OUT.4 MCLK P5IN.4 unused DVCC P5OUT.5 SMCLK P5IN.5 unused DVCC P5OUT.6 ACLK P5IN.6 unused DVSS P5OUT.7 SVSOUT P5IN.7 TBOUTHiZ NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7. 58 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P5, P5.1, input/output with Schmitt trigger P5SEL.1 SYNC MM 0 P5DIR.1 1 DCM_SIMO STC STE 0: Input 1: Output Pad Logic P5.1/SIMO1 0 P5OUT.1 (SI)MO1 From USART1 1 P5IN.1 EN SI(MO)1 To USART1 D port P5, P5.2, input/output with Schmitt trigger P5SEL.2 SYNC MM STC STE 0 P5DIR.2 0: Input 1: Output 1 DCM_SOMI Pad Logic P5.2/SOMI1 0 P5OUT.2 SO(MI)1 From USART1 1 P5IN.2 EN (SO)MI1 To USART1 D POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 59 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P5, P5.3, input/output with Schmitt trigger P5SEL.3 SYNC MM STC STE 0 P5DIR.3 0: Input 1: Output 1 DCM_SIMO Pad Logic P5.3/UCLK1 0 P5OUT.3 UCLK1 From USART1 1 P5IN.3 EN D UCLK1 To USART1 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction is always input. SPI, slave mode: The clock applied to UCLK1 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode). 60 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.0 to P6.5, input/output with Schmitt trigger P6SEL.x 0 P6DIR.x Direction Control From Module 0: Input 1: Output 1 Pad Logic 0 P6OUT.x Module X OUT 1 P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 Bus Keeper P6IN.x EN Module X IN D From ADC To ADC x: Bit Identifier, 0 to 5 for Port P6 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 A. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12. PnSel.x PnDIR.x DIR. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 unused P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 unused P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 unused P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 unused P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 unused P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 unused NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 61 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.6, input/output with Schmitt trigger 0: Port Active, T-Switch Off 1: T-Switch On, Port Disabled INCH = 6 a6 '1', if DAC12.0AMP > 0 P6SEL.6 0: Input 1: Output 0 P6DIR.6 1 P6DIR.6 0 P6OUT.6 1 DVSS Bus Keeper P6IN.6 EN D 0, if DAC12.0CALON = 0 and DAC12.0AMP > 1 + - 1 0 1, if DAC12.0AMP >1 1, if DAC12.0AMP = 1 Signal 62 Pad Logic from or to ADC12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 P6.6/A6/DAC0 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.7, input/output with Schmitt trigger To SVS Mux (15) 0: Port Active, T-Switch Off 1: T-Switch On, Port Disabled INCH = 7 a7 '1', if VLD = 15 '1', if DAC12.0AMP > 0 P6SEL.6 0: Input 1: Output 0 P6DIR.7 Pad Logic 1 P6DIR.7 0 P6OUT.7 1 DVSS Bus Keeper P6.7/A7/ DAC1/SVSIN P6IN.7 EN D 0, if DAC12.0CALON = 0 and DAC12.0AMP > 1 + - 1 0 1, if DAC12.0AMP > 1 1, if DAC12.0AMP = 1 Signal to SVS Block, Selected if VLD = 15 From or To ADC12 VLD Control Bits are Located in SVS Signal POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 63 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger TDO Controlled by JTAG Controlled by JTAG JTAG TDO/TDI Controlled by JTAG DVCC DVCC TDI Fuse Burn & Test Fuse Test TDI/TCLK and DVCC Emulation Module TMS TMS DVCC During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry TCK TCK 64 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITDI/TCLK ITF Figure 27. Fuse Check Mode Current, MSP430F15x/16x/161x POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 65 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G - OCTOBER 2002 - REVISED MARCH 2011 Data Sheet Revision History LITERATURE NUMBER SLAS368F SLAS368G 66 SUMMARY In absolute maximum ratings table, changed Tstg min from -40C to -55C (page 25) Added Development Tools Support section (page 2) Changed limits on td(SVSon) parameter (page 35) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 1-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) MSP430F155IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F155IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F155IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F155IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F156IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F156IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F156IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F156IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F157IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F157IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F157IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F157IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F1610IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F1610IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F1610IRTD ACTIVE VQFN RTD 64 MSP430F1610IRTDR ACTIVE VQFN RTD 64 MSP430F1610IRTDT ACTIVE VQFN RTD 64 TBD Call TI Call TI 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Mar-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430F1611IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F1611IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F1611IRTD ACTIVE VQFN RTD 64 MSP430F1611IRTDR ACTIVE VQFN RTD 64 MSP430F1611IRTDT ACTIVE VQFN RTD MSP430F1612IPM ACTIVE LQFP MSP430F1612IPMR ACTIVE TBD Call TI Call TI 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F1612IRTD ACTIVE VQFN RTD 64 TBD Call TI Call TI MSP430F1612IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F1612IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F167IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F167IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F167IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F167IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F168IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F168IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F168IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F168IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F169IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) Addendum-Page 2 Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Mar-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) MSP430F169IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F169IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR MSP430F169IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F1610IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F1611IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F1612IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F1610IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1611IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1612IPMR LQFP PM 64 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0- 7 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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