MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Supply-Voltage Range: 1.8 V to 3.6 V
DUltralow Power Consumption
− Active Mode: 330 μA at 1 MHz, 2.2 V
− Standby Mode: 1.1 μA
− Off Mode (RAM Retention): 0.2 μA
DFive Power-Saving Modes
DWake-Up From Standby Mode in
Less Than 6 μs
D16-Bit RISC Architecture,
125-ns Instruction Cycle Time
DThree-Channel Internal DMA
D12-Bit Analog-to-Digital (A/D) Converter
With Internal Reference, Sample-and-Hold,
and Autoscan Feature
DDual 12-Bit Digital-to-Analog (D/A)
Converters With Synchronization
D16-Bit Timer_A With Three
Capture/Compare Registers
D16-Bit Timer_B With Three or Seven
Capture/Compare-With-Shadow Registers
DOn-Chip Comparator
DSerial Communication Interface (USART0),
Functions as Asynchronous UART or
Synchronous SPI or I2CTM Interface
DSerial Communication Interface (USART1),
Functions as Asynchronous UART or
Synchronous SPI Interface
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DBrownout Detector
DBootstrap Loader
I2C is a registered trademark of Philips Incorporated.
DSerial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
DFamily Members Include
− MSP430F155
16KB+256B Flash Memory
512B RAM
− MSP430F156
24KB+256B Flash Memory
1KB RAM
− MSP430F157
32KB+256B Flash Memory,
1KB RAM
− MSP430F167
32KB+256B Flash Memory,
1KB RAM
− MSP430F168
48KB+256B Flash Memory,
2KB RAM
− MSP430F169
60KB+256B Flash Memory,
2KB RAM
− MSP430F1610
32KB+256B Flash Memory
5KB RAM
− MSP430F1611
48KB+256B Flash Memory
10KB RAM
− MSP430F1612
55KB+256B Flash Memory
5KB RAM
DAvailable in 64-Pin QFP Package (PM) and
64-Pin QFN Package (RTD)
DFor Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide,
Literature Number SLAU049
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Copyright © 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The MSP430F15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous
communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430F161x series offers
extended RAM addressing for memory-intensive applications and large C-stack requirements.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
AVAILABLE OPTIONS
T
PACKAGED DEVICES
TAPLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RTD)
−40°C to 85°C
MSP430F155IPM
MSP430F156IPM
MSP430F157IPM
MSP430F167IPM
MSP430F168IPM
MSP430F169IPM
MSP430F1610IPM
MSP430F1611IPM
MSP430F1612IPM
MSP430F155IRTD
MSP430F156IRTD
MSP430F157IRTD
MSP430F167IRTD
MSP430F168IRTD
MSP430F169IRTD
MSP430F1610IRTD
MSP430F1611IRTD
MSP430F1612IRTD
†For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
‡Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
DDebugging and Programming Interface
− MSP-FET430UIF (USB)
− MSP-FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
− MSP-FET430U64 (PM package)
DStandalone Target Board
− MSP-TS430PM64 (PM package)
DProduction Programmer
− MSP-GANG430
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F155, MSP430F156, and MSP430F157
17 18 19
P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK 21 22 23 24
63 62 61 60 5964 58 56 55 5457
25 26 27 28 29
53 52 51 50 49
30 31 32
PM, RTD PACKAGE
(TOP VIEW)
AVCC
DVSS
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC
P2.6/ADC12CLK/DMAE0
P2.7/TA0
P3.0/STE0
P3.1/SIMO0/SDA
P3.2/SOMI0
P3.3/UCLK0/SCL
P3.4/UTXD0
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F167, MSP430F168, MSP430F169
17 18 19
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK 21 22 23 24
63 62 61 60 5964 58 56 55 5457
25 26 27 28 29
53 52 51 50 49
30 31 32
PM, RTD PACKAGE
(TOP VIEW)
AVCC
DVSS
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC
P2.6/ADC12CLK/DMAE0
P2.7/TA0
P3.0/STE0
P3.1/SIMO0/SDA
P3.2/SOMI0
P3.3/UCLK0/SCL
P3.4/UTXD0
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F1610, MSP430F1611, MSP430F1612
17 18 19
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK 21 22 23 24
63 62 61 60 5964 58 56 55 5457
25 26 27 28 29
53 52 51 50 49
30 31 32
PM, RTD PACKAGE
(TOP VIEW)
AVCC
DVSS
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC
P2.6/ADC12CLK/DMAE0
P2.7/TA0
P3.0/STE0
P3.1/SIMO0/SDA
P3.2/SOMI0
P3.3/UCLK0/SCL
P3.4/UTXD0
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram, MSP430F15x
Oscillator ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT P3 P4P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5 P6
MAB,
4 Bit
DVCC DVSS AVCC AVSS RST/NMI
System
Clock
ROSC
P1
32KB Flash
24KB Flash
16KB Flash
1KB RAM
1KB RAM
512B RAM
ADC12
12-Bit
8 Channels
<10μs Conv.
DAC12
12-Bit
2 Channels
Voltage out
DMA
Controller
3 Channels
Watchdog
Timer
15/16-Bit
Timer_B3
3 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
SVS
Brownout
Comparator
AUSART0
UART Mode
SPI Mode
I2C Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8 8 8 8 8 8
functional block diagram, MSP430F16x
Oscillator ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT P3 P4P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5 P6
MAB,
4 Bit
DVCC DVSS AVCC AVSS RST/NMI
System
Clock
ROSC
P1
Hardware
Multiplier
MPY, MPYS
MAC,MACS
60KB Flash
48KB Flash
32KB Flash
2KB RAM
2KB RAM
1KB RAM
ADC12
12-Bit
8 Channels
<10μs Conv.
DAC12
12-Bit
2 Channels
Voltage out
DMA
Controller
3 Channels
Watchdog
Timer
15/16-Bit
Timer_B7
7 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
SVS
Brownout
Comparator
AUSART0
UART Mode
SPI Mode
I2C Mode
USART1
UART Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8 8 8 8 8 8
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram, MSP430F161x
Oscillator ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT P3 P4P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5 P6
MAB,
4 Bit
DVCC DVSS AVCC AVSS RST/NMI
System
Clock
ROSC
P1
Hardware
Multiplier
MPY, MPYS
MAC,MACS
55KB Flash
48KB Flash
32KB Flash
5KB RAM
10KB RAM
5KB RAM
ADC12
12-Bit
8 Channels
<10μs Conv.
DAC12
12-Bit
2 Channels
Voltage out
DMA
Controller
3 Channels
Watchdog
Timer
15/16-Bit
Timer_B7
7 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
SVS
Brownout
Comparator
AUSART0
UART Mode
SPI Mode
I2C Mode
USART1
UART Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8 8 8 8 8 8
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
DVCC 1Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK 12 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0 13 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 I/O General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0 17 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK 20 I/O General-purpose digital I/O pin/ACLK output
P2.1/TAINCLK 21 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive
P2.3/CA0/TA1 23 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2 24 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/Rosc 25 I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
P2.6/ADC12CLK/
DMAE0 26 I/O General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external trigger
P2.7/TA0 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0 28 I/O General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode
P3.1/SIMO0/SDA 29 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode, I2C data − USART0/I2C mode
P3.2/SOMI0 30 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0/SCL 31 I/O General-purpose digital I/O pin/external clock input − USART0/UART or SPI mode, clock output –
USART0/SPI mode, I2C clock − USART0/I2C mode
P3.4/UTXD0 32 I/O General-purpose digital I/O pin/transmit data out – USART0/UART mode
P3.5/URXD0 33 I/O General-purpose digital I/O pin/receive data in – USART0/UART mode
P3.6/UTXD1†34 I/O General-purpose digital I/O pin/transmit data out – USART1/UART mode
P3.7/URXD1† 35 I/O General-purpose digital I/O pin/receive data in – USART1/UART mode
P4.0/TB0 36 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1 37 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2 38 I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3† 39 I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4† 40 I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5† 41 I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6† 42 I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK 43 I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/STE1† 44 I/O General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode
P5.1/SIMO1† 45 I/O General-purpose digital I/O pin/slave in/master out of USART1/SPI mode
P5.2/SOMI1† 46 I/O General-purpose digital I/O pin/slave out/master in of USART1/SPI mode
P5.3/UCLK1† 47 I/O General-purpose digital I/O pin/external clock input – USART1/UART or SPI mode, clock output –
USART1/SPI mode
†16x, 161x devices only
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
P5.4/MCLK 48 I/O General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK 50 I/O General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/
SVSOUT 51 I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B TB0 to
TB6/SVS comparator output
P6.0/A0 59 I/O General-purpose digital I/O pin/analog input a0 – 12-bit ADC
P6.1/A1 60 I/O General-purpose digital I/O pin/analog input a1 – 12-bit ADC
P6.2/A2 61 I/O General-purpose digital I/O pin/analog input a2 – 12-bit ADC
P6.3/A3 2 I/O General-purpose digital I/O pin/analog input a3 – 12-bit ADC
P6.4/A4 3 I/O General-purpose digital I/O pin/analog input a4 – 12-bit ADC
P6.5/A5 4 I/O General-purpose digital I/O pin/analog input a5 – 12-bit ADC
P6.6/A6/DAC0 5 I/O General-purpose digital I/O pin/analog input a6 – 12-bit ADC/DAC12.0 output
P6.7/A7/DAC1/
SVSIN 6 I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input
RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
TCK 57 I Test clock. TCK is the clock input port for device programming test and bootstrap loader start
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
VeREF+ 10 I Input for an external reference voltage
VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12
VREF−/VeREF− 11 INegative terminal for the reference voltage for both sources, the internal reference voltage, or an external
applied reference voltage
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
XT2IN 53 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT 52 O Output terminal of crystal oscillator XT2
QFN Pad NA NA QFN package pad connection to DVSS recommended (RTD package only)
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals ar e c onnected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; Table 2 shows the address
modes.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register DDMOV Rs,Rd MOV R10,R11 R10 −−> R11
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)
Indirect DMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement DMOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11
R10 + 2−−> R10
Immediate DMOV #X,TONI MOV #45,TONI #45 −−> M(TONI)
NOTE: S = source D = destination
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode AM
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled
− ACLK and SMCLK remain active. MCLK is disabled
DLow-power mode 1 (LPM1)
− CPU is disabled
− ACLK and SMCLK remain active. MCLK is disabled
− DCO’s dc generator is disabled if DCO not used in active mode
DLow-power mode 2 (LPM2)
− CPU is disabled
− MCLK and SMCLK are disabled
− DCO’s dc generator remains enabled
− ACLK remains active
DLow-power mode 3 (LPM3)
− CPU is disabled
− MCLK and SMCLK are disabled
− DCO’s dc generator is disabled
− ACLK remains active
DLow-power mode 4 (LPM4)
− CPU is disabled
− ACLK is disabled
− MCLK and SMCLK are disabled
− DCO’s dc generator is disabled
− Crystal oscillator is stopped
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash memory
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable 0FFFCh 14
Timer_B7 (see Note 5) TBCCR0 CCIFG
(see Note 2) Maskable 0FFFAh 13
Timer_B7 (see Note 5) TBCCR1 to TBCCR6 CCIFGs,
TBIFG
(see Notes 1 and 2) Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog timer WDTIFG Maskable 0FFF4h 10
USART0 receive URXIFG0 Maskable 0FFF2h 9
USART0 transmit
I2C transmit/receive/others UTXIFG0
I2CIFG (see Note 4) Maskable 0FFF0h 8
ADC12 ADC12IFG
(see Notes 1 and 2) Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG
(see Note 2) Maskable 0FFECh 6
Timer_A3 TACCR1 and TACCR2 CCIFGs,
TAIFG
(see Notes 1 and 2) Maskable 0FFEAh 5
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7
(see Notes 1 and 2) Maskable 0FFE8h 4
USART1 receive URXIFG1 Maskable 0FFE6h 3
USART1 transmit UTXIFG1 Maskable 0FFE4h 2
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7
(see Notes 1 and 2) Maskable 0FFE2h 1
DAC12
DMA DAC12_0IFG, DAC12_1IFG
DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 1 and 2)
Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. I2C interrupt flags located in the module
5. Timer_B7 in MSP430F16x/161x family has 7 CCRs; Timer_B3 in MSP430F15x family has 3 CCRs; in Timer_B3 there are only
interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7654 0
UTXIE0 OFIE WDTIE
321
rw-0 rw-0 rw-0
Address
0h URXIE0 ACCVIE NMIIE
rw-0 rw-0 rw-0
WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
OFIE: Oscillator fault interrupt enable
NMIIE: Nonmaskable interrupt enable
ACCVIE: Flash memory access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable
7654 0
UTXIE1
321
rw-0 rw-0
Address
01h URXIE1
URXIE1†: USART1: UART and SPI receive interrupt enable
UTXIE1†: USART1: UART and SPI transmit interrupt enable
†URXIE1 and UTXIE1 are not present in MSP430F15x devices.
interrupt flag register 1 and 2
7654 0
UTXIFG0 OFIFG WDTIFG
321
rw-0 rw-1 rw-(0)
Address
02h URXIFG0 NMIIFG
rw-1 rw-0
WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7654 0
UTXIFG1
321
rw-1 rw-0
Address
03h URXIFG1
URXIFG1‡: USART1: UART and SPI receive flag
UTXIFG1‡: USART1: UART and SPI transmit flag
‡URXIFG1 and UTXIFG1 are not present in MSP430F15x devices.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
module enable registers 1 and 2
7654 0
UTXE0 321
rw-0 rw-0
Address
04h URXE0
USPIE0
URXE0: USART0: UART mode receive enable
UTXE0: USART0: UAR T mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable
7654 0
UTXE1 321
rw-0 rw-0
Address
05h URXE1
USPIE1
URXE1†: USART1: UART mode receive enable
UTXE1†: USART1: UART mode transmit enable
USPIE1†: USART1: SPI mode transmit and receive enable
†URXE1, UTXE1, and USPIE1 are not present in MSP430F15x devices.
rw-0:
Legend: rw: Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
memory organization, MSP430F15x
MSP430F155 MSP430F156 MSP430F157
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
24KB
0FFFFh − 0FFE0h
0FFFFh − 0A000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory Size
Flash 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h
Boot memory Size
ROM 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h
RAM Size 512B
03FFh − 0200h 1KB
05FFh − 0200h 1KB
05FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
memory organization, MSP430F16x
MSP430F167 MSP430F168 MSP430F169
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
60KB
0FFFFh − 0FFE0h
0FFFFh − 01100h
Information memory Size
Flash 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h
Boot memory Size
ROM 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h
RAM Size 1KB
05FFh − 0200h 2KB
09FFh − 0200h 2KB
09FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
memory organization, MSP430F161x
MSP430F1610 MSP430F1611 MSP430F1612
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
55KB
0FFFFh − 0FFE0h
0FFFFh − 02500h
RAM (Total) Size 5KB
024FFh − 01100h 10KB
038FFh − 01100h 5KB
024FFh − 01100h
Extended Size 3KB
024FFh − 01900h 8KB
038FFh − 01900h 3KB
024FFh − 01900h
Mirrored Size 2KB
018FFh − 01100h 2KB
018FFh − 01100h 2KB
018FFh − 01100h
Information memory Size
Flash 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h
Boot memory Size
ROM 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h
RAM
(mirrored at
018FFh - 01100h)
Size 2KB
09FFh − 0200h 2KB
09FFh − 0200h 2KB
09FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of t h e f e a t u r e s o f the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL FUNCTION PM, RTD PACKAGE PINS
Data Transmit 13 - P1.1
Data Receive 22 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
w/ Interrupt Vectors
Segment 1
Segment 2
Segment n-1
Segment n†
Segment A
Segment B
Main
Memory
Info
Memory
32KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
48KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
08400h
083FFh
08200h
081FFh
08000h
024FFh
01100h
010FFh
01080h
0107Fh
01000h
04400h
043FFh
04200h
041FFh
04000h
038FFh
01100h
010FFh
01080h
0107Fh
01000h
RAM
(’F161x
only)
48KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
60KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
04400h
043FFh
04200h
041FFh
04000h
010FFh
01080h
0107Fh
01000h
01400h
013FFh
01200h
011FFh
01100h
010FFh
01080h
0107Fh
01000h
24KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
32KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0A400h
0A3FFh
0A200h
0A1FFh
0A000h
010FFh
01080h
0107Fh
01000h
08400h
083FFh
08200h
081FFh
08000h
010FFh
01080h
0107Fh
01000h
16KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0C400h
0C3FFh
0C200h
0C1FFh
0C000h
010FFh
01080h
0107Fh
01000h
MSP430F161x
MSP430F15x and MSP430F16x
55KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
02800h
027FFh
02600h
025FFh
02500h
024FFh
01100h
010FFh
01080h
0107Fh
01000h
†MSP430F169 and MSP430F1612 flash segment n = 256 bytes.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number
SLAU049.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430F15x and MSP430F16x(x) family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator
(DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements
of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source
and stabilizes in less than 6 μs. The basic clock module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
DMain clock (MCLK), the system clock used by the CPU.
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) a t that time. The user must insure the default DCO settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
hardware multiplier (MSP430F16x/161x only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
USART0
The MSP430F15x and the MSP430F16x(x) have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered
transmit and receive channels.
The I2C support is compliant with the Philips I2C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported,
as well as master and slave modes. The USART0 also supports 16-bit-wide I2C data transfers and has two
dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C
mode.
USART1 (MSP430F16x/161x only)
The MSP430F16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit
(USART1) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels. With the exception of I2C support, operation of USART1 is identical to USART0.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER DEVICE INPUT
SIGNAL MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL OUTPUT PIN
NUMBER
12 - P1.0 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
21 - P2.1 TAINCLK INCLK
13 - P1.1 TA0 CCI0A 13 - P1.1
22 - P2.2 TA0 CCI0B
CCR0
TA0
17 - P1.5
DVSS GND CCR0 TA0 27 - P2.7
DVCC VCC
14 - P1.2 TA1 CCI1A 14 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
18 - P1.6
DVSS GND CCR1 TA1 23 - P2.3
DVCC VCC ADC12 (internal)
15 - P1.3 TA2 CCI2A 15 - P1.3
ACLK (internal) CCI2B
CCR2
TA2
19 - P1.7
DVSS GND CCR2 TA2 24 - P2.4
DVCC VCC
Timer_B3 (MSP430F15x only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Timer_B7 (MSP430F16x/161x only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3/B7 SIGNAL CONNECTIONS†
INPUT PIN
NUMBER DEVICE INPUT
SIGNAL MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL OUTPUT PIN
NUMBER
43 - P4.7 TBCLK TBCLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
43 - P4.7 TBCLK INCLK
36 - P4.0 TB0 CCI0A 36 - P4.0
36 - P4.0 TB0 CCI0B
CCR0
TB0
ADC12 (internal)
DVSS GND CCR0 TB0
DVCC VCC
37 - P4.1 TB1 CCI1A 37 - P4.1
37 - P4.1 TB1 CCI1B
CCR1
TB1
ADC12 (internal)
DVSS GND CCR1 TB1
DVCC VCC
38 - P4.2 TB2 CCI2A 38 - P4.2
38 - P4.2 TB2 CCI2B
CCR2
TB2
DVSS GND CCR2 TB2
DVCC VCC
39 - P4.3 TB3 CCI3A 39 - P4.3
39 - P4.3 TB3 CCI3B
CCR3
TB3
DVSS GND CCR3 TB3
DVCC VCC
40 - P4.4 TB4 CCI4A 40 - P4.4
40 - P4.4 TB4 CCI4B
CCR4
TB4
DVSS GND CCR4 TB4
DVCC VCC
41 - P4.5 TB5 CCI5A 41 - P4.5
41 - P4.5 TB5 CCI5B
CCR5
TB5
DVSS GND CCR5 TB5
DVCC VCC
42 - P4.6 TB6 CCI6A 42 - P4.6
ACLK (internal) CCI6B
CCR6
TB6
DVSS GND CCR6 TB6
DVCC VCC
†Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERAL FILE MAP
DMA DMA channel 2 transfer size DMA2SZ 01F6h
DMA channel 2 destination address DMA2DA 01F4h
DMA channel 2 source address DMA2SA 01F2h
DMA channel 2 control DMA2CTL 01F0h
DMA channel 1 transfer size DMA1SZ 01EEh
DMA channel 1 destination address DMA1DA 01ECh
DMA channel 1 source address DMA1SA 01EAh
DMA channel 1 control DMA1CTL 01E8h
DMA channel 0 transfer size DMA0SZ 01E6h
DMA channel 0 destination address DMA0DA 01E4h
DMA channel 0 source address DMA0SA 01E2h
DMA channel 0 control DMA0CTL 01E0h
DMA module control 1 DMACTL1 0124h
DMA module control 0 DMACTL0 0122h
DAC12 DAC12_1 data DAC12_1DAT 01CAh
DAC12_1 control DAC12_1CTL 01C2h
DAC12_0 data DAC12_0DAT 01C8h
DAC12_0 control DAC12_0CTL 01C0h
ADC12 Interrupt-vector-word register ADC12IV 01A8h
Inerrupt-enable register ADC12IE 01A6h
Inerrupt-flag register ADC12IFG 01A4h
Control register 1 ADC12CTL1 01A2h
Control register 0 ADC12CTL0 01A0h
Conversion memory 15 ADC12MEM15 015Eh
Conversion memory 14 ADC12MEM14 015Ch
Conversion memory 13 ADC12MEM13 015Ah
Conversion memory 12 ADC12MEM12 0158h
Conversion memory 11 ADC12MEM11 0156h
Conversion memory 10 ADC12MEM10 0154h
Conversion memory 9 ADC12MEM9 0152h
Conversion memory 8 ADC12MEM8 0150h
Conversion memory 7 ADC12MEM7 014Eh
Conversion memory 6 ADC12MEM6 014Ch
Conversion memory 5 ADC12MEM5 014Ah
Conversion memory 4 ADC12MEM4 0148h
Conversion memory 3 ADC12MEM3 0146h
Conversion memory 2 ADC12MEM2 0144h
Conversion memory 1 ADC12MEM1 0142h
Conversion memory 0 ADC12MEM0 0140h
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
ADC12 ADC memory-control register15 ADC12MCTL15 08Fh
(continued) ADC memory-control register14 ADC12MCTL14 08Eh
ADC memory-control register13 ADC12MCTL13 08Dh
ADC memory-control register12 ADC12MCTL12 08Ch
ADC memory-control register11 ADC12MCTL11 08Bh
ADC memory-control register10 ADC12MCTL10 08Ah
ADC memory-control register9 ADC12MCTL9 089h
ADC memory-control register8 ADC12MCTL8 088h
ADC memory-control register7 ADC12MCTL7 087h
ADC memory-control register6 ADC12MCTL6 086h
ADC memory-control register5 ADC12MCTL5 085h
ADC memory-control register4 ADC12MCTL4 084h
ADC memory-control register3 ADC12MCTL3 083h
ADC memory-control register2 ADC12MCTL2 082h
ADC memory-control register1 ADC12MCTL1 081h
ADC memory-control register0 ADC12MCTL0 080h
Timer_B7/ Capture/compare register 6 TBCCR6 019Eh
_
Timer_B3
(see Note 1)
Capture/compare register 5 TBCCR5 019Ch
(see Note 1) Capture/compare register 4 TBCCR4 019Ah
Capture/compare register 3 TBCCR3 0198h
Capture/compare register 2 TBCCR2 0196h
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 6 TBCCTL6 018Eh
Capture/compare control 5 TBCCTL5 018Ch
Capture/compare control 4 TBCCTL4 018Ah
Capture/compare control 3 TBCCTL3 0188h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Reserved 017Eh
_Reserved 017Ch
Reserved 017Ah
Reserved 0178h
Capture/compare register 2 TACCR2 0176h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Reserved 016Eh
Reserved 016Ch
Reserved 016Ah
Reserved 0168h
NOTE 1: Timer_B7 in MSP430F16x/161x family has seven CCRs, Timer_B3 in MSP430F15x family has three CCRs.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
Timer_A3 Capture/compare control 2 TACCTL2 0166h
_
(continued) Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Hardware Sum extend SUMEXT 013Eh
Multiplier
(MSP430F16x and
Result high word RESHI 013Ch
(MSP430F16x and
MSP430F161x
Result low word RESLO 013Ah
MSP430F161
x
onl
y)
Second operand OP2 0138h
only)
Multiply signed +accumulate/operand1 MACS 0136h
Multiply+accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Watchdog Timer control WDTCTL 0120h
USART1 Transmit buffer U1TXBUF 07Fh
(MSP430F16x and
MSP430F161x
Receive buffer U1RXBUF 07Eh
MSP430F161x
only)
Baud rate U1BR1 07Dh
on
l
y
)
Baud rate U1BR0 07Ch
Modulation control U1MCTL 07Bh
Receive control U1RCTL 07Ah
Transmit control U1TCTL 079h
USART control U1CTL 078h
USART0 Transmit buffer U0TXBUF 077h
(UART or
SPI mode)
Receive buffer U0RXBUF 076h
SPI mode) Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
USART0
2
I2C interrupt vector I2CIV 011Ch
(I2C mode) I2C slave address I2CSA 011Ah
I2C own address I2COA 0118h
I2C data I2CDR 076h
I2C SCLL I2CSCLL 075h
I2C SCLH I2CSCLH 074h
I2C PSC I2CPSC 073h
I2C data control I2CDCTL 072h
I2C transfer control I2CTCTL 071h
USART control U0CTL 070h
I2C data count I2CNDAT 052h
I2C interrupt flag I2CIFG 051h
I2C interrupt enable I2CIE 050h
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
Comparator_A Comparator_A port disable CAPD 05Bh
p
_Comparator_A control2 CACTL2 05Ah
Comparator_A control1 CACTL1 059h
Basic Clock Basic clock system control2 BCSCTL2 058h
Basic clock system control1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 055h
Port P6 Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Functions SFR module enable 2 ME2 005h
p
SFR module enable 1 ME1 004h
SFR interrupt flag2 IFG2 003h
SFR interrupt flag1 IFG1 002h
SFR interrupt enable2 IE2 001h
SFR interrupt enable1 IE1 000h
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg: Unprogrammed device −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmed device −55°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V SS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage during program execution,
VCC (AVCC = DVCC = VCC)MSP430F15x/16x/161x 1.8 3.6 V
Supply voltage during flash memory programming, VCC
(AVCC = DVCC = VCC)MSP430F15x/16x/161x 2.7 3.6 V
Supply voltage during program execution, SVS enabled
(see Note 1), VCC (AVCC = DVCC = VCC)MSP430F15x/16x/161x 2 3.6 V
Supply voltage, VSS (AVSS = DVSS = VSS) 0 0 V
Operating free-air temperature range, TAMSP430F15x/16x/161x −40 85 °C
LFXT1 t l f f
LF selected, XTS=0 Watch crystal 32.768 kHz
LFXT1 crystal frequency, f(LFXT1)
(see Notes 2 and 3)
XT1 selected, XTS=1 Ceramic resonator 450 8000 kHz
(
see
N
o
t
es
2
an
d
3)
XT1 selected, XTS=1 Crystal 1000 8000 kHz
XT2 crystal frequency f
Ceramic resonator 450 8000
kHz
XT2 crystal frequency, f(XT2) Crystal 1000 8000 kHz
Processor frequency (signal MCLK) f
VCC = 1.8 V DC 4.15
MHz
Processor frequency (signal MCLK), f(System) VCC = 3.6 V DC 8 MHz
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the VCC is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1-MΩ resistor from XOUT to VSS is recommended when
VCC < 2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15 MHz at VCC ≥ 2.2 V. In
XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8 MHz at VCC ≥ 2.8 V.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f (MHz)
1.8 V 3.6 V
2.7 V 3 V
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
4.15 MHz
8.0 MHz
Supply Voltage − V
Supply voltage range,
’F15x/16x/161x,
during flash memory programming
Supply voltage range,
’F15x/16x/161x, during
program execution
Figure 1. Frequency vs Supply Voltage, MSP430F15x/16x/161x
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
MSP430F15x/16x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Active mode, (see Note 1)
f
(MCLK)
= f
(SMCLK)
= 1 MHz,
T40°Cto85°C
2.2 V 330 400
A
I
f(MCLK)
=
f(SMCLK)
=
1
MHz
,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
TA = −40°C to 85°C3 V 500 600 μA
I(AM) Active mode, (see Note 1)
f
(MCLK)
= f
(SMCLK)
= 4,096 Hz,
T40°Cto85°C
2.2 V 2.5 7
A
f(MCLK)
=
f(SMCLK)
=
4
,
096
Hz
,
f(ACLK) = 4,096 Hz
XTS=0, SELM=3
TA = −40°C to 85°C3 V 9 20 μA
I
Low-power mode, (LPM0)
f(MCLK) = 0 MHz, f(SMCLK) = 1 MHz,
f32 768 Hz
T40°Cto85°C
2.2 V 50 60
A
I(LPM0)
() ()
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
(see Note 1)
TA = −40°C to 85°C3 V 75 90
μA
I
Low-power mode, (LPM2),
f f 0 MHz
T40°Cto85°C
2.2 V 11 14
A
I(LPM2) f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32.768 Hz, SCG0 = 0 TA = −40°C to 85°C3 V 17 22 μA
TA = −40°C 1.1 1.6
Low-power mode (LPM3)
TA = 25°C2.2 V 1.1 1.6
I
L
ow-power mo
d
e,
(LPM3)
f
(MCLK)
= f
(SMCLK)
= 0 MHz, TA = 85°C
2.2
V
2.2 3.0
A
I(LPM3)
f(MCLK)
=
f(SMCLK)
=
0
MHz
,
f(ACLK) = 32,768 Hz, SCG0 = 1
(Nt2)
TA = −40°C 2.2 2.8 μA
(ACLK)
(see Note 2) TA = 25°C3 V 2.0 2.6
TA = 85°C
3
V
3.0 4.3
Low
-
power mode, (LPM4)
TA = −40°C 0.1 0.5
I
(
LPM4
)
Low
-
power
mode
,
(LPM4)
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, TA = 25°C2.2V / 3 V 0.2 0.5 μA
I(LPM4)
f(MCLK)
0
MHz,
f(SMCLK)
0
MHz,
f(ACLK) = 0 Hz, SCG0 = 1 TA = 85°C
2.2V
/
3
V
1.3 2.5
μA
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. WDT is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 210 μA/V × (VCC – 3 V)
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
MSP430F161x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Active mode, (see Note 1)
f
(MCLK)
= f
(SMCLK)
= 1 MHz,
T40°Cto85°C
2.2 V 330 400
A
I
f(MCLK)
=
f(SMCLK)
=
1
MHz
,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
TA = −40°C to 85°C3 V 500 600 μA
I(AM) Active mode, (see Note 1)
f
(MCLK)
= f
(SMCLK)
= 4,096 Hz,
T40°Cto85°C
2.2 V 2.5 7
A
f(MCLK)
=
f(SMCLK)
=
4
,
096
Hz
,
f(ACLK) = 4,096 Hz
XTS=0, SELM=3
TA = −40°C to 85°C3 V 9 20 μA
I
Low-power mode, (LPM0)
f(MCLK) = 0 MHz, f(SMCLK) = 1 MHz,
f32 768 Hz
T40°Cto85°C
2.2 V 50 60
A
I(LPM0)
() ()
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
(see Note 1)
TA = −40°C to 85°C3 V 75 95
μA
I
Low-power mode, (LPM2),
f f 0 MHz
T40°Cto85°C
2.2 V 11 14
A
I(LPM2) f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32.768 Hz, SCG0 = 0 TA = −40°C to 85°C3 V 17 22 μA
TA = −40°C 1.3 1.6
Low-power mode (LPM3)
TA = 25°C2.2 V 1.3 1.6
I
L
ow-power mo
d
e,
(LPM3)
f
(MCLK)
= f
(SMCLK)
= 0 MHz, TA = 85°C
2.2
V
3.0 6.0
A
I(LPM3)
f(MCLK)
=
f(SMCLK)
=
0
MHz
,
f(ACLK) = 32,768 Hz, SCG0 = 1
(Nt2)
TA = −40°C 2.6 3.0 μA
(ACLK)
(see Note 2) TA = 25°C3 V 2.6 3.0
TA = 85°C
3
V
4.4 8.0
Low
-
power mode, (LPM4)
TA = −40°C 0.2 0.5
I
(
LPM4
)
Low
-
power
mode
,
(LPM4)
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, TA = 25°C2.2V / 3 V 0.2 0.5 μA
I(LPM4)
f(MCLK)
0
MHz,
f(SMCLK)
0
MHz,
f(ACLK) = 0 Hz, SCG0 = 1 TA = 85°C
2.2V
/
3
V
2.0 5.0
μA
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. WDT is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 210 μA/V × (VCC – 3 V)
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER VCC MIN TYP MAX UNIT
V
Positive going input threshold voltage
2.2 V 1.1 1.5
V
VIT+ Positive-going input threshold voltage 3 V 1.5 1.98 V
V
Negative going input threshold voltage
2.2 V 0.4 0.9
V
VIT− Negative-going input threshold voltage 3 V 0.9 1.3 V
V
Input voltage hysteresis (V V )
2.2 V 0.3 1.1
V
Vhys Input voltage hysteresis (VIT+ − VIT−)3 V 0.5 1 V
inputs Px.x, TAx, TBx
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
t
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger 2.2 V 62
ns
t(int) External interrupt timing
Port
P1,
P2:
P1.x
to
P2.x,
external
trigger
signal for the interrupt flag (see Note 1) 3 V 50 ns
TA0, TA1, TA2 2.2 V 62
t(cap) Timer_A, Timer_B capture timing TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 2) 3 V 50 ns
f(TAext) Timer_A, Timer_B clock frequenc
y
TACLK TBCLK INCLK: t=t
2.2 V 8
MHz
f(TBext)
Timer
_
A
,
Timer
_
B
clock
frequency
externally applied to pin TACLK, TBCLK, INCLK: t(H) = t(L) 3 V 10 MHz
f(TAint)
Timer A Timer B clock frequency
SMCLK or ACLK signal selected
2.2 V 8
MHz
f(TBint) Timer_A, Timer_B clock frequency SMCLK or ACLK signal selected 3 V 10 MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
2. Seven capture/compare registers in ’F16x/161x and three capture/compare registers in ’F15x.
leakage current − ports P1, P2, P3, P4, P5, P6 (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Ilkg(Px.y) Leakage
current Port Px V(Px.y) (see Note 2) 2.2 V/3 V ±50 nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P3, P4, P5, P6
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC
V
High level output voltage
IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC
V
VOH High-level output voltage IOH(max) = −1.5 mA, VCC = 3 V, See Note 1 VCC−0.25 VCC V
IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC
IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25
V
Low level output voltage
IOL(max) = 6 mA, VCC = 2.2 V, See Note 2 VSS VSS+0.6
V
VOL Low-level output voltage IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25 V
IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(1 ≤x≤60≤y≤7)
CL = 20 pF,
V22V/3V
DC
f
MHz
f(Px.y) (1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
CL
=
20
pF
,
IL = ±1.5 mA VCC = 2.2 V / 3 V DC fSystem MHz
f(ACLK)
f
P2.0/ACLK, P5.6/ACLK
P5 4/MCLK
C20 pF
V22V/3V
f
Syste
m
MHz
f(MCLK)
f(SMCLK) P5.4/MCLK,
P1.4/SMCLK, P5.5/SMCLK CL = 20 pF VCC = 2.2 V / 3 V
fSystem
MHz
P1.0/TACLK
f(ACLK) = f(LFXT1) = f(XT1) 40% 60%
P1
.
0/TACLK
CL = 20 pF f(ACLK) = f(LFXT1) = f(LF) 30% 70%
CL
20
pF
VCC = 2.2 V / 3 V f(ACLK) = f(LFXT1) 50%
P1.1/TA0/MCLK
,
f(MCLK) = f(XT1) 40% 60%
t(Xdc) Duty cycle of output frequency
P1
.
1/TA0/MCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(MCLK) = f(DCOCLK) 50%−
15 ns 50% 50%+
15 ns
P1.4/TBCLK/SMCLK
,
f(SMCLK) = f(XT2) 40% 60%
P1
.
4/TBCLK/SMCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(SMCLK) = f(DCOCLK) 50%−
15 ns 50% 50%+
15 ns
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P3, P4, P5, P6 (continued)
Figure 2
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P3.5
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I − Low-Level Output Current − mA
Figure 3
VOL − Low-Level Output Voltage − V
0
10
20
30
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P3.5
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I − Low-Level Output Current − mA
Figure 4
VOH − High-Level Output Voltage − V
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OH
I − High-Level Output Current − mA
Figure 5
VOH − High-Level Output Voltage − V
−45
−35
−25
−15
−5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OH
I − High-Level Output Current − mA
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(LPM3) Delay time VCC = 2.2 V/3 V, fDCO ≥ fDCO43 6μs
RAM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMh See Note 1 CPU HALTED 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
CAON=1 CARSEL=0 CAREF=0
2.2 V 25 40
μA
I(DD) CAON=1, CARSEL=0, CAREF=0 3 V 45 60 μA
I
CAON=1, CARSEL=0,
CAREF 1/2/3 no load at
2.2 V 30 50
μA
I(Refladder/Refdiode) CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2 3 V 45 71 μA
V(IC) Common-mode input
voltage CAON =1 2.2 V/3 V 0 VCC−1 V
V(Ref025) Voltage @ 0.25 VCC node
VCC
PCA0=1, CARSEL=1, CAREF=1,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2 2.2 V/3 V 0.23 0.24 0.25
V(Ref050) Voltage @ 0.5VCC node
VCC
PCA0=1, CARSEL=1, CAREF=2,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2 2.2 V/3 V 0.47 0.48 0.5
V
(see Figure 6 and Figure 7)
PCA0=1, CARSEL=1, CAREF=3,
no load at P2 3/CA0/TA1 and
2.2 V 390 480 540
mV
V(RefVT) (see Figure 6 and Figure 7) no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2 TA = 85°C3 V 400 490 550 mV
V(offset) Offset voltage See Note 2 2.2 V/3 V −30 30 mV
Vhys Input hysteresis CAON=1 2.2 V/3 V 0 0.7 1.4 mV
TA = 25°C, Overdrive 10 mV, 2.2 V 130 210 300
ns
t
TA
=
25 C
,
Overdrive
10
mV
,
Without filter: CAF=0 3 V 80 150 240 ns
t(response LH) TA = 25°C, Overdrive 10 mV, 2.2 V 1.4 1.9 3.4
μs
TA
=
25 C
,
Overdrive
10
mV
,
With filter: CAF=1 3 V 0.9 1.5 2.6 μs
TA = 25°C, Overdrive 10 mV, 2.2 V 130 210 300
ns
t
TA
=
25 C
,
Overdrive
10
mV
,
Without filter: CAF=0 3 V 80 150 240 ns
t(response HL) TA = 25°C, Overdrive 10 mV, 2.2 V 1.4 1.9 3.4
μs
TA
=
25 C
,
Overdrive
10
mV
,
With filter: CAF=1 3 V 0.9 1.5 2.6 μs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 3 V
Figure 6. V
(
RefVT
)
vs Temperature, VCC = 3 V
V(REFVT) − Reference Volts −mV
Typical
Figure 7. V
(
RefVT
)
vs Temperature, VCC = 2.2 V
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 2.2 V
V(REFVT) − Reference Volts −mV
Typical
_
+
CAON
0
1
V+ 0
1
CAF
Low Pass Filter
τ ≈ 2.0 μs
To Internal
Modules
Set CAIFG
Flag
CAOUT
V−
VCC
1
0 V
0
Figure 8. Block Diagram of Comparator_A Module
Overdrive VCAOUT
t(response)
V+
V−
400 mV
Figure 9. Overdrive Definition
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(BOR) 2000 μs
VCC(Start) dVCC/dt ≤ 3 V/s (see Figure 10) 0.7 × V(B_IT−) V
V(B_IT−)
Brownout
dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) 1.71 V
Vhys(B_IT−)
B
rownout dVCC/dt ≤ 3 V/s (see Figure 10) 70 130 180 mV
t(reset) Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V 2μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of tBOR(delay) after VCC = V(B_IT−) + Vhys(B_IT−). The
default DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x1xx Family User’s Guide (SLAU049) for more information on the brownout/SVS circuit.
typical characteristics
0
1
td(BOR)
VCC
V(B_IT−)
Vhys(B_IT−)
VCC(Start)
BOR
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics (continued)
VCC(min)
VCC
3 V tpw
0
0.5
1
1.5
2
0.001 1 1000
Vcc = 3 V
typical conditions
1 ns 1 ns
tpw − Pulse Width − μs
VCC(min)− V
tpw − Pulse Width − μs
Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
0
0.5
1
1.5
2
Vcc = 3 V
typical conditions
VCC(min)
tpw
tpw − Pulse Width − μs
VCC(min)− V
3 V
0.001 1 1000 tftr
tpw − Pulse Width − μs
tf = tr
Figure 12. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
dVCC/dt > 30 V/ms (see Figure 13) 5 150
μs
t(SVSR) dVCC/dt ≤ 30 V/ms 2000 μs
td(SVSon) SVSON, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V 150 300 μs
tsettle VLD ≠ 0‡12 μs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
SVS_IT−
)
VCC/dt ≤ 3 V/s (see Figure 13) VLD = 2 to 14 V(SVS_IT−)
x 0.004 V(SVS_IT−)
x 0.008
Vhys(SVS
_
IT
−
)
VCC/dt ≤ 3 V/s (see Figure 13),
External voltage applied on A7 VLD = 15 4.4 10.4 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.25
VLD = 3 2.05 2.2 2.37
VLD = 4 2.14 2.3 2.48
VLD = 5 2.24 2.4 2.6
VLD = 6 2.33 2.5 2.71
VCC/dt ≤3 V/s (see Figure 13 and Figure 14)
VLD = 7 2.46 2.65 2.86
V(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 13 and Figure 14) VLD = 8 2.58 2.8 3
V
V
(SVS_IT−) VLD = 9 2.69 2.9 3.13
V
VLD = 10 2.83 3.05 3.29
VLD = 11 2.94 3.2 3.42
VLD = 12 3.11 3.35 3.61†
VLD = 13 3.24 3.5 3.76†
VLD = 14 3.43 3.7†3.99†
VCC/dt ≤ 3 V/s (see Figure 13 and Figure 14),
External voltage applied on A7 VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA
†The recommended operating voltage range is limited to 3.6 V.
‡tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
VCC(start)
AVCC
V(B_IT−)
Brownout
Region
V(SVSstart)
V(SVS_IT−)
Software sets VLD >0:
SVS is active
td(SVSR)
undefined
Vhys(SVS_IT−)
0
1
td(BOR)
Brownout
0
1
td(SVSon)
td(BOR)
0
1
Set POR
Brown-
out
Region
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
SVS out
Vhys(B_IT−)
Figure 13. SVS Reset (SVSR) vs Supply Voltage
0
0.5
1
1.5
2
VCC
VCC
1 ns 1 ns
VCC(min)
tpw
tpw − Pulse Width − μs
VCC(min)− V
3 V
1 10 1000
tftr
t − Pulse Width − μs
100
tpw
3 V
tf = tr
Rectangular Drop
Triangular Drop
VCC(min)
Figure 14. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f
R0 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 0.08 0.12 0.15
MHz
f(DCO03) Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.08 0.13 0.16 MHz
f
R1 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 0.14 0.19 0.23
MHz
f(DCO13) Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.14 0.18 0.22 MHz
f
R2 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 0.22 0.30 0.36
MHz
f(DCO23) Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.22 0.28 0.34 MHz
f
R3 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 0.37 0.49 0.59
MHz
f(DCO33) Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.37 0.47 0.56 MHz
f
R4 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 0.61 0.77 0.93
MHz
f(DCO43) Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 0.61 0.75 0.90 MHz
f
R5 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 1 1.2 1.5
MHz
f(DCO53) Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 1 1.3 1.5 MHz
f
R6 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 1.6 1.9 2.2
MHz
f(DCO63) Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 1.69 2.0 2.29 MHz
f
R7 DCO 3 MOD 0 DCOR 0 T 25°C
2.2 V 2.4 2.9 3.4
MHz
f(DCO73) Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C3 V 2.7 3.2 3.65 MHz
f(DCO47) Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C2.2 V/3 V fDCO40
×1.7 fDCO40
×2.1 fDCO40
×2.5 MHz
f
R7 DCO 7 MOD 0 DCOR 0 T 25°C
2.2 V 4 4.5 4.9
MHz
f(DCO77) Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C3 V 4.4 4.9 5.4 MHz
SRsel SR = fRsel+1 / fRsel 2.2 V/3 V 1.35 1.65 2
SDCO SDCO = f(DCO+1) / f(DCO) 2.2 V/3 V 1.07 1.12 1.16
D
Temperature drift R 4 DCO 3 MOD 0 (see Note 2)
2.2 V −0.31 −0.36 −0.40
%/°C
DtTemperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) 3 V −0.33 −0.38 −0.43 %/°C
DVDrift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
(see Note 2) 2.2 V/3 V 0 5 10 %/V
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System).
2. This parameter is not production tested.
2.2 3
fDCO_0Max
Min
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Max
Min
fDCO_7
DCO
0 1 2 3 4 5 6 7
fDCOCLK
1
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
VCC − V
Frequency Variance
Figure 15. DCO Characteristics
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
main DCO characteristics
DIndividual devices have a minimum and maximum operation frequency. The specified parameters for
f(DCOx0) to f(DCOx7) are valid for all devices.
DAll ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
DDCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.
DModulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage +32 f(DCO) f(DCO)1)
MOD f(DCO))(32*MOD) f(DCO)1)
DCO when using ROSC (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fDCO output frequency
R
se
l = 4, DCO = 3, MOD = 0, DCOR = 1, 2.2 V 1.8±15% MHz
fDCO, DCO output frequency
Rsel
=
4
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
1
,
TA = 25°C3 V 1.95±15% MHz
Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V ±0.1 %/°C
Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V 10 %/V
NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
crystal oscillator, LFXT1 oscillator (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
Integrated input capacitance
XTS=0; LF oscillator selected, VCC = 2.2 V/3 V 12
pF
CXIN Integrated input capacitance XTS=1; XT1 oscillator selected, VCC = 2.2 V/3 V 2pF
C
Integrated output capacitance
XTS=0; LF oscillator selected, VCC = 2.2 V/3 V 12
pF
CXOUT Integrated output capacitance XTS=1; XT1 oscillator selected, VCC = 2.2 V/3 V 2pF
VIL
I t l l t XIN
VCC = 2.2 V/3 V
(N2)
XTS = 0 or 1
XT1 or LF modes VSS 0.2 × VCC
V
V
Input levels at XIN
CC
(see Note 2) XTS = 0, LF mode 0.9 × VCC VCC V
VIH XTS = 1, XT1 mode 0.8 × VCC VCC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CXIN Integrated input capacitance VCC = 2.2 V/3 V 2 pF
CXOUT Integrated output capacitance VCC = 2.2 V/3 V 2 pF
VIL
Input levels at XIN
V= 2 2 V/3 V (see Note 2)
VSS 0.2 × VCC V
VIH Input levels at XIN VCC = 2.2 V/3 V (see Note 2) 0.8 × VCC VCC V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t( )
USART0/USART1: deglitch time
VCC = 2.2 V 200 430 800
ns
t(τ)USART0/USART1: deglitch time VCC = 3 V 150 280 500 ns
NOTE 1: The signal applied to the USART0/USART1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(τ) to ensure
that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V 2.2 3.6 V
V(P6.x/Ax) Analog input voltage
range (see Note 2)
All P6.0/A0 to P6.7/A7 terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
0 ≤ x ≤ 7; V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC) 0 VAVCC V
I
Operating supply current
into AV terminal
fADC12CLK = 5.0 MHz
ADC12ON 1 REFON 0
2.2 V 0.65 1.3
mA
IADC12 into AVCC terminal
(see Note 3) ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0 3 V 0.8 1.6 mA
I
Operating supply current
it AV til
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1 3 V 0.5 0.8 mA
IREF+ into AVCC terminal
(see Note 4) fADC12CLK = 5.0 MHz
ADC12ON 0
2.2 V 0.5 0.8
mA
(see
Note
4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0 3 V 0.5 0.8 mA
CI †Input capacitance Only one terminal can be selected
at one time, P6.x/Ax 2.2 V 40 pF
RI†Input MUX ON resistance 0V ≤ VAx ≤ VAVCC 3 V 2000 Ω
†Not production tested, limits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter IADC12.
4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VeREF+ Positive external
reference voltage input VeREF+ > VREF−/VeREF− (see Note 2) 1.4 VAVCC V
VREF− /VeREF− Negative external
reference voltage input VeREF+ > VREF−/VeREF− (see Note 3) 0 1.2 V
(VeREF+ −
VREF−/VeREF−)Differential external
reference voltage input VeREF+ > VREF−/VeREF− (see Note 4) 1.4 VAVCC V
IVeREF+ Static input current 0V ≤VeREF+ ≤ VAVCC 2.2 V/3 V ±1μA
IVREF−/VeREF− Static input current 0V ≤ VeREF− ≤ VAVCC 2.2 V/3 V ±1μA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external dif ferential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Positive built-in reference REF2_5V = 1 for 2.5 V
IVREF+max ≤IVREF+≤IVREF+min VCC = 3 V 2.4 2.5 2.6
V
VREF+
Positive
built in
reference
voltage output REF2_5V = 0 for 1.5 V
IVREF+max ≤IVREF+≤IVREF+min VCC = 2.2 V/3 V 1.44 1.5 1.56 V
AVCC minimum voltage,
REF2_5V = 0, IVREF+max ≤IVREF+≤IVREF+min 2.2
AVCC
(
min
)
AV
CC
minimum
voltage
,
Positive built-in reference REF2_5V = 1, −0.5mA ≤IVREF+≤IVREF+min 2.8 V
AVCC(min)
Positive
built in
reference
active REF2_5V = 1, −1mA ≤IVREF+≤IVREF+min 2.9
V
I
Load current out of VREF+ VCC = 2.2 V 0.01 −0.5
mA
IVREF+
Load
current
out
of
VREF
+
terminal VCC = 3 V 0.01 −1 mA
IVREF+ = 500 μA +/− 100 μA
Analog input voltage 0 75 V
VCC = 2.2 V ±2
LSB
I†
Load-current re
g
ulation Analog input voltage ~0.75 V,
REF2_5V = 0 VCC = 3 V ±2LSB
IL(VREF)+ †
Load current
regulation
VREF+ terminal IVREF+ = 500 μA ± 100 μA
Analog input voltage ~1.25 V,
REF2_5V = 1 VCC = 3 V ±2 LSB
I‡
Load current re
g
ulation IVREF+ =100 μA → 900 μA,
C 5 μFax 05xV
V3V
20
ns
IDL(VREF) +‡
Load
current
regulation
VREF+ terminal CVREF+=5 μF, ax ~0.5 x VREF+ ,
Error of conversion result ≤ 1 LSB VCC = 3 V 20 ns
CVREF+ Capacitance at pin VREF+
(see Note 1) REFON =1,
0 mA ≤ IVREF+ ≤IVREF+max VCC = 2.2 V/3 V 5 10 μF
TREF+†Temperature coefficient of
built-in reference IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA VCC = 2.2 V/3 V ±100 ppm/°C
tREFON†Settle time of internal
reference voltage (see
Figure 16 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 μF, VREF+ = 1.5 V,
VAVCC = 2.2 V 17 ms
†Not production tested, limits characterized
‡Not production tested, limits verified by design
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 μF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
1 μF
01 ms 10 ms 100 ms tREFON
tREFON ≈.66 x CVREF+ [ms] with CVREF+ in μF
100 μF
10 μF
Figure 16. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
+
−
10 μF 100 nF AVSS
MSP430F15x
MSP430F16x
+
−
+
−
10 μF 100 nF
10 μF 100 nF
AVCC
10 μF 100 nF DVSS
DVCC
From
Power
Supply
Apply
External
Reference
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
MSP430F161x
Figure 17. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply
+
−
10 μF 100 nF AVSS
MSP430F15x
MSP430F16x
+
−
10 μF 100 nF
AVCC
10 μF 100 nF DVSS
DVCC
From
Power
Supply +
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
Reference Is Internally
Switched to AVSS
MSP430F161x
Figure 18. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fADC12CLK For specified performance of ADC12
linearity parameters 2.2V/3 V 0.45 5 6.3 MHz
fADC12OSC Internal ADC12
oscillator ADC12DIV=0,
fADC12CLK=fADC12OSC 2.2 V/ 3 V 3.7 5 6.3 MHz
t
Conversion time
CVREF+ ≥ 5 μF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz 2.2 V/ 3 V 2.06 3.51 μs
tCONVERT Conversion time External fADC12CLK from ACLK, MCLK or SMCLK:
ADC12SSEL ≠ 0 13×ADC12DIV×
1/fADC12CLK μs
tADC12ON‡Turn on settling time of
the ADC (see Note 1) 100 ns
t‡
Sampling time
RS = 400 Ω, RI = 1000 Ω,
C30 pF
3 V 1220
ns
tSample
‡
Sampling time CI = 30 pF
τ = [RS + RI] x CI;(see Note 2) 2.2 V 1400 ns
†Not production tested, limits characterized
‡Not production tested, limits verified by design
NOTES: 1. The condition is that the error in a conversion started after t ADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
E
Integral linearity error
1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V
2 2 V/3 V
±2
LSB
EIIntegral linearity error 1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [VAVCC]2.2 V/3 V ±1.7 LSB
EDDifferential linearity
error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±1 LSB
EOOffset error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±2±4 LSB
EGGain error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±1.1 ±2 LSB
ETTotal unadjusted
error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±2±5 LSB
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
Operatin
g
suppl
y
current into REFON = 0, INCH = 0Ah, 2.2 V 40 120
A
ISENSOR
Operating
supply
current
into
AVCC terminal (see Note 1)
REFON
=
0
,
INCH
=
0Ah
,
ADC12ON=NA, TA = 25_C3 V 60 160 μA
V†
(see Note 2)
ADC12ON = 1, INCH = 0Ah, 2.2 V 986
mV
VSENSOR†(see Note 2)
ADC12ON
=
1
,
INCH
=
0Ah
,
TA = 0°C3 V 986 mV
TC †
ADC12ON 1 INCH 0Ah
2.2 V 3.55 3.55±3%
mV/°C
TCSENSOR†ADC12ON = 1, INCH = 0Ah 3 V 3.55 3.55±3% mV/°C
t†
Sample time required if channel ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤1
2.2 V 30
s
tSENSOR(sample)†
Sample
time
required
if
channel
10 is selected (see Note 3) Error of conversion result ≤1
LSB 3 V 30 μs
I
Current into divider at channel 11
ADC12ON 1 INCH 0Bh
2.2 V NA
A
IVMID
Current
into
divider
at
channel
11
(see Note 4) ADC12ON = 1, INCH = 0Bh, 3 V NA μA
V
AV divider at channel 11
ADC12ON = 1, INCH = 0Bh, 2.2 V 1.1 1.1±0.04
V
VMID AVCC divider at channel 11
ADC12ON
=
1
,
INCH
=
0Bh
,
VMID is ~0.5 x VAVCC 3 V 1.5 1.50±0.04 V
t
Sample time required if channel ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤1
2.2 V 1400
ns
tVMID(sample)
Sample
time
required
if
channel
11 is selected (see Note 5) Error of conversion result ≤ 1
LSB 3 V 1220 ns
†Not production tested, limits characterized
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is already included in IREF+.
2. The temperature sensor of fset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
4. No additional current is needed. The VMID is used during sampling.
5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
12-bit DAC, supply specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC,
AVSS = DVSS =0 V 2.20 3.60 V
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h 2.2V/3V 50 110
I
Supply Current:
Single DAC Channel
DAC12AMPx=2, DAC12IR=1,
DAC12_xDAT=0800h , VeREF+=VREF+= AVCC 2.2V/3V 50 110
A
IDD Single DAC Channel
(see Notes 1 and 2) DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 200 440
μA
DAC12AMPx=7, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 700 1500
PSRR
Power supply
rejection ratio
DAC12_xDAT = 800h, VREF = 1.5 V
ΔAVCC = 100mV 2.2V
70
dB
PSRR rejection ratio
(see Notes 3 and 4) DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V
ΔAVCC = 100mV 3V 70 dB
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{ΔAVCC/ΔVDAC12_xOUT}.
4. VREF is applied externally. The internal reference is not used.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 19)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Resolution (12-bit Monotonic) 12 bits
INL
Integral nonlinearity Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±20
±80
LSB
INL
Integral
nonlinearity
(see Note 1) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V
±2.0 ±8.0 LSB
DNL
Differential nonlinearity Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±04
±10
LSB
DNL
Differential
nonlinearity
(see Note 1) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V
±0.4 ±1.0 LSB
Offset voltage w/o
calibration
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±21
EO
calibration
(see Notes 1, 2) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V
±21
mV
Offset voltage with
calibration
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±25
mV
calibration
(see Notes 1, 2) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V ±2.5
dE(O)/dTOffset error
temperature coefficient
(see Note 1) 2.2V/3V 30 uV/C
E
Gain error (see Note 1)
VREF = 1.5 V 2.2V
±350
% FSR
EGGain error (see Note 1) VREF = 2.5 V 3V ±3.50 % FSR
dE(G)/dTGain temperature
coefficient (see Note 1) 2.2V/3V 10 ppm of
FSR/°C
Time for offset calibration
DAC12AMPx=2 2.2V/3V 100
tOffset_Cal Time for offset calibration
(see Note 3)
DAC12AMPx=3,5 2.2V/3V 32 ms
tOffset
_
Cal
(see Note 3) DAC12AMPx=4,6,7 2.2V/3V 6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AVCC
CLoad = 100pF
2
DAC Output
Figure 19. Linearity Test Load Conditions and Gain/Offset Definition
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
DAC12_xDAT − Digital Code
−4
−3
−2
−1
0
1
2
3
4
0 512 1024 1536 2048 2560 3072 3584
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4095
INL − Integral Nonlinearity Error − LSB
DAC12_xDAT − Digital Code
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
0 512 1024 1536 2048 2560 3072 3584
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
4095
DNL − Differential Nonlinearity Error − LSB
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7 2.2V/3V 0 0.005
V
V
Output voltage
ran
g
e
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7 2.2V/3V AVCC−0.05 AVCC
V
VO
range
(see Note 1,
Figure 22) RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7 2.2V/3V 0 0.1 V
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7 2.2V/3V AVCC−0.13 AVCC V
CL(DAC12)
Max DAC12
load
capacitance 2.2V/3V 100 pF
I
Max DAC12 2.2V −0.5 +0.5 mA
IL(DAC12)
Max
DAC12
load current 3V −1.0 +1.0 mA
RLoad= 3 kΩ
VO/P(DAC12) = 0 V
DAC12AMPx = 7
DAC12_xDAT = 0h
2.2V/3V 150 250
RO/P(DAC12) Output
resistance
(see Figure 22)
RLoad= 3 kΩ
VO/P(DAC12) = AVCC
DAC12AMPx = 7
DAC12_xDAT = 0FFFh
2.2V/3V 150 250 Ω
RLoad= 3 kΩ
0.3 V < VO/P(DAC12) < AVCC − 0.3 V
DAC12AMPx = 7 2.2V/3V 1 4
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
0.3
AVCC
AVCC
−0.3V VOUT
Min
RLoad
AVCC
CLoad
= 100pF
2
ILoad
DAC12
O/P(DAC12_x)
Figure 22. DAC12_x Output Resistance Tests
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Ve
Reference input DAC12IR=0 (see Notes 1 and 2) 2.2V/3V AVCC/3 AVCC+0.2
V
VeREF+
Reference
input
voltage range DAC12IR=1 (see Notes 3 and 4) 2.2V/3V A Vcc AVcc+0.2 V
DAC12_0 IR = DAC12_1 IR = 0 2.2V/3V 20 MΩ
DAC12_0 IR = 1, DAC12_1 IR = 0 2.2V/3V
40
48
56
kΩ
Ri(VREF+),
Ri
Reference input
it
DAC12_0 IR = 0, DAC12_1 IR = 1 2.2V/3V 40 48 56 kΩ
(VREF+)
Ri(VeREF+)
p
resistance DAC12_0 IR = DAC12_1 IR =1,
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5) 2.2V/3V 20 24 28 kΩ
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
2. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / [3*(1 + EG)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
4. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / (1 + EG).
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 23 and Figure 24)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DAC12_xDAT = 800h, DAC12AMPx = 0 → {2, 3, 4} 2.2V/3V 60 120
tON DAC12
on
-
time
_
,
ErrorV(O) < ±0.5 LSB
(see Note
DAC12AMPx = 0 → {5, 6} 2.2V/3V 15 30 μs
ON
on-
ti
me
(
see
N
o
t
e
1,Figure 23) DAC12AMPx = 0 → 7 2.2V/3V 6 12
μ
S ttli ti
DAC12 DAT
DAC12AMPx = 2 2.2V/3V 100 200
tS
(
FS
)
Settling time,
full
-
scale
DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 3,5 2.2V/3V 40 80 μs
tS(FS)
f
u
ll
-sca
l
e
80h
→
F7Fh
→
80h
DAC12AMPx = 4,6,7 2.2V/3V 15 30
μs
S ttli ti
DAC12 xDAT
=DAC12AMPx = 2 2.2V/3V 5
tS
(
C-C
)
Settling time,
code to code
DAC12
_
xDAT
=
3F8h→ 408h→ 3F8h DAC12AMPx = 3,5 2.2V/3V 2 μs
tS(C
-
C)
co
d
e
t
o co
d
e
3F8h→
408h→
3F8h
BF8h→ C08h→ BF8h DAC12AMPx = 4,6,7 2.2V/3V 1
μs
DAC12 DAT
DAC12AMPx = 2 2.2V/3V 0.05 0.12
SR Slew rate DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 3,5 2.2V/3V 0.35 0.7 V/μs
SR
Slew
rate
80h
→
F7Fh
→
80h
DAC12AMPx = 4,6,7 2.2V/3V 1.5 2.7
V/μs
DAC12 DAT
DAC12AMPx = 2 2.2V/3V 10
Glitch energy: full-scale DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 3,5 2.2V/3V 10 nV-s
Glitch
energy:
full scale
80h
→
F7Fh
→
80h
DAC12AMPx = 4,6,7 2.2V/3V 10
nV s
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 23.
2. Slew rate applies to output voltage steps ≥ 200mV.
RLoad
AVCC
CLoad = 100pF
2
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1 Conversion 2
VOUT
Conversion 3
Glitch
Energy +/− 1/2 LSB
+/− 1/2 LSB
tsettleLH tsettleHL
= 3 kΩ
Figure 23. Settling Time and Glitch Energy Testing
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1 Conversion 2
VOUT
Conversion 3
10%
tSRLH tSRHL
90%
10%
90%
Figure 24. Slew Rate Testing
12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 40
BW−3dB 3-dB bandwidth,
VDC=1.5V, VAC=0.1VPP
(see Figure 25)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 180 kHz
(
see
Fi
gure
25)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 550
Channel to channel crosstalk
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h<−>F7Fh, RLoad = 3kΩ
fDAC12_1OUT = 10kHz @ 50/50 duty cycle 2.2V/3V −80
dB
Channel to channel crosstalk
(see Note 1 and Figure 26) DAC12_0DAT = 80h<−>F7Fh, RLoad = 3kΩ,
DAC12_1DAT = 800h, No Load
fDAC12_0OUT = 10kHz @ 50/50 duty cycle 2.2V/3V −80
dB
NOTES: 1. RLOAD = 3 kΩ, CLOAD = 100 pF
VeREF+
AC
DC
RLoad
AVCC
CLoad = 100pF
2
ILoad
DAC12_x DACx
= 3 kΩ
Figure 25. Test Conditions for 3-dB Bandwidth Specification
DAC12_xDAT 080h
VOUT
fToggle
7F7h
VDAC12_yOUT
080h 7F7h 080h
VDAC12_xOUT
e
REF+ RLoad
AVCC
CLoad
= 100pF
2
ILoad
DAC12_1
RLoad
AVCC
CLoad
= 100pF
2
ILoad
DAC12_0 DAC0
DAC1
V
Figure 26. Crosstalk Test Conditions
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
flash memory
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
VCC(PGM/
ERASE) Program and erase supply voltage 2.7 3.6 V
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA
IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA
tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms
tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time 35
tBlock, 0Block program time for 1st byte or word 30
tBlock, 1-63 Block program time for each additional byte or word
see Note 3
21
t
tBlock, End Block program end-sequence wait time see Note 3 6tFTG
tMass Erase Mass erase time 5297
tSeg Erase Segment erase time 4819
NOTES: 1. The cu m ulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG interface
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
f
TCK input frequency
see Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency see Note 1 3 V 0 10 MHz
RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1 ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 J TAG/Test and emulation features is possible. The JT AG block is switched
to bypass mode.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics
port P1, P1.0 to P1.7, input/output with Schmitt trigger
P1.0/TACLK ...
P1IN.x
Module X IN
Pad Logic
Interrupt
Flag
Edge
Select
Interrupt
P1SEL.x
P1IES.x
P1IFG.x
P1IE.xP1IRQ.x
EN
D
Set
EN
Q
P1OUT.x
P1DIR.x
P1SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1P1.7/TA2
PnSel.x PnDIR.x Dir. CONTROL
FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x
P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 DVSS P1IN.0 TACLK†P1IE.0 P1IFG.0 P1IES.0
P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.1 Out0 signal†P1IN.1 CCI0A†P1IE.1 P1IFG.1 P1IES.1
P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 signal†P1IN.2 CCI1A†P1IE.2 P1IFG.2 P1IES.2
P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal†P1IN.3 CCI2A†P1IE.3 P1IFG.3 P1IES.3
P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4
P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 Out0 signal†P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5
P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out1 signal†P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6
P1Sel.7 P1DIR.7 P1DIR.7 P1OUT.7 Out2 signal†P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7
†Signal from or to Timer_A
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt trigger
P2IN.x
P2OUT.x
Pad Logic
P2DIR.x
P2SEL.x
Module X OUT
Edge
Select
Interrupt
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2IRQ.x
Direction Control
P2.0/ACLK
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
DBus Keeper
CAPD.X
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.6/ADC12CLK/DMAE0
P2.7/TA0
0: Input
1: Output
x: Bit Identifier 0 to 2, 6, and 7 for Port P2
From Module
PnSel.x PnDIR.x Dir. CONTROL
FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x
P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P2IES.0
P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 DVSS P2IN.1 INCLK‡P2IE.1 P2IFG.1 P2IES.1
P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT†P2IN.2 CCI0B‡P2IE.2 P2IFG.2 P2IES.2
P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 ADC12CLK¶P2IN.6 DMAE0#P2IE.6 P2IFG.6 P2IES.6
P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 Out0 signal§P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7
†Signal from Comparator_A
‡Signal to Timer_A
§Signal from Timer_A
¶ADC12CLK signal is output of the 12-bit ADC module
#Signal to DMA, channel 0, 1 and 2
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P2, P2.3 to P2.4, input/output with Schmitt trigger
Bus Keeper
P2IN.3
P2OUT.3
Pad Logic
P2DIR.3
P2SEL.3
Module X OUT
Edge
Select
Interrupt
P2SEL.3
P2IES.3
P2IFG.3
P2IE.3P2IRQ.3
Direction Control
From Module P2.3/CA0/TA1
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
D
P2IN.4
P2OUT.4
Pad Logic
P2DIR.4
P2SEL.4
Module X OUT
Edge
Select
Interrupt
P2SEL.4
P2IES.4
P2IFG.4
P2IE.4P2IRQ.4
Direction Control
From Module P2.4/CA1/TA2
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
D
Comparator_A
−
+
Reference Block
CCI1B
CAF CAREFP2CA
CAEX
CAREF
Bus Keeper
CAPD.3
CAPD.4
To Timer_A3
0: Input
1: Output
0: Input
1: Output
PnSel.x PnDIR.x DIRECTION
CONTROL
FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x
P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal†P2IN.3 unused P2IE.3 P2IFG.3 P2IES.3
P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal†P2IN.4 unused P2IE.4 P2IFG.4 P2IES.4
†Signal from Timer_A
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P2, P2.5, input/output with Schmitt trigger and Rosc function for the basic clock module
P2IN.5
P2OUT.5
Pad Logic
P2DIR.5
P2SEL.5
Module X OUT
Edge
Select
Interrupt
P2SEL.5
P2IES.5
P2IFG.5
P2IE.5P2IRQ.5
Direction Control
P2.5/Rosc
0
1
0
1
Interrupt
Flag
Set
EN
Q
DCOR
Module X IN
EN
D
to
01
DC Generator
Bus Keeper
CAPD.5
DCOR: Control Bit From Basic Clock Module
If it Is Set, P2.5 Is Disconnected From P2.5 Pad
Internal to
Basic Clock
Module
VCC
0: Input
1: Output
From Module
PnSel.x PnDIR.x DIRECTION
CONTROL
FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x
P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 DVSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt trigger
P3.0/STE0
P3IN.x
Module X IN
Pad Logic
EN
D
P3OUT.x
P3DIR.x
P3SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1P3.4/UTXD0
P3.5/URXD0
0: Input
1: Output
x: Bit Identifier, 0 and 4 to 7 for Port P3
P3.6/UTXD1‡
P3.7/URXD1¶
PnSel.x PnDIR.x DIRECTION
CONTROL
FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN
P3Sel.0 P3DIR.0 DVSS P3OUT.0 DVSS P3IN.0 STE0
P3Sel.4 P3DIR.4 DVCC P3OUT.4 UTXD0†P3IN.4 Unused
P3Sel.5 P3DIR.5 DVSS P3OUT.5 DVSS P3IN.5 URXD0§
P3Sel.6 P3DIR.6 DVCC P3OUT.6 UTXD1‡P3IN.6 Unused
P3Sel.7 P3DIR.7 DVSS P3OUT.7 DVSS P3IN.7 URXD1¶
†Output from USART0 module
‡Output from USART1 module
‡Input to USART0 module
¶Input to USART1 module
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P3, P3.1, input/output with Schmitt trigger
P3.1/SIMO0/SDA
P3IN.1
Pad Logic
EN
D
P3OUT1
P3DIR.1
P3SEL.1
(SI)MO0 or SDAo/p
0
1
0
1
DCM_SIMO
SYNC
MM
STE
STC
From USART0
SI(MO)0 or SDAi/p
To USAET0
0: Input
1: Output
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P3, P3.2, input/output with Schmitt trigger
P3.2/SOMI0
P3IN.2
Pad Logic
EN
D
P3OUT.2
P3DIR.2
P3SEL.2 0
1
0
1
DCM_SOMI
SYNC
MM
STE
STC
SO(MI)0
From USART0
(SO)MI0
To USART0
0: Input
1: Output
port P3, P3.3, input/output with Schmitt-trigger
P3.3/UCLK0/SCL
P3IN.3
Pad Logic
EN
D
P3OUT.3
P3DIR.3
P3SEL.3
UCLK.0
0
1
0
1
DCM_UCLK
SYNC
MM
STE
STC
From USART0
UCLK0
To USART0
0: Input
1: Output
NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
I2C, slave mode: The clock applied to SCL is used to shift data in and out. The frequency of the clock source of the module must be
w 10 times the frequency of the SCL clock.
I2C, master mode: To shift data in and out, the clock is supplied via the SCL terminal to all I2C slaves. The frequency of the clock source
of the module must be w 10 times the frequency of the SCL clock.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P4, P4.0 to P4.6, input/output with Schmitt trigger
P4OUT.x
Module X OUT
P4DIR.x
Direction Control
From Module
P4SEL.x
D
EN
0
1
1
0
Module X IN
P4IN.x
0: Input
1: Output
Bus
Keeper
Module IN of pin
P5.7/TBOUTH/SVSOUT
x: Bit Identifier, 0 to 6 for Port P4
P4.0/TB0 ...
P4.6/TB6
P4SEL.7
P4DIR.7
PnSel.x PnDIR.x DIRECTION
CONTROL
FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN
P4Sel.0 P4DIR.0 P4DIR.0 P4OUT.0 Out0 signal†P4IN.0 CCI0A / CCI0B‡
P4Sel.1 P4DIR.1 P4DIR.1 P4OUT.1 Out1 signal†P4IN.1 CCI1A / CCI1B‡
P4Sel.2 P4DIR.2 P4DIR.2 P4OUT.2 Out2 signal†P4IN.2 CCI2A / CCI2B‡
P4Sel.3 P4DIR.3 P4DIR.3 P4OUT.3 Out3 signal†P4IN.3 CCI3A / CCI3B‡
P4Sel.4 P4DIR.4 P4DIR.4 P4OUT.4 Out4 signal†P4IN.4 CCI4A / CCI4B‡
P4Sel.5 P4DIR.5 P4DIR.5 P4OUT.5 Out5 signal†P4IN.5 CCI5A / CCI5B‡
P4Sel.6 P4DIR.6 P4DIR.6 P4OUT.6 Out6 signal†P4IN.6 CCI6A
†Signal from Timer_B
‡Signal to Timer_B
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P4, P4.7, input/output with Schmitt trigger
P4.7/TBCLK
P4IN.7
Timer_B,
Pad Logic
EN
D
P4OUT.7
P4DIR.7
P4SEL.7 0
1
0
1
TBCLK
0: Input
1: Output
DVSS
port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt trigger
P5.0/STE1
P5IN.x
Module X IN
Pad Logic
EN
D
P5OUT.x
P5DIR.x
P5SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
x: Bit Identifier, 0 and 4 to 7 for Port P5
0: Input
1: Output
PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN
P5Sel.0 P5DIR.0 DVSS P5OUT.0 DVSS P5IN.0 STE.1
P5Sel.4 P5DIR.4 DVCC P5OUT.4 MCLK P5IN.4 unused
P5Sel.5 P5DIR.5 DVCC P5OUT.5 SMCLK P5IN.5 unused
P5Sel.6 P5DIR.6 DVCC P5OUT.6 ACLK P5IN.6 unused
P5Sel.7 P5DIR.7 DVSS P5OUT.7 SVSOUT P5IN.7 TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with T imer_B7.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P5, P5.1, input/output with Schmitt trigger
P5.1/SIMO1
P5IN.1
Pad Logic
EN
D
P5OUT.1
P5DIR.1
P5SEL.1 0
1
0
1
DCM_SIMO
SYNC
MM
STE
STC
(SI)MO1
From USART1
SI(MO)1
To USART1
0: Input
1: Output
port P5, P5.2, input/output with Schmitt trigger
P5.2/SOMI1
P5IN.2
Pad Logic
EN
D
P5OUT.2
P5DIR.2
P5SEL.2 0
1
0
1
DCM_SOMI
SYNC
MM
STE
STC
SO(MI)1
From USART1
(SO)MI1
To USART1
0: Input
1: Output
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P5, P5.3, input/output with Schmitt trigger
P5.3/UCLK1
P5IN.3
Pad Logic
EN
D
P5OUT.3
P5DIR.3
P5SEL.3 0
1
0
1
DCM_SIMO
SYNC
MM
STE
STC
UCLK1
From USART1
UCLK1
To USART1
0: Input
1: Output
NOTE: UART mode: The UAR T clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction
is always input.
SPI, slave mode: The clock applied to UCLK1 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P6, P6.0 to P6.5, input/output with Schmitt trigger
P6IN.x
Module X IN
Pad Logic
EN
D
P6OUT.x
P6DIR.x
P6SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
Bus Keeper
To ADC
From ADC
0: Input
1: Output
x: Bit Identifier, 0 to 5 for Port P6
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 μA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x PnDIR.x DIR. CONTROL
FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN
P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 unused
P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 unused
P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 unused
P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 unused
P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 unused
P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P6, P6.6, input/output with Schmitt trigger
0, if DAC12.0CALON = 0 and DAC12.0AMP > 1
P6OUT.6
DVSS
P6DIR.6
P6DIR.6
P6SEL.6
D
EN
0
1
1
0
0: Port Active, T-Switch Off
1: T-Switch On, Port Disabled
P6.6/A6/DAC0
P6IN.6
Pad Logic
0: Input
1: Output
Bus
Keeper
1
0
1, if DAC12.0AMP = 1
’1’, if DAC12.0AMP > 0
1, if DAC12.0AMP >1
+
−
INCH = 6†
a6†
†Signal from or to ADC12
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P6, P6.7, input/output with Schmitt trigger
0, if DAC12.0CALON = 0 and DAC12.0AMP > 1
P6OUT.7
DVSS
P6DIR.7
P6DIR.7
P6SEL.6
D
EN
0
1
1
0
0: Port Active, T-Switch Off
1: T-Switch On, Port Disabled
P6.7/A7/
P6IN.7
Pad Logic
0: Input
1: Output
Bus
Keeper
1
0
1, if DAC12.0AMP = 1
’1’, if DAC12.0AMP > 0
1, if DAC12.0AMP > 1
+
−
INCH = 7‡
a7‡
†Signal to SVS Block, Selected if VLD = 15
‡Signal From or To ADC12
§VLD Control Bits are Located in SVS
DAC1/SVSIN
To SVS Mux (15)†
’1’, if VLD = 15§
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDI
TDO
TMS
TCK
Test
JTAG
and
Emulation
Module
Burn & Test
Fuse
Controlled by JTAG
Controlled by JTAG
Controlled
by JTAG DVCC
DVCC
DVCC During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TDO/TDI
TDI/TCLK
TMS
TCK
Fuse
DVCC
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITDI/TCLK
Figure 27. Fuse Check Mode Current, MSP430F15x/16x/161x
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
SLAS368G − O C TOBER 2002 − REVISED MARCH 2011
66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Sheet Revision History
LITERATURE
NUMBER SUMMARY
SLAS368F In absolute maximum ratings table, changed Tstg min from −40°C to −55°C (page 25)
Added Development Tools Support section (page 2)
SLAS368G Changed limits on td(SVSon) parameter (page 35)
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F155IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F155IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F155IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F155IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F156IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F156IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F156IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F156IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F157IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F157IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F157IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F157IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F1610IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F1610IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F1610IRTD ACTIVE VQFN RTD 64 TBD Call TI Call TI
MSP430F1610IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F1610IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F1611IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F1611IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F1611IRTD ACTIVE VQFN RTD 64 TBD Call TI Call TI
MSP430F1611IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F1611IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F1612IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F1612IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F1612IRTD ACTIVE VQFN RTD 64 TBD Call TI Call TI
MSP430F1612IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F1612IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F167IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F167IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F167IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F167IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F168IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F168IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F168IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F168IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F169IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F169IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F169IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F169IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F1610IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430F1611IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430F1612IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F1610IPMR LQFP PM 64 1000 367.0 367.0 45.0
MSP430F1611IPMR LQFP PM 64 1000 367.0 367.0 45.0
MSP430F1612IPMR LQFP PM 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
