Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
General Description
The MAX11253/MAX11254 evaluation kit (EV kit) pro-
vides a proven design to evaluate the MAX11253/
MAX11254 family of 16-bit/24-bit, 6-channel, 64ksps,
integrated PGA delta-sigma ADCs. The EV kit includes
a graphical user interface (GUI) that provides communi-
cation from the target device to the PC. The EV kit can
operate in multiple modes:
1) Standalone Mode: in “standalone” mode, the EV
kit is connected to the PC via a USB cable and
performs a subset of the complete EV kit functions
with limitations for sample rate, sample size, and no
support for coherent sampling.
2) FPGA Mode: in “FPGA” mode, the EV kit is
connected to an Avnet ZedBoard™ through a low-
pin-count FMC connector. ZedBoard features a
Xilinx® Zynq® -7000 SoC, which connects to the
PC through an Ethernet port, allowing the GUI to
perform different operations with full control over
mezzanine card functions. The EV kit with FPGA
platform performs the complete suite of evaluation
tests for the target IC.
3) User-Supplied SPI Mode: In addition to the USB and
FMC interfaces, the EV kit provides a 12-pin Pmod™-
style header for user-supplied SPI interface to con-
nect the signals for SCLK, DIN, DOUT, and CNVST.
The EV kit includes Windows XP®, Windows® 7, and
Windows 8.1-compatible software for exercising the fea-
tures of the IC. The EV kit GUI allows different sample
sizes, adjustable sampling rates, internal or external ref-
erence options, and graphing software that includes the
FFT and histogram of the sampled signals.
The ZedBoard accepts a +12V AC-DC wall adapter. The
EV kit can be powered by a local +12V supply. The EV kit
has on-board transformers and digital isolators to sepa-
rate the IC from the ZedBoard/on-board processor.
The MAX11253/MAX11254 EV kit comes installed with a
MAX11253ATJ+ or MAX11254ATJ+ in a 32-pin TQFN-EP
package.
Features
●High-Speed USB Connector, FMC Connector, and
Pmod-Style Connector
●8MHz SPI Clock Capability through FMC Connector
●8MHz SPI Clock Capability in Standalone Mode
●Various Sample Sizes and Sample Rates
●Collects Up to 1 Million Samples
(with FPGA Platform)
●Time Domain, Frequency Domain, and Histogram
Plotting
●Sync In and Sync Out for Coherent Sampling
(with FPGA Platform)
●On-Board Input Buffers: MAX9632 and MAX44205
(Fully Differential)
●On-Board Voltage References
(MAX6126 and MAX6070)
●Proven PCB Layout
●Fully Assembled and Tested
●Windows XP-, Windows 7-, and Windows
8.1-Compatible Software
Pmod is a trademark of Digilent Inc.
ZedBoard is a trademark of Avnet, Inc.
Xilinx and Zynq are registered trademarks and Xilinx is a regis-
tered service mark of Xilinx, Inc.
Windows and Windows XP are registered trademarks and reg-
istered service marks of Microsoft Corporation.
Ordering Information appears at end of data sheet.
19-7584; Rev 2; 4/18
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX11253/11254 EV Kit Photo
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Quick Start
Required Equipment
●MAX11253/MAX11254 EV kit
●+12V (500mA) power supply
●Micro-USB cable
●ZedBoard FPGA platform
(optional – NOT INCLUDED with EVKit)
●Function generator (optional)
●Windows XP, Windows 7, or Windows 8.1 PC with a
spare USB port
Note: In the following section(s), software-related items
are identified by bolding. Text in bold refers to items direct-
ly from the EV system software. Text in bold and under-
line refers to items from the Windows operating system.
Procedure
The EV kit is fully assembled and tested. Follow the steps
below to verify board operation:
1) Visit http://www.maximintegrated.com/evkitsoft-
ware to download the latest version of the EV kit soft-
ware, MAX11253_54EVKITSetupV1.0.zip. Save the
EV kit software to a temporary folder and uncompress
the ZIP le.
2) Install the EV kit software and USB driver on your
computer by running the MAX11253_54EVKitSetupV1.0.exe
program inside the temporary folder. The program
les are copied to your PC and icons are created in
the Windows Start | Programs menu. At the end of
the installation process the installer will launch the in-
staller for the FTDIChip CDM drivers.
MAX11253/MAX11254 EV Kit Files
System Block Diagram
FILE DECRIPTION
MAX11253_54EVKitSetupV1.0.exe Application Program
(GUI)
Boot.bin
ZedBoard rmware
(SD card to boot
Zynq)
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
For Standalone mode:
1) Verify that all jumpers are in their default positions for
the EV kit board (Table 2).
2) Connect the PC to the EV kit using a micro-USB ca-
ble.
3) Connect the +12V adapter to the EV kit.
4) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. From the Device menu select
Standalone. Verify that the lower left status bar indi-
cates the EV Kit hardware is Connected.
For FPGA mode (when connected to a Zedboard):
1) Connect the Ethernet cable from the PC to the Zed-
Board and congure the Internet Protocol Version
4 (TCP/Ipv4) properties in the local area connec-
tion to IP address 192.168.1.2 and subnet Mask to
255.255.255.0.
2) Verify that the ZedBoard SD card contains the Boot.
bin le for the MAX11253/MAX11254 EV kit.
3) Connect the EV kit FMC connector to the ZedBoard
FMC connector. Gently press them together.
4) Verify that all jumpers are in their default positions for
the ZedBoard (Table 1) and EV kit board (Table 2).
5) Connect the 12V power supply to the ZedBoard.
Leave the Zedboard powered o󰀨.
6) Enable the ZedBoard power supply by sliding SW8 to
ON and connect the +12V adapter to the EV kit.
7) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. From the Device menu select
FPGA. Verify that the lower left status bar indicates
the EV Kit hardware is Connected.
For Either Standalone or FPGA Mode:
1) Connect the positive terminal of the function genera-
tor to the AIN0D+ (TP1) test point on the EV kit. Con-
nect the negative terminal of the function generator to
the AIN0D- (TP2) test point on the EV kit.
2) Congure the signal source to generate a 100Hz,
1VP-P sinusoidal wave with +1V o󰀨set.
3) Turn on the function generator.
4) In the Device menu, choose either standalone or the
FPGA option. In the conguration group, select Chan-
nel 0 and click Convert in the serial interface menu.
5) Click on the Scope tab.
6) Check the Remove DC O󰀨set checkbox to remove
the DC component of the sampled data.
7) Click the Capture button to start the data analysis.
8) The EV kit software appears as shown in Figure 1.
9) Verify that the frequency, which is displayed on the
right, is approximately 100Hz. The scope image has
buttons in the upper right corner that allow zooming
in to detail.
Table 1. ZedBoard Jumper Settings
JUMPER SHUNT POSITION DESCIPTION
J18 1-2 VDDIO set for 3.3V.
JP11
JP10
JP9
JP8
JP7
2-3
1-2
1-2
2-3
2-3
Boot from SD Card
J12 NA SD Card installed
J20 NA Connected to 12V wall adapter
SW8 OFF ZedBoard power switch, OFF while connecting boards
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Table 2. MAX11253/MAX11254 Board Jumper Settings
HEADER JUMPER
POSITION DESCRIPTION
JMP1
1-2* Use MAX6126 3.0V as VREF
signal
1-3 Use MAX6070 3.0V as VREF
signal
1-4 Use MAX6070 1.8V as VREF
signal
J8 Open* Generate +3.3V for DVDD
1-2 Generate +2.0V for DVDD
J10 1-2* Select +3.3V or +2.0V as DVDD
2-3 Select +1.8V as DVDD
J11
Open* U1 uses internal clock
1-2 External clock from FPGA
2-3 External clock from U10
J12 1-2* Select +3.3V as AVDD
2-3 Select +1.8V as AVDD
J13
1-2* Select AVSS as REFN
2-3 Select REFN_S from J1 as
REFN for external sense point
J14
Open* Use internal 1.8V subregulator if
DVDD ≥ 2.0V
1-2 Use DVDD for internal logic if
DVDD ≤ 2.0V
J15 Open* Use TP23 as GPIO1
1-2 Use external SYNC signal
J16
1-2* Select REFP_F signal as REFP
input
2-3 Select REFP_S signal from J1
as REFP input
J17
1-2* Use AGND as AVSS. Use this
setting if AVDD is +3.3V
2-3 Use -1.8V as AVSS. Use this
setting if AVDD is +1.8V
J24 1-2* Use VREF as REFP_F
2-3 Use AVDD as REFP_F
J31
1-2*
Short AIN2.1- (J27, TP38) to
AGND and for U11 noninverting
conguration
3-4*
Short AIN2.1+ (J28, TP39) to
AGND and for U11 inverting
conguration
HEADER JUMPER
POSITION DESCRIPTION
J32
1-2*
Short AIN2.3- (J29, TP42) to
AGND and for U12 noninverting
conguration
3-4*
Short AIN2.3+ (J30, TP43) to
AGND and for U12 inverting
conguration
J33
1-2*
Short AIN2.2- (TP40) to AGND
and for U13 noninverting
conguration
3-4*
Short AIN2.2+ (TP41) to
AGND and for U13 inverting
conguration
J34
1-2*
Short AIN2.4- (TP44) to AGND
and for U14 noninverting
conguration
3-4*
Short AIN2.4+ (TP45) to
AGND and for U14 inverting
conguration
J35
1-2* Connect output of U11 to
inverting input of U13
3-4 Connect AIN2.2- (TP40) to
inverting input of U13
5-6 Connect output of U11 to
noninverting input of U13
7-8* Connect AIN2.2+ (TP41) to
noninverting input of U13
J36
1-2* Connect output of U12 to
inverting input of U14
3-4 Connect AIN2.4- (TP44) to
inverting input of U14
5-6 Connect output of U12 to
noninverting input of U14
7-8* Connect AIN2.4+ (TP45) to
noninverting input of U14
J37 Open* No o󰀨set to U13 noninverting
input
1-2 O󰀨set U13 output by VREF/2
J38 Open* No o󰀨set to U14 noninverting
input
1-2 O󰀨set U14 output by VREF/2
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*Default configuration
Table 2. MAX11253/MAX11254 Board Jumper Settings (continued)
HEADER JUMPER
POSITION DESCRIPTION
J39
1-2*
Short AIN3.1- (TP56) to AGND
and for U15 noninverting
conguration
3-4*
Short AIN3.1+ (TP57) to
AGND and for U15 inverting
conguration
J40
1-2*
Short AIN3.3- (TP60) to AGND
and for U16 noninverting
conguration
3-4*
Short AIN3.3+ (TP61) to
AGND and for U16 inverting
conguration
J41
1-2*
Short AIN3.2- (TP58) to AGND
and for U17 noninverting
conguration
3-4*
Short AIN3.2+ (TP59) to
AGND and for U17 inverting
conguration
J42
1-2*
Short AIN3.4- (TP62) to AGND
and for U18 noninverting
conguration
3-4*
Short AIN3.4+ (TP63) to
AGND and for U18 inverting
conguration
J43
1-2* Connect output of U15 to
inverting input of U17
3-4 Connect AIN3.2- (TP58) to
inverting input of U17
5-6 Connect output of U15 to
noninverting input of U17
7-8* Connect AIN3.2+ (TP59) to
noninverting input of U17
J44
1-2* Connect output of U16 to
inverting input of U18
3-4 Connect AIN3.4- (TP62) to
inverting input of U18
5-6 Connect output of U16 to
noninverting input of U18
7-8* Connect AIN3.4+ (TP63) to
noninverting input of U18
J45 Open* No o󰀨set to U17 noninverting
input
1-2 O󰀨set U17 output by VREF/2
HEADER JUMPER
POSITION DESCRIPTION
J46 Open* No o󰀨set to U18 noninverting
input
1-2 O󰀨set U18 output by VREF/2
J49
1-2* Short AIN4+ (J47, TP72) to
AGND
3-4* Short AIN4- (J48, TP73) to
AGND
J50 1-2* Short AIN5+ (TP74) to AGND
3-4* Short AIN5- (TP75) to AGND
J63 Open* Use external +12V source
1-2 Use +12V from ZedBoard
J64
Open If connected to ZedBoard FPGA
1-2* If connected to PC through USB
interface
J65
1-2*
Enable U28 H-bridge transformer
driver to use onboard ±15V
supply generation
2-3
Disable U28 and use and
external ±15V supply to TP83,
TP86, and TP87
J66
1-2 Use an external -15V power
supply, connected to TP86
3-4* Use U28 driver to generate
isolated -15V
J67
1-2 Use an external +15V power
supply, connected to TP83
3-4* Use U28 driver to generate
isolated +15V
J68
1-2 Use an external +12V power
supply to TP91 as VCC
3-4* Use onboard +12V from U32
LDO as VCC
J69
1-2 AGND as VEE
3-4 Use an external -12V power
supply to TP90 as VEE
5-6* Use onboard -12V from U33
LDO as VEE
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General Description of Software
The main window of the EV kit software contains seven
tabs: Configuration, Scope, DMM, Histogram, FFT, Scan
Mode, and Registers. The Configuration tab provides
control for the ADC configuration including calibration and
data capture. The other six tabs are used for evaluating
the data captured by the ADC.
Conguration Tab
The Configuration tab provides an interface for selecting
and configuring the ADC from a functional perspective.
Select the desired Device for either Standalone or FPGA
in the dropdown menu and the corresponding properties
of the device are displayed including Channel number,
Sample Rate, Number of Samples, Reference Voltage,
Sequencing Mode, Calibration, GPO/GPIO selec-
tion, Input Path (Direct or internal PGA), Delta-Sigma
Modulator type selection for different Data Format and
Conversion Mode, Serial Interface function (Convert,
and Read All), Power setting (NOP, Power Down, and
Standby), Reset Registers, and RSTB Reset, Clock/
SYNC (Internal or External Clock, and Disable or Enable
SYNC Mode), and Other for Disable or Enable Current
Sink/Source and CAPREG LDO.
The sample settings are available on the left of the config-
uration menu, which allow the user to select the Channel,
Sample Rate, Number of Samples and Clock Source if
FPGA device is used.
The Read Data and Status information is displayed on
the right, which shows the data in both voltage and Hex,
the sample rate, and power state for the selected chan-
nel. In addition, if there are any errors, the indicator lights
will turn red.
Channel Selection
To select the desired channel among the six available
channels, click Channel # dropdown menu at the top left
and select the desired channel from 0 to 5. The default
selection is Channel 0.
Figure 1. EV Kit Software (Configuration Tab)
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Sample Rate (SPS)
To select the desired data rate for single-cycle mode from
50sps to 12800sps and for continuous mode data rate
from 1.9sps to 64000sps, choose the Sample Rate (SPS)
from the dropdown menu below the Channel # selection.
Reference Voltage
There are three different reference voltages available
on board: MAX6070AUT18+ (1.8V), MAX6070AUT30+
(3.0V), and MAX6126AASA30+ (3.0V). To select 1.8V,
place JMP1 from position 1 to 4. To select 3.0V MAX6070
with ±0.04% accuracy, place JMP1 from position 1 to 3. To
select 3.0V MAX6126 with ±0.02% accuracy, place JMP1
from position 1 to 2.
Sequencer Mode
To change the sequencer mode, click the Sequence
Mode selection below the Sequencing menu and select
Mode 1, 2, or 3 as desired. Check the GPO Sequencer
Mode box to enable GPO/GPIO function in mode 3. In
addition, check the Enable box to enable the MUX and
GPO Delay. Choose the desired delay in microseconds
by clicking on the + or – buttons.
ADC Calibration
Two types of software calibration for offset and gain are
available: Self calibration and system calibration.
The primary mode for calibration is using the dropdown
list to select a calibration mode, followed by clicking the
Calibrate button. The checkboxes for Self Offset, Self
Gain, System Offset, and System Gain allow for the
user to enable or disable the calibration values. The cali-
bration values can also be changed manually by entering
a hex value in the numeric box.
GPO/GPIO
To select GPO or GPIO ports, choose the option under the
GPO/GPIO dropdown menu and check the Enable box.
Input Path
Select Direct under the Input Path dropdown menu to
bypass the internal amplifiers and apply the analog input
signals directly to the MAX11253/MAX11254 inputs or to
use the external amplifiers.
Select PGA under the Input Path dropdown menu to use
the internal programmable gain amplifiers.
Delta-Sigma Modulator
To select the desired data format, click the Data Format
dropdown menu under the Delta-Sigma Modulator
section and choose either Bipolar or Unipolar with two’s
complement or offset binary options.
Three conversion modes are provided: Continuous,
Single Cycle, and Single Continuous. Click the
Conversion Modes dropdown menu under the Delta-
Sigma Modulator section to select the desired conver-
sion mode.
Serial Interface
To starting converting, click the Convert button under
the Serial interface section. To read all registers, click the
Read All button.
Power
The MAX11253/MAX11254 EV kit features three power-
down states: Normal Operating Power (NOP), Power
down, and Standby. Select the desired power state by
clicking the drop-down menu under the Power section.
To reset the configuration settings back to default values,
press the Reset Registers button.
To exercise the power-on reset feature, click the RSTB
button.
Clock/SYNC
The internal clock mode is set at default condition. To
use the external clock provided on-board, select External
under the Clock/SYNC section and install jumper J11
from 2-3. To user-supplied external clock, select External
under the Clock/SYNC section and install jumper J11
from 1-2. In addition, the Sync mode can be enabled
or disabled by clicking the drop-down menu under this
Clock/SYNC section and install jumper J15. The Sync
signal should be provided externally.
Other
To enable (J14 open) or disable (J14 installed and VDDVD
≤ 2.0V) the internal CAPREG LDO for digital and I/O sup-
ply, select this option from the drop-down menu under
the Other section. Additionally, Current Sink/Source can
also be disabled or enabled under this section.
Read Data and Status
The Read Data and Status on the far right hand side of
this Configuration menu depicts the received data and
status of the device such as the selected channel, data
rate, sample rate, and power state. Click the Read Data
and Status button to view the updated status.
To save a configuration, select Save ADC Config As… in
the File menu. This saves all the ADC register values to a
XML file. To load a configuration, select Load ADC Config
in the File menu. When the XML file is loaded, all the reg-
ister values in the file are written to the ADC.
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Scope Tab
The Scope tab sheet is used to capture data and display it
in the time domain. The desired Channel #, Sample Rate,
Number of Samples, Display Unit, Average Samples,
and Resolution Selection can also be set in this tab if
they were not appropriately adjusted in other tabs. The
Display Unit drop-down list allows counts in LSB and
voltages in V, mV, or µV. Once the desired configuration is
set, click on the Capture button. The right side of the tab
sheet displays details of the waveform, such as average,
standard deviation, maximum, minimum, and fundamen-
tal frequency as shown in Figure 2.
To save the captured data to a file, select Options > Save
Graph > Scope. This saves the setting on the left and the
data captured to a CSV file.
Figure 2. EV Kit Software (ScopeTab)
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DMM Tab
The DMM tab sheet provides the typical information as a
digital multimeter. Once the desired configuration is set,
click on the Capture button. Figure 3 displays the results
shown by the DMM tab when a 1.5V signal is applied to
AIN0+ and 1.0V to AIN0-.
Figure 3. EV Kit Software (DMM Tab)
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Histogram Tab
The Histogram tab sheet is used to show the histogram
of the data. Sample rate and number of samples can also
be set in this tab if they were not appropriately adjusted
in other tabs. Once the desired configuration is set, click
on the Capture button. The right side of the tab sheet
displays details of the histogram such as average, stan-
dard deviation, maximum, minimum, peak-to-peak noise,
effective resolution, and noise-free resolution as shown
in Figure 4.
The histogram tab is enabled at default. Using the his-
togram will slow down the GUI response. To disable it,
check the Disable Histogram box.
To save the histogram data to a file, go to Options > Save
Graph > Histogram. This saves the setting on the left
and the histogram data captured to a CSV file.
Figure 4. EV Kit Software (Histogram Tab)
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FFT Tab
The FFT tab sheet is used to display the FFT of the data.
The Sample Rate, Number of Samples, Resolution and
Window Function type can be set as desired. To calcu-
late the Adjusted Input Signal frequency for Coherent
Sampling, enter the Input Signal frequency in Hertz and
push the Calculate button. Once the preferred configura-
tion is set, click on the Capture button. The right side of
the tab displays the performance based on the FFT, such
as fundamental frequency, SNR, SINAD, THD, SFDR,
ENOB, and Noise Floor as shown in Figure 5.
To save the FFT data to a file, go to Options > Save
Graph > FFT. This saves the setting on the left and the
FFT data captured to a CSV file.
When coherent sampling is needed, this tab allows the
user to calculate the external clock frequency applied
to the board. Adjust the input frequency of the low-
jitter clock to the value as shown in the Adjusted
Master Clock (Hz) and apply it to the EV KIT EXT_
CLK connector. See the Sync Input and Sync Output
section before using this feature.
Figure 5. EV Kit Software (FFT Tab)
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Figure 6 shows the setup Maxim Integrated uses to cap-
ture data for coherent sampling.
For coherent FFT evaluation, use the jumper settings
from Table 2 for proper configurations. The low-jitter clock
is synchronized with the signal generator at 10MHz from
the ZedBoard. To achieve coherent sampling, click on the
Calculate button and enter the Adjusted Master Clock
(Hz) frequency of approximately 8.192MHz into our low-
jitter clock. Timing for all SPI timing and sampling rate are
based off the system clock.
Figure 6. EV Kit Coherent Sampling Setup
LOW-JITTER CLOCK
SIGNAL GENERATOR
-
+
OUT
INV-
INV+
EXT_CLK
10MHz
ZedBoard
8.192 MHz
ETHERNET CABLE
MAX11253/MAX11254EVKIT
RF_IN
RF_IN
PC
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Scan Mode Tab
The Scan Mode tab is used to perform selected data
conversions and read the converted data.
In the Sequence Setting section at the bottom, set the
desired sequencer mode (1 to 3) from the Sequence
Mode drop-down menu and select whether to assert
the RDYB pin after one channel or after scan com-
pletes options under the RDYB menu. Check the GPO
Sequencer Mode and Enable boxes as desired. Then
set the conversion time delay in µs for MUX and GPO by
clicking on the + or - buttons under the MUX Delay and
GPO Delay menu, allowing for high impedance source
networks to stabilize after the channels are selected.
Finally press the Read All button to view the selected
settings.
In the Read Data section on top, select the desired unit
in either LSB or voltage (V, mV, or µV) under the Display
Unit drop-down menu. Then choose the desired sample
rate by clicking on the Sample Rate drop-down menu
under. Finally, click the Scan button to start convert-
ing and press the Read Data button to view the con-
verted data displayed on the right hand side as shown in
Figure 7.
Figure 7. EV Kit Software (Scan Mode Tab)
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ADC Registers Tab
The Registers tab sheet shows the device registers on
the left. The middle section shows the descriptions of the
selected register. Click Read All to read all registers and
refresh the window with the register settings. To write a
register first select the hex value in the Value column,
type the desired hex value and press Enter.
The command byte is on the right side of the tab sheet.
This byte precedes all SPI transactions and is described
in the IC datasheet. To send a command byte enter a
hex value in the numeric box and click the Send button.
The command byte has two different formats includ-
ing Conversion Command and Register Read/Write.
Select the radio button for the desired mode to see the bit
description in the table. See Figure 8.
Detailed Description of Hardware
The MAX11253/MAX11254 EV kit provides a proven signal
path and board layout to demonstrate the performance of
the MAX11253/MAX11254 16-/24-bit, delta-sigma ADCs.
Included in the EV kit are digital isolators, isolated DC-DC
converters, ultra-low-noise LDOs to all supply pins of the
IC, on-board reference (MAX6126 and MAX6070), preci-
sion amplifiers (MAX9632 and MAX44205) for analog
inputs, and sync-in and sync-out signals for coherent
sampling.
An on-board FTDI controller is provided to allow for
evaluation in standalone mode, which has limitations on
maximum sample speed and on sample depth. The EV kit
can be used with FPGA to achieve full speed and a larger
sample depth.
The EV kit supports a number of different devices as
listed in Table 3.
Figure 8. EV Kit Software (ADC Registers Tab)
Table 3. Products Supported with MAX11253/MAX11254 EV Kit
PART NO. RESOLUTION MAX. SAMPLE RATE
MAX11253 16-bits 64ksps
MAX11254 24-bits 64ksps
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
User-Supplied SPI
To evaluate the EV kit with a user-supplied SPI bus,
disconnect from the FMC bus and remove jumper J64.
Apply the user-supplied SPI signals to SCLK, CSB, DIN,
and DOUT at the PMOD_A header (J60). Make sure the
return ground is connected to PMOD ground.
The on-board FTDI chip used for standalone mode does
not conflict with the user-supplied SPI if it is powered off
by removing jumper J64.
CAUTION: DO NOT PLUG THIS HEADER INTO A
STANDARD PMOD INTERFACE FOUND ON OTHER
FPGA OR MICROCONTROLLER PRODUCTS. THE
SIGNAL DEFINITION IS UNIQUE TO THIS EV KIT.
FMC Interface:
The users should confirm compatibility of pin-usage between
their own FMC implementation and that of the Maxim
Integrated EV kit before connecting the Maxim Integrated
EV kit to a different system with FMC connectors.
Voltage References
There are three different reference voltages available
on board: MAX6070AUT18+ (1.8V), MAX6070AUT30+
(3.0V), and MAX6126AASA30+ (3.0V). To select 1.8V,
place JMP1 from position 1 to 4. To select 3.0V MAX6070
with ±0.04% accuracy, place JUMP1 from position 1 to
3. To select 3.0V MAX6126 with ±0.02% accuracy, place
JMP1 from position 1 to 2.
For user-supplied external references, remove jumper
J24 and connect a reference voltage to J24-2. Measure
and enter the value of the external reference voltage into
the Reference Voltage edit box on the Configuration tab
of the GUI. Table 3 depicts the reference source options.
External DVDD Power Supply
The internal 1.8V regulator can be replaced by an exter-
nal supply in the range of 1.7V to 2.0V. To use external
DVDD, disable the internal regulator by selecting the
Disable in the CAPREG LDO drop-down menu in the
Other section and install J14.
User-Supplied Power Supply
The EV kit receives power from a single DC source of
12V, 500mA through a J61 power jack. The MAX13256,
H-bridge driver and transformer create an additional
negative rail for +15V and -15V. The power is then recti-
fied and regulated down to a +12V and -12V supplies for
the MAX9632 op amps, as well as +5V and -5V supplies
for the MAX44205 op amps. Additional supplies are gen-
erated for +1.8V/-1.8V and +2V/+3.3V for the ADCs and
VREFs. See the EV kit schematic pdf for details. Specific
voltages can be connected to the board for each rail, see
Table 4 for corresponding jumper positions.
ADC Input Ampliers
The input amplifiers allow for significant flexibility, support-
ing bipolar or unipolar input paths, as well as the option
for gain control. Selected input amplifiers can be config-
ured as inverting, noninverting, differential bipolar, and
differential unipolar. See Table 5 for these analog input
configurations for channels 0 to 5.
The analog front-end consists of six channels, 0 to 5, and
there are four user-selectable input pairs (for example
AINx+ and AINx- where x is 2, 3, 4 or 5) allowing selec-
tion between one of two op amp solutions, the MAX9632
a 36V, precision, low-noise, wide-band amplifier or the
MAX44205, a 180MHz, low-noise, low-distortion, fully
differential op amp. The op amps can be configured as
inverting or noninverting amplifiers by jumper selectors.
Both op amps work as anti-aliasing lowpass filters (LPF)
and can be daisy-chained to create a second-order LPF.
The range of possible configurations are listed in Table 5.
Table 4. Reference Source Options
REF
SOURCE JUMPER CONNECTION FUNCTION
MAX6070
(1.8V)
JMP1 1-4
Select U7
MAX6070
J13 1-2
J16 1-2
J24 1-2
MAX6070
(3.0V)
JMP1 1-3
Select U8
MAX6070
J13 1-2
J16 1-2
J24 1-2
MAX6126
(3.0V)
JMP1 1-2
Select U9
MAX6126
J13 1-2
J16 1-2
J24 1-2
AVDD
J13 1-2
Select AVDDJ16 1-2
J24 2-3
User-
Supplied
J13 1-2
Select User-
Supplied
Reference
J16 1-2
J24
Open. Connect
user-supplied
reference
to J24-2
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 5. Power Supply to the Board
Table 6. Analog Input Configurations (CH0–CH5)
POWER INPUT CONNECTORS JUMPERS
Single +12V input from a wall
adapter (default) J61
J67: 3-4
J66: 3-4
J68: 3-4
J69: 5-6
J65: 1-2
J64: 1-2 (select onboard FTDI)
J63: 1-2 (select FPGA ZedBoard)
An external ±12V TP91 (+12V)
TP90 (-12V)
J67: 3-4
J66: 3-4
J68: 1-2
J69: 3-4
J65: 1-2
J64: 1-2 (select onboard FTDI)
J63: 1-2 (select FPGA ZedBoard)
An external ±15V TP86 (+15V)
TP83 (-15V)
J67: 1-2
J66: 1-2
J68: 3-4
J69: 5-6
J65: 1-2
J64: 1-2 (select onboard FTDI)
J63: 1-2 (select FPGA ZedBoard)
CONFIGURATION ADC INPUT
CONFIGURATION INPUT CONNECTORS JUMPER POSITIONS
NO. DESCRIPTION
1 Channel 0 User-supplied signals,
di󰀨erential AIN0D+, AIN0D- N/A
2 Channel 1 User-supplied signals,
di󰀨erential AIN1D+, AIN1D- N/A
3 MAX9632, Channel 2 Noninverting, di󰀨erential,
second-order LPF
J28: AIN2.1+ (or TP39):
AIN2.1+ and AGND
J30: AIN2.3+ (or TP43):
AIN2.3+ and AGND
J31: 1-2
J35: 5-6 and 3-4
J33: 1-2
J32: 1-2
J36: 5-6 and 3-4
J34: 1-2
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 6. Analog Input Configurations (CH0–CH5) (continued)
CONFIGURATION ADC INPUT
CONFIGURATION INPUT CONNECTORS JUMPER POSITIONS
NO. DESCRIPTION
4 MAX9632, Channel 2 Inverting, di󰀨erential,
second-order LPF
J27: AIN2.1- (or TP38):
AIN2.1- and AGND
J29: AIN2.3- (or TP42):
AIN2.3- and AGND
J31: 3-4
J35: 1-2 and 7-8
J33: 3-4
J32: 3-4
J36: 1-2 and 7-8
J34: 3-4
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
5 MAX9632, Channel 2 Noninverting, di󰀨erential,
rst-order LPF
AIN2.2+ (or TP41):
AIN2.2+ and AGND
AIN2.4+ (or TP45):
AIN2.4+ and AGND
J35: 7-8 and 3-4
J33: 1-2
J34: 1-2
J36: 7-8 and 3-4
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
6MAX9632, Channel 2 Inverting, di󰀨erential,
rst-order LPF
AIN2.2- (or TP40):
AIN2.2- and AGND
AIN2.4- (or TP44):
AIN2.4- and AGND
J35: 7-8 and 3-4
J33: 3-4
J34: 3-4
J36: 7-8 and 3-4
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
7 MAX9632, Channel 3 Noninverting, di󰀨erential,
second order LPF
AIN3.1+ (or TP57):
AIN3.1+ and AGND
AIN3.3+ (or TP61):
AIN3.3+ and AGND
J39: 1-2
J43: 5-6 and 3-4
J41: 1-2
J40: 1-2
J44: 5-6 and 3-4
J42: 1-2
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 6. Analog Input Configurations (CH0–CH5) (continued)
CONFIGURATION ADC INPUT
CONFIGURATION INPUT CONNECTORS JUMPER POSITIONS
NO. DESCRIPTION
8 MAX9632, Channel 3 Inverting, di󰀨erential,
second-order LPF
AIN3.1- (or TP56):
AIN3.1- and AGND
AIN3.3- (or TP60):
AIN3.3- and AGND
J39: 3-4
J43: 1-2 and 7-8
J41: 3-4
J40: 3-4
J44: 1-2 and 7-8
J42: 3-4
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
9 MAX9632, Channel 3 Noninverting, di󰀨erential,
rst-order LPF
AIN3.2+ (or TP59):
AIN3.2+ and AGND
AIN3.4+ (or TP63):
AIN3.4+ and AGND
J43: 7-8 and 3-4
J41: 1-2
J44: 7-8 and 3-4
J42: 1-2
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
10 MAX9632, Channel 3 Inverting, di󰀨erential,
rst-order LPF
AIN3.2- (or TP58):
AIN3.2- and AGND
AIN3.4- (or TP62):
AIN3.4- and AGND
J43: 7-8 and 3-4
J41: 3-4
J44: 7-8 and 3-4
J42: 3-4
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
11 MAX44205, Channel 4 Di󰀨erential, rst-order LPF
J48: AIN4- (or TP73):
AIN4- and AGND
J47: AIN4+ (or TP72):
AIN4+ and AGND
J6: 3-4 and 5-6
J49: open
12 MAX44205, Channel 5 Di󰀨erential, rst-order LPF
AIN5+ (or TP74):
AIN5+ and AGND
AIN5- (or TP75): AIN5-
and AGND
J7: 3-4 and 5-6
J50: open
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Sync Input and Sync Output
(For Coherent Sampling)
Sync Input and Sync Output is applicable to the FPGA
(ZedBoard) and is not used in Standalone mode. The
SYNC_IN SMA accepts an approximate 100MHz wave-
form signal to generate the system clock of the ZedBoard.
For maximum performance, use a low-jitter clock that
syncs to the user’s analog function generator. The
SYNC_OUT SMA outputs a 10MHz square waveform
that syncs to the user’s analog function generator. Both
options are used for coherent sampling of the IC. Use
only one option at a time. The relationship between fIN, fS,
NCYCLES, and MSAMPLES is given as follows:
CYCLES
IN
S SAMPLES
N
f
fM
=
where:
fIN = Input frequency
fS = Sampling frequency
NCYCLES = Prime number of cycles in the sampled set
MSAMPLES = Total number of samples
#Denotes RoHS compliant.
Contact Avnet to purchase a ZedBoard to communicate with
the MAX11253/MAX11254 EV kit.
This EV kit comes with two assembly options:
The MAX11253EVKIT# comes with a MAX11253ATJ+ in
a 32-pin TQFN package.
The MAX11254EVKIT# comes with a MAX11254ATJ+ in
a 32-pin TQFN package..
Both EV kit variations use the same PCB and bill of mate-
rials, and the only variation is the IC assembled at U1.
Ordering Information
PART TYPE
MAX11253EVKIT# EVKIT
MAX11254EVKIT# EVKIT
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Bill of Materials
ITEM QTY REF DES MFG PART # MFG VALUE COMMENTS
132
TP13, TP15-TP18, TP20, TP22, TP27, TP29, TP31, TP33, TP35-
TP37, TP46, TP52-TP54, TP64, TP65, TP70, TP71, TP76, TP80,
TP82, TP85,TP87,TP89,TP93-TP95, GND_FPGA
5001 TDK N/A
263
C1-C3, C7-C9, C19, C21-C23, C27, C28, C31, C33, C40, C41,
C44, C45, C52, C53, C56, C57, C64, C65, C68, C69, C76, C77,
C80-C84, C95, C96, C99, C100, C116-C118, C121, C122, C125,
C128, C129, C132, C135, C137-C143, C146, C147, C155, C166-
C168, C176, C184, C187
C1608X7R1H104K080AA TDK 0.1UF
341
C4-C6, C20, C26, C29, C30, C38, C39, C42, C43, C50, C51, C54,
C55, C62, C63, C66, C67, C74, C75, C78, C79, C93, C94, C97,
C98, C113, C114, C119, C120, C123, C124, C144, C145, C152-
C154, C173, C174, C186
UMK107AB7105KA TAIYO YUDEN 1UF
4 6 C10-C15 C1608C0G2A332J080AA TDK 3300PF
6 3 C24, C126, C127 C0603C102K1GAC KEMET 1000PF
728
C25, C34-C37, C46-C49, C58-C61, C70-C73, C156, C159, C162,
C165, C171, C172, C175, C177-C179, C185
C1608C0G1H103J080AA TDK 0.01UF
9 4 C115, C130, C131, C136 C1608X5R1E475K080AC TDK 4.7UF
10 2C133, C134 C0603HQN101-180FNP KEMET/VENKEL 18PF
11 9C148, C149, C160, C161, C180-C183, C188 C2012X5R1V106K085 TDK 10UF
12 1C151 GRM188R71E474KA12 MURATA 0.47UF
13 1D1 MBR0520L
FAIRCHILD
SEMICONDUCTOR
MBR0520L
14 2D2, D3 BAS4002A-RPP INFINEON BAS4002A-RPP
15 2DS1, DS2 LGL29K-G2J1-24-Z OSRAM LGL29K-G2J1-24-Z
16 1DS3 LS L29K-G1J2-1-Z OSRAM LS L29K-G1J2-1-Z
19 4 J4-J7 PEC04DAAN
SULLINS ELECTRONICS
CORP.
PEC04DAAN
20 1 J8 PCC02SAAN SULLINS PCC02SAAN
21 9J10-J13, J16, J17, J24, J52, J65 PCC03SAAN SULLINS PCC03SAAN
22 10 J27-J30, J47, J48, J54, J56-J58 5-1814832-1 TYCO 5-1814832-1
23 11 J31-J34, J39-J42, J66-J68 PBC02DAAN
SULLINS ELECTRONIC
CORP.
PBC02DAAN
24 4J35, J36, J43, J44 PBC04DAAN
SULLINS ELECTRONICS
CORP.
PBC04DAAN
25 2J49, J50 PEC02DAAN
SULLINS ELECTRONIC
CORP.
PEC02DAAN
26 1J51 PBC10SAAN
SULLINS ELECTRONICS
CORP.
PBC10SAAN
27 1J53 ASP-134604-01 SAMTEC ASP-134604-01
28 1J59 10118192-0001LF FCI CONNECT 10118192-0001LF MICRO-USB
29 1J61 KLDX-0202-B KYCON KLDX-0202-B
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Bill of Materials (continued)
ITEM QTY REF DES MFG PART # MFG VALUE COMMENTS
30 1J62 282834-2 TE CONNECTIVITY 282834-2
31 1J69 PEC03DAAN
SULLINS ELECTRONICS
CORP.
PEC03DAAN
32 1JMP1 22-28-4043 MOLEX 22-28-4043
33 1L1 MMZ1608B601C TDK 600
34 4L2-L5 XPL2010-333ML COILCRAFT 33UH
35 4R1-R4 RN73C1J49R9B; 9-1614353-1 TE CONNECTIVITY 49.9
36 12 R5, R8-R14, R52, R53, R93, R94 RN73C1J10RBTG; 1614350-2 TE CONNECTIVITY 10
37 1R6
CRCW0603237KFK;
ERJ3EKF2373V
VISHAY
DALE/PANASONIC
237K
38 6R7, R197, R199, R201, R203, R205 ERJ3EKF7322V PANASONIC 73.2K
39 14 R15, R171, R172, R175-R179, R181-R186
CRCW060310K0FK;
9C06031A1002FK; ERJ-
3EKF1002V
VISHAY
DALE/PANASONIC
10K
40 6R16, R17, R162, R164, R166, R167 CRCW060349R9FK VISHAY DALE 49.9
41 3R18, R19, R195
CRCW06031001FK;
CRCW06031K00FK; ERJ-
3EKF1001V
VISHAY
DALE/PANASONIC
1K
42 16 R20-R27, R54-R61
CRCW06031M00FK;
MCR03EZPFX1004
VISHAY DALE/ROHM 1M
43 40
R28-R35, R40-R43, R46-R49, R62-R69, R81-R84, R87-R90, R97-
R104
RG1608N-102-B-T1 SUSUMU CO LTD. 1K
44 12 R36-R39, R50, R51, R70-R72, R80, R91, R92
CR0603-16W-000T; CR0603-
16W-000RJT
VENKEL LTD. 0
45 4R44, R45, R85, R86
TNPW06031K50BE; ERA-
3YEB152V
PANASONIC 1.5K
46 44 R73-R79, R105, R111-R117, R139-R161, R168, R169, R187-R190 ERJ-3EKF28R0V PANASONIC 28
47 2R95, R96
TNPW060310K0BE;
RN731JTTD1002B
VISHAY DALE/KOA
SPEER ELECTRONICS
10K
48 2R163, R165
CRCW06030000ZS;
MCR03EZPJ000; ERJ-
3GEY0R00V
VISHAY DALE 0
49 1R170 CRCW060315K0FK VISHAY DALE 15K
50 1R173 CRCW06032K20FK VISHAY DALE 2.2K
51 1R174 CRCW060312K0FK VISHAY DALE 12K
52 1R180 CRCW06034K70FK VISHAY DALE 4.7K
53 2R191, R194
PANASONIC;CRCW0603200
2FK; MCR03EZPFX2002;ERJ-
3EKF2002V
VISHAY DALE/ROHM 20K
54 1R192 CRCW0603750KFK VISHAY DALE 750K
55 1R193 CRCW0603165KFK VISHAY DALE 165K
56 1R196 ERJ-3EKF3832 PANASONIC 38.3K
57 2R198, R200 ERJ3EKF6813V PANASONIC 681K
58 1R202
CRCW060310R0FK;
MCR03EZPFX10R0
VISHAY DALE/ROHM 10
59 1R204 CRCW0603124KFK VISHAY DALE 124K
60 49 SU1-SU49 SX1100-B KYCON SX1100-B
61 1T1 TGM-H240V8LF
HALO ELECTRONICS,
INC
TGM-H240V8LF
62 58
TP1-TP12,TP14,TP19,TP21,TP23-TP26,TP30,TP38-TP45,TP48-
TP51,TP56-TP63,TP66-TP69,TP72-TP75,TP77-
TP79,TP81,TP84,TP86,TP91,TP92,5V_TTL
5000 ?N/A
Maxim Integrated
│
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Bill of Materials (continued)
64 1 U1 MAX11254ATJ+ MAXIM MAX11254ATJ+
65 1 U5 MAX14935CAWE+ MAXIM MAX14935CAWE+
66 1 U6 MAX14935CAWE+ MAXIM MAX14935CAWE+
MAX14931CASE
+
67 1 U7 MAX6070AAUT18+ MAXIM MAX6070AAUT18+
68 1 U8 MAX6070AAUT30+ MAXIM MAX6070AAUT30+
69 1 U9 MAX6126AASA30+ MAXIM MAX6126AASA30
70 1 U10 LTC6930HDCB-8.19 LINEAR TECHNOLOGY LTC6930HDCB-8.19
71 8 U11-U18 MAX9632AUA+ MAXIM MAX9632AUA+
72 2 U19, U20 MAX44205 MAXIM MAX44205
73 2 U21, U22 74LVC2G125DP ? 74LVC2G125DP
74 2 U23, U24 93LC66BT-I/OT MICROCHIP 93LC66BT-I/OT
75 1 U25 FT2232HL
FUTURE TECHNOLOGY
DEVICES INTL LTD.
FT2232HL
76 2 U26, U35 MAX15006BATT+ MAXIM MAX15006BATT+
77 1 U27 MAX16910CATA9+ MAXIM MAX16910CATA9+
78 1 U28 MAX13256ATB+ MAXIM MAX13256ATB+
79 1 U29 MAX15006CATT+ MAXIM MAX15006CATT+
80 1 U30 MAX8840ELT18+ MAXIM MAX8840ELT18+ MAX8840ELT18+
81 3 U31, U33, U34 TPS7A3001DGN TEXAS INSTRUMENTS TPS7A3001DGN
82 1 U32 TPS7A4901DGN TEXAS INSTRUMENTS TPS7A4901DGN
83 1 U36 MAX15006AATT+ MAXIM MAX15006AATT+
84 1 Y1 ABM7-12.000MHZ-D2Y-T ABRACON 12MHZ
85 1 PCB EPCB11254 MAXIM PCB
63 5 TP28,TP83,TP88,TP90,TP96 5004 ? N/A
ITEM QTY REF DES MFG PART # MFG VALUE COMMENTS
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams
MAX1153/MAX11254 Family EV Kit—Top Silkscreen
MAX1153/MAX11254 Family EV Kit—Top Paste
MAX1153/MAX11254 Family EV Kit—Bottom Silkscreen
MAX1153/MAX11254 Family EV Kit—Bottom Paste
Maxim Integrated
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams (continued)
MAX1153/MAX11254 Family EV Kit—Internal 2
MAX1153/MAX11254 Family EV Kit—Internal 4
MAX1153/MAX11254 Family EV Kit —Internal 3
MAX1153/MAX11254 Family EV Kit—Internal 5
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams (continued)
MAX1153/MAX11254 Family EV Kit—Top
MAX1153/MAX11254 Family EV Kit—Top Mask
MAX1153/MAX11254 Family EV Kit —Bottom
MAX1153/MAX11254 Family EV Kit—Bottom Mask
Maxim Integrated
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic
ALL INPUTS +/- 3V MAX
1282834-0
49.9
282834-4
282834-4
1282834-0
1282834-0
1K
1K
49.9
J25
J26
R17
R18
R19
R16
J3
J2
J1
GPO0
GPO1
AIN5D-
AIN5-
AIN5+
AIN4D+
AIN4D-
AIN4-
AIN4+
AIN3.3-
AIN3.3+
AIN3.2+
AIN3.1-
AIN3.1+
AIN3D+
AIN2.4-
AIN2D-
AIN3.2-
AIN3.4+
AIN3D-
AIN3.4-
AIN2.4+
AIN2.3-
AIN2.3+
AIN2.2-
AIN2.2+
AIN2.1-
AIN2.1+
AIN2D+
REFN_S
AIN1D-
AIN1D+
AIN0D-
AIN0D+
REFP_S
REFP
AVSS
AIN5D+
10
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
4
3
2
1
4
3
2
1
9
8
7
6
5
4
3
2
1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Maxim Integrated
│
28
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
AIN2.4-
AIN2.3+
AIN2.3-
AIN2.2+
AGND
AIN2.2-
AIN2.1+
AIN2.1-
AIN2.4+
0
AGND
0.1UF
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
0.1%
10PPM
10
1M
1M
1M
AGND
0
0.01UF
AGND
AGND
1K
1K
1K
.1%
1K
.1%
1K
.1%
.1%
AGND
1K
0.01UF
AGND
1K
0
.1%
1K 1K
1K .1%
10
0.1%
10PPM
1K
.1%
AGND
.1%
.1%
0.1%
1.5K
.1%
0.1%
1.5K
.1%
AGND
1K
AGND
1M
.1%
1K
AGND
1M
.1%
0.01UF
1UF 0.1UF 1UF 0.1UF
AGND
AGND
0.01UF
AGND
AGND
1M
AGND
1M
.1%
AGND
1M
AGND AGND
0.01UF
0
MAX9632AUA+
0
1K
0.1UF 0.1UF
AGND 1K
MAX9632AUA+
AGND
0.1UF1UF
0.1UF1UF
AGND
.1%
0
0.01UF
1K
MAX9632AUA+
0.01UF
AGND
1UF1UF
0.01UF
1UF
1UF 0.1UF
AGNDAGND
MAX9632AUA+
AGND
.1%
J37
J27
J30
J29
TP45
R25
C49
R47
R43
R30
R33
R35
C37
R32
R50
R40
R53
R52
R48
R41
R46
R44
R45
J28
TP38
TP36
TP39
TP40
J31
R29
R26
R20
R34
C36
C38 C40 C42 C44
J35
TP48
R36
R38
C34
R21
TP37
R22
TP41
R23
R37
R31
J32
TP42
TP35
TP43
TP44
R27
R24
J34
C35
U12
R39
R42
TP50
J36
TP51
C39 C41 C45C43
J38
U14
C53 C55 C57
C51
R49
R51
C47
J33
TP46
U11
U13
C46
C48
C50 C52 C54 C56
TP49
R28
VEE
AIN2BN
AIN2BP
VCC
AIN2.2-
AIN2.2+
AIN2.1+
VEE
VEE
AIN2.3+
AIN2.4+
AIN2.4-
AIN2.1-
AIN2.3-
VCC
VCC
VCC
VEE
VEE
VCC
VCC
VCC
VREF
VEE
VCC
VREF
VEE
VEE
8
2
6
5
3
2
3
5
7
1
2
5
4
3
2
1
5
4
3
2
1
4 3
2
3
21
4
5
2
3
87 6
4
7
5
4
3
2
5
4
3
2
3
1
8
2
87 6
4
1
7
5
1
1
1
1
4
6
3
4
4
6
6
8
2
1
2
1
3
2
42
5
4
4
1
7
5
3
1
1
8
3
1
2
OUT
JUMPER
5432
1
5432
1
4 3
2 1
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
43
21
87
65
1
3 4
2
IN
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
ININ
IN
ININ
IN
ININ
IN
ININ
ININ
IN
ININ
IN
IN
IN
IN
IN
IN
IN
IN
5432
1
5432
1
4 3
2 1
43
21
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
87
65
1
3 4
2
IN
JUMPER
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
OUT
Maxim Integrated
│
29
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
AIN3.2+
AIN3.1-
AIN3.1+
AIN3.2-
AIN3.3-
AIN3.3+
AGND
AIN3.4+
AIN3.4-
AGND
0
1UF
AGND
0.1UF
0.1UF
0.1UF
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
1UF
10
0
1UF
1M
1M
1UF
1UF
1M
1UF
1M
AGND
0.1%
10PPM
10
1UF
0
AGND
AGND
0
0.01UF
0.01UF
0.01UF
0
AGND
0.01UF
AGND
1K .1%
AGND
MAX9632AUA+
.1%1K
.1%
AGND
0.01UF
1K
0.01UF
.1%
AGND
MAX9632AUA+
1K
.1%
AGND
0.1UF
0.1%
10PPM
1K
.1%1K
MAX9632AUA+
AGND
.1%
1K
0
1K .1%
AGND
.1%1K
1K .1%
AGND
AGND
1K
1K
0.1%
1.5K
0.1%
1.5K
.1%
0.1UF
0.01UF
.1%
MAX9632AUA+
0.1UF
AGND
1M
AGND
AGND
1M
.1%
1K
.1%1K
1M
1M
AGND
AGND
.1%
AGND
0.1UF
1UF
0.1UF
.1%1K
1K
AGND
0.01UF
AGND
J40
C66
C65
R59
C80C78C76C74
C69
C81C79C77C75
R54
J39
J41
R56
J42
R58
R72 R93
C62
U15
R92
C67
R71
J44
R57
C61 C73
R94
C60
J43
TP64
R70
R68
R63
R66
C58
C70
R89
R91
U17
C72
C63 C68
TP65
C59
U18
R90
R83R80
R69
R65
R64
R84
R87
J45
J46
R86 R88
R85
TP59
C64
C71
TP56
TP57
R55
TP58
R82
R81
TP54
TP66
TP67
TP60
R61
TP61
TP53
TP62
TP52
TP68
TP69
TP63
R60
R62
R67
U16
AIN3BP
VCC VEE
VCC
VCC
AIN3.2-
AIN3.1+
AIN3.1-
VCC
AIN3.2+
AIN3.4-
AIN3.4+
AIN3.3-
AIN3BN
VCC
AGND
VCC
AGND
VEE VEE
VEE
VEEVCC
VCC
VEE
VEE
AIN3.3+
VEE
VREF
VREF
6
7
1
7
87 6
43
1
5
2
765 4
21
7
8
5
1
2
4 3
2 1
4
4 3
2
6
5
8
5
2
44
3
1
6
18
4
3
2
7
2
6
4
3
1
2
8
5
4
2
3
2
2
3
3
1
1
8
1
3
1
JUMPER
IN
87
65
1
3 4
2
IN
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
IN
43
21
IN
87
65
1
3 4
2
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
IN
4 3
2 1
IN
IN
43
21
4 3
2 1
ININ
IN
IN
IN
IN
ININ
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
OUT
JUMPER
IN
IN
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
Maxim Integrated
│
30
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
AIN5+
AIN5-
AIN4+
AIN4-
0.1%
0.1%
0.1UF
1K
1K
4700PF
4700PF
1K
4700PF
1K
AGND
AGND
AGND
4700PF
0.1UF
4700PF
AGND
0.1UF
0.1UF
AGND
4700PF
AGND
AGND
AGND
AGND
10K
1UF
0.1UF
AGND
10K
1K
0.1UF
4700PF
1K
AGND
MAX44205
4700PF
1UF
AGND
1UF
1UF
0.1UF
AGND
MAX44205
1K
AGND
1K
R101
R103
R98
R102
C84
R104
C91
C90
C99
C98
C97C93
C85
C86
C92
C89
C83
C82
R95
R96
C100
R100
R97
J47
J48
TP70
TP73
TP72
C94
C95
U19
C96
U20
R99
TP71
TP75
TP74
J50
J49
C87
C88
AIN4BP
VOCM
VCLPL
VOCM
+5V
VCLPL
REFN
-5V+5V
VOCM
REFP
AIN4+
AIN5+
AIN4-
VCLPH
AIN4BN
-5V
AIN5-
-5V
+5V
+5V
-5V
AIN5BN
AIN5BP
VCLPH
10
6
11 9
3
1
2
3
4
5
1
2
3
4
5
9
5
4
7
1
2
1 2
3
13
5
12 4
7
1
8
1 2
4
6
10
3
11
82
12
13
3
4
IN
IN
43
21
OUT-
VCLPL
SHDN
NC
EP
IN-
IN+
OUT+
VS+
VOCM
VS-
VCLPH
GND
IN
IN
OUT
OUT
IN
5432
1
IN
IN
ININ
ININ
IN
IN
IN
IN
OUT
IN
IN
43
21
OUT-
VCLPL
SHDN
NC
EP
IN-
IN+
OUT+
VS+
VOCM
VS-
VCLPH
GND
IN
IN
OUT
OUT
IN
5432
1
Maxim Integrated
│
31
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Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
GPO0
GPO1
3V_VREF
GPIO0_CLK
GPIO1_SYNC
3V_VREF
1.8V_VREF
GPOGND
MAX6070AAUT18+
MAX6070AAUT30+
4.7UF
AGND
AGND
MAX11254ETJ+
AGND
3300PF
3300PF
AGND
3300PF
0.1%
49.9
49.9
3300PF
0.1UF1UF 0.1UF1UF
AGND
1UF
AGND
AGND
4.7UF
0.1UF
AGND
1.0UF
0.1UF
AGND AGND
3300PF
3300PF
AGND
49.9
LTC6930HDCB-8.19
0.1UF
10
0.1%
0.1UF
AGND
AGND
MAX6126AASA30
1000PF
0.1UF
AGND
0.1UF
10K
AGND
10PPM
0.1%
AGND
10PPM
10PPM
10PPM
10PPM
0.1%
10
10
0.1%
10
10PPM
10
0.1%
10
10
10PPM
4.7UF
1UF
4.7UF
0.1%
10PPM
10
1UF
AGNDAGND
AGND
AGND
AGND
0.1UF 0.1UF
0.1UF
0.1UF
10PPM 0.1%
10PPM
0.1%
10
10PPM
0.01UF
0.1UF1UF
0.1UF
AGND
AGND
AGND
0.1%
0.1%10PPM
0.1%
49.9
AGND
TP33
J24
U7
U8
U9
C18
TP18
TP12
TP11
TP16
TP17
TP10
TP9
TP8
TP7
C13
TP6
TP5
TP15
C12
TP3
C11
TP4
TP13
TP2
TP1
C10
J16J13
J17
C26
J10
J12
TP28
C30
TP21
TP19
C19
C20 C31C27
TP22
C32 C33
C28
C5
JMP1
C15
C14
U1
C23
J11
U10
R202
C29
J15
J14
R11
C21
TP23
R15
TP30
R5
R13
R4
R1
C22
C1 C7C4 C17
C8C2
C25
C16
C9C6C3
TP27
TP24
TP26
TP25
C24
J7
R14
R12
R10
R9
R8
J6
J5
J4
R2
R3
TP29
TP20
VREF
AIN3N
AIN4P
AIN4N
AIN2P
AIN0N
+1.8V
AIN1N
AIN0P
AIN0N
AVDD AVSS
+3.3V
AVDD
REFP
REFP
RSTB
AIN1P
AIN2N
REFP_F
AIN3P
AIN5N
AIN5P
AIN2N
AIN1P
SCLK
AVSS
DOUT
CSB
DIN
AGND
AIN3N
AIN4P
DVDD
REFP_S
+1.8V
REFN_S
-1.8V
+2V/+3.3V
DVDD
AIN5P
EXT_CLK
AIN2P
AIN3P
AIN4N
AIN1N
AIN0P
AVDD
VREF
AIN3D-
AIN1D-
AIN1D+
AIN0D-
AIN0D+
AIN3BP
AIN3BN
AIN3D+
AIN4D-
AIN4D+
AIN4BN
AIN4BP
AIN2D-
AIN2BP
AIN2BN
AIN2D+
AIN5BN
+3.3V
AIN5D+
AIN5BP
AGND
GPO1
RSTB
AVSS
REFN
REFP_F
AIN5N
AIN5D-
DVDD
AVSS
AVSS
RDYB
GPO0
SYNC
2
2
3
1
13
17
18
19
20
2
6
4 7 3
2
5
1
25
15
2
26
21
6
1
13
8
1
2
7
2
16
14
24
4
3
4 2
8
1
9
3
5
6
4
2
1
3
5
6
4
1
3
3
6
5
4
3
3
2
3
2
1
1
87 65 43 21
87 65 43 21
87 65 43 21
87 65 43 21
5
1
22
23
33
32
29
31
3
12
10
9
8
7
11
2
1
30
28
27
OUT
IN
IN
OUT OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT OUT
IN
V+
OUT
GND
DIVC
DIVB
DIVA
GND
V+
EP
IN
OUTF
OUTSIN
EN
GND
FILTER
OUTF
OUTSIN
EN
GND
FILTER
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
I.C.
I.C.
OUTF
OUTS
GNDS
GND
NR
ININ
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
87
65
1
3 4
2
IN
IN
IN
IN
IN
IN
IN
IN
IN
87
65
1
3 4
2
IN
IN
IN
IN
87
65
1
3 4
2
IN
IN
IN
IN
87
65
1
3 4
2
IN
IN
DGND
DIN
CSB
DOUT
DVDD
RSTB
CAPREG
GPIO1/SYNC
GPO0
GPIO0_CLK
GPO1
GPOGND
CAPP
CAPN
AIN5P
AIN5N
AIN4P
AIN4N
AIN3P
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
AIN0P
AIN0N
REFN
REFP
AVSS
AVDD
SCLK
RDYB
EP
Maxim Integrated
│
32
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
4.7UF
1UF
1UF
0.1UF
0.1UF
AGND
1UF
AGND
AGND
28
28
28
28
0.1UF
AGND
1UF
MAX14935CAWE+
AGND
0.1UF
28
AGND
MAX14935CAWE+
28
28
AGND
AGND
0.1UF
28
U5
C115
C119 C121
C120
C117
C116C113
R113
R105
C114
R112
R111
R116
R117
C122
U6
J52
TP77
TP76
R115
J51
C118
R114
DIN
DOUT
RDYB
VDD
VDD
VDDIO
CSB_FPGA
DIN_FPGA
SCLK_FPGA
DOUT_FPGA
VDDIO
SCLK
RSTB_FPGA
SYNC
RSTB
EXT_CLK
SYNC_FPGA
RDYB_FPGA
EXT_CLK_FPGA
VDD
GND_FPGA
VDDIO
GND_FPGA
VDD
VDD
+3.3V
GND_FPGA
VDDIO
GND_FPGA
CSB
EXT_CLK
SYNC
DOUT
CSB
RDYB
RSTB
SCLK
DIN
DVDD
11
13
12
1
16
1
8
9
15
3
4
5
11
13
10
12
7
2
3
14
6
14
16
1
2
10
3
6
7
5
4
8
9
10
9
8
7
6
4
3
2
1
5
2
15
IN
VDDB VDDA
OUTB3
OUTB2
OUTB1
ENA
OUTA1
INB1
INA3
INA2
INA1
GNDBGNDB GNDAGNDA
ENB
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUT
OUT
IN IN
IN
IN
IN
VDDB VDDA
OUTB3
OUTB2
OUTB1
ENA
OUTA1
INB1
INA3
INA2
INA1
GNDBGNDB GNDAGNDA
ENB
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
Maxim Integrated
│
33
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
GND
SYNC_CLK_IN_SPLIT
SYNC_CLK_OUT
SYNC_CLK_OUT
SYNC_CLK_OUT
SYNC_CLK_IN
SYNC_CLK_IN
28
28
28
1000PF
28
74LVC2G125DP
0.1UF
0
0.1UF
28
93LC66BT-I/OT
28
PBC06SAAN
28
28
28
49.9
49.9
28
49.9
49.9
28
74LVC2G125DP
28
28
1UF
0.1UF
1UF
28
28
28
28
28
28
ASP-134604-01
28
28
28
28
ASP-134604-01
0
1000PF
ASP-134604-01
ASP-134604-01
U22
R167
J58
R148
R157
R146
R145
R144
R142
R158
R156
R153
R151
TP78
R163
J54
R166
C127
R164
J55
C128
U23
J57
TP80
J56
TP79
C125
R150
R152
R147
C129
U21
R160
R159
R155
R154
C124
C123
J53
R139
R141
R140
R161
R143
J53
R149
C126
R162
R165
J53
J53
SYNC_CLK_IN
SYNC_CLK_OUT
5V_TTL
GND_FPGA
GND_FPGA
GND_FPGA
SYNC_FPGA
GND_FPGA
GND_FPGA
GND_FPGA
RSTB_FPGA
SO_EEPROM_FPGA
GND_FPGA
GND_FPGA
GND_FPGA
VDDIO
SO_EEPROM_FPGA
CSB_FPGA
DIN_FPGA
DOUT_FPGA
EXT_CLK_FPGA
VADJ
SYNC_CLK_OUT
GND_FPGAGND_FPGA
3V3_FPGA
GND_FPGA
GND_FPGA
SCLK_FPGA
RDYB_FPGA
3V3_FPGA
VDDIO
GND_FPGA
SYNC_CLK_IN
VADJ
GND_FPGA
+12V_FPGA
1
7
2 6
5 3
4 8
1
2
3
4
5
1
2
3
4
7
2 6
5 3
4 8
1
2
3
4
5
6
4
5
3
1
62
1
2
3
4
5
1
2
3
4
5
C36
C35
C34
C33
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C14
C13
C12
C11
C10
C8
C6
C4
C5
H39
H38
H37
H36
H33
H32
H31
H30
H29
H26
H24
H23
H22
H20
H19
H10
H9
H8
H7
H6
H4
H3
H2
H1
G22
C9
H35
D31
D24
D14
D9
D5
D4
D1
H27
H25
D6
D8
D7
D10
D11
D13
D15
D17
D16
D18
D12
D19
D23
D22
H21
H12
H13
H14
H15
H16
H17
D25
D26
D27
D28
D29
D30
D35
D36
D38
D32
D39
D40
C7
G1
G2
G3
G7
G6
G8
G9
G10
G11
G12
G13
G15
G16
G17
G19
G20
G21
G24
G23
G26
G27
G30
G33
G32
G37
G36
G38
G40
G39
G31
H40
D34
D33
G35
G34
C3
C2
G5
G4
C1
G14
H5
D2
D3
H11
H18
D21
D20
H34
C15
C16
C17
G25
1
C39
C40
C38
C37
H28
G29
G28
5
G18
D37
C31
C32
IN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUT
5432
1
5432
1
OUT
VCC
VSS
DO
DI
CLK
CS
5432
1
IN
2A
2OE
2Y
VCC
1Y
GND
1A
1OE
5432
1
IN
IN
OUT
2A
2OE
2Y
VCC
1Y
GND
1A
1OE
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Maxim Integrated
│
34
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
PMOD HEADER
ONE CAPACITOR PER EACH POWER PIN
10118192-0001LF
MICRO-USB
28
600
10K
0.1UF
10K
4.7K
28
28
93LC66BT-I/OT
4.7UF
0.1UF
12K
FT2232HL
0.1UF
4.7UF 0.1UF
0.1UF 0.1UF
10K
10K
10K
0.1UF
10K
10K
10K
28
10K
28
28
28
28
28
12MHZ
18PF
2.2K
10K
28
10K
15K
28
0.1UF
4.7UF
10K
28
18PF
DNI
28
10K
0.1UF
GREEN
J59
DS1
U25
J60
C143C142C141
R189
R190
R73
R187
R76
R74
R78
R77
R186
R183
R184
R182
R179
R176
R177
R175
R180
C139C137C135
C132C131
C136
R174
Y1
C133
C134
R170
U24
R172
R173
R171
R168
R169
L1
R185
C138
R79
R75
R181
R178
C140
R188
C130
3V3_USB
+5V_USB
GND_FPGA
GND_FPGA
GND_FPGA
SCLK_FPGA
GND_FPGA
3V3_USB
GND_FPGA
CSB_FPGA
GND_FPGA
GND_FPGA
+1.8V_USB
DOUT_FPGA
RSTB_FPGA
DIN_FPGA
GND_FPGA
GND_FPGA
GND_FPGA
CSB_FPGA
GND_FPGA
GND_FPGA
+1.8V_USB
DIN_FPGA
DOUT_FPGA
GND_FPGA
3V3_USB
3V3_FPGA
SCLK_FPGA
3V3_USB
+5V_USB
3V3_USB
3V3_USB
GND_FPGA
RSTB_FPGA
GND_FPGA
RDYB_FPGA
3V3_FPGA
RDYB_FPGA
SYNC_FPGA
1 2
43
42
49
50
9
4
64
37
12
56
20
13 36
14
6
3
2
51
47
35
25
15
11
5
1
61
63
62
7
44
41
40
39
38
59
58
57
55
54
53
52
48
10
24
23
22
21
19
18
17
16
34
33
32
30
29
28
27
26
10
9
8
7
3
2
1
K A
2 1
2 6
1
3
5
4
31
60
11
10
9
8
7
6
5
4
3
2
1
4
5
612
11
46
45
8
IN
BCBUS7
BCBUS6
BCBUS5
BCBUS4
BCBUS3
BCBUS2
BCBUS1
BCBUS0
ACBUS7
ACBUS6
ACBUS5
ACBUS4
ACBUS3
ACBUS2
ACBUS1
ACBUS0
BDBUS7
BDBUS6
BDBUS5
BDBUS4
BDBUS3
BDBUS2
BDBUS1
BDBUS0
ADBUS7
ADBUS6
ADBUS5
ADBUS4
ADBUS3
ADBUS2
ADBUS1
ADBUS0
OSCO
OSCI
VCORE
GND
GND
VCCIO
EECS
EECLK
EEDATA
TEST
VREGOUT
VREGIN
VCORE
VCORE
GND
GND
RESET#
SUSPEND#
PWREN#
VCCIO
GND
GND
VCCIO
GND
GND
VCCIO
VPLL
DP
DM
REF
AGND VPHY
IN
IN
IN
IN
IN
IN
IN
J1-12
J1-11
J1-10
J1-9
J1-8
J1-7
J1-6
J1-5
J1-4
J1-3
J1-2
J1-1
IN
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
ININ
IN
IN
IN
11
10
9
8
7
6
5
4
3
2
1
IN
IN
VCC
VSS
DO
DI
CLK
CS
Maxim Integrated
│
35
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
GND
150MA
50MA
50MA
-1.8V
+5V
AGND
+12V_EXT
DC IN
AGND
-12V_EXT
50MA
AGND
1:1:1.3:1.3
-15V_EXT
+15V_EXT
AGND
AGND
AGND
+2V/+3.3V
50MA
+3.3V
AGND
-5V
OFF: +3.3V
JUMPER ON: +2V
200MA
38.3K
0.1UF
0.1UF
10UF
AGND
1UF
73.2K
MAX15006AATT+
1UF
10UF
10UF
0.1UF
123K
0.01UF
AGND
MAX15006CATT+
0.1UF
AGND
MAX15006BATT+
0.1UF
237K
AGND
TPS7A3001DGN
73.2K
0.01UF
0.01UF
AGND
1UF
0.01UF
1UF
AGND
681K
RED
KLDX-0202-B
BAS4002A-RPP
20K
33UH
1UF
TPS7A4901DGN
BAS4002A-RPP
MBR0520L
GREEN
1K
750K MAX13256ATB+
165K
LS L29K-G1J2-1-Z
TGM-H240V8LF
4.7UF
50V
4.7UF
33UH
TPS7A3001DGN
0.01UF
73.2K
73.2K
681K
0.01UF
25V
10UF
MAX15006BATT+
10UF
0.47UF
20K
4.7UF
AGND
0.1UF
50V
33UH
0.01UF
50V
4.7UF
XPL2010-333ML
33UH
25V
10UF
AGND
TGM-H240V8LF
0.1UF
4.7UF
0.01UF
TPS7A3001DGN
0.1UF
4.7UF
10UF
73.2K
0.01UF
1UF
AGND
0.01UF
1UF
MAX8840ELT18+
0.01UF
0.1UF
MAX16910CATA9+
4.7UF
50V
10UF
73.2K
10UF
1UF
DNI
TERM_BLK
TP14
C182
TP95
C174
C187
C159
C186
TP85
R205R204
J8
C185
C155
U29
C152
C188
TP31
U36
C153
C177
C184
C183
R6R196
TP89
R197
C162
U31
C173
U34
C179
TP96
R7
TP91
J69
TP94
C180
C181
TP90
R198
R199
U32
C170
C168
TP86
J67
C164
TP83
L2
L3
C158
D3
C178
R200
R201
U33
C172
C169
C167
J66
C163
TP87
L4
L5
D2
T1
R194 DS3
U28
J65
C151
C150
R191
D1
J62
TP81
R195
DS2
5V_TTL
C148
J64
U26
C146C145
GND_FPGA
J61
C171
R192
R193
J63
J68
C176
U35
TP88
C166
C175
C165
TP92
TP93
U30
C161
U27
C156
C147
C154
C157
TP84
C160
R203
C149
TP82
C189
C144
-5V
+1.8V
-1.8V
VCC
VCC
+3.3V
-5V
+12V_FPGA
5V_TTL
GND_FPGA
EXT_+12V
GND_FPGA
VEE
+5V
VCC
VEE
EXT_+12V
VCC
+2V/+3.3V
+5V
GND_FPGA
GND_FPGA
GND_FPGA
3V3_USB
VDDIO
77
6
4
1
7
2
4
6
2
1
3
6
5
4
2
3
6
2
1
3 4
5
6
8 1
5
9
6
3
8
4
7
6
3
4
9
7
5
1
3 4
1 2
3 4
5
7
5
9
2
4
8
3
6
1
1 2
3 41 2
1 2
1
2 3
4
7
5
9
2
4
8
6
1 2
3 4
1 2
1 2
1
2 3
4
1
2
3
4 5
6
7
8
A K
4 6
3
11
7
9
5
10
8
1
2
1
2
3
A C
1
2
A K
1 2
7
1
2
3
5
6
1
2
3
1 2
2
51
2
3
1
2
4
3
1 5
FB
OUT
NC
IN
IN
DNG PE
65
1
3 4
2
EP
ST1
GND2
ST2
GND1
FAULT
ITH
EN
CLK
VDD2
VDD1
8
7
6
5
4
3
2
1
~
~-
+
D4
D3
D2
D1
43
21
OUT
OUT
NC
IN
IN
DNG PE
EP
IN
DNC
NR/SS
EN
GND
NC
FB
OUT
~
~-
+
D4
D3
D2
D1
43
21
43
21
IN
EP
IN
DNC
NR/SS
EN
GND
NC
FB
OUT
OUT
OUT
OUT
NC
IN
IN
DNG PE
OUT
OUT
OUT
OUT
IN IN
IN
IN
IN
IN OUT
OUT
OUT
OUT
OUT
OUT
IN
EP
IN
DNC
NR/SS
EN
GND
NC
FB
OUT
OUT
NC
BPSHDN
IN
GND
EP
IN
DNC
NR/SS
EN
GND
NC
FB
OUT
IN
JUMPER
1
3
2
OUT
GND
SETOV
TIMEOUT
RESET
SET
ENABLE
IN
EP
OUT
OUT
NC
IN
IN
DNG PE
JUMPER
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc.
│
36
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/15 Initial release —
1 5/15 Added the MAX11253 EV kit to data sheet 1–22
2 4/18 Updated PCB layout diagrams, schematic, and bill of materials 21-35
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MAX11254EVKIT#