R1
GND
1.8 V to 36 V
OUTA
OUTB
R2
R3
VMON
INA
INB
VDD
Device
RP2
RP1
0.1 Fm
To a reset
or enable
input of
the system.
V
0 V to 25 V
PULLUP
TJ
Typical Threshold Error (%)
-40 -20 0 20 40 60 80 100 120 140
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
D012
INA Negative Threshold
INB Positive Threshold
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3701
SBVS240B –NOVEMBER 2014–REVISED JUNE 2018
TPS3701 36-V Window Supervisor With Internal Reference
for Over- and Undervoltage Detection
1
1 Features
1• Wide Supply Voltage Range: 1.8 V to 36 V
• Adjustable Threshold: Down to 400 mV
• Open-Drain Outputs for Over- and Undervoltage
Detection
• Low Quiescent Current: 7 µA (Typical)
• High Threshold Accuracy:
– 0.75% Over Temperature
– 0.25% (Typical)
• Internal Hysteresis: 5.5 mV (Typical)
• Temperature Range: –40°C to 125°C
• Package:
– SOT-6
2 Applications
• Industrial Control Systems
• Embedded Computing Modules
• DSPs, Microcontrollers, and Microprocessors
• Notebook and Desktop Computers
• Portable- and Battery-Powered Products
• FPGA and ASIC Systems
3 Description
The TPS3701 wide-supply voltage window supervisor
operates over a 1.8-V to 36-V range. The device has
two precision comparators with an internal 400-mV
reference and two open-drain outputs (OUTA and
OUTB) rated to 25 V for over- and undervoltage
detection. Use the TPS3701 as a window supervisor
or as two independent voltage monitors; set the
monitored voltage with the use of external resistors.
OUTA is driven low when the voltage at the INA pin
drops below the negative threshold, and goes high
when the voltage returns above the positive
threshold. OUTB is driven low when the voltage at
the INB pin rises above the positive threshold, and
goes high when the voltage drops below the negative
threshold. Both comparators in the TPS3701 include
built-in hysteresis for noise rejection, thereby
ensuring stable output operation without false
triggering.
The TPS3701 is available in a SOT-6 package and is
specified over the junction temperature range of
–40°C to 125°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS3701 SOT (6) 2.90 mm × 1.60 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application Typical Error vs Junction Temperature
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 10
7.1 Overview................................................................. 10
7.2 Functional Block Diagram....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
8 Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 16
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support................. 20
11.1 Documentation Support ....................................... 20
11.2 Receiving Notification of Documentation Updates 20
11.3 Community Resources.......................................... 20
11.4 Trademarks........................................................... 20
11.5 Electrostatic Discharge Caution............................ 20
11.6 Glossary................................................................ 20
12 Mechanical, Packaging, and Orderable
Information........................................................... 20
4 Revision History
Changes from Revision A (November 2017) to Revision B Page
• Changed the text 'window comparator' to 'window supervisor' throughout the data sheet ................................................... 1
Changes from Original (November 2014) to Revision A Page
• Changed input pin voltage maximum from: 1.7 V to: 6.5 V.................................................................................................... 4
• Added a tablenote for the input pin voltage maximum........................................................................................................... 4
• Changed Figure 19 .............................................................................................................................................................. 12
1
2
3
6
5
4
OUTB
VDD
INB
OUTA
GND
INA
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5 Pin Configuration and Functions
DDC Package
6-Pin SOT
(Top View)
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
GND 2 — Ground
INA 3 I Comparator A input. This pin is connected to the voltage to be monitored with the use of an
external resistor divider. When the voltage at this terminal drops below the threshold voltage
VIT–(INA), OUTA is driven low.
INB 4 I Comparator B input. This pin is connected to the voltage to be monitored with the use of an
external resistor divider. When the voltage at this terminal exceeds the threshold voltage
VIT+(INB), OUTB is driven low.
OUTA 1 O INA comparator open-drain output. OUTA is driven low when the voltage at this comparator
is less than VIT–(INA). The output goes high when the sense voltage rises above VIT+(INA).
OUTB 6 O INB comparator open-drain output. OUTB is driven low when the voltage at this comparator
exceeds VIT+(INB). The output goes high when the sense voltage falls below VIT–(INB).
VDD 5 I Supply voltage input. Connect a 1.8-V to 36-V supply to VDD to power the device. It is good
analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range, unless otherwise noted.(1)
MIN MAX UNIT
Voltage(2) VDD –0.3 +40 VVOUTA, VOUTB –0.3 +28
VINA, VINB –0.3 +7
Current Output pin current 40 mA
Temperature Operating junction, TJ–40 +125 °C
Storage temperature, Tstg –65 +150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±500
(1) Operating VINA or VINB at 2.4 V or higher and at 125°C continuously for 10 years or more would cause a degradation of accuracy spec
to 1.5% maximum
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT
VDD Supply pin voltage 1.8 36 V
VINA, VINB Input pin voltage 0 6.5(1) V
VOUTA, VOUTB Output pin voltage 0 25 V
IOUTA, IOUTB Output pin current 0 10 mA
TJJunction temperature –40 +25 +125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.4 Thermal Information
THERMAL METRIC(1) TPS3701
UNITDDC (SOT)
6 PINS
RθJA Junction-to-ambient thermal resistance 201.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.8 °C/W
RθJB Junction-to-board thermal resistance 51.2 °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 50.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
5
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(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined.
(2) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined if less than
V(POR).
6.5 Electrical Characteristics
Over the operating temperature range of TJ= –40°C to +125°C, 1.8 V ≤VDD < 36 V, and pullup resistors RP1,2 = 100 kΩ,
unless otherwise noted. Typical values are at TJ= 25°C and VDD = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply voltage range 1.8 36 V
V(POR) Power-on reset voltage(1) VOL ≤0.2 V 0.8 V
VIT–(INA) INA pin negative input threshold voltage VDD = 1.8 V to 36 V 397 400 403 mV
VIT+(INA) INA pin positive input threshold voltage VDD = 1.8 V to 36 V 400 405.5 413 mV
VHYS(INA) INA pin hysteresis voltage
(HYS = VIT+(INA) – VIT–(INA))2 5.5 12 mV
VIT–(INB) INB pin negative input threshold voltage VDD = 1.8 V to 36 V 387 394.5 400 mV
VIT+(INB) INB pin positive input threshold voltage VDD = 1.8 V to 36 V 397 400 403 mV
VHYS(INB) INB pin hysteresis voltage
(HYS = VIT+(INB) – VIT–(INB))2 5.2 12 mV
VOL Low-level output voltage VDD = 1.8 V, IOUT = 3 mA 130 250 mV
VDD = 5 V, IOUT = 5 mA 150 250 mV
IIN Input current (at INA, INB pins) VDD = 1.8 V and 36 V, VINA, VINB = 6.5 V –25 +1 +25 nA
VDD = 1.8 V and 36 V, VINA, VINB = 0.1 V –15 +1 +15 nA
ID(leak) Open-drain output leakage current VDD = 1.8 V and 36 V, VOUT = 25 V 10 300 nA
IDD Supply current VDD = 1.8 V – 36 V 8 11 µA
UVLO Undervoltage lockout(2) VDD falling 1.3 1.5 1.7 V
VDD
INA
OUTA
INB
OUTB
VIT+(INA) VHYS
VHYS
tpd(LH) tpd(LH)
tpd(LH)
tpd(HL)
tpd(HL)
VIT±(INA)
VIT+(INB)
VIT±(INB)
td(start)
V(POR)
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(1) High-to-low and low-to-high refers to the transition at the input pins (INA and INB).
(2) During power on, VDD must exceed 1.8 V for at least 150 µs (typical) before the output state reflects the input condition.
6.6 Timing Requirements
PARAMETER TEST CONDITION MIN TYP MAX UNIT
.tpd(HL) High-to-low propagation delay(1) VDD = 24 V, ±10-mV input overdrive,
RL= 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV 9.9 µs
tpd(LH) Low-to-high propagation delay(1) VDD = 24 V, ±10-mV input overdrive,
RL= 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV 28.1 µs
td(start)(2) Startup delay VDD = 5 V 155 µs
trOutput rise time VDD = 12 V, 10-mV input overdrive,
RL= 100 kΩ, CL= 10 pF, VO= (0.1 to 0.9) × VDD 2.7 µs
tfOutput fall time VDD = 12 V, 10-mV input overdrive,
RL= 100 kΩ, CL= 10 pF, VO= (0.9 to 0.1) × VDD 0.12 µs
Figure 1. Timing Diagram
TJ (qC)
VIT+(INB) (mV)
-40 -20 0 20 40 60 80 100 120 140
399.45
399.6
399.75
399.9
400.05
400.2
400.35
D004
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
TJ (qC)
VIT-(INB) (mV)
-40 -20 0 20 40 60 80 100 120 140
392.7
393
393.3
393.6
393.9
394.2
394.5
394.8
395.1
395.4
395.7
D003
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
TJ (qC)
VIT-(INB) (mV)
-40 -20 0 20 40 60 80 100 120 140
404
404.5
405
405.5
406
406.5
407
407.5
408
408.5
D005
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
TJ (qC)
VIT-(INA) (mV)
-40 -20 0 20 40 60 80 100 120 140
399.3
399.45
399.6
399.75
399.9
400.05
400.2
D002
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
Supply Voltage (V)
Supply Current (PA)
0 6 12 18 24 30 36
0
2
4
6
8
10
D001
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
Overdrive (%)
Minimum Pulse Width (Ps)
0 5 10 15 20 25 30 35 40 45 50
0
2
4
6
8
10
12
14
16
18
20
22
D011
INA
INB
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(1) Minimum pulse duration required to trigger output high-to-low transition. INA = negative spike below VIT– and INB = positive spike above
VIT+.
6.7 Typical Characteristics
At TJ= 25°C and VDD = 12 V, unless otherwise noted.
Figure 2. Supply Current vs Supply Voltage
VDD = 24 V
Figure 3. Minimum Pulse Duration vs
Threshold Overdrive Voltage(1) (1)
Figure 4. INA Positive Input Threshold Voltage (VIT+(INA)) vs
Temperature Figure 5. INA Negative Input Threshold Voltage (VIT–(INA)) vs
Temperature
Figure 6. INB Positive Input Threshold Voltage (VIT+(INB)) vs
Temperature Figure 7. INB Negative Input Threshold Voltage (VIT–(INB)) vs
Temperature
TJ (qC)
High-to-Low Propagation Delay (Ps)
-40 -20 0 20 40 60 80 100 120 140
5
6
7
8
9
10
11
12
D007
VDD = 1.8 V, INA to OUTA
VDD = 36 V, INA to OUTA
VDD = 1.8 V, INB to OUTB
VDD = 36 V, INB to OUTB
TJ (qC)
Low-to-High Propagation Delay (Ps)
-40 -20 0 20 40 60 80 100 120 140
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
D008
VDD = 1.8 V, INA to OUTA
VDD = 36 V, INA to OUTA
VDD = 1.8 V, INB to OUTB
VDD = 36 V, INB to OUTB
VIT+(INB) Threshold Voltage (mV)
Count
0
500
1000
1500
2000
2500
3000
398
399
400
401
402
D021
VIT-(INB) Threshold Voltage (mV)
Count
0
500
1000
1500
2000
2500
3000
3500
393
394
395
396
397
D023
VIT+(INA) Threshold Voltage (mV)
Count
0
500
1000
1500
2000
2500
3000
3500
404
405
406
407
408
D022
VIT-(INA) Threshold Voltage (mV)
Count
0
500
1000
1500
2000
2500
3000
3500
4000
4500
398
399
400
401
402
D020
8
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Typical Characteristics (continued)
At TJ= 25°C and VDD = 12 V, unless otherwise noted.
VDD = 1.8 V
Figure 8. INA Positive Input Threshold Voltage (VIT+(INA))
Distribution
VDD = 1.8 V
Figure 9. INA Negative Input Threshold Voltage (VIT–(INA))
Distribution
VDD = 1.8 V
Figure 10. INB Positive Input Threshold Voltage (VIT+(INB))
Distribution
VDD = 1.8 V
Figure 11. INB Negative Input Threshold Voltage (VIT–(INB))
Distribution
Input step ±200 mV
Figure 12. Propagation Delay vs Temperature
(High-to-Low Transition at the Inputs)
Input step ±200 mV
Figure 13. Propagation Delay vs Temperature
(Low-to-High Transition at the Inputs)
Time (50 µs/div)
OUTB (2 V/div)
OUTA (2 V/div)
VDD (2 V/div) Startup
Delay
Period
TJ (qC)
Startup Delay (Ps)
-40 -20 0 20 40 60 80 100 120 140
120
135
150
165
180
195
210
D025
Time (50 µs/div)
OUTB (2 V/div)
OUTA (2 V/div)
VDD (2 V/div) Startup
Delay
Period
IOUT (mA)
VOL (V)
0 1 2 3 4 5 6 7 8 9 10
0
0.1
0.2
0.3
0.4
0.5
0.6
D009
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
IOUT (mA)
VOL (V)
0 1 2 3 4 5 6 7 8 9 10
0
0.1
0.2
0.3
0.4
0.5
D010
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
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Typical Characteristics (continued)
At TJ= 25°C and VDD = 12 V, unless otherwise noted.
VDD = 1.8 V
Figure 14. Output Voltage Low vs Output Sink Current
VDD = 12 V
Figure 15. Output Voltage Low vs Output Sink Current
VDD = 5 V
Figure 16. Start-Up Delay vs Temperature
VDD = 5 V, VINA = 390 mV, VINB = 410 mV, VPULLUP = 3.3 V
Figure 17. Start-Up Delay
VDD = 5 V, VINA = 410 mV, VINB = 390 mV, VPULLUP = 3.3 V
Figure 18. Start-Up Delay
INA
GND
INB
VDD
OUTA
OUTB
Reference
A
B
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7 Detailed Description
7.1 Overview
The TPS3701 combines two comparators (referred to as A and B) and a precision reference for over- and
undervoltage detection. The TPS3701 features a wide supply voltage range (1.8 V to 36 V) and high-accuracy
window threshold voltages of 400 mV (0.75% over temperature) with built-in hysteresis. The outputs are rated to
25 V and can sink up to 10 mA.
Set each input pin (INA, INB) to monitor any voltage above 0.4 V by using an external resistor divider network.
Each input pin has very low input leakage current, allowing the use of large resistor dividers without sacrificing
system accuracy. To form a window supervisor, use the two input pins and three resistors (see the Window
Supervisor Considerations section). In this configuration, the TPS3701 is designed to assert the output signals
when the monitored voltage is within the window band. Each input can also be used independently. The
relationship between the inputs and the outputs is shown in Table 1. Broad voltage thresholds are supported that
enable the device to be used in a wide array of applications.
Table 1. Truth Table
CONDITION OUTPUT STATUS
INA > VIT+(INA) OUTA high Output A high impedance
INA < VIT–(INA) OUTA low Output A asserted
INB > VIT+(INB) OUTB low Output B asserted
INB < VIT–(INB) OUTB high Output B high impedance
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Inputs (INA, INB)
The TPS3701 combines two comparators with a precision reference voltage. Each comparator has one external
input; the other input is connected to the internal reference. The rising threshold on INB and the falling threshold
on INA are designed and trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the
device accuracy when used as a window supervisor. Both comparators also have built-in hysteresis that proves
immunity to noise and ensures stable operation.
The comparator inputs swings from ground to 1.7 V (7.0 V absolute maximum), regardless of the device supply
voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF
bypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltage
changes on the monitored signal.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA voltage drops
below VIT–(INA). When the voltage exceeds VIT+(INA), OUTA goes to a high-impedance state; see Figure 1.
For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB exceeds
VIT+(INB). When the voltage drops below VIT–(INB) OUTB goes to a high-impedance state; see Figure 1. Together,
these two comparators form a window-detection function as described in the Window Supervisor Considerations
section.
7.3.2 Outputs (OUTA, OUTB)
In a typical TPS3701 application, the outputs are connected to a reset or enable input of the processor [such as
a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the
outputs are connected to the enable input of a voltage regulator [such as a DC-DC converter or low-dropout
regulator (LDO)].
The TPS3701 provides two open-drain outputs (OUTA and OUTB); use pullup resistors to hold these lines high
when the output goes to a high-impedance state. Connect pullup resistors to the proper voltage rails to enable
the outputs to be connected to other devices at correct interface voltage levels. The TPS3701 outputs can be
pulled up to 25 V, independent of the device supply voltage. To ensure proper voltage levels, give some
consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, output
capacitive loading, and output leakage current (ID(leak)). These values are specified in the Electrical
Characteristics table. Use wired-OR logic to merge OUTA and OUTB into one logic signal.
Table 1 and the Inputs (INA, INB) section describe how the outputs are asserted or high impedance. See
Figure 1 for a timing diagram that describes the relationship between threshold voltages and the respective
output.
7.4 Device Functional Modes
7.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUTA and OUTB signals correspond to
the voltage on INA and INB as listed in Table 1.
7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on-reset voltage,
V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on
INA and INB.
7.4.3 Power-On-Reset (VDD < V(POR))
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND
(V(POR)), both outputs are in a high-impedance state.
Overvoltage
Limit
Undervoltage
Limit
VMON
OUTB
OUTA
VMON(OV)
VMON(OV_HYS)
VMON(UV)
VMON(UV_HYS)
R1
(2.21 M )W
GND
1.8 V to 25 V
OUTA
OUTB
R2
(13.7 k )W
R3
(69.8 k )W
VMON
INA
INB
VDD
Device
RP1
(50 k )W
OUT
VMON
UV OV
OUT
Reset or to MCU
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS3701 is used as a precision dual-voltage supervisor in several different configurations. The monitored
voltage (VMON), VDD voltage, and output pullup voltage can be independent voltages or connected in any
configuration. The following sections show the connection configurations and the voltage limitations for each
configuration.
8.1.1 Window Supervisor Considerations
The inverting and noninverting configuration of the comparators forms a window-supervisor detection circuit
using a resistor divider network, as shown in Figure 19 and Figure 20. The input pins can monitor any system
voltage above 400 mV with the use of a resistor divider network. INA and INB monitor for undervoltage and
overvoltage conditions, respectively.
Figure 19. Window Supervisor Block Diagram
Figure 20. Window Supervisor Timing Diagram
R =
2
-R3
VIT (INA)-
R
V
TOTAL
MON(UV)
R =
2
-R3
VIT+(INA)
R
V
TOTAL
MON(UV_HYS)
R =
3VIT+(INB)
R
V
TOTAL
MON(OV)
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Application Information (continued)
The TPS3701 flags the overvoltage or undervoltage condition with the greatest accuracy. The highest accuracy
threshold voltages are VIT–(INA) and VIT+(INB), and correspond with the falling undervoltage flag, and the rising
overvoltage flag, respectively. These thresholds represent the accuracy when the monitored voltage is within the
valid window (both OUTA and OUTB are in a high-impedance state), and correspond to the VMON(UV) and
VMON(OV) trigger voltages, respectively. If the monitored voltage is outside of the valid window (VMON is less than
the undervoltage limit, VMON(UV), or greater than overvoltage limit, VMON(OV)), then the input threshold voltages to
re-enter the valid window are VIT+(INA) or VIT–(INB), and correspond with the VMON(UV_HYS) and VMON(OV_HYS)
monitored voltages, respectively.
The resistor divider values and target threshold voltage can be calculated by using Equation 1 through
Equation 4:
RTOTAL = R1+ R2+ R3(1)
Choose an RTOTAL value so that the current through the divider is approximately 100 times higher than the input
current at the INA and INB pins. Resistors with high values minimize current consumption; however, the input
bias current degrades accuracy if the current through the resistors is too low. See application report SLVA450,
Optimizing Resistor Dividers at a Comparator Input (SLVA450), for details on sizing input resistors.
R3is determined by Equation 2:
where
• VMON(OV) is the target voltage at which an overvoltage condition is detected. (2)
R2is determined by either Equation 3 or Equation 4:
where
• VMON(UV_HYS) is the target voltage at which an undervoltage condition is removed as VMON rises. (3)
where
• VMON(UV) is the target voltage at which an undervoltage condition is detected. (4)
8.1.2 Input and Output Configurations
Figure 21 to Figure 24 show examples of the various input and output configurations.
GND
1.8 V to 25 V
OUTA
OUTB
INA
INB
VDD
Device To a reset or enable input
of the system.
GND
1.8 V to 36 V
OUTA
OUTB
INA
INB
VDD
Device
V
(up to 25 V)
PULLUP
To a reset or enable input
of the system.
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Application Information (continued)
Figure 21. Interfacing to Voltages Other than VDD
Figure 22. Monitoring the Same Voltage as VDD
GND
1.8 V to 18 V
OUTA
OUTB
INA
INB
VDD
Device
5 V
12 V
VIT+(INA)
To a reset or enable
input of the system.
VIT±(INA)
VIT+(INB)
VIT±(INB)
R1
GND
1.8 V to 25 V
OUTA
OUTB
R2
R3
VMON
INA
INB
VDD
Device
To a reset or enable input
of the system.
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Application Information (continued)
NOTE: The inputs can monitor a voltage higher than VDD (max) with the use of an external resistor divider network.
Figure 23. Monitoring a Voltage Other than VDD
NOTE: In this case, OUTA is driven low when an undervoltage condition is detected at the 5-V rail and OUTB is driven low when an
overvoltage condition is detected at the 12-V rail.
Figure 24. Monitoring Overvoltage for One Rail and Undervoltage for a Different Rail
8.1.3 Immunity to Input Pin Voltage Transients
The TPS3701 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and amplitude; see Figure 3,Minimum Pulse Duration vs Threshold Overdrive Voltage.
( )
( )
TOTAL
2 IT INA 3
MON UV
R2.03 M
R V R 0.4 V 30.9 kN
V 21.6 V
:
x x
R =
3=VIT+(INB)
R
V
TOTAL
MON(OV)
2.03 M
26.4 V
W0.4 V = 30.7 kW
( ) .
MON OV
TOTAL V26.4 V
R 2 03 M
I 13 A
P
Device
+
±
VDD
INA
INB
OUTA
OUTB
GND
2.0 MŸ
6.81 kŸ
VPULLUP
3.3 V
30.9 kŸ
100 kŸ
100 kŸ
VMON
24 V 0.01 F
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8.2 Typical Application
Figure 25. 24-V, 10% Window Supervisor
8.2.1 Design Requirements
Table 2 lists the design parameters for this example.
Table 2. Design Parameters
PARAMETER DESIGN REQUIREMENT DESIGN RESULT
Monitored voltage 24-V nominal, rising (VMON(OV)) and
falling (VMON(UV)) threshold
±10% nominal (26.4 V and 21.6 V,
respectively) VMON(OV) = 26.4 V ±2.7%, VMON(UV) = 21.6 V ±2.7%
Output logic voltage 3.3-V CMOS 3.3-V CMOS
Maximum current consumption 30 µA 24 µA
8.2.2 Detailed Design Procedure
1. Determine the minimum total resistance of the resistor network necessary to achieve the current
consumption specification by using Equation 1. For this example, the current flow through the resistor
network was chosen to be 13 µA; a lower current can be selected. However, take care to avoid leakage
currents that are artifacts of the manufacturing process. Leakage currents significantly impact the accuracy if
they are greater than 1% of the resistor network current.
where
• VMON(OV) is the target voltage at which an overvoltage condition is detected as VMON rises.
• I is the current flowing through the resistor network. (5)
2. After RTOTAL is determined, R3can be calculated using Equation 6. Select the nearest 1% resistor value for
R3. In this case, 30.9 kΩis the closest value.
(6)
3. Use Equation 7 to calculate R2. Select the nearest 1% resistor value for R2. In this case, 6.81 kΩis the
closest value.
(7)
4. Use Equation 8 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 2 MΩis the closest
value.
Time (5 ms/div)
OUTB (2 V/div)
OUTA (2 V/div)
VDD (10 V/div)
( )
( ) ( )
..
IT INB
IT INB R
MON OV
V0 4
$&& 72/9 ‡ ‡72/ ‡ ‡
V 26 4
§ · § ·
¨ ¸ ¨ ¸
¨ ¸ © ¹
© ¹
1 TOTAL 2 3
R R R R 2.03 MNN0
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(8)
5. The worst-case tolerance can be calculated by referring to Equation 13 in application report Optimizing
Resistor Dividers at a Comparator Input (SLVA450). An example of the rising threshold error, VMON(OV), is
given in Equation 9:
where
• % TOL(VIT+(INB)) is the tolerance of the INB positive threshold.
• % ACC is the total tolerance of the VMON(OV) voltage.
• % TOLRis the tolerance of the resistors selected. (9)
6. When the outputs switch to the high-Z state, the rise time of the OUTA or OUTB node depends on the pullup
resistance and the capacitance on the node. Choose pullup resistors that satisfy the downstream timing
requirements; 100-kΩresistors are a good choice for low-capacitive loads.
8.2.3 Application Curve
Figure 26. 24-V Window Monitor Output Response
100 Ÿ
0.01 F
+
±
VDD
INA
INB
OUTA
OUTB
GND
R1
R2
R3
VPULLUP
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9 Power Supply Recommendations
The TPS3701 has a 40-V absolute maximum rating on the VDD pin, with a recommended operating condition of
36 V. If the voltage supply that is providing power to VDD is susceptible to any large voltage transient that may
exceed 40 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, take additional precautions.
Place an RC filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. A
100-Ωresistor and 0.01-µF capacitor is required in these cases, as shown in Figure 27.
Figure 27. Using an RC Filter to Remove High-Frequency Disturbances on VDD
Input
Supply
1
2
34
6
5
R2
R1R3
Monitored
Voltage
RP1RP2Overvoltage
Flag
Undervoltage
Flag
Pullup
Voltage
CVDD
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10 Layout
10.1 Layout Guidelines
• Place R1, R2, and R3close to the device to minimize noise coupling into the INA and INB nodes.
• Place the VDD decoupling capacitor close to the device.
• Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, may form an LC tank and create ringing with peak voltages above the
maximum VDD voltage. If this is unavoidable, see Figure 27 for an example of filtering VDD.
10.2 Layout Example
Figure 28. Recommended Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following application reports and user guide (available through the TI
website):
• Application report Using the TPS3700 as a Negative Rail Over- and Undervoltage Detector (SLVA600).
• Application report Optimizing Resistor Dividers at a Comparator Input (SLVA450).
• User guide TPS3700EVM-114 Evaluation Module (SLVU683).
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jun-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS3701DDCR ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ZABO
TPS3701DDCT ACTIVE SOT-23-THIN DDC 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ZABO
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jun-2018
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS3701DDCR SOT-
23-THIN DDC 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS3701DDCT SOT-
23-THIN DDC 6 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS3701DDCR SOT-23-THIN DDC 6 3000 195.0 200.0 45.0
TPS3701DDCT SOT-23-THIN DDC 6 250 195.0 200.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2018
Pack Materials-Page 2
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