Document Number: MMPF0100
Rev. 12.0, 9/2015
Freescale Semiconductor
Advance Information
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2012-2015. All rights reserved.
14 Channel Configurable Power
Management Integrated Circuit
The PF0100 SMARTMOS Power Management Integrated Circuit
(PMIC) provides a highly programmable/ configurable architecture,
with fully integrated power devices and minimal external components.
With up to six buck converters, six linear regulators, RTC supply, and
coin-cell charger, the PF0100 can provide power for a complete
system, including applications processors, memory, and system
peripherals, in a wide range of applications. With on-chip One Time
Programmable (OTP) memory, the PF0100 is available in pre-
programmed standard versions, or non-programmed to support
custom programming. The PF0100 is defined to power an entire
embedded MCU platform solution such as i.MX 6 based eReader,
IPTV, medical monitoring, and home/factory automation.
Features:
• Four to six buck converters, depending on configuration
• Single/Dual phase/ parallel options
• DDR termination tracking mode option
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (One Time Programmable) memory for device configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event detection
•I
2C control
• Individually programmable ON, OFF, and Standby modes
Figure 1. Simplified Application Diagram
POWER MANAGEMENT
PF0100
Applications:
• Tablets
•IPTV
• eReaders
• Set Top Boxes
• Industrial control
• Medical monitoring
• Home automation/ alarm/ energy management
EP SUFFIX (E-TYPE)
98ASA00405D
56 QFN 8X8
ES SUFFIX (WF-TYPE)
98ASA00589D
56 QFN 8X8
VGEN3
100 mA
VGEN5
100 mA
Camera
Audio
Codec
Cluster/HUD
External AMP
Microphones
Speakers
Front USB
POD
Rear USB
POD
Rear Seat
Infotaiment
Sensors
i.MX 6X
I2C Communication I2C Communication
PF0100
Control Signals Parallel control/GPIOS
LICELL
Charger
COINCELL Main Supply
2.8 – 4.5 V
VGEN1
100 mA
VGEN2
250 mA
VGEN4
350 mA
VGEN6
200 mA
SWBST
600 mA
SW3A/B
2500 mA
SW1C
2000 mA
SW1A/B
2500 mA
SW2
2000 mA
SW4
1000 mA
GPS
MIPI
uPCIe
SATA - FLASH
NAND - NOR
Interfaces
Processor Core
Voltages
Camera
VREFDDR
DDR Memory DDR MEMORY
INTERFACE
SD-MMC/
NAND Mem.
SATA
HDD
WAM
GPS
MIPI
HDMI
LDVS Display
USB
Ethernet
CAN
Analog Integrated Circuit Device Data
2Freescale Semiconductor
PF0100
Table of Contents
1 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.1 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.2 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Functional Block Requirements and Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.1 Device Start-up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.2 One Time Programmability (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.3 OTP Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.4 Reading OTP Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.5 Programming OTP Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 16 MHz and 32 kHz Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.1 Clock adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 Bias and References Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.1 Internal Core Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.2 VREFDDR Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4.2 State Machine Flow Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4.3 Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.4 Buck Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.5 Boost Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.6 LDO Regulators Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.4.7 VSNVS LDO/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.5 Control Interface I2C Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.5.1 I2C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.5.2 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.5.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.5.4 Interrupt Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.5.5 Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.5.6 Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
PF0100
7 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.1.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.1.2 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.2 PF0100 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.1 General Board Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.2 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.3 General Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.4 Parallel Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2.5 Switching Regulator Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.3 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.3.1 Rating Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.3.2 Estimation of Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.1 Packaging Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9 Reference Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Analog Integrated Circuit Device Data
4Freescale Semiconductor
PF0100
Orderable Parts
1 Orderable Parts
The PF0100 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed
device uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1,
which also list the associated Freescale reference designs where applicable. Details of the OTP programming for each device
can be found in Table 10.
Table 1. Orderable Part Variations
Part Number Temperature (TA)Package Programming Reference Designs Qualification
Tier Notes
MMPF0100NPEP
-40 to 85 °C 56 QFN 8x8 mm - 0.5 mm pitch
E-Type QFN (full lead)
NP N/A
Consumer and
Industrial
(1), (2)
MMPF0100F0EP F0
MCIMX6Q-SDP
MCIMX6Q-SDB
MCIMX6DL-SDP
MMPF0100F1EP F1 MCIMX6SLEVK (1), (2),
(3)
MMPF0100F2EP F2 N/A
MMPF0100NPAEP
-40 to 85 °C 56 QFN 8x8 mm - 0.5 mm pitch
E-Type QFN (full lead)
NP N/A
Consumer
(1), (2)
MMPF0100F0AEP F0
MCIMX6Q-SDP
MCIMX6Q-SDB
MCIMX6DL-SDP
MMPF0100F1AEP F1 MCIMX6SLEVK (1), (2),
(3)
MMPF0100F2AEP F2 N/A
MMPF0100F3AEP F3 N/A
(1), (2)
MMPF0100F4AEP F4 N/A
MMPF0100F6AEP F6 MCIMX6SX-SDB
MMPF0100NPANES
-40 to 105 °C 56 QFN 8x8 mm - 0.5 mm pitch
WF-Type QFN (wettable flank)
NP N/A
Extended
Industrial
MMPF0100F0ANES F0
MCIMX6Q-SDP
MCIMX6Q-SDB
MCIMX6DL-SDP
MMPF0100F3ANES F3 N/A
MMPF0100F4ANES F4 N/A
MMPF0100F6ANES F6 MCIMX6SX-SDB
MMPF0100F9ANES F9 N/A
MMPF0100FAANES FA N/A
Notes
1. For Tape and Reel, add an R2 suffix to the part number.
2. For programming details see Table 10. The available OTP options are not restricted to the listed reference designs. They can be used
in any application where the listed voltage and sequence details are acceptable.
3. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option
instead of the F2 OTP option.
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
PF0100
Orderable Parts
PF0100 Version Differences
1.1 PF0100 Version Differences
PF0100A is an improved version of the PF0100 Power Management IC. Table 2 summarizes the difference between the two
versions and should be referred to when migrating from the PF0100 to the PF0100A. Note that programming options are the
same for both versions of the device.
In addition to the version differences, Table 3 shows the differences on the test temperature rating for each version of PF0100
covered on this datasheet.
Table 2. Differences between PF0100 and PF0100A
Description PF0100 PF0100A
Version identification
Reading SILICON REV register at address
0x03 will return 0x11. DEVICEID register at
address 0x00 will read 0x10 in PF0100 and
PF0100A
Reading SILICON REV register at address
0x03 will return 0x21. DEVICEID register at
address 0x00 will read 0x10 in PF0100 and
PF0100A
VSNVS current limit VSNVS current limit increased in the PF0100A
OTP_FUSE_PORx register setting during OTP
programming
In the PF0100, FUSE_POR1, FUSE_POR2,
and FUSE_POR3 bits are XOR’ed into the
FUSE_POR_XOR bit. The FUSE_POR_XOR
bit has to be 1 for fuses to be loaded during
startup. This can be achieved by setting any
one or all of the FUSE_PORx bits during OTP
programming.
In the PF0100A, the XOR function is removed.
It is required to set FUSE_POR1,
FUSE_POR2, and FUSE_POR3 bits during
OTP programming.
Erratum ER19
Erratum ER19 applicable to PF0100.
Applications expecting to operate in the
conditions mentioned in ER19 need to
implement an external workaround to
overcome the problem. Refer to the product
errata for details
Errata ER19 fixed in PF0100A. External
workaround not required
Erratum ER20 Erratum ER20 applicable to PF0100 Errata ER20 fixed in PF0100A
Erratum ER22 Erratum ER22 applicable to PF0100 Errata ER22 fixed in PF0100A. Workaround
not required
Table 3. Ambient Temperature Range
Device Qualification Tier Ambient Temperature range
(TMIN to TMAX)
MMPF0100 Consumer and Industrial TA = -40 to 85 °C
MMPF0100A Consumer TA = -40 to 85 °C
MMPF0100AN Extended Industrial TA = -40 to 105 °C
Analog Integrated Circuit Device Data
6Freescale Semiconductor
PF0100
Internal Block Diagram
PF0100 Version Differences
2 Internal Block Diagram
Figure 2. Simplified Internal Block Diagram
VIN
INTB
LICELL
SWBSTFB
SWBSTIN
SWBSTLX
O/P
Drive
SWBST
600 mA
Boost
PWRON
STANDBY
ICTEST
SCL
SDA
VDDIO
SW3A/B
Single/Dual
DDR
2500 mA
Buck
VCOREDIG
VCOREREF
SDWNB
GNDREF
SW1CFB
SW1AIN
SW1C
2000 mA
Buck
SW1FB
SW1ALX
SW1BLX
SW1A/B
Single/Dual
2500 mA
Buck
SW1VSSSNS
VSNVS
VSNVS
Li Cell
Charger
RESETBMCU
SW2
2000 mA
Buck
VGEN1
100 mA
VGEN1
VIN1
VGEN2
250 mA
VGEN2
VGEN3
100 mA
VGEN3
VIN2
VGEN4
350 mA
VGEN4
VGEN5
100 mA
VGEN5
VIN3
VGEN6
200 mA
VGEN6
Best
of
Supply
OTP
SW4
1000 mA
Buck
VREFDDR
VDDOTP
VINREFDDR
VHALF
VCORE
PF0100
CONTROL
Clocks
32 kHz and 16 MHz
Initialization State Machine
I2C
Interface
Clocks and
resets
I2C Register
map
Trim-In-Package
O/P
Drive
O/P
Drive SW1BIN
SW1CLX
O/P
Drive SW1CIN
SW2FB
SW2LX
O/P
Drive SW2IN
SW2IN
SW3AIN
SW3AFB
SW3ALX
SW3BLX
O/P
Drive
O/P
Drive SW3BIN
SW3BFB
SW3VSSSNS
SW4IN
SW4FB
SW4LX
O/P
Drive
Supplies
Control
DVS Control
DVS CONTROL
Reference
Generation
Core Control logic
GNDREF1
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
PF0100
Pin Connections
Pinout Diagram
3 Pin Connections
3.1 Pinout Diagram
Figure 3. Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
4344454647484950515253545556
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2827262524232221201918171615
INTB
SDWNB
RESETBMCU
STANDBY
ICTEST
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
SW1CLX
SW1CIN
SW1CFB
SW1VSSSNS
LICELL
VGEN6
VIN3
VGEN5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
PWRON
VDDIO
SCL
SDA
VCOREREF
VCOREDIG
VIN
VCORE
GNDREF
VDDOTP
SWBSTLX
SWBSTIN
SWBSTFB
VSNVS
GNDREF1
VGEN1
VIN1
VGEN2
SW4FB
SW4IN
SW4LX
SW2LX
SW2IN
SW2IN
SW2FB
VGEN3
VIN2
VGEN4
EP
Analog Integrated Circuit Device Data
8Freescale Semiconductor
PF0100
Pin Connections
Pin Definitions
3.2 Pin Definitions
Table 4. PF0100 Pin Definitions
Pin Number Pin Name Pin
Function Max Rating Type Definition
1 INTB O 3.6 V Digital Open drain interrupt signal to processor
2 SDWNB O 3.6 V Digital Open drain signal to indicate an imminent system shutdown
3 RESETBMCU O 3.6 V Digital Open drain reset output to processor. Alternatively can be used
as a Power Good output.
4 STANDBY I 3.6 V Digital Standby input signal from processor
5 ICTEST I 7.5 V Digital/
Analog Reserved pin. Connect to GND in application.
6SW1FB
(5) I 3.6 V Analog
Output voltage feedback for SW1A/B. Route this trace separately
from the high current path and terminate at the output
capacitance.
7SW1AIN
(5) I 4.8 V Analog
Input to SW1A regulator. Bypass with at least a 4.7 F ceramic
capacitor and a 0.1 F decoupling capacitor as close to the pin as
possible.
8 SW1ALX (5) O 4.8 V Analog Regulator 1A switch node connection
9 SW1BLX (5) O 4.8 V Analog Regulator 1B switch node connection
10 SW1BIN (5) I 4.8 V Analog
Input to SW1B regulator. Bypass with at least a 4.7 F ceramic
capacitor and a 0.1 F decoupling capacitor as close to the pin as
possible.
11 SW1CLX (5) O 4.8 V Analog Regulator 1C switch node connection
12 SW1CIN (5) I 4.8 V Analog
Input to SW1C regulator. Bypass with at least a 4.7 F ceramic
capacitor and a 0.1 F decoupling capacitor as close to the pin as
possible.
13 SW1CFB (5) I 3.6V Analog
Output voltage feedback for SW1C. Route this trace separately
from the high current path and terminate at the output
capacitance.
14 SW1VSSSNS GND - GND Ground reference for regulators SW1ABC. It is connected
externally to GNDREF through a board ground plane.
15 GNDREF1 GND - GND Ground reference for regulators SW2 and SW4. It is connected
externally to GNDREF, via board ground plane.
16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 F ceramic output
capacitor.
17 VIN1 I 3.6 V Analog VGEN1, 2 input supply. Bypass with a 1.0 F decoupling
capacitor as close to the pin as possible.
18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 F ceramic output
capacitor.
19 SW4FB (5) I 3.6 V Analog
Output voltage feedback for SW4. Route this trace separately
from the high current path and terminate at the output
capacitance.
20 SW4IN (5) I 4.8 V Analog
Input to SW4 regulator. Bypass with at least a 4.7F ceramic
capacitor and a 0.1 F decoupling capacitor as close to the pin as
possible.
21 SW4LX (5) O 4.8 V Analog Regulator 4 switch node connection
22 SW2LX (5) O 4.8 V Analog Regulator 2 switch node connection
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
PF0100
Pin Connections
Pin Definitions
23 SW2IN (5) I 4.8 V Analog Input to SW2 regulator. Connect pin 23 together with pin 24 and
bypass with at least a 4.7 F ceramic capacitor and a 0.1 F
decoupling capacitor as close to these pins as possible.
24 SW2IN (5) I 4.8 V Analog
25 SW2FB (5) I 3.6 V Analog
Output voltage feedback for SW2. Route this trace separately
from the high current path and terminate at the output
capacitance.
26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 F ceramic output
capacitor.
27 VIN2 I 3.6 V Analog VGEN3,4 input. Bypass with a 1.0 F decoupling capacitor as
close to the pin as possible.
28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 F ceramic output
capacitor.
29 VHALF I 3.6 V Analog Half supply reference for VREFDDR
30 VINREFDDR I 3.6 V Analog VREFDDR regulator input. Bypass with at least 1.0 F decoupling
capacitor as close to the pin as possible.
31 VREFDDR O 3.6 V Analog VREFDDR regulator output
32 SW3VSSSNS GND - GND Ground reference for the SW3 regulator. Connect to GNDREF
externally via the board ground plane.
33 SW3BFB (5) I 3.6 V Analog
Output voltage feedback for SW3B. Route this trace separately
from the high current path and terminate at the output
capacitance.
34 SW3BIN (5) I 4.8 V Analog
Input to SW3B regulator. Bypass with at least a 4.7 F ceramic
capacitor and a 0.1 F decoupling capacitor as close to the pin as
possible.
35 SW3BLX (5) O 4.8 V Analog Regulator 3B switch node connection
36 SW3ALX (5) O 4.8 V Analog Regulator 3A switch node connection
37 SW3AIN (5) I 4.8 V Analog
Input to SW3A regulator. Bypass with at least a 4.7 F ceramic
capacitor and a 0.1 F decoupling capacitor as close to the pin as
possible.
38 SW3AFB (5) I 3.6 V Analog
Output voltage feedback for SW3A. Route this trace separately
from the high current path and terminate at the output
capacitance.
39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 F ceramic output
capacitor.
40 VIN3 I 4.8 V Analog VGEN5, 6 input. Bypass with a 1.0 F decoupling capacitor as
close to the pin as possible.
41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 F ceramic output
capacitor.
42 LICELL I/O 3.6 V Analog Coin cell supply input/output
43 VSNVS O 3.6 V Analog LDO or coin cell output to processor
44 SWBSTFB (5) I 5.5 V Analog
Boost regulator feedback. Connect this pin to the output rail close
to the load. Keep this trace away from other noisy traces and
planes.
45 SWBSTIN (5) I 4.8 V Analog
Input to SWBST regulator. Bypass with at least a 2.2 F ceramic
capacitor and a 0.1 F decoupling capacitor as close to the pin as
possible.
46 SWBSTLX (5) O 7.5 V Analog SWBST switch node connection
Table 4. PF0100 Pin Definitions (continued)
Pin Number Pin Name Pin
Function Max Rating Type Definition
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
PF0100
Pin Connections
Pin Definitions
47 VDDOTP I 10 V(4) Digital &
Analog Supply to program OTP fuses
48 GNDREF GND - GND Ground reference for the main band gap regulator.
49 VCORE O 3.6 V Analog Analog Core supply
50 VIN I 4.8 V Analog Main chip supply
51 VCOREDIG O 1.5 V Analog Digital Core supply
52 VCOREREF O 1.5 V Analog Main band gap reference
53 SDA I/O 3.6 V Digital I2C data line (Open drain)
54 SCL I 3.6 V Digital I2C clock
55 VDDIO I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 F ceramic capacitor
56 PWRON I 3.6 V Digital Power On/off from processor
- EP GND - GND
Expose pad. Functions as ground return for buck regulators. Tie
this pad to the inner and external ground planes through vias to
allow effective thermal dissipation.
Notes
4. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.
5. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should
be connected to VIN with a 0.1 F bypass capacitor.
Table 4. PF0100 Pin Definitions (continued)
Pin Number Pin Name Pin
Function Max Rating Type Definition
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
PF0100
General Product Characteristics
Absolute Maximum Ratings
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent
damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol Description Value Unit
ELECTRICAL RATINGS
VIN Main input supply voltage -0.3 to 4.8 V
VDDOTP OTP programming input supply voltage -0.3 to 10 V
VLICELL Coin cell voltage -0.3 to 3.6 V
VESD
ESD Ratings
Human Body Model(6)
Charge Device Model(6)
±2000
±500
V
Notes
6. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
PF0100
General Product Characteristics
Thermal Characteristics
4.2 Thermal Characteristics
Table 6. Thermal Ratings
Symbol Description (Rating) Min. Max. Unit
THERMAL RATINGS
TA
Ambient Operating Temperature Range
PF0100
PF0100A
PF0100AN
-40
-40
-40
85
85
105
C
TJOperating Junction Temperature Range (7) -40 125 C
TST Storage Temperature Range -65 150 C
TPPRT Peak Package Reflow Temperature (8)(9) – Note 9 C
QFN56 THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
RJA
Junction to Ambient (10)(11)(12)
Natural Convection
Four layer board (2s2p)
Eight layer board (2s6p)
–
–
28
15
°C/W
RJMA
Junction to Ambient (@200 ft/min)(10)(12)
Four layer board (2s2p) – 22 °C/W
RJB Junction to Board(13) –10°C/W
RJCBOTTOM Junction to Case Bottom(14) – 1.2 °C/W
JT Junction to Package Top(15)
Natural Convection – 2.0 °C/W
Notes
7. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See
Table 7 for thermal protection features.
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause a malfunction or permanent damage to the device.
9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
10. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
11. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
12. Per JEDEC JESD51-6 with the board horizontal.
13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
14. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
15. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
PF0100
General Product Characteristics
Electrical Characteristics
4.2.1 Power Dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 6. To optimize
the thermal management and to avoid overheating, the PF0100 provides thermal protection. An internal comparator monitors the
die temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective
thresholds specified in Table 7 are crossed in either direction. The temperature range can be determined by reading the
THERMxxxS bits in register INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry will shut down the PF0100. This thermal protection will
act above the thermal protection threshold listed in Table 7. To avoid any unwanted power downs resulting from internal noise,
the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system
should be configured such that this protection is not tripped under normal conditions.
4.3 Electrical Characteristics
4.3.1 General Specifications
Table 7. Thermal Protection Thresholds
Parameter Min. Typ. Max. Units
Thermal 110 °C Threshold (THERM110) 100 110 120 °C
Thermal 120 °C Threshold (THERM120) 110 120 130 °C
Thermal 125 °C Threshold (THERM125) 115 125 135 °C
Thermal 130 °C Threshold (THERM130) 120 130 140 °C
Thermal Warning Hysteresis 2.0 – 4.0 °C
Thermal Protection Threshold 130 140 150 °C
Table 8. General PMIC Static Characteristics.
TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current
range, unless otherwise noted.
Pin Name Parameter Load Condition Min. Max. Unit
PWRON
VIL –0.00.2 * VSNVSV
VIH – 0.8 * VSNVS 3.6 V
RESETBMCU
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7* VIN VIN V
SCL
VIL – 0.0 0.2 * VDDIO V
VIH – 0.8 * VDDIO 3.6 V
SDA
VIL – 0.0 0.2 * VDDIO V
VIH – 0.8 * VDDIO 3.6 V
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7*VDDIO VDDIO V
INTB
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7* VIN VIN V
SDWNB
VOL -2.0 mA 0.0 0.4 V
VOH Open Drain 0.7* VIN VIN V
Analog Integrated Circuit Device Data
14 Freescale Semiconductor
PF0100
General Product Characteristics
Electrical Characteristics
STANDBY
VIL –0.00.2 * VSNVSV
VIH – 0.8 * VSNVS 3.6 V
VDDOTP
VIL –0.00.3V
VIH –1.11.7V
Table 8. General PMIC Static Characteristics.
TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current
range, unless otherwise noted.
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
PF0100
General Product Characteristics
Electrical Characteristics
4.3.2 Current Consumption
Table 9. Current Consumption Summary
TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 to 3.6 V, LICELL = 1.8 to 3.3 V, VSNVS = 3.0 V, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V,
VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode PF0100 Conditions System Conditions Typical MAX Unit
Coin Cell
(16),(18),(22)
VSNVS from LICELL
All other blocks off
VIN = 0.0 V
VSNVSVOLT[2:0] = 110
No load on VSNVS 4.0 7.0 A
Off (17),(18)
MMPF0100
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN UVDET
No load on VSNVS, PMIC able to wake-up 16 21 A
Off (17),(18)
MMPF0100A
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN UVDET
No load on VSNVS, PMIC able to wake-up 17 25 A
Sleep (18)
VSNVS from VIN
Wake-up from PWRON active
Trimmed reference active
SW3A/B PFM
Trimmed 16 MHz RC off
32 k RC on
VREFDDR disabled
No load on VSNVS. DDR memories in self
refresh
122
122
220(21)
250(20)
A
Standby (18)
MMPF0100
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
297
297
450 (19)
1000 (21)
A
Analog Integrated Circuit Device Data
16 Freescale Semiconductor
PF0100
General Product Characteristics
Electrical Characteristics
Figure 4. Coin cell Mode Current Vs Temperature
Standby (18)
MMPF0100A
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
297
297
450 (21)
550(20)
A
Notes
16. Refer to Figure 4 for Coin Cell mode characteristics over temperature.
17. When VIN is below the UVDET threshold, in the range of 1.8 V VIN < 2.65 V, the quiescent current increases by 50 A, typically.
18. For PFM operation, headroom should be 300 mV or greater.
19. From 0 °C to 85 °C
20. From -40 °C to 105 °C, Applicable only to Extended Industrial parts.
21. From -40 °C to 85 °C, Applicable to Consumer, Industrial and Extended Industrial part numbers.
22. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from
RESETBMCU to VIN. The additional current is <30A with a pull up resistor of 100k. The i.MX 6x processors have an internal pull up
from the POR_B pin to the VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use
an external switch to disconnect the RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull up RESETBMCU to a
rail that is off in the coin cell mode.
Table 9. Current Consumption Summary (continued)
TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 to 3.6 V, LICELL = 1.8 to 3.3 V, VSNVS = 3.0 V, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V,
VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode PF0100 Conditions System Conditions Typical MAX Unit
Coin Cell mode current (uA)
Coin Cell Mode
1
10
100
‐40 ‐20 0 20406080
Temperature(oC)
MMPF0100
MMPF0100A
Temperature (°C)
Analog Integrated Circuit Device Data
Freescale Semiconductor 17
PF0100
General Description
Features
5 General Description
The PF0100 is the Power Management Integrated Circuit (PMIC) designed primarily for use with Freescale’s i.MX 6 series of
application processors.
5.1 Features
This section summarizes the PF0100 features.
• Input voltage range to PMIC: 2.8 - 4.5 V
• Buck regulators
• Four to six channel configurable
• SW1A/B/C, 4.5 A (single); 0.3 to 1.875 V
• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 to 1.875 V
•SW2, 2.0 A; 0.4 to 3.3 V
• SW3A/B, 2.5 A (single/dual); 0.4 to 3.3 V
• SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V
•SW4, 1.0 A; 0.4 to 3.3 V
• SW4, VTT mode provide DDR termination at 50% of SW3A
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable soft start
• Programmable PWM switching frequency
• Programmable OCP with fault interrupt
• Boost regulator
• SWBST, 5.0 to 5.15 V, 0.6 A, OTG support
• Modes: PFM and Auto
• OCP fault interrupt
•LDOs
• Six user programable LDO
• VGEN1, 0.80 to 1.55 V, 10 0 mA
• VGEN2, 0.80 to 1.55 V, 25 0 mA
• VGEN3, 1.8 to 3.3 V, 100 mA
• VGEN4, 1.8 to 3.3 V, 350 mA
• VGEN5, 1.8 to 3.3 V, 100 mA
• VGEN6, 1.8 to 3.3 V, 200 mA
• Soft start
• LDO/Switch supply
• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 A
• DDR memory reference voltage
• VREFDDR, 0.6 to 0.9 V, 10 mA
•16 MHz internal master clock
• OTP(One time programmable) memory for device configuration
• User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
•I
2C interface
• User programmable Standby, Sleep, and Off modes
Analog Integrated Circuit Device Data
18 Freescale Semiconductor
PF0100
General Description
Functional Block Diagram
5.2 Functional Block Diagram
Figure 5. Functional Block Diagram
5.3 Functional Description
5.3.1 Power Generation
The PF0100 PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs,
one switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral
devices.
The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with
higher current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current
demands. Further, SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the
buck regulators, SW4, can also operate as a tracking regulator when used for memory termination. The buck regulators provide
the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to
allow controlled supply rail adjustments for the processor cores and/or other circuitry.
Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the
main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A
specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operating with or
without VTT termination. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on
the i.MX processors; VSNVS may be powered from VIN, or from a coin cell.
5.3.2 Control Logic
The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing
including interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-
up section, or by configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP
configuration.
The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures
supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger
for the coin cell is included as well.
Logic and Control
Switching Regulators
SW1A/B/C
(0.3 to 1.875V)
Configurable 4.5A or
2.5A+2.0A
Linear Regulators
SW2
(0.4 to 3.3V, 2A)
SW3A/B
(0.4 to 3.3V)
Configurable 2.5A or
1.25A+1.25A
SW4
(0.4 to 3.3V, 1A)
Boost Regulator
(5 to 5.15V, 600mA)
USB OTG Supply
VGEN1
(0.8 to 1.55V, 100mA)
VGEN2
(0.8 to 1.55V, 250mA)
VGEN3
(1.8 to 3.3V, 100mA)
VGEN4
(1.8 to 3.3V, 350mA)
VGEN5
(1.8 to 3.3V, 100mA)
VGEN6
(1.8 to 3.3V, 200mA)
Bias & References
Parallel MCU Interface Regulator Control
VSNVS
(1.0 to 3.0V, 400uA)
RTC supply with coin cell
charger
MMPF0100 Functional Internal Block Diagram
I2C Communication & Registers
Power Generation
Fault Detection and Protection
DDR Voltage Reference
Current Limit
Short-Circuit
Internal Core Voltage Reference
Thermal
OTP Startup Configuration
Sequence and
timing
OTP Prototyping
(Try before buy) Voltage
Phasing and
Frequency Selection
Analog Integrated Circuit Device Data
Freescale Semiconductor 19
PF0100
General Description
Functional Description
5.3.2.1 Interface Signals
PWRON
PWRON is an input signal to the IC that generates a turn-on event. It can be configured to detect a level, or an edge using the
PWRON_CFG bit. Refer to section Turn On Events for more details.
STANDBY
STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits
standby mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section
Standby Mode for more details.
Note: When operating the PMIC at VIN 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to
provide VSNVS, or the PMIC will not reliably enter and exit the STANDBY mode.
RESETBMCU
RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted
2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal
can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a
turn-off event.
When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults
occurred during start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The
PF0100 is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault
persists, the sequence described above will be repeated. To enter the fault mode, set bit OTP_PG_EN of register
OTP PWRGD EN to “1”. This register, 0xE8, is located on Extended Page 1 of the register map. To test the fault mode, the bit
may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses.
SDWNB
SDWNB is an open-drain, active low output that notifies the processor of an imminent PMIC shut down. It is asserted low for one
32 kHz clock cycle before powering down and is then de-asserted in the OFF state.
INTB
INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB
is de-asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
Analog Integrated Circuit Device Data
20 Freescale Semiconductor
PF0100
Functional Block Requirements and Behaviors
Start-up
6 Functional Block Requirements and Behaviors
6.1 Start-up
The PF0100 can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in
to the device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a
100 kohm resistor. The OTP configuration is enabled by connecting VDDOTP to GND.
For NP devices, selecting the OTP configuration causes the PF0100 to not start-up. However, the PF0100 can be controlled
through the I2C port for prototyping and programming. Once programmed, the NP device will startup with the customer
programmed configuration.
6.1.1 Device Start-up Configuration
Table 10 shows the Default Configuration which can be accessed on all devices as described above, as well as the pre-
programmed OTP configurations.
Table 10. Start-up Configuration
Registers
Default
Configuration Pre-programmed OTP Configuration
All Devices F0 F1(23) F2(23) F3 F4 F6 F9 FA
Default I2C Address 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x80 0x80
VSNVS_VOLT 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V
SW1AB_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V
SW1AB_SEQ 1 1 1 1 2 2 2 5 5
SW1C_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V
SW1C_SEQ 1 2 1 1 2 2 2 5 5
SW2_VOLT 3.0 V 3.3 V 3.15 V 3.15 V 3.15 V 3.15 V 3.3 V 1.375 V 1.375 V
SW2_SEQ 2 5 2 2 1 1 4 5 5
SW3A_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V
SW3A_SEQ 3 3 4 4 4 4 3 6 6
SW3B_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V
SW3B_SEQ 3 3 4 4 4 4 3 6 6
SW4_VOLT 1.8 V 3.15 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.825 V 1.825 V
SW4_SEQ 3 6 3 3 3 3 4 7 7
SWBST_VOLT - 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V
SWBST_SEQ - 13 6 6 6 6 Off 10 10
VREFDDR_SEQ 3 3 4 4 4 4 3 6 6
VGEN1_VOLT - 1.5 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
VGEN1_SEQ - 9 4 4 4 4 5 - -
VGEN2_VOLT 1.5 V 1.5 V - - - - 1.5 V 1.5 V 1.5 V
VGEN2_SEQ 2 10 - - - - Off 8 8
VGEN3_VOLT - 2.5 V - - - - 2.8 V 1.8 V 1.8 V
VGEN3_SEQ - 11 - - - - 5 8 8
Analog Integrated Circuit Device Data
Freescale Semiconductor 21
PF0100
Functional Block Requirements and Behaviors
Start-up
VGEN4_VOLT 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 3.0 V 3.0 V
VGEN4_SEQ 3 7 3 3 3 3 4 4 4
VGEN5_VOLT 2.5 V 2.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5 V 2.5 V
VGEN5_SEQ 3 12 5 5 5 5 5 8 8
VGEN6_VOLT 2.8 V 3.3 V - - - - 3.0 V 2.8 V 2.8 V
VGEN6_SEQ 3 8 - - - - 1 7 7
PU CONFIG,
SEQ_CLK_SPEED 1.0 ms 2.0 ms 1.0 ms 1.0 ms 1.0 ms 1.0 ms 0.5 ms 0.5 ms 0.5 ms
PU CONFIG,
SWDVS_CLK 6.25 mV/s1.5625 mV/
s12.5 mV/s 12.5 mV/s 12.5 mV/s 12.5 mV/s 6.25 mV/s6.25 mV/s 6.25 mV/s
PU CONFIG,
PWRON Level sensitive
SW1AB CONFIG SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz SW1ABC Single
Phase, 2.0 MHz
SW1C CONFIG 2.0 MHz
SW2 CONFIG 2.0 MHz
SW3A CONFIG SW3AB Single Phase, 2.0 MHz
SW3B CONFIG 2.0 MHz
SW4 CONFIG No VTT, 2.0 MHz
PG EN RESETBMCU in Default Mode
Notes
23. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option
instead of the F2 OTP option.
Table 10. Start-up Configuration (continued)
Registers
Default
Configuration Pre-programmed OTP Configuration
All Devices F0 F1(23) F2(23) F3 F4 F6 F9 FA
Analog Integrated Circuit Device Data
22 Freescale Semiconductor
PF0100
Functional Block Requirements and Behaviors
Start-up
Figure 6. Default Start-up Sequence
Table 11. Default Start-up Sequence Timing
Parameter Description Min. Typ. Max. Unit
tD1 Turn-on delay of VSNVS (24) –5.0–ms
tR1 Rise time of VSNVS – 3.0 – ms
tD2 User determined delay – 1.0 – ms
tR2 Rise time of PWRON – (25) –ms
tD3
Turn-on delay of first regulator
SEQ_CLK_SPEED[1:0] = 00 – 2.0 –
ms
SEQ_CLK_SPEED[1:0] = 01(26) –2.5–
SEQ_CLK_SPEED[1:0] = 10 – 4.0 –
SEQ_CLK_SPEED[1:0] = 11 – 7.0 –
*VSNVS will start from 1.0 V if LICELL is valid before VIN.
UVDET
LICELL
VIN
VSNVS
PWRON
SW1A/B
SW1C
SW2
VGEN2
SW3A/B
SW4
VREFDDR
VGEN4
VGEN5
VGEN6
RESETBMCU
td1
td3
td4
td4
tr1
tr3
tr3
tr3
td5tr4
tr2
td2
1V