Freescale Semiconductor Advance Information Document Number: MMPF0100 Rev. 12.0, 9/2015 14 Channel Configurable Power Management Integrated Circuit The PF0100 SMARTMOS Power Management Integrated Circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With up to six buck converters, six linear regulators, RTC supply, and coin-cell charger, the PF0100 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip One Time Programmable (OTP) memory, the PF0100 is available in preprogrammed standard versions, or non-programmed to support custom programming. The PF0100 is defined to power an entire embedded MCU platform solution such as i.MX 6 based eReader, IPTV, medical monitoring, and home/factory automation. Features: * Four to six buck converters, depending on configuration * Single/Dual phase/ parallel options * DDR termination tracking mode option * Boost regulator to 5.0 V output * Six general purpose linear regulators * Programmable output voltage, sequence, and timing * OTP (One Time Programmable) memory for device configuration * Coin cell charger and RTC supply * DDR termination reference voltage * Power control logic with processor interface and event detection * I2C control * Individually programmable ON, OFF, and Standby modes PF0100 PF0100 POWER MANAGEMENT EP SUFFIX (E-TYPE) 98ASA00405D 56 QFN 8X8 ES SUFFIX (WF-TYPE) 98ASA00589D 56 QFN 8X8 Applications: * Tablets * IPTV * eReaders * Set Top Boxes * Industrial control * Medical monitoring * Home automation/ alarm/ energy management i.MX 6X VREFDDR SW4 1000 mA DDR MEMORY INTERFACE DDR Memory SW3A/B 2500 mA SW1A/B 2500 mA Processor Core Voltages SW1C 2000 mA SW2 2000 mA SWBST 600 mA SD-MMC/ NAND Mem. SATA HDD Control Signals Parallel control/GPIOS I2 C Communication I2C Communication VGEN1 100 mA VGEN2 250 mA VGEN3 100 mA VGEN4 350 mA Camera COINCELL Audio Codec Sensors Camera HDMI LDVS Display USB Ethernet CAN VGEN6 200 mA Main Supply 2.8 - 4.5 V External AMP Microphones Speakers GPS MIPI uPCIe WAM GPS MIPI VGEN5 100 mA LICELL Charger SATA - FLASH NAND - NOR Interfaces Cluster/HUD Front USB POD Rear Seat Infotaiment Figure 1. Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2012-2015. All rights reserved. Rear USB POD Table of Contents 1 2 3 4 5 6 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2.1 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.1 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.2 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional Block Requirements and Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.1 Device Start-up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.2 One Time Programmability (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.3 OTP Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.4 Reading OTP Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.5 Programming OTP Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 16 MHz and 32 kHz Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.1 Clock adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 Bias and References Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.1 Internal Core Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.2 VREFDDR Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.2 State Machine Flow Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4.3 Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.4 Buck Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4.5 Boost Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.6 LDO Regulators Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.4.7 VSNVS LDO/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.5 Control Interface I2C Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.5.1 I2C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.5.2 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.5.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.5.4 Interrupt Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.5.5 Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.5.6 Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 PF0100 2 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 PF0100 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 General Board Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 General Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 Parallel Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 Switching Regulator Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Rating Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Estimation of Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Packaging Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 133 133 134 138 138 138 138 139 140 141 141 141 142 142 149 149 150 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 3 Orderable Parts 1 Orderable Parts The PF0100 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device uses "NP" as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list the associated Freescale reference designs where applicable. Details of the OTP programming for each device can be found in Table 10. Table 1. Orderable Part Variations Part Number Temperature (TA) Package Programming Reference Designs MMPF0100NPEP NP N/A MMPF0100F0EP F0 MCIMX6Q-SDP MCIMX6Q-SDB MCIMX6DL-SDP MMPF0100F1EP F1 MCIMX6SLEVK MMPF0100F2EP F2 N/A MMPF0100NPAEP NP N/A MMPF0100F0AEP F0 MCIMX6Q-SDP MCIMX6Q-SDB MCIMX6DL-SDP F1 MCIMX6SLEVK F2 N/A MMPF0100F3AEP F3 N/A MMPF0100F4AEP F4 N/A MMPF0100F6AEP F6 MCIMX6SX-SDB MMPF0100NPANES NP N/A MMPF0100F0ANES F0 MCIMX6Q-SDP MCIMX6Q-SDB MCIMX6DL-SDP MMPF0100F1AEP -40 to 85 C -40 to 85 C MMPF0100F2AEP MMPF0100F3ANES 56 QFN 8x8 mm - 0.5 mm pitch E-Type QFN (full lead) 56 QFN 8x8 mm - 0.5 mm pitch E-Type QFN (full lead) F3 N/A F4 N/A MMPF0100F6ANES F6 MCIMX6SX-SDB MMPF0100F9ANES F9 N/A MMPF0100FAANES FA N/A MMPF0100F4ANES -40 to 105 C 56 QFN 8x8 mm - 0.5 mm pitch WF-Type QFN (wettable flank) Qualification Tier Notes (1), (2) Consumer and Industrial (1), (2), (3) (1), (2) Consumer (1), (2), (3) (1), (2) Extended Industrial Notes 1. For Tape and Reel, add an R2 suffix to the part number. 2. For programming details see Table 10. The available OTP options are not restricted to the listed reference designs. They can be used in any application where the listed voltage and sequence details are acceptable. 3. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of the F2 OTP option. PF0100 4 Analog Integrated Circuit Device Data Freescale Semiconductor Orderable Parts PF0100 Version Differences 1.1 PF0100 Version Differences PF0100A is an improved version of the PF0100 Power Management IC. Table 2 summarizes the difference between the two versions and should be referred to when migrating from the PF0100 to the PF0100A. Note that programming options are the same for both versions of the device. Table 2. Differences between PF0100 and PF0100A Description PF0100 Version identification Reading SILICON REV register at address 0x03 will return 0x11. DEVICEID register at address 0x00 will read 0x10 in PF0100 and PF0100A VSNVS current limit VSNVS current limit increased in the PF0100A In the PF0100, FUSE_POR1, FUSE_POR2, and FUSE_POR3 bits are XOR'ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR OTP_FUSE_PORx register setting during OTP bit has to be 1 for fuses to be loaded during programming startup. This can be achieved by setting any one or all of the FUSE_PORx bits during OTP programming. PF0100A Reading SILICON REV register at address 0x03 will return 0x21. DEVICEID register at address 0x00 will read 0x10 in PF0100 and PF0100A In the PF0100A, the XOR function is removed. It is required to set FUSE_POR1, FUSE_POR2, and FUSE_POR3 bits during OTP programming. Errata ER19 fixed in PF0100A. External workaround not required Erratum ER19 Erratum ER19 applicable to PF0100. Applications expecting to operate in the conditions mentioned in ER19 need to implement an external workaround to overcome the problem. Refer to the product errata for details Erratum ER20 Erratum ER20 applicable to PF0100 Errata ER20 fixed in PF0100A Erratum ER22 Erratum ER22 applicable to PF0100 Errata ER22 fixed in PF0100A. Workaround not required In addition to the version differences, Table 3 shows the differences on the test temperature rating for each version of PF0100 covered on this datasheet. Table 3. Ambient Temperature Range Device Qualification Tier Ambient Temperature range (TMIN to TMAX) MMPF0100 Consumer and Industrial TA = -40 to 85 C MMPF0100A Consumer TA = -40 to 85 C MMPF0100AN Extended Industrial TA = -40 to 105 C PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 5 Internal Block Diagram PF0100 Version Differences 2 Internal Block Diagram PF0100 VGEN1 100 mA VIN1 VGEN1 SW1FB SW1A/B Single/Dual 2500 mA Buck VGEN2 250 mA VGEN2 VIN2 VGEN3 VGEN3 100 mA VGEN4 VGEN4 350 mA SW1C 2000 mA Buck O/P Drive O/P Drive SW1BLX O/P Drive SW1CLX Initialization State Machine SW2 2000 mA Buck VGEN6 200 mA VGEN6 SW1CIN SW1VSSSNS VGEN5 100 mA VGEN5 SW1BIN SW1CFB Core Control logic VIN3 SW1AIN SW1ALX O/P Drive SW2LX SW2IN SW2IN SW2FB Supplies Control OTP SW3AFB VDDOTP CONTROL I2C Interface VDDIO SCL SDA SW3A/B Single/Dual DDR 2500 mA Buck O/P Drive O/P Drive DVS CONTROL SW3AIN SW3ALX SW3BLX SW3BIN SW3BFB DVS Control SW3VSSSNS SW4FB I2C Register map VCOREDIG VCOREREF Trim-In-Package O/P Drive SW4IN SW4LX GNDREF1 Reference Generation VCORE SW4 1000 mA Buck Clocks and resets SWBST 600 mA Boost O/P Drive SWBSTLX SWBSTIN GNDREF SWBSTFB VREFDDR VINREFDDR Clocks 32 kHz and 16 MHz VHALF VIN Li Cell Charger Best of Supply LICELL INTB SDWNB STANDBY RESETBMCU ICTEST PWRON VSNVS VSNVS Figure 2. Simplified Internal Block Diagram PF0100 6 Analog Integrated Circuit Device Data Freescale Semiconductor Pin Connections Pinout Diagram SDA VCOREREF VCOREDIG VIN VCORE GNDREF VDDOTP SWBSTLX SWBSTIN SWBSTFB VSNVS Pinout Diagram SCL 3.1 VDDIO Pin Connections PWRON 3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 INTB 1 42 LICELL SDWNB 2 41 VGEN6 RESETBMCU 3 40 VIN3 STANDBY 4 39 VGEN5 ICTEST 5 38 SW3AFB SW1FB 6 37 SW3AIN SW1AIN 7 36 SW3ALX SW1ALX 8 35 SW3BLX SW1BLX 9 34 SW3BIN SW1BIN 10 33 SW3BFB SW1CLX 11 32 SW3VSSSNS SW1CIN 12 31 VREFDDR SW1CFB 13 30 VINREFDDR SW1VSSSNS 14 29 VHALF 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GNDREF1 VGEN1 VIN1 VGEN2 SW4FB SW4IN SW4LX SW2LX SW2IN SW2IN SW2FB VGEN3 VIN2 VGEN4 EP Figure 3. Pinout Diagram PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Pin Connections Pin Definitions 3.2 Pin Definitions Table 4. PF0100 Pin Definitions Pin Number Pin Name Pin Function Max Rating Type 1 INTB O 3.6 V Digital Open drain interrupt signal to processor 2 SDWNB O 3.6 V Digital Open drain signal to indicate an imminent system shutdown 3 RESETBMCU O 3.6 V Digital Open drain reset output to processor. Alternatively can be used as a Power Good output. 4 STANDBY I 3.6 V Digital Standby input signal from processor 5 ICTEST I 7.5 V Digital/ Analog Reserved pin. Connect to GND in application. 6 SW1FB (5) I 3.6 V Analog Output voltage feedback for SW1A/B. Route this trace separately from the high current path and terminate at the output capacitance. 7 SW1AIN (5) I 4.8 V Analog Input to SW1A regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 8 SW1ALX (5) O 4.8 V Analog Regulator 1A switch node connection 9 SW1BLX (5) O 4.8 V Analog Regulator 1B switch node connection 10 SW1BIN (5) I 4.8 V Analog Input to SW1B regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 11 SW1CLX (5) O 4.8 V Analog Regulator 1C switch node connection 12 SW1CIN (5) I 4.8 V Analog Input to SW1C regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 13 SW1CFB (5) I 3.6V Analog Output voltage feedback for SW1C. Route this trace separately from the high current path and terminate at the output capacitance. 14 SW1VSSSNS GND - GND Ground reference for regulators SW1ABC. It is connected externally to GNDREF through a board ground plane. 15 GNDREF1 GND - GND Ground reference for regulators SW2 and SW4. It is connected externally to GNDREF, via board ground plane. 16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 F ceramic output capacitor. 17 VIN1 I 3.6 V Analog VGEN1, 2 input supply. Bypass with a 1.0 F decoupling capacitor as close to the pin as possible. 18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 F ceramic output capacitor. 19 SW4FB (5) I 3.6 V Analog Output voltage feedback for SW4. Route this trace separately from the high current path and terminate at the output capacitance. 20 SW4IN (5) I 4.8 V Analog Input to SW4 regulator. Bypass with at least a 4.7F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 21 SW4LX (5) O 4.8 V Analog Regulator 4 switch node connection 22 (5) O 4.8 V Analog Regulator 2 switch node connection SW2LX Definition PF0100 8 Analog Integrated Circuit Device Data Freescale Semiconductor Pin Connections Pin Definitions Table 4. PF0100 Pin Definitions (continued) Pin Number Pin Name Pin Function Max Rating Type Definition 23 SW2IN (5) I 4.8 V Analog 24 SW2IN (5) I 4.8 V Analog Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to these pins as possible. 25 SW2FB (5) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high current path and terminate at the output capacitance. 26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 F ceramic output capacitor. 27 VIN2 I 3.6 V Analog VGEN3,4 input. Bypass with a 1.0 F decoupling capacitor as close to the pin as possible. 28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 F ceramic output capacitor. 29 VHALF I 3.6 V Analog Half supply reference for VREFDDR 30 VINREFDDR I 3.6 V Analog VREFDDR regulator input. Bypass with at least 1.0 F decoupling capacitor as close to the pin as possible. 31 VREFDDR O 3.6 V Analog VREFDDR regulator output 32 SW3VSSSNS GND - GND Ground reference for the SW3 regulator. Connect to GNDREF externally via the board ground plane. 33 SW3BFB (5) I 3.6 V Analog Output voltage feedback for SW3B. Route this trace separately from the high current path and terminate at the output capacitance. 34 SW3BIN (5) I 4.8 V Analog Input to SW3B regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 35 SW3BLX (5) O 4.8 V Analog Regulator 3B switch node connection 36 SW3ALX (5) O 4.8 V Analog Regulator 3A switch node connection 37 SW3AIN (5) I 4.8 V Analog Input to SW3A regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 38 SW3AFB (5) I 3.6 V Analog Output voltage feedback for SW3A. Route this trace separately from the high current path and terminate at the output capacitance. 39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 F ceramic output capacitor. 40 VIN3 I 4.8 V Analog VGEN5, 6 input. Bypass with a 1.0 F decoupling capacitor as close to the pin as possible. 41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 F ceramic output capacitor. 42 LICELL I/O 3.6 V Analog Coin cell supply input/output 43 VSNVS O 3.6 V Analog LDO or coin cell output to processor 44 SWBSTFB (5) I 5.5 V Analog Boost regulator feedback. Connect this pin to the output rail close to the load. Keep this trace away from other noisy traces and planes. 45 SWBSTIN (5) I 4.8 V Analog Input to SWBST regulator. Bypass with at least a 2.2 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 46 SWBSTLX (5) O 7.5 V Analog SWBST switch node connection PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Pin Connections Pin Definitions Table 4. PF0100 Pin Definitions (continued) Pin Number Pin Name Pin Function Max Rating Type 47 VDDOTP I 10 V(4) Digital & Analog 48 GNDREF GND - GND 49 VCORE O 3.6 V Analog Analog Core supply 50 VIN I 4.8 V Analog Main chip supply 51 VCOREDIG O 1.5 V Analog Digital Core supply 52 VCOREREF O 1.5 V Analog Main band gap reference 53 SDA I/O 3.6 V Digital I2C data line (Open drain) 54 SCL I 3.6 V Digital I2C clock 55 VDDIO I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 F ceramic capacitor 56 PWRON I 3.6 V Digital Power On/off from processor - EP GND - GND Expose pad. Functions as ground return for buck regulators. Tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. Definition Supply to program OTP fuses Ground reference for the main band gap regulator. Notes 4. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise. 5. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected to VIN with a 0.1 F bypass capacitor. PF0100 10 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics Absolute Maximum Ratings 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 5. Absolute Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section. Symbol Description Value Unit Main input supply voltage -0.3 to 4.8 V VDDOTP OTP programming input supply voltage -0.3 to 10 V VLICELL Coin cell voltage -0.3 to 3.6 V 2000 500 V ELECTRICAL RATINGS VIN VESD ESD Ratings Human Body Model(6) Charge Device Model(6) Notes 6. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 11 General Product Characteristics Thermal Characteristics 4.2 Thermal Characteristics Table 6. Thermal Ratings Symbol Description (Rating) Min. Max. Unit TA Ambient Operating Temperature Range PF0100 PF0100A PF0100AN -40 -40 -40 85 85 105 TJ Operating Junction Temperature Range (7) -40 125 C Storage Temperature Range -65 150 C - Note 9 C Junction to Ambient (10)(11)(12) Natural Convection Four layer board (2s2p) Eight layer board (2s6p) - - 28 15 Junction to Ambient (@200 ft/min)(10)(12) Four layer board (2s2p) - 22 Junction to Board(13) - 10 C/W - 1.2 C/W - 2.0 C/W THERMAL RATINGS TST TPPRT Peak Package Reflow Temperature (8)(9) C QFN56 THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS RJA RJMA RJB RJCBOTTOM JT Junction to Case Bottom(14) Junction to Package Top Natural Convection (15) C/W C/W Notes 7. Do not operate beyond 125 C for extended periods of time. Operation above 150 C may cause permanent damage to the IC. See Table 7 for thermal protection features. 8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 9. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 10. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 11. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. 12. Per JEDEC JESD51-6 with the board horizontal. 13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 14. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 15. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. PF0100 12 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics Electrical Characteristics 4.2.1 Power Dissipation During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 6. To optimize the thermal management and to avoid overheating, the PF0100 provides thermal protection. An internal comparator monitors the die temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds specified in Table 7 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register INTSENSE0. In the event of excessive power dissipation, thermal protection circuitry will shut down the PF0100. This thermal protection will act above the thermal protection threshold listed in Table 7. To avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured such that this protection is not tripped under normal conditions. Table 7. Thermal Protection Thresholds Parameter Min. Typ. Max. Units Thermal 110 C Threshold (THERM110) 100 110 120 C Thermal 120 C Threshold (THERM120) 110 120 130 C Thermal 125 C Threshold (THERM125) 115 125 135 C Thermal 130 C Threshold (THERM130) 120 130 140 C Thermal Warning Hysteresis 2.0 - 4.0 C Thermal Protection Threshold 130 140 150 C 4.3 Electrical Characteristics 4.3.1 General Specifications Table 8. General PMIC Static Characteristics. TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current range, unless otherwise noted. Pin Name PWRON RESETBMCU SCL SDA INTB SDWNB Parameter Load Condition Min. Max. Unit VIL - 0.0 0.2 * VSNVS V VIH - 0.8 * VSNVS 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VIL - 0.0 0.2 * VDDIO V VIH - 0.8 * VDDIO 3.6 V VIL - 0.0 0.2 * VDDIO V VIH - 0.8 * VDDIO 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7*VDDIO VDDIO V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 13 General Product Characteristics Electrical Characteristics Table 8. General PMIC Static Characteristics. TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current range, unless otherwise noted. STANDBY VDDOTP VIL - 0.0 0.2 * VSNVS V VIH - 0.8 * VSNVS 3.6 V VIL - 0.0 0.3 V VIH - 1.1 1.7 V PF0100 14 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics Electrical Characteristics 4.3.2 Current Consumption Table 9. Current Consumption Summary TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 to 3.6 V, LICELL = 1.8 to 3.3 V, VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 C, unless otherwise noted. Mode PF0100 Conditions System Conditions Typical MAX Unit (16),(18),(22) VSNVS from LICELL All other blocks off VIN = 0.0 V VSNVSVOLT[2:0] = 110 No load on VSNVS 4.0 7.0 A Off (17),(18) MMPF0100 VSNVS from VIN or LICELL Wake-up from PWRON active 32 k RC on All other blocks off VIN UVDET No load on VSNVS, PMIC able to wake-up 16 21 A Off MMPF0100A VSNVS from VIN or LICELL Wake-up from PWRON active 32 k RC on All other blocks off VIN UVDET No load on VSNVS, PMIC able to wake-up 17 25 A Sleep (18) VSNVS from VIN Wake-up from PWRON active Trimmed reference active SW3A/B PFM Trimmed 16 MHz RC off 32 k RC on VREFDDR disabled No load on VSNVS. DDR memories in self refresh 122 220(21) 122 250(20) VSNVS from either VIN or LICELL SW1A/B combined in PFM SW1C in PFM SW2 in PFM SW3A/B combined in PFM SW4 in PFM SWBST off Trimmed 16 MHz RC enabled Trimmed reference active VGEN1-6 enabled VREFDDR enabled No load on VSNVS. Processor enabled in low power mode. All rails powered on except boost (load = 0 mA) 297 450 (19) 297 1000 (21) Coin Cell (17),(18) Standby (18) MMPF0100 A A PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 15 General Product Characteristics Electrical Characteristics Table 9. Current Consumption Summary (continued) TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 to 3.6 V, LICELL = 1.8 to 3.3 V, VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 C, unless otherwise noted. Mode Standby (18) MMPF0100A Notes 16. 17. 18. 19. 20. 21. 22. PF0100 Conditions VSNVS from either VIN or LICELL SW1A/B combined in PFM SW1C in PFM SW2 in PFM SW3A/B combined in PFM SW4 in PFM SWBST off Trimmed 16 MHz RC enabled Trimmed reference active VGEN1-6 enabled VREFDDR enabled System Conditions Typical MAX No load on VSNVS. Processor enabled in low power mode. All rails powered on except boost (load = 0 mA) 297 450 (21) 297 550(20) Unit A Refer to Figure 4 for Coin Cell mode characteristics over temperature. When VIN is below the UVDET threshold, in the range of 1.8 V VIN < 2.65 V, the quiescent current increases by 50 A, typically. For PFM operation, headroom should be 300 mV or greater. From 0 C to 85 C From -40 C to 105 C, Applicable only to Extended Industrial parts. From -40 C to 85 C, Applicable to Consumer, Industrial and Extended Industrial part numbers. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN. The additional current is <30A with a pull up resistor of 100k. The i.MX 6x processors have an internal pull up from the POR_B pin to the VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use an external switch to disconnect the RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull up RESETBMCU to a rail that is off in the coin cell mode. Coin Cell mode current (uA) Coin Cell Mode 100 MMPF0100 10 MMPF0100A 1 40 20 0 20 40 60 80 Temperature (C) Temperature (oC) Figure 4. Coin cell Mode Current Vs Temperature PF0100 16 Analog Integrated Circuit Device Data Freescale Semiconductor General Description Features 5 General Description The PF0100 is the Power Management Integrated Circuit (PMIC) designed primarily for use with Freescale's i.MX 6 series of application processors. 5.1 Features This section summarizes the PF0100 features. * Input voltage range to PMIC: 2.8 - 4.5 V * Buck regulators * Four to six channel configurable * SW1A/B/C, 4.5 A (single); 0.3 to 1.875 V * SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 to 1.875 V * SW2, 2.0 A; 0.4 to 3.3 V * SW3A/B, 2.5 A (single/dual); 0.4 to 3.3 V * SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V * SW4, 1.0 A; 0.4 to 3.3 V * SW4, VTT mode provide DDR termination at 50% of SW3A * Dynamic voltage scaling * Modes: PWM, PFM, APS * Programmable output voltage * Programmable current limit * Programmable soft start * Programmable PWM switching frequency * Programmable OCP with fault interrupt * Boost regulator * SWBST, 5.0 to 5.15 V, 0.6 A, OTG support * Modes: PFM and Auto * OCP fault interrupt * LDOs * Six user programable LDO * VGEN1, 0.80 to 1.55 V, 100 mA * VGEN2, 0.80 to 1.55 V, 250 mA * VGEN3, 1.8 to 3.3 V, 100 mA * VGEN4, 1.8 to 3.3 V, 350 mA * VGEN5, 1.8 to 3.3 V, 100 mA * VGEN6, 1.8 to 3.3 V, 200 mA * Soft start * LDO/Switch supply * VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 A * DDR memory reference voltage * VREFDDR, 0.6 to 0.9 V, 10 mA * 16 MHz internal master clock * OTP(One time programmable) memory for device configuration * User programmable start-up sequence and timing * Battery backed memory including coin cell charger * I2C interface * User programmable Standby, Sleep, and Off modes PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 17 General Description Functional Block Diagram 5.2 Functional Block Diagram MMPF0100 Functional Internal Block Diagram OTP Startup Configuration OTP Prototyping (Try before buy) Sequence and timing Power Generation Voltage Switching Regulators Phasing and Frequency Selection SW1A/B/C (0.3 to 1.875V) Configurable 4.5A or 2.5A+2.0A Bias & References Internal Core Voltage Reference SW2 (0.4 to 3.3V, 2A) DDR Voltage Reference Logic and Control Parallel MCU Interface Regulator Control I2C Communication & Registers Linear Regulators VGEN1 (0.8 to 1.55V, 100mA) VGEN2 (0.8 to 1.55V, 250mA) VGEN3 (1.8 to 3.3V, 100mA) SW3A/B (0.4 to 3.3V) Configurable 2.5A or 1.25A+1.25A VGEN4 (1.8 to 3.3V, 350mA) SW4 (0.4 to 3.3V, 1A) VGEN6 (1.8 to 3.3V, 200mA) Boost Regulator (5 to 5.15V, 600mA) USB OTG Supply VSNVS (1.0 to 3.0V, 400uA) RTC supply with coin cell charger VGEN5 (1.8 to 3.3V, 100mA) Fault Detection and Protection Thermal Current Limit Short-Circuit Figure 5. Functional Block Diagram 5.3 Functional Description 5.3.1 Power Generation The PF0100 PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices. The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further, SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for the processor cores and/or other circuitry. Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be powered from VIN, or from a coin cell. 5.3.2 Control Logic The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Startup section, or by configuring the "Try Before Buy" feature to test different power up sequences before choosing the final OTP configuration. The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger for the coin cell is included as well. PF0100 18 Analog Integrated Circuit Device Data Freescale Semiconductor General Description Functional Description 5.3.2.1 Interface Signals PWRON PWRON is an input signal to the IC that generates a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG bit. Refer to section Turn On Events for more details. STANDBY STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section Standby Mode for more details. Note: When operating the PMIC at VIN 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide VSNVS, or the PMIC will not reliably enter and exit the STANDBY mode. RESETBMCU RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100 is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described above will be repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to "1". This register, 0xE8, is located on Extended Page 1 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses. SDWNB SDWNB is an open-drain, active low output that notifies the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock cycle before powering down and is then de-asserted in the OFF state. INTB INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is de-asserted after the fault interrupt is cleared by software, which requires writing a "1" to the fault interrupt bit. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 19 Functional Block Requirements and Behaviors Start-up 6 Functional Block Requirements and Behaviors 6.1 Start-up The PF0100 can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kohm resistor. The OTP configuration is enabled by connecting VDDOTP to GND. For NP devices, selecting the OTP configuration causes the PF0100 to not start-up. However, the PF0100 can be controlled through the I2C port for prototyping and programming. Once programmed, the NP device will startup with the customer programmed configuration. 6.1.1 Device Start-up Configuration Table 10 shows the Default Configuration which can be accessed on all devices as described above, as well as the preprogrammed OTP configurations. Table 10. Start-up Configuration Registers Default Configuration Pre-programmed OTP Configuration All Devices F0 F1(23) F2(23) F3 F4 F6 F9 FA Default I C Address 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x80 0x80 VSNVS_VOLT 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V SW1AB_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V SW1AB_SEQ 1 1 1 1 2 2 2 5 5 SW1C_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V SW1C_SEQ 1 2 1 1 2 2 2 5 5 SW2_VOLT 3.0 V 3.3 V 3.15 V 3.15 V 3.15 V 3.15 V 3.3 V 1.375 V 1.375 V SW2_SEQ 2 5 2 2 1 1 4 5 5 SW3A_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V SW3A_SEQ 3 3 4 4 4 4 3 6 6 SW3B_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V SW3B_SEQ 3 3 4 4 4 4 3 6 6 SW4_VOLT 1.8 V 3.15 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.825 V 1.825 V SW4_SEQ 3 6 3 3 3 3 4 7 7 SWBST_VOLT - 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V SWBST_SEQ - 13 6 6 6 6 Off 10 10 VREFDDR_SEQ 3 3 4 4 4 4 3 6 6 VGEN1_VOLT - 1.5 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V VGEN1_SEQ - 9 4 4 4 4 5 - - VGEN2_VOLT 1.5 V 1.5 V - - - - 1.5 V 1.5 V 1.5 V VGEN2_SEQ 2 10 - - - - Off 8 8 VGEN3_VOLT - 2.5 V - - - - 2.8 V 1.8 V 1.8 V VGEN3_SEQ - 11 - - - - 5 8 8 2 PF0100 20 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Start-up Table 10. Start-up Configuration (continued) Registers Default Configuration Pre-programmed OTP Configuration All Devices F0 F1(23) F2(23) F3 F4 F6 F9 FA VGEN4_VOLT 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 3.0 V 3.0 V VGEN4_SEQ 3 7 3 3 3 3 4 4 4 VGEN5_VOLT 2.5 V 2.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5 V 2.5 V VGEN5_SEQ 3 12 5 5 5 5 5 8 8 VGEN6_VOLT 2.8 V 3.3 V - - - - 3.0 V 2.8 V 2.8 V VGEN6_SEQ 3 8 - - - - 1 7 7 1.0 ms 2.0 ms 1.0 ms 1.0 ms 1.0 ms 1.0 ms 0.5 ms 0.5 ms 0.5 ms PU CONFIG, SEQ_CLK_SPEED PU CONFIG, SWDVS_CLK 6.25 mV/s 1.5625 mV/ 12.5 mV/s 12.5 mV/s 12.5 mV/s 12.5 mV/s 6.25 mV/s 6.25 mV/s 6.25 mV/s s PU CONFIG, PWRON SW1AB CONFIG Level sensitive SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz SW1C CONFIG 2.0 MHz SW2 CONFIG 2.0 MHz SW3A CONFIG SW3AB Single Phase, 2.0 MHz SW3B CONFIG 2.0 MHz SW4 CONFIG PG EN SW1ABC Single Phase, 2.0 MHz No VTT, 2.0 MHz RESETBMCU in Default Mode Notes 23. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of the F2 OTP option. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 21 Functional Block Requirements and Behaviors Start-up LICELL UVDET VIN td1 tr1 1V td2 VSNVS tr2 td3 PWRON tr3 SW1A/B SW1C td4 tr3 SW2 VGEN2 td4 tr3 SW3A/B SW4 VREFDDR VGEN4 VGEN5 td5 VGEN6 tr4 RESETBMCU *VSNVS will start from 1.0 V if LICELL is valid before VIN. Figure 6. Default Start-up Sequence Table 11. Default Start-up Sequence Timing Parameter Description Min. Typ. Max. Unit tD1 Turn-on delay of VSNVS (24) - 5.0 - ms tR1 Rise time of VSNVS - 3.0 - ms tD2 User determined delay - 1.0 - ms tR2 Rise time of PWRON - (25) - ms SEQ_CLK_SPEED[1:0] = 00 - 2.0 - SEQ_CLK_SPEED[1:0] = 01(26) - 2.5 - SEQ_CLK_SPEED[1:0] = 10 - 4.0 - SEQ_CLK_SPEED[1:0] = 11 - 7.0 - Turn-on delay of first regulator tD3 ms PF0100 22 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Start-up Table 11. Default Start-up Sequence Timing (continued) Parameter tR3 Description Min. Typ. Max. Unit - 0.2 - ms SEQ_CLK_SPEED[1:0] = 00 - 0.5 - SEQ_CLK_SPEED[1:0] = 01 - 1.0 - SEQ_CLK_SPEED[1:0] = 10 - 2.0 - SEQ_CLK_SPEED[1:0] = 11 - 4.0 - Rise time of regulators (27) Delay between regulators tD4 ms tR4 Rise time of RESETBMCU - 0.2 - ms tD5 Turn-on delay of RESETBMCU - 2.0 - ms Notes 24. Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may extend to a maximum of 24 ms. 25. Depends on the external signal driving PWRON. 26. Default configuration. 27. Rise time is a function of slew rate of regulators and nominal voltage selected. 6.1.2 One Time Programmability (OTP) OTP allows the programming of start-up configurations for a variety of applications. Before permanently programming the IC by programming fuses, a configuration may be prototyped by using the "Try Before Buy" (TBB) feature. Further, an error correction code(ECC) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. The parameters that can be configured by OTP are listed below. * General: I2C slave address, PWRON pin configuration, start-up sequence and timing * Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching frequency, and soft start ramp rate * Boost regulator and LDOs: Output voltage NOTE: When prototyping or programming fuses, the user must ensure that register settings are consistent with the hardware configuration. This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single/dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it will be gated by the buck regulator in the start-up sequence. 6.1.2.1 Start-up Sequence and Timing Each regulator has 5-bits allocated to program its start-up time slot from a turn on event; therefore, each can be placed from position one to thirty-one in the start-up sequence. The all zeros code indicates that a regulator is not part of the start-up sequence and will remain off. See Table 12. The delay between each position is equal; however, four delay options are available. See Table 13. The start-up sequence will terminate at the last programmed regulator. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 23 Functional Block Requirements and Behaviors Start-up Table 12. Start-up Sequence SWxx_SEQ[4:0]/ VGENx_SEQ[4:0]/ VREFDDR_SEQ[4:0] Sequence 00000 Off 00001 SEQ_CLK_SPEED[1:0] * 1 00010 SEQ_CLK_SPEED[1:0] * 2 * * * * * * * * 11111 SEQ_CLK_SPEED[1:0] * 31 Table 13. Start-up Sequence Clock Speed 6.1.2.2 SEQ_CLK_SPEED[1:0] Time (s) 00 500 01 1000 10 2000 11 4000 PWRON Pin Configuration The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input (PWRON_CFG = 1). As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into Sleep mode. As an edge sensitive input, such as when connected to a mechanical switch, a falling edge will turn on the part and if the switch is held low for greater than or equal to 4.0 seconds, the part will turn off or enter Sleep mode. Table 14. PWRON Configuration PWRON_CFG 6.1.2.3 Mode 0 PWRON pin HIGH = ON PWRON pin LOW = OFF or Sleep mode 1 PWRON pin pulled LOW momentarily = ON PWRON pin LOW for 4.0 seconds = OFF or Sleep mode I2C Address Configuration The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts. Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to "1" while the lower three LSBs of the I2C address (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 15. Table 15. I2C Address Configuration I2C_SLV_ADDR[3] Hard Coded I2C_SLV_ADDR[2:0] I2C Device Address (Hex) 1 000 0x08 1 001 0x09 1 010 0x0A PF0100 24 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Start-up Table 15. I2C Address Configuration (continued) 6.1.2.4 I2C_SLV_ADDR[3] Hard Coded I2C_SLV_ADDR[2:0] I2C Device Address (Hex) 1 011 0x0B 1 100 0x0C 1 101 0x0D 1 110 0x0E 1 111 0x0F Soft Start Ramp Rate The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in Dynamic Voltage Scaling. 6.1.3 OTP Prototyping Before permanently programming fuses, it is possible to test the desired configuration by using the "Try Before Buy" feature. With this feature, the configuration is loaded from the OTP registers. These registers merely serve as temporary storage for the values to be written to the fuses, for the values read from the fuses, or for the values read from the default configuration. To avoid confusion, these registers will be referred to as the TBBOTP registers. The portion of the register map that concerns OTP is shown in Table 137 and Table 138. The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied. The values that are then loaded into the TBBOTP registers depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR_XOR bits. Refer to Table 16. * If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration. * If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1, the values are loaded from the fuses. In the MMPF0100, FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR'ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In the MMPF0100A, the XOR function is removed. It is required to set all of the FUSE_PORx bits to be able to load the fuses. * If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 0, the TBBOTP registers remain initialized at zero. The initial value of TBB_POR is always "0"; only when VDDOTP = 0.0 V and TBB_POR is set to "1" are the values from the TBBOTP registers maintained and not loaded from a different source. The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 1 and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping. 6.1.4 Reading OTP Fuses As described in the previous section, the contents of the fuses are loaded to the TBBOTP registers when the following conditions are met; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1. If ECC were enabled at the time the fuses were programmed, the error corrected values can be loaded into the TBBOTP registers if desired. Once the fuses are loaded and a turn-on event occurs, the PMIC will power on with the configuration programmed in the fuses. For more details on reading the OTP fuses, see application note AN4536. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 25 Functional Block Requirements and Behaviors 16 MHz and 32 kHz Clocks 6.1.5 Programming OTP Fuses The parameters that can be programmed are shown in the TBBOTP registers in the Extended Page 1 of the register map. The PF0100 offers ECC, the control registers for which functions are located in Extended Page 2 of the register map. There are ten banks of twenty-six fuses each that can be programmed. Programming the fuses requires an 8.25 V, 100 mA supply powering the VDDOTP pin, bypassed with 10 to 20 F of capacitance. For more details on programming the OTP fuses, see application note AN4536. Table 16. Source of Start-up Sequence 6.2 VDDOTP(V) TBB_POR FUSE_POR_XOR Start-up Sequence 0 0 0 None 0 0 1 OTP fuses 0 1 x TBBOTP registers 1.5 x x Factory defined 16 MHz and 32 kHz Clocks There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within -8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions: * VIN < UVDET * All regulators are in SLEEP mode * All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions: * During start-up, VIN > UVDET * PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 27 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock. Table 17. 16 MHz Clock Specifications TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, LICELL = 1.8 to 3.3 V and typical external component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 C, unless otherwise noted. Parameters Operating Voltage From VIN 16 MHz Clock Frequency 2.0 MHz Clock Frequency (28) Symbol Min. Typ. Max. Units VIN16MHz 2.8 - 4.5 V f16MHZ 14.7 16 17.2 MHz f2MHZ 1.84 - 2.15 MHz Notes 28. 2.0 MHz clock is derived from the 16 MHz clock. 6.2.1 Clock adjustment The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By changing the factory trim values of the 16MHz clock, the user may add an offset as small as 3.0% of the nominal frequency. Contact your Freescale representative for detailed information on this feature. PF0100 26 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Bias and References Block Description 6.3 Bias and References Block Description 6.3.1 Internal Core Voltage References All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a valid supply and/or valid coin cell. Table 18 shows the main characteristics of the core circuitry. Table 18. Core Voltages Electrical Specifications(30) TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, LICELL = 1.8 to 3.3 V, and typical external component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 C, unless otherwise noted. Parameters Symbol Min. Typ. Max. Units VCOREDIG - - 1.5 1.3 - - V VCORE - - 2.775 0.0 - - V Output Voltage(29) VCOREREF - 1.2 - V Absolute Accuracy VCOREREFACC - 0.5 - % Temperature Drift VCOREREFTACC - 0.25 - % VCOREDIG (DIGITAL CORE SUPPLY) Output Voltage ON mode (29) Coin cell mode and OFF VCORE (ANALOG CORE SUPPLY) Output Voltage ON mode and charging(29) OFF and Coin cell mode VCOREREF (BANDGAP / REGULATOR REFERENCE) Notes 29. 3.0 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction. 30. For information only. 6.3.1.1 External Components Table 19. External Components for Core Voltages 6.3.2 Regulator Capacitor Value (F) VCOREDIG 1.0 VCORE 1.0 VCOREREF 0.22 VREFDDR Voltage Reference VREFDDR is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then utilizes a voltage follower to drive the load. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 27 Functional Block Requirements and Behaviors Bias and References Block Description VINREFDDR VINREFDDR CHALF1 100 nf VHALF _ CHALF2 100 nf + Discharge VREFDDR VREFDDR CREFDDR 1.0 uf Figure 7. VREFDDR Block Diagram 6.3.2.1 VREFDDR Control Register The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 20. Table 20. Register VREFDDCRTL - ADDR 0x6A Name UNUSED VREFDDREN UNUSED Bit # R/W Default Description 3:0 - 0x00 UNUSED 4 R/W 0x00 Enable or disables VREFDDR output voltage 0 = VREFDDR Disabled 1 = VREFDDR Enabled 7:5 - 0x00 UNUSED External Components Table 21. VREFDDR External Components(31) Capacitor VINREFDDR (32) to VHALF Capacitance (F) 0.1 VHALF to GND 0.1 VREFDDR 1.0 Notes 31. Use X5R or X7R capacitors. 32. VINREFDDR to GND, 1.0 F minimum capacitance is provided by buck regulator output. PF0100 28 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Bias and References Block Description VREFDDR Specifications Table 22. VREFDDR Electrical Characteristics TMIN to TMAX (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Operating Input Voltage Range VINREFDDR 1.2 - 1.8 V Operating Load Current Range IREFDDR 0.0 - 10 mA IREFDDRLIM 10.5 15 25 mA IREFDDRQ - 8.0 - A VREFDDR - VINREFDDR/2 - V Output Voltage Tolerance (TA = -40 to 85 C) 1.2 V < VINREFDDR < 1.8 V 0.6 mA IREFDDR 10 mA VREFDDRTOL -1.0 - 1.0 % Output Voltage Tolerance (TA = -40 to 105 C), Applicable only to the Extended Industrial version 1.2 V < VINREFDDR < 1.8 V 0.6 mA IREFDDR 10 mA VREFDDRTOL -1.2 - 1.2 % Load Regulation 1.0 mA < IREFDDR < 10 mA 1.2 V < VINREFDDR < 1.8 V VREFDDRLOR - 0.40 - mV/mA Turn-on Time Enable to 90% of end value VINREFDDR = 1.2 V, 1.8 V IREFDDR = 0.0 mA tONREFDDR - - 100 s Turn-Off Time Disable to 10% of initial value VINREFDDR = 1.2 V, 1.8 V IREFDDR = 0.0 mA tOFFREFDDR - - 10 ms Start-up Overshoot VINREFDDR = 1.2 V, 1.8 V IREFDDR = 0.0 mA VREFDDROSH - 1.0 6.0 % Transient Load Response VINREFDDR = 1.2 V, 1.8 V VREFDDRTLR - 5.0 - mV VREFDDR Current Limit IREFDDR when VREFDDR is forced to VINREFDDR/4 Quiescent Current(33) ACTIVE MODE - DC Output Voltage 1.2 V < VINREFDDR < 1.8 V 0.0 mA < IREFDDR < 10 mA ACTIVE MODE - AC Notes 33. When VREFDDR is off there is a quiescent current of 1.5 A typical. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 29 Functional Block Requirements and Behaviors Power Generation 6.4 Power Generation 6.4.1 Modes of Operation The operation of the PF0100 can be reduced to five states, or modes: ON, OFF, Sleep, Standby, and Coin Cell. Figure 8 shows the state diagram of the PF0100, along with the conditions to enter and exit from each state. Coin Cell VIN < UVDET VIN < UVDET VIN > UVDET PWRON = 0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) VIN < UVDET PWRON = 0 Any SWxOMODE bits=1 (PWRON_CFG=0) Or PWRON=0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) Thermal shutdown OFF PWRON=1 & VIN > UVDET VIN < UVDET (PWRON_CFG = 0) Sleep Or PWRON = 0 PWRON= 0 < 4.0 sec Any SWxOMODE bits=1 & VIN > UVDET (PWRON_CFG=0) (PWRON_CFG=1) Or PWRON = 0 PWRON=0 held >= 4.0 sec All SWxOMODE bits= 0 Any SWxOMODE bits=1 (PWRON_CFG = 0) & PWRONRSTEN = 1 Or (PWRON_CFG=1) PWRON = 0 held >= 4.0 sec PWRON=1 All SWxOMODE bits= 0 & VIN > UVDET & PWRONRSTEN = 1 (PWRON_CFG =0) (PWRON_CFG = 1) Or ON PWRON= 0 < 4.0 sec & VIN > UVDET Thermal shudown (PWRON_CFG=1) STANDBY asserted STANDBY de-asserted Standby PWRON = 0 All SWxOMODE bits= 0 (PWRON_CFG = 0) Or PWRON = 0 held >= 4.0 sec All SWxOMODE bits= 0 & PWRONRSTEN = 1 (PWRON_CFG = 1) Thermal shutdown Figure 8. State Diagram To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the rising UVDET threshold to allow a power up. Refer to Table 29 for the UVDET thresholds. Additionally, I2C control is not possible in the Coin Cell mode and the interrupt signal, INTB, is only active in Sleep, Standby, and ON states. 6.4.1.1 ON Mode The PF0100 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation. PF0100 30 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.1.2 OFF Mode The PF0100 enters the Off mode after a turn-off event. A thermal shutdown event also forces the PF0100 into the Off mode. Only VCOREDIG and VSNVS are powered in the mode of operation. To exit the Off mode, a valid turn-on event is required. RESETBMCU is asserted, LOW, in this mode. 6.4.1.3 Standby Mode * Depending on STANDBY pin configuration, Standby is entered when the STANDBY pin is asserted. This is typically used for low-power mode of operation. * When STANDBY is de-asserted, Standby mode is exited. A product may be designed to go into a Low-power mode after periods of inactivity. The STANDBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby is preprogrammed through the I2C interface. Note that the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarity as shown in Table 23. When the PF0100 is powered up first, regulator settings for the Standby mode are mirrored from the regulator settings for the ON mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY will generally be referred to as active high throughout this document. Table 23. Standby Pin and Polarity Control STANDBY (Pin)(35) STANDBYINV (I2C bit)(36) STANDBY Control (34) 0 0 0 0 1 1 1 0 1 1 1 0 Notes 34. STANDBY = 0: System is not in Standby, STANDBY = 1: System is in Standby 35. The state of the STANDBY pin only has influence in On mode. 36. Bit 6 in Power Control Register (ADDR - 0x1B) Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into Standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 24, STBYDLY will delay the Standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event. Table 24. STANDBY Delay - Initiated Response STBYDLY[1:0](37) Function 00 No Delay 01 One 32 k period (default) 10 Two 32 k periods 11 Three 32 k periods Notes 37. Bits [5:4] in Power Control Register (ADDR - 0x1B) PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 31 Functional Block Requirements and Behaviors Power Generation 6.4.1.4 Sleep Mode * Depending on PWRON pin configuration, Sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set. * To exit Sleep mode, assert the PWRON pin. In the Sleep mode, the regulator will use the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 25 shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event. Table 25. Regulator Mode Control SWxOMODE Off Operational Mode (Sleep) (38) 0 Off 1 PFM Notes 38. For sleep mode, an activated switching regulator, should use the off mode set point as programmed by SW1xOFF[5:0] for SW1A/B/C and SWxOFF[6:0] for SW2, SW3A/B, and SW4. 6.4.1.5 Coin Cell Mode In the Coin Cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the Coin Cell state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. If the coin cell is depleted, a complete system reset will occur. At the next application of power and the detection of a Turn-on event, the system will be re-initialized with all I2C bits including, those that reset on COINPORB are restored to their default states. PF0100 32 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.2 State Machine Flow Summary Table 26 provides a summary matrix of the PF0100 flow diagram to show the conditions needed to transition from one state to another. Table 26. State Machine Flow Summary Next State STATE OFF Coin cell Sleep Standby ON OFF X VIN < UVDET X X PWRON_CFG = 0 PWRON = 1 & VIN > UVDET or PWRON_CFG = 1 PWRON = 0 < 4.0 s & VIN > UNDET Coin cell VIN > UVDET X X X X Thermal Shutdown Initial State Sleep PWRON_CFG = 1 PWRON = 0 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 VIN < UVDET X X PWRON_CFG = 0 PWRON = 1 & VIN > UVDET or PWRON_CFG = 1 PWRON = 0 < 4.0 s & VIN > UNDET VIN < UVDET PWRON_CFG = 0 PWRON = 0 Any SWxOMODE = 1 or PWRON_CFG = 1 PWRON = 0 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 X Standby de-asserted VIN < UVDET PWRON_CFG = 0 PWRON = 0 Any SWxOMODE = 1 or PWRON_CFG = 1 PWRON = 0 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 Standby asserted X Thermal Shutdown Standby PWRON_CFG = 0 PWRON = 0 All SWxOMODE = 0 or PWRON_CFG = 1 PWRON = 0 4.0 s All SWxOMODE = 0 & PWRONRSTEN = 1 Thermal Shutdown ON 6.4.2.1 PWRON_CFG = 0 PWRON = 0 All SWxOMODE = 0 or PWRON_CFG = 1 PWRON = 0 4.0 s All SWxOMODE = 0 & PWRONRSTEN = 1 Turn On Events From OFF and Sleep modes, the PMIC is powered on by a turn-on event. The type of Turn-on event depends on the configuration of PWRON. PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1. VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON is high (pulled up to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a Turn-on event. See the State diagram, Figure 8, and the Table 26 for more details. Any regulator enabled in the Sleep mode will remain enabled when transitioning from Sleep to ON, i.e., the regulator will not be turned off and then on again to match the startup sequence. The following is a more detailed description of the PWRON configurations: * If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set. * If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 33 Functional Block Requirements and Behaviors Power Generation The sense bit will show the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press. The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode. Table 27. PWRON Hardware Debounce Bit Settings Bits PWRONDBNC[1:0] State Turn On Debounce (ms) Falling Edge INT Debounce (ms) Rising Edge INT Debounce (ms) 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 39. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin. 6.4.2.2 Turn Off Events PWRON Pin The PWRON pin is used to power off the PF0100. The PWRON pin can be configured with OTP to power off the PMIC under the following two conditions: 1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low. 2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. Thermal Protection If the die temperature surpasses a given threshold, the thermal protection circuit will power off the PMIC to avoid damage. A turnon event will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature decreases below a given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power Dissipation section for more detailed information. Undervoltage Detection When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine will transition to the Coin Cell mode. 6.4.3 Power Tree The PF0100 PMIC features six buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a DDR voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR. VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 28 for a summary of all power supplies provided by the PF0100. PF0100 34 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 28. Power Tree Summary Supply Output Voltage (V) Step Size (mV) Maximum Load Current (mA) SW1A/B 0.3 - 1.875 25 2500 SW1C 0.3 - 1.875 25 2000 SW2 0.4 - 3.3 25/50 2000 SW3A/B 0.4 - 3.3 25/50 1250(40) SW4 0.5*SW3A_OUT, 0.4 - 3.3 25/50 1000 SWBST 5.00/5.05/5.10/5.15 50 600 VGEN1 0.80 - 1.55 50 100 VGEN2 0.80 - 1.55 50 250 VGEN3 1.8 - 3.3 100 100 VGEN4 1.8 - 3.3 100 350 VGEN5 1.8 - 3.3 100 100 VGEN6 1.8 - 3.3 100 200 VSNVS 1.0 - 3.0 NA 0.4 VREFDDR 0.5*SW3A_OUT NA 10 Notes 40. Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up to 2500 mA. Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0100, as well as the typical application voltage domain on the i.MX 6X processor. Note that each application power tree is dependent upon the system's voltage and current requirements, therefore a proper input voltage should be selected for the regulators. The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 29 summarizes the UVDET thresholds. Table 29. UVDET Threshold UVDET Threshold VIN Rising 3.1 V Falling 2.65 V PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 35 Functional Block Requirements and Behaviors Power Generation SW1A CORE (0.3 to 1.875 V), 1.25 A i.MX6X MCU VDDARM_IN SW1B CORE (0.3 to 1.875 V), 1.25 A VIN 2.8 - 4.5 V SW1C SOC (0.3 to 1.875 V), 2.0 A VDDSOC_IN SW2 VDDHIGH (0.4 to 3.3 V), 2.0 A VDDHIGH_IN SW3A DDR CORE (0.4 to 3.3 V), 1.25 A SW3B DDR IO (0.4 to 3.3 V), 1.25 A VDD_DDR_IO SW4 System/VTT (0.4 to 3.3 V) (0.5*VDDR) 1.0 A SWBST 5.0 V, 0.6 A VREFDDR 0.5*VDDR, 10 mA SW3A/B VIN MUX / COIN CHRG Coincell VINMAX = 3.4 V SW4 VINMAX = 3.6 V SW4 SW4 VSNVS_IN USB_OTG DDR3 Peripherals VGEN4 (1.8 to 3.3 V), 350 mA VGEN5 (1.8 to 3.3 V), 100 mA VIN SW2 VGEN2 (0.80 to 1.55 V), 250 mA VGEN3 (1.8 to 3.3 V), 100 mA VIN SW2 VSNVS 1.0 to 3.0 V, 400 uA VGEN1 (0.80 to 1.55 V), 100 mA VIN SW2 LDO_3p0 VINMAX = 4.5 V VGEN6 (1.8 to 3.3 V), 200 mA Figure 9. PF0100 Typical Power Map PF0100 36 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.4 Buck Regulators Each buck regulator is capable of operating in PFM, APS, and PWM switching modes. 6.4.4.1 Current Limit Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit condition persists for more than 8.0 ms, a fault interrupt is generated. 6.4.4.2 General Control To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current variation. Available switching modes for buck regulators are presented in Table 30. Table 30. Switching Mode Description Mode Description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions. During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Table 31 summarizes the Buck regulator programmability for Normal and Standby modes. Table 31. Regulator Mode Control SWxMODE[3:0] Normal Mode Standby Mode 0000 Off Off 0001 PWM Off 0010 Reserved Reserved 0011 PFM Off 0100 APS Off 0101 PWM PWM 0110 PWM APS 0111 Reserved Reserved 1000 APS APS 1001 Reserved Reserved 1010 Reserved Reserved 1011 Reserved Reserved 1100 APS PFM 1101 PWM PFM PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 37 Functional Block Requirements and Behaviors Power Generation Table 31. Regulator Mode Control (continued) SWxMODE[3:0] Normal Mode Standby Mode 1110 Reserved Reserved 1111 Reserved Reserved Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate of the output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic Voltage Scaling. For each regulator, the output voltage options are the same for Normal and Standby modes. When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage programmed in its voltage register. Any regulators whose SWxOMODE bit is set to "1" will enter Sleep mode if a PWRON turn-off event occurs, and any regulator whose SWxOMODE bit is set to "0" will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit is set to "1" will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state. Any regulator whose SWxOMODE bit is set to "0" will be powered up with the same delay in the start-up sequence as when powering On from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings. Table 25 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4. Dynamic Voltage Scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. 1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 34 and Table 35. 2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SW1xSTBY[5:0] for SW1A/B/C and by bits SWxSTBY[6:0] for SW2, SW3A/B, and SW4. Voltage transitions initiated by a Standby event are governed by the SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively. 3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SW1xOFF[5:0] for SW1A/B/C and by bits SWxOFF[6:0] for SW2, SW3A/B, and SW4. Voltage transitions initiated by a turn-off event are governed by the SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively. Table 32, Table 33, Table 34, and Table 35 summarize the set point control and DVS time stepping applied to all regulators. Table 32. DVS Control Logic for SW1A/B/C STANDBY Set Point Selected by 0 SW1x[5:0] 1 SW1xSTBY[5:0] Table 33. DVS Control Logic for SW2, SW3A/B, and SW4 STANDBY Set Point Selected by 0 SWx[6:0] 1 SWxSTBY[6:0] PF0100 38 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 34. DVS Speed Selection for SW1A/B/C SW1xDVSSPEED[1:0] Function 00 25 mV step each 2.0 s 01 (default) 25 mV step each 4.0 s 10 25 mV step each 8.0 s 11 25 mV step each 16 s Table 35. DVS Speed Selection for SW2, SW3A/B, and SW4 SWxDVSSPEED[1:0] Function SWx[6] = 0 or SWxSTBY[6] = 0 Function SWx[6] = 1 or SWxSTBY[6] = 1 00 25 mV step each 2.0 s 50 mV step each 4.0 s 01 (default) 25 mV step each 4.0 s 50 mV step each 8.0 s 10 25 mV step each 8.0 s 50 mV step each 16 s 11 25 mV step each 16 s 50 mV step each 32 s The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the overcurrent condition on the regulator should be masked. Requested Set Point Internally Controlled Steps Example Actual Output Voltage Output Voltage Initial Set Point Actual Output Voltage Internally Controlled Steps Voltage Change Request Output Voltage with light Load Request for Higher Voltage Possible Output Voltage Window Request for Lower Voltage Initiated by I2C Programming, Standby Control Figure 10. Voltage Stepping with DVS Regulator Phase Clock The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 36. By default, each regulator is initialized at 90 out of phase with respect to each other. For example, SW1x is set to 0 , SW2 is set to 90 , SW3A/B is set to 180 , and SW4 is set to 270 by default at power up. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 39 Functional Block Requirements and Behaviors Power Generation Table 36. Regulator Phase Clock Selection SWxPHASE[1:0] Phase of Clock Sent to Regulator (degrees) 00 0 01 90 10 180 11 270 The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 38 shows the selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 and 4.0 MHz, 180 are the same in terms of phasing. Table 37 shows the optimum phasing when using more than one switching frequency. Table 37. Optimum Phasing Frequencies Optimum Phasing 1.0 MHz 2.0 MHz 0 180 1.0 MHz 4.0 MHz 0 180 2.0 MHz 4.0 MHz 0 180 1.0 MHz 2.0 MHz 4.0 MHz 0 90 90 Table 38. Regulator Frequency Configuration SWxFREQ[1:0] Frequency 00 1.0 MHz 01 2.0 MHz 10 4.0 MHz 11 Reserved Programmable Maximum Current The maximum current, ISWxMAX, of each buck regulator is programmable. This allows the use of smaller inductors where lower currents are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. The SWx_PWRSTG[2:0] bits on the Extended Page 2 of the register map control the number of power stages. See Table 39 for the programmable options. Bit[0] must always be enabled to ensure the stage with the current sensor is chosen. The default setting, SWx_PWRSTG[2:0] = 111, represents the highest maximum current. The current limit for each option is also scaled by the percentage of power stages that are enabled. PF0100 40 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 39. Programmable Current Configuration Regulators % of Power Stages Enabled Control Bits SW1AB_PWRSTG[2:0] SW1AB ISW1ABMAX 0 0 1 40% 1.0 0 1 1 80% 2.0 1 0 1 60% 1.5 1 1 1 100% 2.5 SW1C_PWRSTG[2:0] SW1C ISW1CMAX 0 0 1 43% 0.9 0 1 1 58% 1.2 1 0 1 86% 1.7 1 1 1 100% 2.0 SW2_PWRSTG[2:0] SW2 ISW2MAX 0 0 1 38% 0.75 0 1 1 75% 1.5 1 0 1 63% 1.25 1 1 1 100% 2.0 SW3A_PWRSTG[2:0] SW3A ISW3AMAX 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 SW3B_PWRSTG[2:0] SW3B ISW3BMAX 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 SW4_PWRSTG[2:0] SW4 Rated Current (A) ISW4MAX 0 0 1 50% 0.5 0 1 1 75% 0.75 1 0 1 75% 0.75 1 1 1 100% 1.0 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 41 Functional Block Requirements and Behaviors Power Generation 6.4.4.3 SW1A/B/C SW1/A/B/C are 2.5 to 4.5 A buck regulators that can be configured in various phasing schemes, depending on the desired cost/ performance trade-offs. The following configurations are available: * SW1A/B/C single phase with one inductor * SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor * SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Extended Page 1, as shown in Table 40. . Table 40. SW1 Configuration SW1_CONFIG[1:0] Description 00 A/B/C Single Phase 01 A/B Single Phase C Independent mode 10 A/B Dual Phase C Independent mode 11 Reserved PF0100 42 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation SW1A/B/C Single Phase In this configuration, all phases A, B, and C, are connected together to a single inductor, thus, providing up to 4.50 A current capability for high current applications. The feedback and all other controls are accomplished by use of pin SW1CFB and SW1C control registers, respectively. Figure 11 shows the connection for SW1A/B/C in single phase mode. During Single Phase mode operation, all three phases will use the same configuration for frequency, phase, and DVS speed set in SW1CCONF register. However, the same configuration settings for frequency, phase, and DVS speed setting on SW1AB registers should be used. The SW1FB pin should be left floating in this configuration. VIN SW1AIN SW1AMODE ISENSE CINSW1A SW1A/B/C SW1ALX LSW1 Controller Driver COSW1A SW1AFAULT Internal Compensation SW1FB I2C Z2 Z1 EA DAC VREF VIN SW1BIN SW1BMODE ISENSE CINSW1B SW1BLX Controller I2C Interface Driver SW1BFAULT VIN SW1CIN SW1CMODE ISENSE CINSW1C SW1CLX Controller Driver SW1CFAULT EP Internal Compensation SW1CFB I2C Z2 Z1 EA VREF DAC Figure 11. SW1A/B/C Single Phase Block Diagram PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 43 Functional Block Requirements and Behaviors Power Generation SW1A/B Single Phase - SW1C Independent Mode In this configuration, SW1A/B is connected as a single phase with a single inductor, while SW1C is used as an independent output, using its own inductor and configurations parameters. This configuration allows reduced component count by using only one inductor for SW1A/B. As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage set point for Normal, Standby, and Sleep modes, as well as switching mode selection and on/ off control. Figure 12 shows the physical connection for SW1A/B in single phase and SW1C as an independent output. VIN SW1AIN SW1AMODE ISENSE CINSW1A SW1A/B SW1ALX LSW1A Controller Driver COSW1A SW1AFAULT Internal Compensation SW1FB I2C Z2 Z1 EA DAC VREF VIN SW1BIN SW1BMODE ISENSE CINSW1B SW1BLX Controller I2C Interface Driver SW1BFAULT VIN SW1CIN SW1C SW1CLX LSW1C COSW1C SW1CMODE ISENSE CINSW1C Controller Driver SW1CFAULT EP Internal Compensation SW1CFB I2C Z2 Z1 EA VREF DAC Figure 12. SW1A/B Single Phase, SW1C Independent Mode Block Diagram Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register, while SW1CLX node operates independently, using the configuration in the SW1CCONF register. PF0100 44 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation SW1A/B Dual Phase - SW1C Independent Mode In this mode, SW1A/B is connected in dual phase mode using one inductor per switching node, while SW1C is used as an independent output using its own inductor and configuration parameters. This mode provides a smaller output voltage ripple on the SW1A/B output. As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage set point for Normal, Standby, and Sleep modes, as well as switching mode selection and on/ off control. Figure 13 shows the physical connection for SW1A/B in dual phase and SW1C as an independent output. VIN SW1AIN SW1AMODE ISENSE CINSW1A SW1AB SW1ALX LSW1A Controller Driver COSW1A SW1AFAULT Internal Compensation SW1FB I2C Z2 Z1 EA DAC VREF VIN SW1BIN SW1BMODE ISENSE CINSW1B SW1BLX LSW1B I2C Interface Controller Driver COSW1B SW1BFAULT VIN SW1CIN SW1C SW1CMODE ISENSE CINSW1C SW1CLX LSW1C COSW1C Controller Driver SW1CFAULT EP Internal Compensation SW1CFB I2C Z2 Z1 EA VREF DAC Figure 13. SW1A/B Dual Phase, SW1C Independent Mode Block Diagram In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at 180 phase shift from each other and use the same frequency and DVS configured by SW1ABCONF register, while SW1CLX node operate independently using the configuration in the SW1CCONF register. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 45 Functional Block Requirements and Behaviors Power Generation SW1A/B/C Setup and Control Registers SW1A/B and SW1C output voltages are programmable from 0.300 to 1.875 V in steps of 25 mV. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW1x[5:0], SW1xSTBY[5:0], and SW1xOFF[5:0] bits respectively. Table 41 shows the output voltage coding for SW1A/B or SW1C. Note: Voltage set points of 0.6 V and below are not supported. Table 41. SW1A/B/C Output Voltage Configuration Set Point SW1x[5:0] SW1xSTBY[5:0] SW1xOFF[5:0] SW1x Output (V) Set Point SW1x[5:0] SW1xSTBY[5:0] SW1xOFF[5:0] SW1x Output (V) 0 000000 0.3000 32 100000 1.1000 1 000001 0.3250 33 100001 1.1250 2 000010 0.3500 34 100010 1.1500 3 000011 0.3750 35 100011 1.1750 4 000100 0.4000 36 100100 1.2000 5 000101 0.4250 37 100101 1.2250 6 000110 0.4500 38 100110 1.2500 7 000111 0.4750 39 100111 1.2750 8 001000 0.5000 40 101000 1.3000 9 001001 0.5250 41 101001 1.3250 10 001010 0.5500 42 101010 1.3500 11 001011 0.5750 43 101011 1.3750 12 001100 0.6000 44 101100 1.4000 13 001101 0.6250 45 101101 1.4250 14 001110 0.6500 46 101110 1.4500 15 001111 0.6750 47 101111 1.4750 16 010000 0.7000 48 110000 1.5000 17 010001 0.7250 49 110001 1.5250 18 010010 0.7500 50 110010 1.5500 19 010011 0.7750 51 110011 1.5750 20 010100 0.8000 52 110100 1.6000 21 010101 0.8250 53 110101 1.6250 22 010110 0.8500 54 110110 1.6500 23 010111 0.8750 55 110111 1.6750 24 011000 0.9000 56 111000 1.7000 25 011001 0.9250 57 111001 1.7250 26 011010 0.9500 58 111010 1.7500 27 011011 0.9750 59 111011 1.7750 28 011100 1.0000 60 111100 1.8000 29 011101 1.0250 61 111101 1.8250 30 011110 1.0500 62 111110 1.8500 31 011111 1.0750 63 111111 1.8750 PF0100 46 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 42 provides a list of registers used to configure and operate SW1A/B/C and a detailed description on each one of these register is provided in Table 43 through Table 52. Table 42. SW1A/B/C Register Summary Register Address Output SW1ABVOLT 0x20 SW1AB Output voltage set point in normal operation SW1ABSTBY 0x21 SW1AB Output voltage set point on Standby SW1ABOFF 0x22 SW1AB Output voltage set point on Sleep SW1ABMODE 0x23 SW1AB Switching Mode selector register SW1ABCONF 0x24 SW1AB DVS, Phase, Frequency and ILIM configuration SW1CVOLT 0x2E SW1C Output voltage set point in normal operation SW1CSTBY 0x2F SW1C Output voltage set point in Standby SW1COFF 0x30 SW1C Output voltage set point in Sleep SW1CMODE 0x31 SW1C Switching Mode selector register SW1CCONF 0x32 SW1C DVS, Phase, Frequency and ILIM configuration Table 43. Register SW1ABVOLT - ADDR 0x20 Name Bit # R/W Default Description SW1AB 5:0 R/W 0x00 Sets the SW1AB output voltage during normal operation mode. See Table 41 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED Table 44. Register SW1ABSTBY - ADDR 0x21 Name Bit # R/W Default Description SW1ABSTBY 5:0 R/W 0x00 Sets the SW1AB output voltage during Standby mode. See Table 41 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED Table 45. Register SW1ABOFF - ADDR 0x22 Name Bit # R/W Default Description SW1ABOFF 5:0 R/W 0x00 Sets the SW1AB output voltage during Sleep mode. See Table 41 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 47 Functional Block Requirements and Behaviors Power Generation Table 46. Register SW1ABMODE - ADDR 0x23 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW1AB switching operation mode. See Table 31 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW1ABOMODE 5 R/W 0x00 Set status of SW1AB when in Sleep mode 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW1ABMODE UNUSED Description Table 47. Register SW1ABCONF - ADDR 0x24 Name Bit # R/W Default Description SW1ABILIM 0 R/W 0x00 SW1AB current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW1ABFREQ 3:2 R/W 0x00 SW1A/B switching frequency selector. See Table 38. SW1ABPHASE 5:4 R/W 0x00 SW1A/B Phase clock selection. See Table 36. SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection. See Table 34. Table 48. Register SW1CVOLT - ADDR 0x2E Name Bit # R/W Default Description SW1C 5:0 R/W 0x00 Sets the SW1C output voltage during normal operation mode. See Table 41 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED Table 49. Register SW1CSTBY - ADDR 0x2F Name Bit # R/W Default Description SW1CSTBY 5:0 R/W 0x00 Sets the SW1C output voltage during Standby mode. See Table 41 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED Table 50. Register SW1COFF - ADDR 0x30 Name Bit # R/W Default Description SW1COFF 5:0 R/W 0x00 Sets the SW1C output voltage during Sleep mode. See Table 41 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED PF0100 48 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 51. Register SW1CMODE - ADDR 0x31 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW1C switching operation mode. See Table 30 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW1COMODE 5 R/W 0x00 Set status of SW1C when in Sleep mode 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW1CMODE UNUSED Description Table 52. Register SW1CCONF - ADDR 0x32 Name Bit # R/W Default Description SW1CILIM 0 R/W 0x00 SW1C current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW1CFREQ 3:2 R/W 0x00 SW1C switching frequency selector. See Table 38. SW1CPHASE 5:4 R/W 0x00 SW1C Phase clock selection. See Table 36. SW1CDVSSPEED 7:6 R/W 0x00 SW1C DVS speed selection. See Table 34. SW1A/B/C External Components Table 53. SW1A/B/C External Component Recommendations Mode Components Description A/B/C Single Phase A/B Single - C Independent Mode A/B Dual - C Independent Mode CINSW1A(41) SW1A Input capacitor 4.7 F 4.7 F 4.7 F CIN1AHF(41) SW1A Decoupling input capacitor 0.1 F 0.1 F 0.1 F CINSW1B(41) SW1B Input capacitor 4.7 F 4.7 F 4.7 F CIN1BHF(41) SW1B Decoupling input capacitor 0.1 F 0.1 F 0.1 F CINSW1C(41) SW1C Input capacitor 4.7 F 4.7 F 4.7 F CIN1CHF(41) SW1C Decoupling input capacitor 0.1 F 0.1 F 0.1 F COSW1AB(41) SW1A/B Output capacitor 6 x 22 F 2 x 22 F 4 x 22 F COSW1C(41) SW1C Output capacitor - 3 x 22 F 3 x 22 F LSW1A SW1A Inductor 1.0 H 1.0 H 1.0 H LSW1B SW1B Inductor - - 1.0 H LSW1C SW1C Inductor - 1.0 H 1.0 H Notes 41. Use X5R or X7R capacitors. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 49 Functional Block Requirements and Behaviors Power Generation SW1A/B/C Specifications Table 54. SW1A/B/C Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Operating Input Voltage VINSW1A VINSW1B VINSW1C 2.8 - 4.5 V Nominal Output Voltage VSW1ABC - Table 41 - V -25 -3.0% - - 25 3.0% -65 -45 -3.0% - - - 65 45 3.0% - - 4500 7.1 5.3 10.5 7.9 13.7 10.3 Start-up Overshoot VSW1ABCOSH ISW1ABC = 0 mA DVS clk = 25 mV/4 s, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V - - 66 mV Turn-on Time Enable to 90% of end value ISW1x = 0 mA DVS clk = 25 mV/4.0 s, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V - - 500 s - - - 1.0 2.0 4.0 - - - SW1A/B/C (SINGLE PHASE) Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 4.5 A 0.625 V VSW1ABC 1.450 V 1.475 V VSW1ABC 1.875 V * PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 150 mA VSW1ABCACC 0.625 V < VSW1ABC < 0.675 V 0.7 V < VSW1ABC < 0.85 V 0.875 V < VSW1ABC < 1.875 V Rated Output Load Current, 2.8 V < VIN < 4.5 V, 0.625 V < VSW1ABC < 1.875 V Current Limiter Peak Current Detection * Current through Inductor SW1ABILIM = 0 SW1ABILIM = 1 Switching Frequency SW1xFREQ[1:0] = 00 SW1xFREQ[1:0] = 01 SW1xFREQ[1:0] = 10 ISW1ABC ISW1ABCLIM tONSW1ABC fSW1ABC mV % mA A MHz PF0100 50 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 54. SW1A/B/C Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit - - - - - - 77 82 86 84 80 68 - - - - - - VSW1ABC - 10 - mV Line Regulation (APS, PWM) VSW1ABCLIR - - 20 mV DC Load Regulation (APS, PWM) VSW1ABCLOR - - 20 mV Transient Load Regulation * Transient load = 0 to 2.25 A, di/dt = 100 mA/s Overshoot Undershoot VSW1ABCLOTR - - - - 50 50 ISW1ABCQ - - 18 145 - - A RSW1ABCDIS - 600 - Operating Input Voltage VINSW1A VINSW1B 2.8 - 4.5 V Nominal Output Voltage VSW1AB - Table 41 - V -25 -3.0% - 25 3.0% -65 -45 -3.0% - - - 65 45 3.0% - - 2500 4.5 3.3 6.5 4.9 8.5 6.4 2.2 1.6 3.2 2.4 4.3 3.2 SW1A/B/C (SINGLE PHASE) (CONTINUED) Efficiency * VIN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 H PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 850 mA APS, PWM, 1.2 V, 1275 mA APS, PWM, 1.2 V, 2125 mA APS, PWM, 1.2 V, 4500 mA Output Ripple Quiescent Current PFM Mode APS Mode Discharge Resistance SW1ABC % mV SW1A/B (SINGLE/DUAL PHASE) Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 2.5 A 0.625 V VSW1AB 1.450 V 1.475 V VSW1AB 1.875 V * PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 150 mA VSW1ABACC 0.625 V < VSW1AB < 0.675 V 0.7 V < VSW1AB < 0.85 V 0.875 V < VSW1AB < 1.875 V Rated Output Load Current, (43) 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V Current Limiter Peak Current Detection (43) * SW1A/B Single Phase (current through inductor) SW1ABILIM = 0 SW1ABILIM = 1 * SW1A/B Dual Phase (current through inductor per phase) SW1ABILIM = 0 SW1ABILIM = 1 ISW1AB ISW1ABLIM mV % mA A PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 51 Functional Block Requirements and Behaviors Power Generation Table 54. SW1A/B/C Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Start-up Overshoot ISW1AB = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V VSW1ABOSH - - 66 mV Turn-on Time Enable to 90% of end value ISW1AB = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V tONSW1AB - - 500 s - - - 1.0 2.0 4.0 - - - - - - - - - 82 84 86 87 82 71 - - - - - - VSW1AB - 10 - mV Line Regulation (APS, PWM) VSW1ABLIR - - 20 mV DC Load Regulation (APS, PWM) VSW1ABLOR - - 20 mV Transient Load Regulation * Transient load = 0 to 1.25 A, di/dt = 100 mA/s Overshoot Undershoot VSW1ABLOTR - - - - 50 50 ISW1ABQ - - 18 235 - - A SW1A P-MOSFET RDSON VINSW1A = 3.3 V RONSW1AP - 215 245 m SW1A N-MOSFET RDSON VINSW1A = 3.3 V RONSW1AN - 258 326 m SW1A P-MOSFET Leakage Current VINSW1A = 4.5 V ISW1APQ - - 7.5 A SW1A N-MOSFET Leakage Current VINSW1A = 4.5 V ISW1ANQ - - 2.5 A SW1B P-MOSFET RDSON VINSW1B = 3.3 V RONSW1BP - 215 245 m SW1B N-MOSFET RDSON VINSW1B = 3.3 V RONSW1BN - 258 326 m ISW1BPQ - - 7.5 A SW1A/B (SINGLE/DUAL PHASE) (CONTINUED) Switching Frequency SW1ABFREQ[1:0] = 00 SW1ABFREQ[1:0] = 01 SW1ABFREQ[1:0] = 10 fSW1AB MHz Efficiency (Single Phase) * VIN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 H PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 500 mA APS, PWM, 1.2 V, 750 mA APS, PWM, 1.2 V, 1250 mA APS, PWM, 1.2 V, 2500 mA Output Ripple Quiescent Current PFM Mode APS Mode SW1B P-MOSFET Leakage Current VINSW1B = 4.5 V SW1AB % mV PF0100 52 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 54. SW1A/B/C Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit ISW1BNQ - - 2.5 A RSW1ABDIS - 600 - Operating Input Voltage VINSW1C 2.8 - 4.5 V Nominal Output Voltage VSW1C - Table 41 - V -25 -3.0% - - 25 3.0% SW1A/B (SINGLE/DUAL PHASE) (CONTINUED) SW1B N-MOSFET Leakage Current VINSW1B = 4.5 V Discharge Resistance SW1C (INDEPENDENT) Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1C < 2.0 A 0.625 V VSW1C 1.450 V 1.475 V VSW1C 1.875 V * PFM, steady state 2.8 V < VIN < 4.5 V, 0 < ISW1C < 50 mA VSW1CACC mV -65 -45 -3.0% - - - 65 45 3.0% ISW1C - - 2000 ISW1CLIM 2.6(42) 1.95 4.0 3.0 5.2 3.9 Start-up Overshoot ISW1C = 0 mA DVS clk = 25 mV/4 s, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V VSW1COSH - - 66 mV Turn-on Time Enable to 90% of end value ISW1C = 0 mA DVS clk = 25 mV/4 s, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V tONSW1C - - 500 s - - - 1.0 2.0 4.0 - - - - - - - - - 77 78 86 84 78 65 - - - - - - VSW1C - 10 - mV VSW1CLIR - - 20 mV 0.625 V < VSW1C < 0.675 V 0.7 V < VSW1C < 0.85 V 0.875 V < VSW1C < 1.875 V Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.625 V < VSW1C < 1.875 V Current Limiter Peak Current Detection * Current through Inductor SW1CILIM = 0 SW1CILIM = 1 Switching Frequency SW1CFREQ[1:0] = 00 SW1CFREQ[1:0] = 01 SW1CFREQ[1:0] = 10 fSW1C mA A MHz Efficiency * VIN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 H PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 400 mA APS, PWM, 1.2 V, 600 mA APS, PWM, 1.2 V, 1000 mA APS, PWM, 1.2 V, 2000 mA Output Ripple Line Regulation (APS, PWM) SW1C % PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 53 Functional Block Requirements and Behaviors Power Generation Table 54. SW1A/B/C Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit DC Load Regulation (APS, PWM) VSW1CLOR - - 20 mV Transient Load Regulation * Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/s Overshoot Undershoot VSW1CLOTR - - - - 50 50 ISW1CQ - - 22 145 - - SW1C P-MOSFET RDSON at VINSW1C = 3.3 V RONSW1CP - 184 206 SW1C N-MOSFET RDSON at VINSW1C = 3.3 V RONSW1CN - 211 260 SW1C P-MOSFET Leakage Current VINSW1C = 4.5 V ISW1CPQ - - 10.5 A SW1C N-MOSFET Leakage Current VINSW1C = 4.5 V ISW1CNQ - - 3.5 A Discharge Resistance RSW1CDIS - 600 - SW1C (INDEPENDENT) (CONTINUED) Quiescent Current PFM Mode APS Mode mV A m m Notes 42. Meets 1.89 A current rating for VDDSOC_IN domain on i.MX 6X processor. 43. Current rating of SW1AB supports the Power Virus mode of operation of the i.MX 6X processor. PF0100 54 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c fif 40 E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 14. SW1AB Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.375 V; Consumer Version PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 55 Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) % ( 70 y 60 c n 50 e i 40 c if f 30 E 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 15. SW1AB Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.375 V; Extended Industrial Version PF0100 56 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 16. SW1C Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.375 V; Consumer Version PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 57 Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 17. SW1C Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.375 V; Extended Industrial Version PF0100 58 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.4.4 SW2 SW2 is a single phase, 2.0 A rated buck regulator. Table 30 describes the modes, and Table 31 show the options for the SWxMODE[3:0] bits. Figure 18 shows the block diagram and the external component connections for SW2 regulator. VIN SW2IN SW2MODE ISENSE CINSW2 SW2 Controller SW2LX Driver LSW2 COSW2 SW2FAULT EP Internal Compensation SW2FB I2C Interface I2C Z2 Z1 VREF EA DAC Figure 18. SW2 Block Diagram SW2 Setup and Control Registers SW2 output voltage is programmable from 0.400 to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW2[6] is set to "0", the output will be limited to the lower output voltages from 0.400 to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. Likewise, once bit SW2[6] is set to "1", the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by bits SW2[5:0]. In order to optimize the performance of the regulator, it is recommended that only voltages from 2.000 to 3.300 V be used in the high range, and the lower range be used for voltages from 0.400 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW2[5:0], SW2STBY[5:0] and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] will be copied into bits SW2STBY[6], and SW2OFF[6] bits. Therefore, the output voltage range will remain the same in all three operating modes. Table 55 shows the output voltage coding valid for SW2. Note: Voltage set points of 0.6 V and below are not supported. Table 55. SW2 Output Voltage Configuration Low Output Voltage Range(44) High Output Voltage Range Set Point SW2[6:0] SW2 Output Set Point SW2[6:0] SW2 Output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 59 Functional Block Requirements and Behaviors Power Generation Table 55. SW2 Output Voltage Configuration (continued) Low Output Voltage Range(44) High Output Voltage Range Set Point SW2[6:0] SW2 Output Set Point SW2[6:0] SW2 Output 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 PF0100 60 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 55. SW2 Output Voltage Configuration (continued) Low Output Voltage Range(44) High Output Voltage Range Set Point SW2[6:0] SW2 Output Set Point SW2[6:0] SW2 Output 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 44. For voltages less than 2.0 V, only use set points 0 to 63. Setup and control of SW2 is done through I2C registers listed in Table 56, and a detailed description of each one of the registers is provided in Tables 57 to Table 61. Table 56. SW2 Register Summary Register Address Description SW2VOLT 0x35 Output voltage set point on normal operation SW2STBY 0x36 Output voltage set point on Standby SW2OFF 0x37 Output voltage set point on Sleep SW2MODE 0x38 Switching Mode selector register SW2CONF 0x39 DVS, Phase, Frequency, and ILIM configuration Table 57. Register SW2VOLT - ADDR 0x35 Name Bit # R/W Default Description SW2 5:0 R/W 0x00 Sets the SW2 output voltage during normal operation mode. See Table 55 for all possible configurations. SW2 6 R 0x00 Sets the operating output voltage range for SW2. Set during OTP or TBB configuration only. See Table 55 for all possible configurations. UNUSED 7 - 0x00 UNUSED PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 61 Functional Block Requirements and Behaviors Power Generation Table 58. Register SW2STBY - ADDR 0x36 Name Bit # R/W Default Description SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during Standby mode. See Table 55 for all possible configurations. SW2STBY 6 R 0x00 Sets the operating output voltage range for SW2 on Standby mode. This bit inherits the value configured on bit SW2[6] during OTP or TBB configuration. See Table 55 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 59. Register SW2OFF - ADDR 0x37 Name Bit # R/W Default Description SW2OFF 5:0 R/W 0x00 Sets the SW2 output voltage during Sleep mode. See Table 55 for all possible configurations. SW2OFF 6 R 0x00 Sets the operating output voltage range for SW2 on Sleep mode. This bit inherits the value configured on bit SW2[6] during OTP or TBB configuration. See Table 55 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 60. Register SW2MODE - ADDR 0x38 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW2 switching operation mode. See Table 30 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW2OMODE 5 R/W 0x00 Set status of SW2 when in Sleep mode 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW2MODE UNUSED Description Table 61. Register SW2CONF - ADDR 0x39 Name Bit # R/W Default Description SW2ILIM 0 R/W 0x00 SW2 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. See Table 38. SW2PHASE 5:4 R/W 0x00 SW2 Phase clock selection. See Table 36. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. See Table 35. PF0100 62 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation SW2 External Components Table 62. SW2 External Component Recommendations Components CINSW2(45) CIN2HF Description Values SW2 Input capacitor 4.7 F (45) SW2 Decoupling input capacitor 0.1 F (45) SW2 Output capacitor COSW2 LSW2 3 x 22 F 1.0 H SW2 Inductor Notes 45. Use X5R or X7R capacitors. SW2 Specifications Table 63. SW2 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit VINSW2 2.8 - 4.5 V VSW2 - Table 55 - V -25 -3.0% -6.0% - - - 25 3.0% 6.0% -65 -45 -3.0% -3.0% - - - - 65 45 3.0% 3.0% ISW2 - - 2000 mA ISW2LIM 2.8 2.1 4.0 3.0 5.2 3.9 A Start-up Overshoot ISW2 = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW2 = 4.5 V VSW2OSH - - 66 mV Turn-on Time Enable to 90% of end value ISW2 = 0.0 mA DVS clk = 50 mV/8 s, VIN = VINSW2 = 4.5 V tONSW2 - - 550 s SWITCH MODE SUPPLY SW2 Operating Input Voltage(46) Nominal Output Voltage Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 2.0 A 0.625 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V * PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 50 mA VSW2ACC 0.625 V < VSW2 < 0.675 V 0.7 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V Rated Output Load Current (47) 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V Current Limiter Peak Current Detection * Current through Inductor SW2ILIM = 0 SW2ILIM = 1 mV % PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 63 Functional Block Requirements and Behaviors Power Generation Table 63. SW2 Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit - - - 1.0 2.0 4.0 - - - - - - - - - 94 95 96 94 92 86 - - - - - - VSW2 - 10 - mV Line Regulation (APS, PWM) VSW2LIR - - 20 mV DC Load Regulation (APS, PWM) VSW2LOR - - 20 mV Transient Load Regulation * Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/s Overshoot Undershoot VSW2LOTR - - - - 50 50 - - - 23 145 305 - - - SWITCH MODE SUPPLY SW2 (CONTINUED) Switching Frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 fSW2 MHz Efficiency * VIN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 H PFM, 3.15 V, 1.0 mA PFM, 3.15 V, 50 mA APS, PWM, 3.15 V, 400 mA APS, PWM, 3.15 V, 600 mA APS, PWM, 3.15 V, 1000 mA APS, PWM, 3.15 V, 2000 mA Output Ripple Quiescent Current PFM Mode APS Mode (Low output voltage settings) APS Mode (High output voltage settings) SW2 ISW2Q % mV A SW2 P-MOSFET RDSON at VIN = VINSW2 = 3.3 V RONSW2P - 190 209 m SW2 N-MOSFET RDSON at VIN = VINSW2 = 3.3 V RONSW2N - 212 255 m SW2 P-MOSFET Leakage Current VIN = VINSW2 = 4.5 V ISW2PQ - - 12 A SW2 N-MOSFET Leakage Current VIN = VINSW2 = 4.5 V ISW2NQ - - 4.0 A Discharge Resistance RSW2DIS - 600 - Notes 46. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V. 47. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance). PF0100 64 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 19. SW2 Efficiency Waveforms: VIN = 4.2 V; VOUT = 3.0 V; Consumer Version PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 65 Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 20. SW2 Efficiency Waveforms: VIN = 4.2 V; VOUT = 3.0 V; Extended Industrial Version PF0100 66 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.4.5 SW3A/B SW3A/B are 1.25 to 2.5 A rated buck regulators, depending on the configuration. Table 30 describes the available switching modes and Table 31 show the actual configuration options for the SW3xMODE[3:0] bits. SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following configurations are available: * A single phase * A dual phase * Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 64 shows the options for the SW3CFG[1:0] bits. Table 64. SW3 Configuration SW3_CONFIG[1:0] Description 00 A/B Single Phase 01 A/B Single Phase 10 A/B Dual Phase 11 A/B Independent PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 67 Functional Block Requirements and Behaviors Power Generation SW3A/B Single Phase In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 21. This configuration reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3 SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA DAC I2C Interface VIN SW3BIN SW3BMODE ISENSE CINSW3B SW3BLX Controller Driver SW3BFAULT EP I2C Internal Compensation SW3BFB Z2 VREF Z1 EA DAC Figure 21. SW3A/B Single Phase Block Diagram PF0100 68 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation SW3A/B Dual Phase SW3A/B can be connected in dual phase configuration using one inductor per switching node, as shown in Figure 22. This mode allows a smaller output voltage ripple. Feedback is taken from pin SW3AFB and pin SW3BFB must be left open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. In this configuration, the regulators switch 180 degrees apart. VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3 SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA I2C Interface DAC VIN SW3BIN SW3BMODE ISENSE CINSW3B SW3BLX LSW3B COSW3B Controller Driver SW3BFAULT EP I2C Internal Compensation SW3BFB Z2 VREF Z1 EA DAC Figure 22. SW3A/B Dual Phase Block Diagram PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 69 Functional Block Requirements and Behaviors Power Generation SW3A - SW3B Independent Outputs SW3A and SW3B can be configured as independent outputs as shown in Figure 23, providing flexibility for applications requiring more voltage rails with less current capability. Each output is configured and controlled independently by its respective I2C registers as shown in Table 66. VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3A SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA DAC VIN SW3BIN I2C Interface ISENSE CINSW3B SW3B SW3BLX LSW3B COSW3B SW3BMODE Controller Driver SW3BFAULT EP Internal Compensation SW3BFB I2C Z2 Z1 EA VREF DAC Figure 23. SW3A/B Independent Output Block Diagram SW3A/B Setup and Control Registers SW3A/B output voltage is programmable from 0.400 to 3.300 V; however, bit SW3x[6] in register SW3xVOLT is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW3x[6] is set to "0", the output will be limited to the lower output voltages from 0.40 to 1.975 V with 25 mV increments, as determined by bits SW3x[5:0]. Likewise, once bit SW3x[6] is set to "1", the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by bits SW3x[5:0]. In order to optimize the performance of the regulator, it is recommended that only voltages from 2.00 to 3.300 V be used in the high range and that that the lower range be used for voltages from 0.400 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW3x[5:0], SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively; however, the initial state of the SW3x[6] bit will be copied into the SW3xSTBY[6] and SW3xOFF[6] bits. Therefore, the output voltage range will remain the same on all three operating modes. Table 65 shows the output voltage coding valid for SW3x. Note: Voltage set points of 0.6 V and below are not supported. PF0100 70 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 65. SW3A/B Output Voltage Configuration Low Output Voltage Range(48) High Output Voltage Range Set Point SW3x[6:0] SW3x Output Set Point SW3x[6:0] SW3xOutput 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 71 Functional Block Requirements and Behaviors Power Generation Table 65. SW3A/B Output Voltage Configuration Low Output Voltage Range(48) High Output Voltage Range Set Point SW3x[6:0] SW3x Output Set Point SW3x[6:0] SW3xOutput 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 48. For voltages less than 2.0 V, only use set points 0 to 63. PF0100 72 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 66 provides a list of registers used to configure and operate SW3A/B. A detailed description on each of these register is provided on Tables 67 through Table 76. Table 66. SW3AB Register Summary Register Address Output SW3AVOLT 0x3C SW3A Output voltage set point on normal operation SW3ASTBY 0x3D SW3A Output voltage set point on Standby SW3AOFF 0x3E SW3A Output voltage set point on Sleep SW3AMODE 0x3F SW3A Switching mode selector register SW3ACONF 0x40 SW3A DVS, phase, frequency and ILIM configuration SW3BVOLT 0x43 SW3B Output voltage set point on normal operation SW3BSTBY 0x44 SW3B Output voltage set point on Standby SW3BOFF 0x45 SW3B Output voltage set point on Sleep SW3BMODE 0x46 SW3B Switching mode selector register SW3BCONF 0x47 SW3B DVS, phase, frequency and ILIM configuration Table 67. Register SW3AVOLT - ADDR 0x3C Name SW3A Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3A output voltage (Independent) or SW3A/B output voltage (Single/Dual phase), during normal operation mode. See Table 65 for all possible configurations. SW3A 6 R 0x00 Sets the operating output voltage range for SW3A (Independent) or SW3A/B (Single/Dual phase). Set during OTP or TBB configuration only. See Table 65 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 68. Register SW3ASTBY - ADDR 0x3D Name SW3ASTBY Bit # 5:0 R/W R/W Default Description 0x00 Sets the SW3A output voltage (Independent) or SW3A/B output voltage (Single/Dual phase), during Standby mode. See Table 65 for all possible configurations. SW3ASTBY 6 R 0x00 Sets the operating output voltage range for SW3A (Independent) or SW3A/B (Single/Dual phase) on Standby mode. This bit inherits the value configured on bit SW3A[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 - 0x00 UNUSED PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 73 Functional Block Requirements and Behaviors Power Generation Table 69. Register SW3AOFF - ADDR 0x3E Name SW3AOFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3A output voltage (Independent) or SW3A/B output voltage (Single/Dual phase), during Sleep mode. See Table 65 for all possible configurations. SW3AOFF 6 R 0x00 Sets the operating output voltage range for SW3A (Independent) or SW3A/B (Single/Dual phase) on Sleep mode. This bit inherits the value configured on bit SW3A[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 70. Register SW3AMODE - ADDR 0x3F Name SW3AMODE UNUSED SW3AOMODE UNUSED Bit # R/W Default Description 3:0 R/W 0x08 Sets the SW3A (Independent) or SW3A/B (Single/Dual phase) switching operation mode. See Table 30 for all possible configurations. 4 - 0x00 UNUSED 5 R/W 0x00 Set status of SW3A (Independent) or SW3A/B (Single/Dual phase) when in Sleep mode. 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED Table 71. Register SW3ACONF - ADDR 0x40 Name Bit # R/W Default Description SW3AILIM 0 R/W 0x00 SW3A current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW3AFREQ 3:2 R/W 0x00 SW3A switching frequency selector. See Table 38. SW3APHASE 5:4 R/W 0x00 SW3A Phase clock selection. See Table 36. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 35. Table 72. Register SW3BVOLT - ADDR 0x43 Name SW3B Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (Independent) during normal operation mode. See Table 65 for all possible configurations. SW3B 6 R 0x00 Sets the operating output voltage range for SW3B (Independent). Set during OTP or TBB configuration only. See Table 65 for all possible configurations. UNUSED 7 - 0x00 UNUSED PF0100 74 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 73. Register SW3BSTBY - ADDR 0x44 Name SW3BSTBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (Independent) during Standby mode. See Table 65 for all possible configurations. SW3BSTBY 6 R 0x00 Sets the operating output voltage range for SW3B (Independent) on Standby mode. This bit inherits the value configured on bit SW3B[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 74. Register SW3BOFF - ADDR 0x45 Name SW3BOFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (Independent) during Sleep mode. See Table 65 for all possible configurations. SW3BOFF 6 R 0x00 Sets the operating output voltage range for SW3B (Independent) on Sleep mode. This bit inherits the value configured on bit SW3B[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 75. Register SW3BMODE - ADDR 0x46 Name SW3BMODE UNUSED SW3BOMODE UNUSED Bit # R/W Default Description 3:0 R/W 0x08 Sets the SW3B (Independent) switching operation mode. See Table 30 for all possible configurations. 4 - 0x00 UNUSED 5 R/W 0x00 Set status of SW3B (Independent) when in Sleep mode. 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED Table 76. Register SW3BCONF - ADDR 0x47 Name Bit # R/W Default Description SW3BILIM 0 R/W 0x00 SW3B current limit level selection 0 = High level Current limit 1 = Low level Current limit UNUSED 1 R/W 0x00 Unused SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 38. SW3BPHASE 5:4 R/W 0x00 SW3B Phase clock selection. See Table 36. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 35. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 75 Functional Block Requirements and Behaviors Power Generation SW3A/B External Components Table 77. SW3A/B External Component Requirements Mode Components CINSW3A(49) Description SW3A/B Single Phase SW3A/B Dual Phase SW3A Independent SW3B Independent SW3A Input capacitor 4.7 F 4.7 F 4.7 F (49) SW3A Decoupling input capacitor 0.1 F 0.1 F 0.1 F (49) SW3B Input capacitor 4.7 F 4.7 F 4.7 F (49) SW3B Decoupling input capacitor 0.1 F 0.1 F 0.1 F COSW3A (49) SW3A Output capacitor 3 x 22 F 2 x 22 F 2 x 22 F COSW3B (49) SW3B Output capacitor - 2 x 22 F 2 x 22 F CIN3AHF CINSW3B CIN3BHF LSW3A SW3A Inductor 1.0 H 1.0 H 1.0 H LSW3B SW3B Inductor - 1.0 H 1.0 H Notes 49. Use X5R or X7R capacitors. SW3A/B Specifications Table 78. SW3A/B Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max VINSW3x VSW3x Unit 2.8 - 4.5 V - Table 65 - V -25 -3.0% -6.0% - - - 25 3.0% 6.0% -65 -45 -3.0% -3.0% - - - - 65 45 3.0% 3.0% - - - - 2500 1250 SWITCH MODE SUPPLY SW3A/B Operating Input Voltage(50) Nominal Output Voltage Output Voltage Accuracy * PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3x < ISW3xMAX 0.625 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V * PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3x < 50 mA) VSW3xACC 0.625 V < VSW3x < 0.675 V 0.7 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V Rated Output Load Current (51) * 2.8 V < VIN < 4.5 V, 0.625 V < VSW3x < 3.3 V PWM, APS mode single/dual phase PWM, APS mode independent (per phase) ISW3x mV % mA PF0100 76 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 78. SW3A/B Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max 3.5 2.7 5.0 3.8 6.5 4.9 Unit SWITCH MODE SUPPLY SW3A/B (CONTINUED) Current Limiter Peak Current Detection * Single phase (Current through inductor) SW3xILIM = 0 SW3xILIM = 1 ISW3xLIM * Independent mode or Dual phase (Current through inductor per phase) SW3xILIM = 0 SW3xILIM = 1 A 1.8 1.3 2.5 1.9 3.3 2.5 Start-up Overshoot ISW3x = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW3x = 4.5 V VSW3xOSH - - 66 mV Turn-on Time Enable to 90% of end value ISW3x = 0 mA DVS clk = 25 mV/4 s, VIN = VINSW3x = 4.5 V tONSW3x - - 500 s - - - 1.0 2.0 4.0 - - - - - - - - - 84 85 85 84 80 74 - - - - - - VSW3x - 10 - mV Line Regulation (APS, PWM) VSW3xLIR - - 20 mV DC Load Regulation (APS, PWM) VSW3xLOR - - 20 mV - - - - 50 50 - - - - - 22 300 50 250 150 - - - - - 215 245 258 326 Switching Frequency SW3xFREQ[1:0] = 00 SW3xFREQ[1:0] = 01 SW3xFREQ[1:0] = 10 fSW3x MHz Efficiency (Single Phase) * fSW3 = 2.0 MHz, LSW3x 1.0 H PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA Output Ripple Transient Load Regulation * Transient Load = 0.0 mA to ISW3x/2, di/dt = 100 mA/s Overshoot Undershoot Quiescent Current PFM Mode (Single/Dual Phase) APS Mode (Single/Dual Phase) PFM Mode (Independent mode) APS Mode (SW3A Independent mode) APS Mode (SW3B Independent mode) SW3AB VSW3xLOTR ISW3xQ SW3A P-MOSFET RDSON at VIN = VINSW3A = 3.3 V RONSW3AP - SW3A N-MOSFET RDSON at VIN = VINSW3A = 3.3 V RONSW3AN - % mV A m m PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 77 Functional Block Requirements and Behaviors Power Generation Table 78. SW3A/B Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit SW3A P-MOSFET Leakage Current VIN = VINSW3A = 4.5 V ISW3APQ - - 7.5 A SW3A N-MOSFET Leakage Current VIN = VINSW3A = 4.5 V ISW3ANQ - - 2.5 A SW3B P-MOSFET RDSON at VIN = VINSW3B = 3.3 V RONSW3BP - 215 245 SW3B N-MOSFET RDSON at VIN = VINSW3B = 3.3 V RONSW3BN - 258 326 SW3B P-MOSFET Leakage Current VIN = VINSW3B = 4.5 V ISW3BPQ - - 7.5 A SW3B N-MOSFET Leakage Current VIN = VINSW3B = 4.5 V ISW3BPQ - - 2.5 A Discharge Resistance RSW3xDIS - 600 - SWITCH MODE SUPPLY SW3A/B (CONTINUED) m m Notes 50. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V. 51. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance). PF0100 78 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) 70 (% y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 24. SW3AB Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.5 V; Consumer Version PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 79 Functional Block Requirements and Behaviors Power Generation Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 25. SW3AB Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.5 V; Extended Industrial Version 6.4.4.6 SW4 SW4 is a 1.0 A rated single phase buck regulator capable of operating in two modes. In its default mode, it operates as a normal buck regulator with a programmable output between 0.400 and 3.300 V. It is capable of operating in the three available switching modes: PFM, APS, and PWM, described on Table 30 and configured by the SW4MODE[3:0] bits, as shown in Table 31. If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage will track the output voltage of SW3A, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The VTT mode can be configured by use of VTT bit in the OTP_SW4_CONFIG register. Figure 26 shows the block diagram and the external component connections for the SW4 regulator. PF0100 80 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation VIN SW4IN SW4MODE ISENSE CINSW4 SW4 Controller SW4LX Driver LSW4 COSW4 SW4FAULT EP Internal Compensation SW4FB I2C Interface I2C Z2 Z1 VREF EA DAC Figure 26. SW4 Block Diagram SW4 Setup and Control Registers To set the SW4 in regulator or VTT mode, bit VTT of the register OTP_SW4_CONF register on Extended Page 1, is programmed during OTP or TBB configuration; setting bit VTT to "1" will enable SW4 to operate in VTT mode and "0" in Regulator mode. See One Time Programmability (OTP) for detailed information on OTP configuration. In Regulator mode, the SW4 output voltage is programmable from 0.400 to 3.300 V; however, bit SW4[6] in the SW4VOLT register is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Once SW4[6] is set to "0", the output will be limited to the lower output voltages, from 0.400 to 1.975 V with 25 mV increments, as determined by the SW4[5:0] bits. Likewise, once the SW4[6] bit is set to "1", the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits. In order to optimize the performance of the regulator, it is recommended that only voltages from 2.000 to 3.300 V be used in the high range and that that the lower range be used for voltages from 0.400 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW4[5:0], SW4STBY[5:0], and SW4OFF[5:0] bits, respectively. However, the initial state of the SW4[6] bit will be copied into bits SW4STBY[6], and SW4OFF[6] bits, so the output voltage range will remain the same on all three operating modes. Table 79 shows the output voltage coding valid for SW4. Note: Voltage set points of 0.6 V and below are not supported, except in the VTT mode. Table 79. SW4 Output Voltage Configuration Low Output Voltage Range(52) High Output Voltage Range Set Point SW4[6:0] SW4 Output Set Point SW4[6:0] SW4 Output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 81 Functional Block Requirements and Behaviors Power Generation Table 79. SW4 Output Voltage Configuration (continued) Low Output Voltage Range(52) High Output Voltage Range Set Point SW4[6:0] SW4 Output Set Point SW4[6:0] SW4 Output 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 PF0100 82 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 79. SW4 Output Voltage Configuration (continued) Low Output Voltage Range(52) High Output Voltage Range Set Point SW4[6:0] SW4 Output Set Point SW4[6:0] SW4 Output 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 52. For voltages less than 2.0 V, only use set points 0 to 63. Full setup and control of SW4 is done through the I2C registers listed on Table 80, and a detailed description of each one of the registers is provided in Tables 81 to Table 85. Table 80. SW4 Register Summary Register Address Description SW4VOLT 0x4A Output voltage set point on normal operation SW4STBY 0x4B Output voltage set point on Standby SW4OFF 0x4C Output voltage set point on Sleep SW4MODE 0x4D Switching mode selector register SW4CONF 0x4E DVS, phase, frequency and ILIM configuration Table 81. Register SW4VOLT - ADDR 0x4A Name Bit # R/W Default Description SW4 5:0 R/W 0x00 Sets the SW4 output voltage during normal operation mode. See Table 79 for all possible configurations. SW4 6 R 0x00 Sets the operating output voltage range for SW4. Set during OTP or TBB configuration only. See Table 79 for all possible configurations. UNUSED 7 - 0x00 UNUSED PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 83 Functional Block Requirements and Behaviors Power Generation Table 82. Register SW4STBY - ADDR 0x4B Name SW4STBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW4 output voltage during Standby mode. See Table 79 for all possible configurations. SW4STBY 6 R 0x00 Sets the operating output voltage range for SW4 on Standby mode. This bit inherits the value configured on bit SW4[6] during OTP or TBB configuration. See Table 79 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 83. Register SW4OFF - ADDR 0x4C Name SW4OFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW4 output voltage during Sleep mode. See Table 79 for all possible configurations. SW4OFF 6 R 0x00 Sets the operating output voltage range for SW4 on Sleep mode. This bit inherits the value configured on bit SW4[6] during OTP or TBB configuration. See Table 79 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 84. Register SW4MODE - ADDR 0x4D Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW4 switching operation mode. See Table 30 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW4OMODE 5 R/W 0x00 Set status of SW4 when in Sleep mode 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW4MODE UNUSED Description Table 85. Register SW4CONF - ADDR 0x4E Name Bit # R/W Default Description SW4ILIM 0 R/W 0x00 SW4 current limit level selection 0 = High level Current limit 1 = Low level Current limit UNUSED 1 R/W 0x00 Unused SW4FREQ 3:2 R/W 0x00 SW4 switching frequency selector. See Table 38. SW4PHASE 5:4 R/W 0x00 SW4 Phase clock selection. See Table 36. SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 35. PF0100 84 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation SW4 External Components Table 86. SW4 External Component Requirements Components CINSW4(53) CIN4HF Description Values SW4 Input capacitor 4.7 F (53) SW4 Decoupling input capacitor 0.1 F (53) SW4 Output capacitor COSW4 LSW4 3 x 22 F 1.0 H SW4 Inductor Notes 53. Use X5R or X7R capacitors SW4 Specifications Table 87. SW4 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit VINSW4 2.8 - 4.5 V VSW4 - - Table 79 VSW3AFB/2 - - V -25 -3.0 -6.0 - - - 25 3.0 6.0 mV % % -65 -45 -3.0 -3.0 - - - - 65 45 3.0 3.0 mV mV % % -40 - 40 mV - - 1000 mA 1.4 1.0 2.0 1.5 3.0 2.4 - - 66 SWITCH MODE SUPPLY SW4 Operating Input Voltage (54) Nominal Output Voltage Normal operation VTT Mode Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A 0.625 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V 2.0 V < VSW4 < 3.3 V * PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA VSW4ACC 0.625 V < VSW4 < 0.675 V 0.7 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V 2.0 V < VSW4 < 3.3 V * VTT Mode , 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A Rated Output Load Current (55) 2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 3.3 V Current Limiter Peak Current Detection Current through inductor SW4ILIM = 0 SW4ILIM = 1 Start-up Overshoot ISW4 = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW4 = 4.5 V ISW4 ISW4LIM VSW4OSH A mV PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 85 Functional Block Requirements and Behaviors Power Generation Table 87. SW4 Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit tONSW4 - - 500 s - - - 1.0 2.0 4.0 - - - - - - - - 81 78 87 88 83 - - - - - - - - 78 76 66 - - - VSW4 - 10 - mV Line Regulation (APS, PWM) VSW4LIR - - 20 mV DC Load Regulation (APS, PWM) VSW4LOR - - 20 mV Transient Load Regulation * Transient Load = 0.0 mA to 500 mA, di/dt = 100 mA/s Overshoot Undershoot VSW4LOTR - - - - ISW4Q - - 22 145 - - A SW4 P-MOSFET RDSON at VIN = VINSW4 = 3.3 V RONSW4P - 236 274 m SW4 N-MOSFET RDSON at VIN = VINSW4 = 3.3 V RONSW4N - 293 378 m SW4 P-MOSFET Leakage Current VIN = VINSW4 = 4.5 V ISW4PQ - - 6.0 A SW4 N-MOSFET Leakage Current VIN = VINSW4 = 4.5 V ISW4NQ - - 2.0 A Discharge Resistance RSW4DIS - 600 - SWITCH MODE SUPPLY SW4 (CONTINUED) Turn-on Time Enable to 90% of end value ISW4 = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW4 = 4.5 V Switching Frequency SW4FREQ[1:0] = 00 SW4FREQ[1:0] = 01 SW4FREQ[1:0] = 10 fSW4 MHz Efficiency * fSW4 = 2.0 MHz, LSW4 = 1.0 H PFM, 1.8 V, 1.0 mA PFM, 1.8 V, 50 mA APS, PWM 1.8 V, 200 mA APS, PWM 1.8 V, 500 mA APS, PWM 1.8 V, 1000 mA SW4 PWM 0.75 V, 200 mA PWM 0.75 V, 500 mA PWM 0.75 V, 1000 mA Output Ripple Quiescent Current PFM Mode APS Mode 50 50 % mV Notes 54. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V. 55. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW4 - VSW4) = ISW4* (DCR of Inductor +RONSW4P + PCB trace resistance). PF0100 86 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 90 80 Efficiency (%) 70 ) % ( 60 y 50 c n e i 40 c if f 30 E 20 PFM 10 0 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c fif 40 E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 27. SW4 Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.8 V; Consumer Version PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 87 Functional Block Requirements and Behaviors Power Generation 90 80 Efficiency (%) 70 ) % ( 60 y c 50 n e i 40 c if f 30 E 20 PFM 10 0 0.1 1 10 100 1000 Load Current (mA) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 28. SW4 Efficiency Waveforms: VIN = 4.2 V; VOUT = 1.8 V; Extended Industrial Version 6.4.5 Boost Regulator SWBST is a boost regulator with a programmable output from 5.0 to 5.15 V. SWBST can supply the VUSB regulator for the USB PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator will cause the SWBSTOUT and SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. Figure 29 shows the block diagram and component connection for the boost regulator. PF0100 88 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation VIN CINBST VOBST LBST SWBSTIN DBST SWBSTMODE SWBSTLX Driver OC RSENSE EP VREFSC Controller SWBSTFAULT I2C Interface SC VREFUV UV SWBSTFB Internal Compensation Z2 COSWBST Z1 EA VREF Figure 29. Boost Regulator Architecture 6.4.5.1 SWBST Setup and Control Boost regulator control is done through a single register SWBSTCTL described in Table 88. SWBST is included in the power-up sequence if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros. Table 88. Register SWBSTCTL - ADDR 0x66 Name Bit # SWBST1VOLT SWBST1MODE UNUSED SWBST1STBYMODE UNUSED 1:0 R/W R/W Default Description 0x00 Set the output voltage for SWBST 00 = 5.000 V 01 = 5.050 V 10 = 5.100 V 11 = 5.150 V 3:2 R 0x02 Set the Switching mode on Normal operation 00 = OFF 01 = PFM 10 = Auto (Default)(56) 11 = APS 4 - 0x00 UNUSED 6:5 R/W 0x02 Set the Switching mode on Standby 00 = OFF 01 = PFM 10 = Auto (Default)(56) 11 = APS 7 - 0x00 UNUSED Notes 56. In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current. The SWBST regulator starts up by default in the Auto mode if SWBST is part of the startup sequence. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 89 Functional Block Requirements and Behaviors Power Generation 6.4.5.2 SWBST External Components Table 89. SWBST External Component Requirements Components CINBST (57) CINBSTHF COBST (57) (57) Description Values SWBST input capacitor 10 F SWBST decoupling input capacitor 0.1 F 2 x 22 F SWBST output capacitor 2.2 H LSBST SWBST inductor DBST SWBST boost diode 1.0 A, 20 V Schottky Notes 57. Use X5R or X7R capacitors. 6.4.5.3 SWBST Specifications Table 90. SWBST Electrical Specifications All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 C, unless otherwise noted. Parameters Symbol Min Typ Max Units VINSWBST 2.8 - 4.5 V VSWBST - Table 88 - V VSWBSTACC -4.0 - 3.0 % VSWBST - - 120 mV Vp-p DC Load Regulation 0 < ISWBST < ISWBSTMAX VSWBSTLOR - 0.5 - mV/ mA DC Line Regulation 2.8 V VIN 4.5 V, ISWBST = ISWBSTMAX VSWBSTLIR - 50 - mV ISWBST - - - - 500 600 mA ISWBSTQ - 222 289 A RDSONBST - 206 306 m ISWBSTLIM 1400 2200 3200 mA VSWBSTOSH - - 500 mV Transient Load Response ISWBST from 1.0 to 100 mA in 1.0 s Maximum transient Amplitude VSWBSTTR - - 300 mV Transient Load Response ISWBST from 100 to 1.0 mA in 1.0 s Maximum transient Amplitude VSWBSTTR - - 300 mV SWITCH MODE SUPPLY SWBST Input Voltage Range Nominal Output Voltage Output Voltage Accuracy 2.8 V VIN 4.5 V 0 < ISWBST < ISWBSTMAX Output Ripple 2.8 V VIN 4.5 V 0 < ISWBST < ISWBSTMAX, excluding reverse recovery of Schottky diode Continuous Load Current 2.8 V VIN 3.0 V 3.0 V VIN 4.5 V Quiescent Current AUTO MOSFET on Resistance Peak Current Limit (58) Start-up Overshoot ISWBST = 0.0 mA PF0100 90 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 90. SWBST Electrical Specifications (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 C, unless otherwise noted. Parameters Symbol Min Typ Max Units Transient Load Response ISWBST from 1.0 to 100 mA in 1.0 s Time to settle 80% of transient tSWBSTTR - - 500 s Transient Load Response ISWBST from 100 to 1.0 mA in 1.0 s Time to settle 80% of transient tSWBSTTR - - 20 ms NMOS Off Leakage SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00 ISWBSTHSQ - 1.0 5.0 A Turn-on Time Enable to 90% of VSWBST, ISWBST = 0.0 mA tONSWBST - - 2.0 ms Switching Frequency fSWBST - 2.0 - MHz Efficiency ISWBST = ISWBSTMAX SWBST - 86 - % SWITCH MODE SUPPLY SWBST (CONTINUED) Notes 58. Only in Auto mode. 6.4.6 LDO Regulators Description This section describes the LDO regulators provided by the PF0100. All regulators use the main bandgap as reference. Refer to Bias and References Block Description section for further information on the internal reference voltages. A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest bias currents may be attained by forcing the part into its Low Power mode by setting the VGENxLPWR bit. The use of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 91 Functional Block Requirements and Behaviors Power Generation VINx VINx VREF _ VGENxEN + VGENxLPWR VGENx VGENx I2C Interface CGENx VGENx Discharge Figure 30. General LDO Block Diagram PF0100 92 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.6.1 Transient Response Waveforms Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 31. Note that the transient line and load response refers to the overshoot, or undershoot only, excluding the DC shift. IMAX ILOAD IMAX/10 1.0 us 1.0 us Transient Load Stimulus IL = IMAX/10 IL = IMAX Overshoot VOUT Undershoot VOUT Transient Load Response VINx_INITIAL VINx VINx_FINAL 10 us 10 us Transient Line Stimulus VINx_INITIAL VINx_FINAL Overshoot VOUT Undershoot VOUT Transient Line Response Figure 31. Transient Waveforms PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 93 Functional Block Requirements and Behaviors Power Generation 6.4.6.2 Short-circuit Protection All general purpose LDOs have short-circuit protection capability. The Short-circuit Protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VGENxEN bit, while at the same time, an interrupt VGENxFAULTI will be generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the VGENxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators will not automatically be disabled upon a short-circuit detection. However, the current limiter will continue to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, VGENxFAULTI, will be generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 91 for SCP behavior configuration. Table 91. Short-circuit Behavior 6.4.6.3 REGSCPEN[0] Short-circuit Behavior 0 Current limit 1 Shutdown LDO Regulator Control Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage according to Table 92 for VGEN1 and VGEN2; and uses the voltage set point on Table 93 for VGEN3 through VGEN6. Table 92. VGEN1, VGEN2 Output Voltage Configuration Set Point VGENx[3:0] VGENx Output (V) 0 0000 0.800 1 0001 0.850 2 0010 0.900 3 0011 0.950 4 0100 1.000 5 0101 1.050 6 0110 1.100 7 0111 1.150 8 1000 1.200 9 1001 1.250 10 1010 1.300 11 1011 1.350 12 1100 1.400 13 1101 1.450 14 1110 1.500 15 1111 1.550 PF0100 94 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 93. VGEN3/ 4/ 5/ 6 Output Voltage Configuration Set Point VGENx[3:0] VGENx Output (V) 0 0000 1.80 1 0001 1.90 2 0010 2.00 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as programmed to stay "ON" or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 94 presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output. Table 94. LDO Control VGENxEN VGENxLPWR VGENxSTBY STANDBY(59) VGENxOUT 0 X X X Off 1 0 0 X On 1 1 0 X Low Power 1 X 1 0 On 1 0 1 1 Off 1 1 1 1 Low Power Notes 59. STANDBY refers to a Standby event as described earlier. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 95 Functional Block Requirements and Behaviors Power Generation For more detail information, Table 95 through Table 100 provide a description of all registers necessary to operate all six general purpose LDO regulators. Table 95. Register VGEN1CTL - ADDR 0x6C Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 92 for all possible configurations. VGEN1EN 4 - 0x00 Enables or Disables VGEN1 output 0 = OFF 1 = ON VGEN1STBY 5 R/W 0x00 Set VGEN1 output state when in Standby. Refer to Table 94. VGEN1LPWR 6 R/W 0x00 Enable Low Power Mode for VGEN1. Refer to Table 94. UNUSED 7 - 0x00 UNUSED VGEN1 Description Table 96. Register VGEN2CTL - ADDR 0x6D Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 92 for all possible configurations. VGEN2EN 4 - 0x00 Enables or Disables VGEN2 output 0 = OFF 1 = ON VGEN2STBY 5 R/W 0x00 Set VGEN2 output state when in Standby. Refer to Table 94. VGEN2LPWR 6 R/W 0x00 Enable Low Power Mode for VGEN2. Refer to Table 94. UNUSED 7 - 0x00 UNUSED VGEN2 Description Table 97. Register VGEN3CTL - ADDR 0x6E Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 93 for all possible configurations. VGEN3EN 4 - 0x00 Enables or Disables VGEN3 output 0 = OFF 1 = ON VGEN3STBY 5 R/W 0x00 Set VGEN3 output state when in Standby. Refer to Table 94. VGEN3LPWR 6 R/W 0x00 Enable Low Power Mode for VGEN3. Refer to Table 94. UNUSED 7 - 0x00 UNUSED VGEN3 Description PF0100 96 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 98. Register VGEN4CTL - ADDR 0x6F Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 93 for all possible configurations. VGEN4EN 4 - 0x00 Enables or Disables VGEN4 output 0 = OFF 1 = ON VGEN4STBY 5 R/W 0x00 Set VGEN4 output state when in Standby. Refer to Table 94. VGEN4LPWR 6 R/W 0x00 Enable Low Power Mode for VGEN4. Refer to Table 94. UNUSED 7 - 0x00 UNUSED VGEN4 Description Table 99. Register VGEN5CTL - ADDR 0x70 Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 93 for all possible configurations. VGEN5EN 4 - 0x00 Enables or Disables VGEN5 output 0 = OFF 1 = ON VGEN5STBY 5 R/W 0x00 Set VGEN5 output state when in Standby. Refer to Table 94. VGEN5LPWR 6 R/W 0x00 Enable Low Power Mode for VGEN5. Refer to Table 94. UNUSED 7 - 0x00 UNUSED VGEN5 Description Table 100. Register VGEN6CTL - ADDR 0x71 Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 93 for all possible configurations. VGEN6EN 4 - 0x00 Enables or Disables VGEN6 output 0 = OFF 1 = ON VGEN6STBY 5 R/W 0x00 Set VGEN6 output state when in Standby. Refer to Table 94. VGEN6LPWR 6 R/W 0x00 Enable Low Power Mode for VGEN6. Refer to Table 94. UNUSED 7 - 0x00 UNUSED VGEN6 Description PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 97 Functional Block Requirements and Behaviors Power Generation 6.4.6.4 External Components Table 101 lists the typical component values for the general purpose LDO regulators. Table 101. LDO External Components Regulator Output Capacitor (F)(60) VGEN1 2.2 VGEN2 4.7 VGEN3 2.2 VGEN4 4.7 VGEN5 2.2 VGEN6 2.2 Notes 60. 6.4.6.5 Use X5R/X7R ceramic capacitors. LDO Specifications VGEN1 Table 102. VGEN1 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit Operating Input Voltage VIN1 1.75 - 3.40 V Nominal Output Voltage VGEN1NOM - Table 92 - V Operating Load Current IGEN1 0.0 - 100 mA Output Voltage Tolerance 1.75 V < VIN1 < 3.4 V 0.0 mA < IGEN1 < 100 mA VGEN1[3:0] = 0000 to 1111 VGEN1TOL -3.0 - 3.0 % Load Regulation (VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA) For any 1.75 V < VIN1 < 3.4 V VGEN1LOR - 0.15 - mV/ mA Line Regulation (VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V) For any 0.0 mA < IGEN1 < 100 mA VGEN1LIR - 0.30 - mV/ mA Current Limit IGEN1 when VGEN1 is forced to VGEN1NOM/2 IGEN1LIM 122 167 200 mA Overcurrent Protection Threshold IGEN1 required to cause the SCP function to disable LDO when REGSCPEN = 1 IGEN1OCP 115 - 200 mA IGEN1Q - 14 - A VGEN1 VGEN1 DC Quiescent Current No load, Change in IVIN and IVIN1 When VGEN1 enabled PF0100 98 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 102. VGEN1 Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max 50 37 60 45 - - - - - -108 -118 -124 -100 -108 -112 - - - - 12.5 16.5 Unit VGEN1 AC AND TRANSIENT PSRR(61) * IGEN1 = 75 mA, 20 Hz to 20 kHz VGEN1[3:0] = 0000 - 1101 VGEN1[3:0] = 1110, 1111 Output Noise Density VIN1 = 1.75 V, IGEN1 = 75 mA 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz Turn-on Slew Rate * 10% to 90% of end value * 1.75 V VIN1 3.4 V, IGEN1 = 0.0 mA PSRRVGEN1 NOISEVGEN1 SLWRVGEN1 VGEN1[3:0] = 0000 to 0111 VGEN1[3:0] = 1000 to 1111 dB dBV/ Hz mVs Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN1 = 0.0 mA GEN1tON 60 - 500 s Turn-Off Time Disable to 10% of initial value, VIN1 = 1.75 V IGEN1 = 0.0 mA GEN1tOFF - - 10 ms Start-Up Overshoot VIN1 = 1.75 V, 3.4 V, IGEN1 = 0.0 mA GEN1OSHT - 1.0 2.0 % VGEN1LOTR - - 3.0 % VGEN1LITR - 5.0 8.0 mV Transient Load Response * VIN1 = 1.75 V, 3.4 V * IGEN1 = 10 to 100 mA in 1.0 s. Peak of overshoot or undershoot of VGEN1 with respect to final value Refer to Figure 31 Transient Line Response * IGEN1 = 75 mA * VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN1[3:0] = 0000 to 1101 VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for VGEN1[3:0] = 1110, 1111 Refer to Figure 31 Notes 61. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 99 Functional Block Requirements and Behaviors Power Generation VGEN2 Table 103. VGEN2 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25C, unless otherwise noted. Parameter Symbol Min Typ Max Unit Operating Input Voltage VIN1 1.75 - 3.40 V Nominal Output Voltage VGEN2NOM - Table 92 - V Operating Load Current IGEN2 0.0 - 250 mA Output VoltageTolerance 1.75 V < VIN1 < 3.4 V 0.0 mA < IGEN2 < 250 mA VGEN2[3:0] = 0000 to 1111 VGEN2TOL -3.0 - 3.0 % Load Regulation (VGEN2 at IGEN2 = 250 mA) - (VGEN2 at IGEN2 = 0.0 mA) For any 1.75 V < VIN1 < 3.4 V VGEN2LOR - 0.05 - mV/ mA Line Regulation (VGEN2 at VIN1 = 3.4 V) - (VGEN2 at VIN1 = 1.75 V) For any 0.0 mA < IGEN2 < 250 mA VGEN2LIR - 0.50 - mV/ mA Current Limit IGEN2 when VGEN2 is forced to VGEN2NOM/2 MMPF0100 MMPF0100A IGEN2LIM 333 305 417 417 510 510 Overcurrent Protection Threshold IGEN2 required to cause the SCP function to disable LDO when REGSCPEN = 1 MMPF0100 MMPF0100A IGEN2OCP 300 290 - - 500 500 - 16 - 50 37 60 45 - - - - - -108 -118 -124 -100 -108 -112 - - - - 12.5 16.5 VGEN2 VGEN2 ACTIVE MODE - DC Quiescent Current No load, Change in IVIN and IVIN1 When VGEN2 enabled IGEN2Q mA mA A VGEN2 AC AND TRANSIENT PSRR(62) * IGEN2 = 187.5 mA, 20 Hz to 20 kHz VGEN2[3:0] = 0000 - 1101 VGEN2[3:0] = 1110, 1111 PSRRVGEN2 Output Noise Density * VIN1 = 1.75 V, IGEN2 = 187.5 mA 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz Turn-On Slew Rate * 10% to 90% of end value * 1.75 V VIN1 3.4 V, IGEN2 = 0.0 mA VGEN2[3:0] = 0000 to 0111 VGEN2[3:0] = 1000 to 1111 NOISEVGEN2 SLWRVGEN2 dB dBV/ Hz mVs PF0100 100 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 103. VGEN2 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25C, unless otherwise noted. Parameter Symbol Min Typ Max Unit Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN2 = 0.0 mA GEN2tON 60 - 500 s Turn-Off Time Disable to 10% of initial value, VIN1 = 1.75 V IGEN2 = 0.0 mA GEN2tOFF - - 10 ms Start-up Overshoot VIN1 = 1.75 V, 3.4 V, IGEN2 = 0.0 mA GEN2OSHT - 1.0 2.0 % Transient Load Response VIN1 = 1.75 V, 3.4 V IGEN2 = 25 to 250 mA in 1.0 s Peak of overshoot or undershoot of VGEN2 with respect to final value Refer to Figure 31 VGEN2LOTR - - 3.0 % Transient Line Response IGEN2 = 187.5 mA VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN2[3:0] = 0000 to 1101 VIN1INITIAL = VGEN2+0.3 V to VIN1FINAL = VGEN2+0.8 V for VGEN2[3:0] = 1110, 1111 Refer to Figure 31 VGEN2LITR - 5.0 8.0 mV VGEN2 AC AND TRANSIENT (CONTINUED) Notes 62. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 101 Functional Block Requirements and Behaviors Power Generation VGEN3 Table 104. VGEN3 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit 2.8 VGEN3NOM+ 0.250 - - 3.6 3.6 V VGEN3 Operating Input Voltage 1.8 V VGEN3NOM 2.5 V 2.6 V VGEN3NOM 3.3 V(63) VIN2 Nominal Output Voltage VGEN3NOM - Table 93 - V Operating Load Current IGEN3 0.0 - 100 mA Output Voltage Tolerance VIN2MIN < VIN2 < 3.6 V 0.0 mA < IGEN3 < 100 mA VGEN3[3:0] = 0000 to 1111 VGEN3TOL -3.0 - 3.0 % Load Regulation (VGEN3 at IGEN3 = 100 mA) - (VGEN3 at IGEN3 = 0.0 mA) For any VIN2MIN < VIN2 < 3.6 V VGEN3LOR - 0.07 - mV/ mA Line Regulation (VGEN3 at VIN2 = 3.6 V) - (VGEN3 at VIN2MIN ) For any 0.0 mA < IGEN3 < 100 mA VGEN3LIR - 0.8 - mV/ mA Current Limit IGEN3 when VGEN3 is forced to VGEN3NOM/2 IGEN3LIM 127 167 200 mA Over-current Protection Threshold IGEN3 required to cause the SCP function to disable LDO when REGSCPEN = 1 IGEN3OCP 120 - 200 mA IGEN3Q - 13 - A 35 55 40 60 - - NOISEVGEN3 - - - -114 -129 -135 -102 -123 -130 SLWRVGEN3 - - - - - - - - 22.0 26.5 30.5 34.5 VGEN3 DC Quiescent Current No load, Change in IVIN and IVIN2 When VGEN3 enabled VGEN3 AC AND TRANSIENT PSRR(64) * IGEN3 = 75 mA, 20 Hz to 20 kHz VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V PSRRVGEN3 Output Noise Density * VIN2 = VIN2MIN, IGEN3 = 75 mA 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz dB dBV/ Hz Turn-On Slew Rate * 10% to 90% of end value * VIN2MINVIN2 3.6 V, IGEN3 = 0.0 mA VGEN3[3:0] = 0000 to 0011 VGEN3[3:0] = 0100 to 0111 VGEN3[3:0] = 1000 to 1011 VGEN3[3:0] = 1100 to 1111 mVs PF0100 102 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 104. VGEN3 Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit Turn-On Time Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V IGEN3 = 0.0 mA GEN3tON 60 - 500 s Turn-Off Time Disable to 10% of initial value, VIN2 = VIN2MIN IGEN3 = 0.0 mA GEN3tOFF - - 10 ms Start-up Overshoot VIN2 = VIN2MIN, 3.6 V, IGEN3 = 0.0 mA GEN3OSHT - 1.0 2.0 % Transient Load Response VIN2 = VIN2MIN, 3.6 V IGEN3 = 10 to 100 mA in 1.0s Peak of overshoot or undershoot of VGEN3 with respect to final value. Refer to Figure 31 VGEN3LOTR - - 3.0 % Transient Line Response IGEN3 = 75 mA VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for GEN3[3:0] = 0000 to 0111 VIN2INITIAL = VGEN3+0.3 V to VIN2FINAL = VGEN3+0.8 V for VGEN3[3:0] = 1000 to 1010 VIN2INITIAL = VGEN3+0.25 V to VIN2FINAL = 3.6 V for VGEN3[3:0] = 1011 to 1111 Refer to Figure 31 VGEN3LITR - 5.0 8.0 mV VGEN3 AC AND TRANSIENT (CONTINUED) Notes 63. When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper regulation due to the dropout voltage generated through the internal LDO transistor. 64. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 103 Functional Block Requirements and Behaviors Power Generation VGEN4 Table 105. VGEN4 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit 2.8 VGEN4NOM+ 0.250 - - 3.6 3.6 V VGEN4 Operating Input Voltage 1.8 V VGEN4NOM 2.5 V 2.6 V VGEN4NOM 3.3 V(65) VIN2 Nominal Output Voltage VGEN4NOM - Table 93 - V Operating Load Current IGEN4 0.0 - 350 mA Output Voltage Tolerance VIN2MIN < VIN2 < 3.6 V 0.0 mA < IGEN4 < 350 mA VGEN4[3:0] = 0000 to 1111 VGEN4TOL -3.0 - 3.0 % Load Regulation (VGEN4 at IGEN4 = 350 mA) - (VGEN4 at IGEN4 = 0.0 mA ) For any VIN2MIN < VIN2 < 3.6 V VGEN4LOR - 0.07 - mV/ mA Line Regulation (VGEN4 at 3.6 V) - (VGEN4 at VIN2MIN) For any 0.0 mA < IGEN4 < 350 mA VGEN4LIR - 0.80 - mV/ mA Current Limit IGEN4 when VGEN4 is forced to VGEN4NOM/2 IGEN4LIM 435 584.5 700 mA Over-current Protection Threshold IGEN4 required to cause the SCP function to disable LDO when REGSCPEN = 1 IGEN4OCP 420 - 700 mA IGEN4Q - 13 - A 35 55 40 60 - - NOISEVGEN4 - - - -114 -129 -135 -102 -123 -130 SLWRVGEN4 - - - - - - - - 22.0 26.5 30.5 34.5 VGEN4 DC Quiescent Current No load, Change in IVIN and IVIN2 When VGEN4 enabled VGEN4 AC AND TRANSIENT PSRR(66) * IGEN4 = 262.5 mA, 20 Hz to 20 kHz VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V PSRRVGEN4 Output Noise Density * VIN2 = VIN2MIN, IGEN4 = 262.5 mA 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz dB dBV/ Hz Turn-On Slew Rate * 10% to 90% of end value * VIN2MIN VIN2 3.6 V, IGEN4 = 0.0 mA VGEN4[3:0] = 0000 to 0011 VGEN4[3:0] = 0100 to 0111 VGEN4[3:0] = 1000 to 1011 VGEN4[3:0] = 1100 to 1111 mVs PF0100 104 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 105. VGEN4 Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit GEN4tON 60 - 500 s Turn-Off Time Disable to 10% of initial value, VIN2 = VIN2MIN IGEN4 = 0.0 mA GEN4tOFF - - 10 ms Start-up Overshoot VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA GEN4OSHT - 1.0 2.0 % Transient Load Response VIN2 = VIN2MIN, 3.6 V IGEN4 = 35 to 350 mA in 1.0 s Peak of overshoot or undershoot of VGEN4 with respect to final value. Refer to Figure 31 VGEN4LOTR - - 3.0 % Transient Line Response IGEN4 = 262.5 mA VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for VGEN4[3:0] = 0000 to 0111 VIN2INITIAL = VGEN4+0.3 V to VIN2FINAL = VGEN4+0.8 V for VGEN4[3:0] = 1000 to 1010 VIN2INITIAL = VGEN4+0.25 V to VIN2FINAL = 3.6 V for VGEN4[3:0] = 1011 to 1111 Refer to Figure 31 VGEN4LITR - 5.0 8.0 mV VGEN4 AC AND TRANSIENT (CONTINUED) Turn-On Time Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V IGEN4 = 0.0 mA Notes 65. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 66. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 105 Functional Block Requirements and Behaviors Power Generation VGEN5 Table 106. VGEN5 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit 2.8 VGEN5NOM+ 0.250 - - 4.5 4.5 V VGEN5 Operating Input Voltage 1.8 V VGEN5NOM 2.5 V 2.6 V VGEN5NOM 3.3 V(67) VIN3 Nominal Output Voltage VGEN5NOM - Table 93 - V Operating Load Current IGEN5 0.0 - 100 mA Output Voltage Tolerance VIN3MIN < VIN3 < 4.5 V 0.0 mA < IGEN5 < 100 mA VGEN5[3:0] = 0000 to 1111 VGEN5TOL -3.0 - 3.0 % Load Regulation (VGEN5 at IGEN5 = 100 mA) - (VGEN5 at IGEN5 = 0.0 mA) For any VIN3MIN < VIN3 < 4.5 mV VGEN5LOR - 0.10 - mV/ mA Line Regulation (VGEN5 at VIN3 = 4.5 V) - (VGEN5 at VIN3MIN) For any 0.0 mA < IGEN5 < 100 mA VGEN5LIR - 0.50 - mV/ mA Current Limit IGEN5 when VGEN5 is forced to VGEN5NOM/2 IGEN5LIM 122 167 200 mA Over-current Protection threshold IGEN5 required to cause the SCP function to disable LDO when REGSCPEN = 1 IGEN5OCP 120 - 200 mA IGEN5Q - 13 - A 35 52 40 60 - - NOISEVGEN5 - - - -114 -129 -135 -102 -123 -130 SLWRVGEN5 - - - - - - - - 22.0 26.5 30.5 34.5 VGEN5 ACTIVE MODE - DC Quiescent Current No load, Change in IVIN and IVIN3 When VGEN5 enabled VGEN5 AC AND TRANSIENT PSRR(68) * IGEN5 = 75 mA, 20 Hz to 20 kHz VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V PSRRVGEN5 Output Noise Density * VIN3 = VIN3MIN, IGEN5 = 75 mA 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz dB dBV/ Hz Turn-On Slew Rate * 10% to 90% of end value * VIN3MIN VIN3 4.5 mV, IGEN5 = 0.0 mA VGEN5[3:0] = 0000 to 0011 VGEN5[3:0] = 0100 to 0111 VGEN5[3:0] = 1000 to 1011 VGEN5[3:0] = 1100 to 1111 mVs PF0100 106 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 106. VGEN5 Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit Turn-On Time Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V IGEN5 = 0.0 mA GEN5tON 60 - 500 s Turn-Off Time Disable to 10% of initial value, VIN3 = VIN3MIN IGEN5 = 0.0 mA GEN5tOFF - - 10 ms Start-Up Overshoot VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA GEN5OSHT - 1.0 2.0 % Transient Load Response VIN3 = VIN3MIN, 4.5 V IGEN5 = 10 to 100 mA in 1.0 s Peak of overshoot or undershoot of VGEN5 with respect to final value. Refer to Figure 31 VGEN5LOTR - - 3.0 % Transient Line Response IGEN5 = 75 mA VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN5[3:0] = 0000 to 0111 VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for VGEN5[3:0] = 1000 to 1111 Refer to Figure 31 VGEN5LITR - 5.0 8.0 mV VGEN5 ACTIVE MODE - DC (CONTINUED) Notes 67. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 68. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 107 Functional Block Requirements and Behaviors Power Generation VGEN6 Table 107. VGEN6 Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit VIN3 2.8 VGEN6NOM+ 0.250 - - 4.5 4.5 V Nominal Output Voltage VGEN6NOM - Table 93 - V Operating Load Current IGEN6 0.0 - 200 mA Output Voltage Tolerance VIN3MIN < VIN3 < 4.5 V 0.0 mA < IGEN6 < 200 mA VGEN6[3:0] = 0000 to 1111 VGEN6TOL -3.0 - 3.0 % Load Regulation (VGEN6 at IGEN6 = 200 mA) - (VGEN6 at IGEN6 = 0.0 mA) For any VIN3MIN < VIN3 < 4.5 V VGEN6LOR - 0.10 - mV/ mA Line Regulation (VGEN6 at VIN3 = 4.5 V) - (VGEN6 at VIN3MIN) For any 0.0 mA < IGEN6 < 200 mA VGEN6LIR - 0.50 - mV/ mA Current Limit IGEN6 when VGEN6 is forced to VGEN6NOM/2 MMPF0100 MMPF0100A IGEN6LIM 232 232 333 333 400 475 Over Current Protection Threshold IGEN6 required to cause the SCP function to disable LDO when REGSCPEN = 1 MMPF0100 MMPF0100A IGEN6OCP 220 220 - - 400 475 - 13 - 35 52 40 60 - - - - - -114 -129 -135 -102 -123 -130 VGEN6 Operating Input Voltage 1.8 V VGEN6NOM 2.5 V 2.6 V VGEN6NOM 3.3 V(69) VGEN6 DC Quiescent Current No load, Change in IVIN and IVIN3 When VGEN6 enabled IGEN6Q mA mA A VGEN6 AC AND TRANSIENT PSRR(70) * IGEN6 = 150 mA, 20 Hz to 20 kHz VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V PSRRVGEN6 Output Noise Density * VIN3 = VIN3MIN, IGEN6 = 150 mA 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz NOISEVGEN6 dB dBV/ Hz PF0100 108 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 107. VGEN6 Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit SLWRVGEN6 - - - - - - - - 22.0 26.5 30.5 34.5 mVs GEN6tON 60 - 500 s Turn-Off Time Disable to 10% of initial value, VIN3 = VIN3MIN IGEN6 = 0.0 mA GEN6tOFF - - 10 ms Start-Up Overshoot VIN3 = VIN3MIN, 4.5 V, IGEN6 = 0 mA GEN6OSHT - 1.0 2.0 % Transient Load Response VIN3 = VIN3MIN, 4.5 V IGEN6 = 20 to 200 mA in 1.0 s Peak of overshoot or undershoot of VGEN6 with respect to final value. Refer to Figure 31 VGEN6LOTR - - 3.0 % Transient Line Response IGEN6 = 150 mA VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN6[3:0] = 0000 to 0111 VIN3INITIAL = VGEN6+0.3 V to VIN3FINAL = VGEN6+0.8 V for VGEN6[3:0] = 1000 to 1111 Refer to Figure 31 VGEN6LITR - 5.0 8.0 mV VGEN6 AC AND TRANSIENT (CONTINUED) Turn-On Slew Rate * 10% to 90% of end value * VIN3MIN VIN3 4.5 V. IGEN6 = 0.0 mA VGEN6[3:0] = 0000 to 0011 VGEN6[3:0] = 0100 to 0111 VGEN6[3:0] = 1000 to 1011 VGEN6[3:0] = 1100 to 1111 Turn-On Time Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V IGEN6 = 0.0 mA Notes 69. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 70. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage. 6.4.7 VSNVS LDO/Switch VSNVS powers the low power, SNVS/RTC domain on the processor. It derives its power from either VIN, or coin cell, and cannot be disabled. When powered by both, VIN takes precedence when above the appropriate comparator threshold. When powered by VIN, VSNVS is an LDO capable of supplying seven voltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 V. The bits VSNVSVOLT[2:0] in register VSNVS_CONTROL determine the output voltage. When powered by coin cell, VSNVS is an LDO capable of supplying 1.8, 1.5, 1.3, 1.2, 1.1, or 1.0 V as shown in Table 108. If the 3.0 V option is chosen with the coin cell, VSNVS tracks the coin cell voltage by means of a switch, whose maximum resistance is 100 . In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across the switch, which is 40 mV at a rated maximum load current of 400 A. The default setting of the VSNVSVOLT[2:0] is 110, or 3.0 V, unless programmed otherwise in OTP. However, when the coin cell is applied for the very first time, VSNVS will output 1.0 V. Only when VIN is applied thereafter will VSNVS transition to its default, or programmed value if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS will change configuration from an LDO to a switch for the "110" setting, and will remain as an LDO for the other settings, continuing to output the same voltages as when VIN is applied, providing certain conditions are met as described in Table 108. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 109 Functional Block Requirements and Behaviors Power Generation PF0100 VIN 2.25 V (VTL0) 4.5 V LDO/SWITCH LICELL Charger Input Sense/ Selector VREF LDO\ _ VSNVS + Z Coin Cell 1.8 - 3.3 V I2C Interface Figure 32. VSNVS Supply Switch Architecture Table 108 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system. Table 108. VSNVS Modes of Operation VSNVSVOLT[2:0] VIN MODE 110 > VTH1 VIN LDO 3.0 V 110 < VTL1 Coin cell switch 000 - 101 > VTH0 VIN LDO 000 - 101 < VTL0 Coin cell LDO VSNVS Control The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 109. Table 109. Register VSNVSCTL - ADDR 0x6B Name Bit # R/W Default Description VSNVSVOLT 2:0 R/W 0x80 Configures VSNVS output voltage.(71) 000 = 1.0 V 001 = 1.1 V 010 = 1.2 V 011 = 1.3 V 100 = 1.5 V 101 = 1.8 V 110 = 3.0 V 111 = RSVD UNUSED 7:3 - 0x00 UNUSED Notes 71. Only valid when a valid input voltage is present. VSNVS External Components Table 110. VSNVS External Components Capacitor Value (F) VSNVS 0.47 PF0100 110 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation VSNVS Specifications Table 111. VSNVS Electrical Characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit Operating Input Voltage Valid Coin Cell range Valid VIN VINSNVS 1.8 2.25 - - 3.3 4.5 V Operating Load Current VINMIN < VIN < VINMAX ISNVS 5.0 - 400 A -5.0% -8.0% 3.0 1.0 - 1.8 7.0% 7.0% -5.0% -4.0% 3.0 1.0 - 1.8 5.0% 4.0% VCOIN-0.04 -8.0% - 1.0 - 1.8 VCOIN 7.0% VSNVSDROP - - 50 mV ISNVSLIM 750 500 480 - - - 5900 5900 3600 A 1100 500 480 - - - 6750 6750 4500 VSNVS VSNVS DC, LDO Output Voltage * 5.0 A < ISNVS < 400 A (OFF) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101] * 5.0A < ISNVS < 400A (ON) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101] VSNVS * 50A < ISNVS < 400 A (Coin Cell mode) 2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110 1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101](72) Dropout Voltage VIN = VCOIN = 2.85 V, VSNVSVOLT[2:0] = 110, ISNVS = 400 A Current Limit MMPF0100 VIN > VTH1, VSNVSVOLT[2:0] = 110 VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101 VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 MMPF0100A VIN > VTH1, VSNVSVOLT[2:0] = 110 VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101 VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 V VIN Threshold (Coin Cell Powered to VIN Powered) VIN going high with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 VTH0 2.25 2.40 2.55 VIN Threshold (VIN Powered to Coin Cell Powered) VIN going low with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 VTL0 2.20 2.35 2.50 VIN Threshold Hysteresis for VTH1-VTL1 VHYST1 5.0 - - mV VIN Threshold Hysteresis for VTH0-VTL0 VHYST0 5.0 - - mV VSNVSCROSS 2.7 - - V Output Voltage During Crossover VSNVSVOLT[2:0] = 110 VCOIN > 2.9 V Switch to LDO: VIN > 2.825 V, ISNVS = 100 A LDO to Switch: VIN < 3.05 V, ISNVS = 100 A V V (75) PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 111 Functional Block Requirements and Behaviors Power Generation Table 111. VSNVS Electrical Characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, and 25 C, unless otherwise noted. Parameter Symbol Min Typ Max Unit tONSNVS - - 24 ms Start-up Overshoot VSNVSVOLT[2:0] = 000 to 110 ISNVS = 5.0 A dVIN/dt = 50 mV/s VSNVSOSH - 40 70 mV Transient Line Response ISNVS = 75% of ISNVSMAX 3.2 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 2.45 V < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101] VSNVSLITR - - 32 22 - - mV 2.8 - - V - 1.0 2.0 % VSNVS AC AND TRANSIENT Turn-on Time(73),(74) (Load capacitor, 0.47 F) VIN > UVDET to 90% of VSNVS VCOIN = 0.0 V, ISNVS = 5.0 A VSNVSVOLT[2:0] = 000 to 110 Transient Load Response VSNVSVOLT[2:0] = 110 3.1 V (UVDETL)< VIN 4.5 V ISNVS = 75 to 750 A VSNVSVOLT[2:0] = 000 to 101 2.45 V < VIN 4.5 V VTL0 > VIN, 1.8 V VCOIN 3.3 V ISNVS = 40 to 400 A VSNVSLOTR Refer to Figure 31 VSNVS DC, SWITCH Operating Input voltage Valid Coin Cell range VINSNVS 1.8 - 3.3 V Operating Load Current ISNVS 5.0 - 400 A RDSONSNVS - - 100 2.725 2.90 3.00 V 2.775 2.95 3.1 V Internal Switch Rdson VCOIN = 2.6 V VIN Threshold (VIN Powered to Coin Cell Powered) VSNVSVOLT[2:0] = 110 VTL1 (75) VIN Threshold (Coin Cell Powered to VIN Powered) VSNVSVOLT[2:0] = 110 VTH1 Notes 72. For 1.8 V ISNVS limited to 100 A for VCOIN < 2.1 V 73. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tr1 time. 74. 75. From coin cell insertion to VSNVS =1.0 V, the delay time is typically 400 ms. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause any malfunction. The i.MX 6's RTC continues to operate through the transition, and as a worst case it may switch to the internal RC oscillator for a few clock cycles before switching back to the external crystal oscillator. PF0100 112 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.7.1 Coin Cell Battery Backup The LICELL pin provides for a connection of a coin cell backup battery or a "super" capacitor. If the voltage at VIN goes below the VIN threshold (VTL1 and VTL0), contact-bounced, or removed, the coin cell maintained logic will be powered by the voltage applied to LICELL. The supply for internal logic and the VSNVS rail will switch over to the LICELL pin when VIN goes below VTL1 or VTL0, even in the absence of a voltage at the LICELL pin, resulting in clearing of memory and turning off of VSNVS. When system operation below VTL1 is required, for systems not utilizing a coin cell, connect the LICELL pin to any system voltage between 1.8 and 3.0 V. A small capacitor should be placed from LICELL to ground under all circumstances. Coin Cell Charger Control The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit while the coin cell voltage is programmable through the VCOIN[2:0] bits on register COINCTL on Table 113. The coin cell charger voltage is programmable. In the ON state, the charger current is fixed at ICOINHI. In Sleep and Standby modes, the charger current is reduced to a typical 10 A. In the OFF state, coin cell charging is not available as the main battery could be depleted unnecessarily. The coin cell charging will be stopped when VIN is below UVDET. Table 112. Coin Cell Charger Voltage VCOIN[2:0] VCOIN (V)(76) 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 Notes 76. Coin cell voltages selected based on the type of LICELL used on the system. Table 113. Register COINCTL - ADDR 0x1A Name VCOIN COINCHEN UNUSED Bit # R/W Default Description 2:0 R/W 0x00 Coin cell charger output voltage selection. See Table 112 for all options selectable through these bits. 3 R/W 0x00 Enable or disable the Coin cell charger 7:4 - 0x00 UNUSED External Components Table 114. Coin Cell Charger External Components Component LICELL Bypass Capacitor Value Units 100 nF PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 113 Functional Block Requirements and Behaviors Control Interface I2C Block Description Coin Cell Specifications Table 115. Coin Cell Charger Specifications Parameter Typ Unit Voltage Accuracy 100 mV Coin Cell Charge Current in On mode ICOINHI 60 A Current Accuracy 30 % Control Interface I2C Block Description 6.5 The PF0100 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers the resources of the IC can be controlled. The registers also provide status information about how the IC is operating. The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be accomplished by reducing the drive strength of the I2C master via software. The i.MX6 I2C driver defaults to a 40 ohm drive strength. It is recommended to use a drive strength of 80 ohm or higher to increase the edge times. Alternatively, this can be accomplished by using small capacitors from SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of 4.8 kohm. 6.5.1 I2C Device ID I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to One Time Programmability (OTP) for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general call addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the new slave address; these bits take affect right away. 6.5.2 I2C Operation The I2C mode of the interface is implemented generally following the Fast mode definition which supports up to 400 kbits/s operation (exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) Timing diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at: http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte will be sent out unless a STOP command or NACK is received prior to completion. The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The device will respond to the host if the master command packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction. Packet Type Device Add ress 7 Host SDA START 0 7 Host can also drive another Start instead of Stop Master Driven Data ( byte 0 ) Reg ister Addre ss 7 0 0 0 STOP R/W Slave SDA A C K A C K A C K Figure 33. I2C Write Example PF0100 114 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Packet Type Device Address 23 Host SDA Register Address 16 START 15 Device Address 8 7 0 START 0 NA CK 1 STOP R/W R/W A C K Slave SDA Host can also drive another Start instead of Stop PMIC Driven Data A C K A C K 7 0 Figure 34. I2C Read Example 6.5.3 Interrupt Handling The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving the INTB pin low. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a "1" to the appropriate bit in the Interrupt Status register; this will also cause the INTB pin to go high. If there are multiple interrupt bits set the INTB pin will remain low until all are either masked or cleared. If a new interrupt occurs while the processor clears an existing interrupt bit, the INTB pin will remain low. Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB pin will not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the INTB pin will go low after unmasking. The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary Table 116 . Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly. 6.5.4 Interrupt Bit Summary Table 116 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer to the related chapters. Table 116. Interrupt, Mask and Sense Bits Interrupt Mask Sense Purpose Trigger Debounce Time (ms) Low Input Voltage Detect Sense is 1 if below 2.80 V threshold H to L 3.9(77) Power on button event H to L 31.25(77) Sense is 1 if PWRON is high. L to H 31.25 LOWVINI LOWVINM LOWVINS PWRONI PWRONM PWRONS THERM110 THERM110M THERM110S Thermal 110 C threshold Sense is 1 if above threshold Dual 3.9 THERM120 THERM120M THERM120S Thermal 120 C threshold Sense is 1 if above threshold Dual 3.9 THERM125 THERM125M THERM125S Thermal 125 C threshold Sense is 1 if above threshold Dual 3.9 THERM130 THERM130M THERM130S Thermal 130 C threshold Sense is 1 if above threshold Dual 3.9 SW1AFAULTI SW1AFAULTM SW1AFAULTS Regulator 1A over-current limit Sense is 1 if above current limit L to H 8.0 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 115 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 116. Interrupt, Mask and Sense Bits (continued) Interrupt Mask Sense Purpose Trigger Debounce Time (ms) SW1BFAULTI SW1BFAULTM SW1BFAULTS Regulator 1B over-current limit Sense is 1 if above current limit L to H 8.0 SW1CFAULTI SW1CFAULTM SW1CFAULTS Regulator 1C over-current limit Sense is 1 if above current limit L to H 8.0 SW2FAULTI SW2FAULTM SW2FAULTS Regulator 2 over-current limit Sense is 1 if above current limit L to H 8.0 SW3AFAULTI SW3AFAULTM SW3AFAULTS Regulator 3A over-current limit Sense is 1 if above current limit L to H 8.0 SW3BFAULTI SW3BFAULTM SW3BFAULTS Regulator 3B over-current limit Sense is 1 if above current limit L to H 8.0 SW4FAULTI SW4FAULTM SW4FAULTS Regulator 4 over-current limit Sense is 1 if above current limit L to H 8.0 SWBSTFAULTI SWBSTFAULTM SWBSTFAULTS SWBST over-current limit Sense is 1 if above current limit L to H 8.0 VGEN1FAULTI VGEN1FAULTM VGEN1FAULTS VGEN1 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN2FAULTI VGEN2FAULTM VGEN2FAULTS VGEN2 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN3FAULTI VGEN3FAULTM VGEN3FAULTS VGEN3 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN4FAULTI VGEN4FAULTM VGEN4FAULTS VGEN4 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN5FAULTI VGEN5FAULTM VGEN1FAULTS VGEN5 over-current limit Sense is 1 if above current limit L to H 8.0 VGEN6FAULTI VGEN6FAULTM VGEN6FAULTS VGEN6 over-current limit Sense is 1 if above current limit L to H 8.0 OTP_ECCI OTP_ECCM OTP_ECCS 1 or 2 bit error detected in OTP registers Sense is 1 if error detected L to H 8.0 Notes 77. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0]. A full description of all interrupt, mask, and sense registers is provided in Tables 117 to 128. Table 117. Register INTSTAT0 - ADDR 0x05 Name Bit # R/W Default PWRONI 0 R/W1C 0 Power on interrupt bit LOWVINI 1 R/W1C 0 Low-voltage interrupt bit THERM110I 2 R/W1C 0 110 C Thermal interrupt bit THERM120I 3 R/W1C 0 120 C Thermal interrupt bit THERM125I 4 R/W1C 0 125 C Thermal interrupt bit THERM130I 5 R/W1C 0 130 C Thermal interrupt bit 7:6 - 00 Unused UNUSED Description PF0100 116 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 118. Register INTMASK0 - ADDR 0x06 Name Bit # R/W Default PWRONM 0 R/W1C 1 Power on interrupt mask bit LOWVINM 1 R/W1C 1 Low-voltage interrupt mask bit THERM110M 2 R/W1C 1 110 C Thermal interrupt mask bit THERM120M 3 R/W1C 1 120 C Thermal interrupt mask bit THERM125M 4 R/W1C 1 125 C Thermal interrupt mask bit THERM130M 5 R/W1C 1 130 C Thermal interrupt mask bit 7:6 - 00 Unused UNUSED Description Table 119. Register INTSENSE0 - ADDR 0x07 Name Bit # R/W Default Description PWRONS 0 R 0 Power on sense bit 0 = PWRON low 1 = PWRON high LOWVINS 1 R 0 Low voltage sense bit 0 = VIN > 2.8 V 1 = VIN 2.8 V THERM110S 2 R 0 110 C Thermal sense bit 0 = Below threshold 1 = Above threshold THERM120S 3 R 0 120 C Thermal sense bit 0 = Below threshold 1 = Above threshold THERM125S 4 R 0 125 C Thermal sense bit 0 = Below threshold 1 = Above threshold THERM130S 5 R 0 130 C Thermal sense bit 0 = Below threshold 1 = Above threshold UNUSED 6 - 0 Unused VDDOTPS 7 R 00 Additional VDDOTP voltage sense pin 0 = VDDOTP grounded 1 = VDDOTP to VCOREDIG or greater Table 120. Register INTSTAT1 - ADDR 0x08 Name Bit # R/W Default Description SW1AFAULTI 0 R/W1C 0 SW1A Over-current interrupt bit SW1BFAULTI 1 R/W1C 0 SW1B Over-current interrupt bit SW1CFAULTI 2 R/W1C 0 SW1C Over-current interrupt bit SW2FAULTI 3 R/W1C 0 SW2 Over-current interrupt bit SW3AFAULTI 4 R/W1C 0 SW3A Over-current interrupt bit SW3BFAULTI 5 R/W1C 0 SW3B Over-current interrupt bit PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 117 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 120. Register INTSTAT1 - ADDR 0x08 (continued) Name Bit # R/W Default Description SW4FAULTI 6 R/W1C 0 SW4 Over-current interrupt bit UNUSED 7 - 0 Unused Table 121. Register INTMASK1 - ADDR 0x09 Name Bit # R/W Default Description SW1AFAULTM 0 R/W 1 SW1A Over-current interrupt mask bit SW1BFAULTM 1 R/W 1 SW1B Over-current interrupt mask bit SW1CFAULTM 2 R/W 1 SW1C Over-current interrupt mask bit SW2FAULTM 3 R/W 1 SW2 Over-current interrupt mask bit SW3AFAULTM 4 R/W 1 SW3A Over-current interrupt mask bit SW3BFAULTM 5 R/W 1 SW3B Over-current interrupt mask bit SW4FAULTM 6 R/W 1 SW4 Over-current interrupt mask bit UNUSED 7 - 0 Unused Table 122. Register INTSENSE1 - ADDR 0x0A Name Bit # R/W Default Description SW1AFAULTS 0 R 0 SW1A Over-current sense bit 0 = Normal operation 1 = Above current limit SW1BFAULTS 1 R 0 SW1B Over-current sense bit 0 = Normal operation 1 = Above current limit SW1CFAULTS 2 R 0 SW1C Over-current sense bit 0 = Normal operation 1 = Above current limit SW2FAULTS 3 R 0 SW2 Over-current sense bit 0 = Normal operation 1 = Above current limit SW3AFAULTS 4 R 0 SW3A Over-current sense bit 0 = Normal operation 1 = Above current limit SW3BFAULTS 5 R 0 SW3B Over-current sense bit 0 = Normal operation 1 = Above current limit SW4FAULTS 6 R 0 SW4 Over-current sense bit 0 = Normal operation 1 = Above current limit UNUSED 7 - 0 Unused PF0100 118 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 123. Register INTSTAT3 - ADDR 0x0E Name SWBSTFAULTI UNUSED OTP_ECCI Bit # R/W Default 0 R/W1C 0 6:1 - 0x00 7 R/W1C 0 Description SWBST over-current limit interrupt bit Unused OTP error interrupt bit Table 124. Register INTMASK3 - ADDR 0x0F Name SWBSTFAULTM UNUSED OTP_ECCM Bit # R/W Default 0 R/W 1 6:1 - 0x00 7 R/W 1 Description SWBST over-current limit interrupt mask bit Unused OTP error interrupt mask bit Table 125. Register INTSENSE3 - ADDR 0x10 Name SWBSTFAULTS UNUSED OTP_ECCS Bit # R/W Default 0 R 0 6:1 - 0x00 7 R 0 Description SWBST over-current limit sense bit 0 = Normal operation 1 = Above current limit Unused OTP error sense bit 0 = No error detected 1 = OTP error detected Table 126. Register INTSTAT4 - ADDR 0x11 Name Bit # R/W Default VGEN1FAULTI 0 R/W1C 0 VGEN1 Over-current interrupt bit VGEN2FAULTI 1 R/W1C 0 VGEN2 Over-current interrupt bit VGEN3FAULTI 2 R/W1C 0 VGEN3 Over-current interrupt bit VGEN4FAULTI 3 R/W1C 0 VGEN4 Over-current interrupt bit VGEN5FAULTI 4 R/W1C 0 VGEN5 Over-current interrupt bit VGEN6FAULTI 5 R/W1C 0 VGEN6 Over-current interrupt bit 7:6 - 00 Unused UNUSED Description Table 127. Register INTMASK4 - ADDR 0x12 Name Bit # R/W Default VGEN1FAULTM 0 R/W 1 VGEN1 Over-current interrupt mask bit VGEN2FAULTM 1 R/W 1 VGEN2 Over-current interrupt mask bit VGEN3FAULTM 2 R/W 1 VGEN3 Over-current interrupt mask bit VGEN4FAULTM 3 R/W 1 VGEN4 Over-current interrupt mask bit VGEN5FAULTM 4 R/W 1 VGEN5 Over-current interrupt mask bit VGEN6FAULTM 5 R/W 1 VGEN6 Over-current interrupt mask bit 7:6 - 00 Unused UNUSED Description PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 119 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 128. Register INTSENSE4 - ADDR 0x13 Name Bit # R/W Default VGEN1FAULTS 0 R 0 VGEN1 Over-current sense bit 0 = Normal operation 1 = Above current limit VGEN2FAULTS 1 R 0 VGEN2 Over-current sense bit 0 = Normal operation 1 = Above current limit VGEN3FAULTS 2 R 0 VGEN3 Over-current sense bit 0 = Normal operation 1 = Above current limit VGEN4FAULTS 3 R 0 VGEN4 Over-current sense bit 0 = Normal operation 1 = Above current limit VGEN5FAULTS 4 R 0 VGEN5 Over-current sense bit 0 = Normal operation 1 = Above current limit VGEN6FAULTS 5 R 0 VGEN6 Over-current sense bit 0 = Normal operation 1 = Above current limit 7:6 - 00 Unused UNUSED 6.5.5 6.5.5.1 Description Specific Registers IC and Version Identification The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 129 to 131. Table 129. Register DEVICEID - ADDR 0x00 Name Bit # R/W Default Description DEVICEID 3:0 R 0x00 Die version. 0000 = PF0100 UNUSED 7:4 - 0x01 Unused Table 130. Register SILICON REV- ADDR 0x03 Name METAL_LAYER_REV FULL_LAYER_REV Bit # 3:0 7:4 R/W R R Default Description 0x00 Represents the metal mask revision Pass 0.0 = 0000 . . Pass 0.15 = 1111 0x01 Represents the full mask revision Pass 1.0 = 0001 . . Pass 15.0 = 1111 PF0100 120 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 131. Register FABID - ADDR 0x04 Name 6.5.5.2 Bit # R/W Default Description FIN 1:0 R 0x00 Allows for characterizing different options within the same reticule FAB 3:2 R 0x00 Represents the wafer manufacturing facility Unused 7:0 R 0x00 Unused Embedded Memory There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0], MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell backup. Table 132. Register MEMA ADDR 0x1C Name MEMA Bit # R/W Default 7:0 R/W 0 Description Memory bank A Table 133. Register MEMB ADDR 0x1D Name MEMB Bit # R/W Default 7:0 R/W 0 Description Memory bank B Table 134. Register MEMC ADDR 0x1E Name MEMC Bit # R/W Default 7:0 R/W 0 Description Memory bank C Table 135. Register MEMD ADDR 0x1F Name MEMD Bit # R/W Default 7:0 R/W 0 Description Memory bank D PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 121 Functional Block Requirements and Behaviors Control Interface I2C Block Description 6.5.6 Register Bitmap The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page, the functional registers are the same, but the extended registers are different. To access registers on Extended Page 1, one must first write 0x01 to the page register at address 0x7F, and to access registers Extended Page 2, one must first write 0x02 to the page register at address 0x7F. To access the Functional Page from one of the extended pages, no write to the page register is necessary. Registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will have no effect. The contents of all registers are given in the tables defined in this chapter; each table is structure as follows: Name: Name of the bit. Bit #: The bit location in the register (7-0) R/W: Read / Write access and control * R is read-only access * R/W is read and write access * RW1C is read and write access with write 1 to clear Reset: Reset signals are color coded based on the following legend. Bits reset by SC and VCOREDIG_PORB Bits reset by PWRON or loaded default or OTP configuration Bits reset by DIGRESETB Bits reset by PORB or RESETBMCU Bits reset by VCOREDIG_PORB Bits reset by POR or OFFB Default: The value after reset, as noted in the Default column of the memory map. * Fixed defaults are explicitly declared as 0 or 1. * "X" corresponds to Read / Write bits that are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. "X" may also refer to bits that may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts. 6.5.6.1 Register map Table 136. Functional Page BITS[7:0] Add Register Name R/W Default 00 DeviceID R 8'b0001_0000 7 6 5 4 - - - - 0 0 0 1 3 2 SILICONREVID R 0 0 05 FABID INTSTAT0 R 0 0 METAL_LAYER_REV[3:0] 8'b0001_0000 X 04 0 DEVICE ID [3:0] FULL_LAYER_REV[3:0] 03 1 X X X X X X X FIN[1:0] - - - - 0 0 0 0 0 FAB[1:0] 0 0 0 - - THERM130I THERM125I THERM120I THERM110I LOWVINI PWRONI 0 0 0 0 0 0 0 0 8'b0000_0000 RW1C 8'b0000_0000 PF0100 122 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 136. Functional Page (continued) BITS[7:0] Add Register Name R/W Default 06 INTMASK0 R/W 8'b0011_1111 07 08 09 0A 0E 0F 10 11 12 13 1A 1B INTSENSE0 INTSTAT1 INTMASK1 INTSENSE1 INTSTAT3 INTMASK3 INTSENSE3 INTSTAT4 INTMASK4 INTSENSE4 COINCTL PWRCTL R 7 6 5 4 3 2 1 0 - - THERM130M THERM125M THERM120M THERM110M LOWVINM PWRONM 0 0 1 1 1 1 1 1 VDDOTPS RSVD THERM130S THERM125S THERM120S THERM110S LOWVINS PWRONS 0 0 x x x x x x - SW4FAULTI SW3BFAULTI SW3AFAULTI SW2FAULTI SW1CFAULTI SW1BFAULTI SW1AFAULTI 0 0 0 0 0 0 0 0 - SW4FAULTM 0 1 1 1 1 1 1 1 - SW4FAULTS SW3BFAULTS SW3AFAULTS SW2FAULTS SW1CFAULTS SW1BFAULTS SW1AFAULTS 0 x x x x x x x OTP_ECCI - - - - - - SWBSTFAULTI 8'b00xx_xxxx RW1C 8'b0000_0000 R/W R SW3BFAULTM SW3AFAULTM SW2FAULTM SW1CFAULTM SW1BFAULTM SW1AFAULTM 8'b0111_1111 8'b0xxx_xxxx RW1C 8'b0000_0000 R/W R 0 0 0 0 0 0 0 0 OTP_ECCM - - - - - - SWBSTFAULTM 1 0 0 0 0 0 0 1 OTP_ECCS - - - - - - SWBSTFAULTS 0 0 0 0 0 0 0 x - - 0 0 0 0 0 0 0 0 - - VGEN6 FAULTM VGEN5 FAULTM VGEN4 FAULTM VGEN3 FAULTM VGEN2 FAULTM VGEN1 FAULTM 0 0 1 1 1 1 1 1 - - VGEN6 FAULTS VGEN5 FAULTS VGEN4 FAULTS VGEN3 FAULTS VGEN2 FAULTS VGEN1 FAULTS 0 0 x x x x x x - - - - COINCHEN 0 0 0 0 0 REGSCPEN STANDBYINV 0 0 8'b1000_0001 8'b0000_000x VGEN6FAULTI VGEN5FAULTI VGEN4FAULTI VGEN3FAULTI VGEN2FAULTI VGEN1FAULTI RW1C 8'b0000_0000 R/W R R/W R/W 8'b0011_1111 8'b00xx_xxxx VCOIN[2:0] 8'b0000_0000 STBYDLY[1:0] 0 PWRONBDBNC[1:0] 0 0 PWRONRSTEN RESTARTEN 8'b0001_0000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMA[7:0] 1C MEMA R/W 8'b0000_0000 0 0 0 0 MEMB[7:0] 1D MEMB R/W 8'b0000_0000 0 0 0 0 MEMC[7:0] 1E MEMC R/W 8'b0000_0000 0 0 0 0 MEMD[7:0] 1F MEMD R/W 8'b0000_0000 0 0 0 0 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 123 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 136. Functional Page (continued) BITS[7:0] Add Register Name 20 SW1ABVOLT 21 22 23 SW1ABSTBY SW1ABOFF SW1ABMODE R/W Default 7 6 2E 2F 30 31 SW1ABCONF SW1CVOLT SW1CSTBY SW1COFF SW1CMODE - - 0 0 R/W - - 0 0 - - 0 0 x x - - SW1ABOMODE - 0 0 0 0 SW1CCONF R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x 38 SW2MODE SW1BAPHASE[1:0] x x SW2CONF - - 0 0 - - 0 0 R/W R/W R/W R/W R/W R/W 0 0 - - 0 0 x x - - SW1COMODE - 0 0 0 0 x x x R/W SW1ABMODE[3:0] 1 0 0 0 SW1ABFREQ[1:0] - SW1ABILIM x x 0 0 x x x x x x x x SW1CSTBY[5:0] x x x x SW1COFF[5:0] x x SW1CMODE[3:0] 8'b0000_1000 0 0 0 1 SW1CPHASE[1:0] SW1CFREQ[1:0] - SW1CILIM x 0 0 x x 0 0 x x x x x x x x x x x x 8'bxx00_xx00 SW2[6:0] 8'b0xxx_xxxx x SW2STBY[6:0] 8'b0xxx_xxxx x x x x SW2OFF[6:0] 8'b0xxx_xxxx 0 x x x - - SW2OMODE - 0 0 0 0 x SW2MODE[3:0] 8'b0000_1000 1 SW2PHASE[1:0] 0 0 0 - SW2ILIM x 0 0 x x x x x x SW2FREQ[1:0] 8'bxx01_xx00 x 0 1 x SW3A[6:0] 8'b0xxx_xxxx x x x x SW3ASTBY[6:0] - SW3ASTBY x x 8'b00xx_xxxx 0 3D x SW1C[5:0] - SW3AVOLT x 8'b00xx_xxxx x 3C x x 8'b00xx_xxxx SW2DVSSPEED[1:0] 39 x SW1ABOFF[5:0] - SW2OFF x 8'bxx00_xx00 0 37 x SW1ABSTBY[5:0] - SW2STBY 0 8'b0000_1000 0 36 1 SW1AB[5:0] - SW2VOLT 2 8'b00xx_xxxx x 35 3 8'b00xx_xxxx SW1CDVSSPEED[1:0] 32 4 R/W/M 8'b00xx_xxxx SW1ABDVSSPEED[1:0] 24 5 8'b0xxx_xxxx 0 x x x x PF0100 124 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 136. Functional Page (continued) BITS[7:0] Add Register Name R/W Default 3E SW3AOFF R/W 8'b0xxx_xxxx 7 6 5 4 2 1 0 x x x x 1 0 0 0 SW3APHASE[1:0] SW3AFREQ[1:0] - SW3AILIM 1 x x 0 0 x x x x x x x x - 3F SW3AMODE R/W SW3AOFF[6:0] 0 x 0 0 SW3ACONF R/W x x SW3AOMODE - 0 0 8'bxx10_xx00 x x 0 SW3B[6:0] - 43 SW3BVOLT R/W 8'b0xxx_xxxx 0 x x x SW3BSTBY R/W 8'b0xxx_xxxx 0 x x x - 45 46 SW3BOFF SW3BMODE R/W R/W SW3BCONF R/W SW3BOFF[6:0] 0 x x x - - SW3BOMODE - 0 0 0 0 R/W 0 0 SW3BPHASE[1:0] SW3BFREQ[1:0] - SW3BILIM x 1 x x 0 0 x x x x x x x x x 0 R/W SW4[6:0] x x x SW4STBY[6:0] x x x 0 x x x - - SW4OMODE - 0 0 0 0 - 4D SW4OFF SW4MODE R/W R/W SW4CONF R/W SW4OFF[6:0] 6A 6B VREFDDRCTL VSNVSCTL R/W R/W R/W SW4MODE[3:0] 1 SW4PHASE[1:0] 0 SW4FREQ[1:0] 0 0 - SW4ILIM 0 0 8'bxx11_xx00 - SWBSTCTL x 8'b0000_1000 x 66 x 8'b0xxx_xxxx SW4DVSSPEED[1:0] 4E x 8'b0xxx_xxxx 0 4C 1 8'b0xxx_xxxx - SW4STBY SW3BMODE[3:0] 8'bxx10_xx00 0 4B x 0 - SW4VOLT x 8'b0000_1000 x 4A x 8'b0xxx_xxxx SW3BDVSSPEED[1:0] 47 x SW3BSTBY[6:0] - 44 SW3AMODE[3:0] 8'b0000_1000 SW3ADVSSPEED[1:0] 40 3 x 1 SWBST1STBYMODE[1:0] 1 - x x SWBST1MODE[1:0] SWBST1VOLT[1:0] 8'b0xx0_10xx 0 x x 0 1 0 x x - - - VREFDDREN - - - - 0 0 0 x 0 0 0 0 - - - - - 0 0 0 0 0 8'b000x_0000 VSNVSVOLT[2:0] 8'b0000_0xxx 0 x x PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 125 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 136. Functional Page (continued) BITS[7:0] Add Register Name R/W Default 6C VGEN1CTL R/W 8'b000x_xxxx 6D 6E 6F 70 71 7F VGEN2CTL VGEN3CTL VGEN4CTL VGEN5CTL VGEN6CTL Page Register R/W R/W R/W R/W R/W R/W 7 6 5 4 3 - VGEN1LPWR VGEN1STBY VGEN1EN 0 0 0 x - VGEN2LPWR VGEN2STBY VGEN2EN 0 0 0 x - VGEN3LPWR VGEN3STBY VGEN3EN 0 0 0 x - VGEN4LPWR VGEN4STBY VGEN4EN 0 0 0 x - VGEN5LPWR VGEN5STBY VGEN5EN 0 0 0 x - VGEN6LPWR VGEN6STBY VGEN6EN 0 0 0 x - - - 0 0 0 2 1 0 x x x x x x x x x x x x 0 0 VGEN1[3:0] x x x x VGEN2[3:0] 8'b000x_xxxx VGEN3[3:0] 8'b000x_xxxx x x VGEN4[3:0] 8'b000x_xxxx x x VGEN5[3:0] 8'b000x_xxxx x x VGEN6[3:0] 8'b000x_xxxx x x PAGE[4:0] 8'b0000_0000 0 0 0 Table 137. Extended Page 1 BITS[7:0] Address Register Name TYPE 80 84 8A 8B 8C 8D A0 OTP FUSE READ EN OTP LOAD MASK OTP ECC SE1 OTP ECC SE2 OTP ECC DE1 OTP ECC DE2 OTP SW1AB VOLT R/W R/W R R R R R/W Default 7 6 5 4 3 2 1 0 - - - - - - - OTP FUSE READ EN 0 0 0 x x x x 0 START RL PWBRTN FORCE PWRCTL RL PWRCTL RL OTP RL OTP ECC RL OTP FUSE RL TRIM FUSE 0 0 0 0 0 0 0 0 - - - ECC5_SE ECC4_SE ECC3_SE ECC2_SE ECC1_SE x x x 0 0 0 0 0 - - - ECC10_SE ECC9_SE ECC8_SE ECC7_SE ECC6_SE x x x 0 0 0 0 0 - - - ECC5_DE ECC4_DE ECC3_DE ECC2_DE ECC1_DE x x x 0 0 0 0 0 - - - ECC10_DE ECC9_DE ECC8_DE ECC7_DE ECC6_DE x x x 0 0 0 0 0 - - 0 0 x x 8'b000x_xxx0 8'b0000_0000 8'bxxx0_0000 8'bxxx0_0000 8'bxxx0_0000 8'bxxx0_0000 SW1AB_VOLT[5:0] 8'b00xx_xxxx x x x x PF0100 126 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 137. Extended Page 1 (continued) BITS[7:0] Address Register Name TYPE Default 7 6 5 4 3 - A1 A2 A8 OTP SW1AB SEQ R/W OTP SW1AB CONFIG R/W OTP SW1C VOLT R/W 2 AA OTP SW1C SEQ R/W OTP SW1C CONFIG R/W OTP SW2 VOLT R/W AD AE OTP SW2 SEQ R/W OTP SW2 CONFIG R/W 0 0 0 x - - - - 0 0 0 0 - - 0 0 x OTP SW3A VOLT R/W B1 B2 OTP SW3A SEQ R/W OTP SW3A CONFIG R/W OTP SW3B VOLT R/W B5 B6 OTP SW3B SEQ R/W OTP SW3B CONFIG R/W SW1_CONFIG[1:0] x OTP SW4 VOLT R/W B9 OTP SW4 SEQ R/W SW1AB_FREQ[1:0] x x x x x x x x SW1C_VOLT[5:0] x x x SW1C_SEQ[4:0] 8'b000x_xxxx 0 0 0 x x x - - - - - - 0 0 0 0 0 0 x x 0 x x x x x x - - 0 0 0 x x x x x - - - - - - SW2_FREQ[1:0] 0 0 0 0 0 0 x x x x x x x SW1C_FREQ[1:0] 8'b0000_00xx SW2_VOLT[5:0] 8'b0xxx_xxxx x SW2_SEQ[4:0] 8'b000x_xxxx 8'b0000_00xx SW3A_VOLT[6:0] 8'b0xxx_xxxx 0 x x x - - 0 0 0 x - - - - 0 0 0 0 x SW3A_SEQ[4:0] 8'b000x_xxxx x x SW3_CONFIG[1:0] SW3A_FREQ[1:0] 8'b0000_xxxx x x x x x x x x x SW3B_VOLT[6:0] 8'b0xxx_xxxx 0 x x x x - - 0 0 0 x x x - - - - - - 0 0 0 0 0 0 x x x x x x x SW3B_SEQ[4:0] 8'b000x_xxxx SW3B_CONFIG[1:0] 8'b0000_00xx - B8 x 8'b00xx_xxxx - B4 x 8'b0000_xxxx - B0 X SW1AB_SEQ[4:0] - AC 0 8'b000x_xxXx - A9 1 SW4_VOLT[6:0] 8'b00xx_xxxx 0 0 x - - - 0 0 0 x x SW4_SEQ[4:0] 8'b000x_xxxx x x x PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 127 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 137. Extended Page 1 (continued) BITS[7:0] Address Register Name TYPE BA BC BD C0 C4 C8 C9 CC CD D0 D1 D4 D5 D8 D9 OTP SW4 CONFIG R/W OTP SWBST VOLT R/W OTP SWBST SEQ R/W OTP VSNVS VOLT R/W OTP VREFDDR SEQ R/W OTP VGEN1 VOLT R/W OTP VGEN1 SEQ R/W OTP VGEN2 VOLT R/W OTP VGEN2 SEQ R/W OTP VGEN3 VOLT R/W OTP VGEN3 SEQ R/W OTP VGEN4 VOLT R/W OTP VGEN4 SEQ R/W OTP VGEN5 VOLT R/W OTP VGEN5 SEQ R/W Default 7 6 5 4 3 2 1 0 - - - VTT - - SW4_FREQ[1:0] 0 0 0 x x x x - - - - - - 0 0 0 0 0 0 - - - 0 0 0 0 x - - - - - 0 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 - - - 0 0 0 8'b000x_xxxx x SWBST_VOLT[1:0] 8'b0000_00xx x x x x SWBST_SEQ[4:0] 8'b0000_xxxx x VSNVS_VOLT[2:0] 8'b0000_0xxx 0 x x x x VREFDDR_SEQ[4:0] 8'b000x_x0xx x 0 VGEN1_VOLT[3:0] 8'b0000_xxxx x x x x x x VGEN1_SEQ[4:0] 8'b000x_xxxx x x VGEN2_VOLT[3:0] 8'b0000_xxxx x x x x x x VGEN2_SEQ[4:0] 8'b000x_xxxx x x VGEN3_VOLT[3:0] 8'b0000_xxxx x x x x x x VGEN3_SEQ[4:0] 8'b000x_xxxx x x VGEN4_VOLT[3:0] 8'b0000_xxxx x x x x x x VGEN4_SEQ[4:0] 8'b000x_xxxx x x VGEN5_VOLT[3:0] 8'b0000_xxxx x x x x x x VGEN5_SEQ[4:0] 8'b000x_xxxx x x x PF0100 128 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 137. Extended Page 1 (continued) BITS[7:0] Address Register Name TYPE DC DD E0 E1 E2 E3 E4 (78) E5 E6 E7 E8 F0 F1 OTP VGEN6 VOLT OTP VGEN6 SEQ OTP PU CONFIG1 OTP PU CONFIG2 OTP PU CONFIG3 OTP PU CONFIG XOR OTP FUSE POR1 OTP FUSE POR1 OTP FUSE POR1 OTP FUSE POR XOR OTP PWRGD EN OTP EN ECCO OTP EN ECC1 R/W R/W R/W R/W R/W R R/W R/W R/W R R/W/M R/W R/W Default 7 6 5 4 3 2 1 0 - - - - 0 0 0 0 - - - 0 0 0 x - - - PWRON_ CFG1 0 0 0 x - - - PWRON_ CFG2 0 0 0 x - - - PWRON_ CFG3 0 0 0 x - - - PWRON_CFG _XOR 0 0 0 x x x x x TBB_POR SOFT_FUSE _POR - - - - FUSE_POR1 - VGEN6_VOLT[3:0] 8'b0000_xxxx x x x x x x VGEN6_SEQ[4:0] 8'b000x_xxxx 8'b000x_xxxx 8'b000x_xxxx 8'b000x_xxxx 8'b000x_xxxx 8'b0000_00x0 x x SWDVS_CLK1[1:0] x x SWDVS_CLK2[1:0] x x SWDVS_CLK3[1:0] x x SWDVS_CLK3_XOR SEQ_CLK_SPEED1[1:0] x x SEQ_CLK_SPEED2[1:0] x x SEQ_CLK_SPEED3[1:0] x x SEQ_CLK_SPEED_XOR 0 0 0 0 0 0 x 0 RSVD RSVD - - - - FUSE_POR2 - 0 0 0 0 0 0 x 0 RSVD RSVD - - - - FUSE_POR3 - 0 0 0 0 0 0 x 0 RSVD RSVD - - - - FUSE_POR_ XOR - 0 0 0 0 0 0 x 0 8'b0000_00x0 8'b0000_00x0 8'b0000_00x0 - - - - - - - OTP_PG_EN 0 0 0 0 0 0 x 0 - - - EN_ECC_ BANK5 EN_ECC_ BANK4 EN_ECC_ BANK3 EN_ECC_ BANK2 EN_ECC_ BANK1 0 0 0 x x x x x - - - EN_ECC_ BANK10 EN_ECC_ BANK9 EN_ECC_ BANK8 EN_ECC_ BANK7 EN_ECC_ BANK6 0 0 0 x x x x x 8'b0000_000x 8'b000x_xxxx 8'b000x_xxxx Notes 78. In the MMPF0100 FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR'ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In MMPF0100A, the XOR function is removed. It is required to set all of the FUSE_PORx bits to be able to load the fuses. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 129 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 137. Extended Page 1 (continued) BITS[7:0] Address Register Name TYPE F4 F5 F6 F7 FE FF OTP SPARE2_4 OTP SPARE4_3 OTP SPARE6_2 OTP SPARE7_1 OTP DONE OTP I2C ADDR R/W R/W R/W R/W R/W R/W Default 7 6 5 4 3 2 1 0 - - - - 0 0 0 0 x x x - - - - - 0 0 0 0 0 x - - - - - - 0 0 0 0 0 0 x x - - - - - - - RSVD 0 0 0 0 0 x x x - - - - - - - OTP_DONE 0 0 0 0 0 0 0 x - - - - I2C_SLV ADDR[3] 0 0 0 0 1 x x x 2 1 0 RSVD 8'b0000_xxxx x RSVD 8'b0000_0xxx x x RSVD 8'b0000_00xx 8'b0000_0xxx 8'b0000_000x 8'b0000_0xxx I2C_SLV ADDR[2:0] Table 138. Extended Page 2 BITS[7:0] Address 81 Register Name SW1AB PWRSTG TYPE R/W Default 7 6 5 4 3 RSVD RSVD RSVD RSVD RSVD 1 1 1 1 1 1 1 1 0 0 0 SW1AB_PWRSTG[2:0] 8'b1111_1111 PWRSTGRSVD 82 83 84 85 86 87 88 PWRSTG RSVD SW1C PWRSTG SW2 PWRSTG SW3A PWRSTG SW3B PWRSTG SW4 PWRSTG PWRCTRL OTP CTRL R R R R R R R/W 8'b0000_0000 0 0 0 0 0 RSVD RSVD RSVD RSVD RSVD 1 1 1 1 1 RSVD RSVD RSVD RSVD RSVD 1 1 1 1 1 RSVD RSVD RSVD RSVD RSVD 1 1 1 1 1 RSVD RSVD RSVD RSVD RSVD SW1C_PWRSTG[2:0] 8'b1111_1111 1 1 1 SW2_PWRSTG[2:0] 8'b1111_1111 1 1 1 SW3A_PWRSTG[2:0] 8'b1111_1111 1 1 1 SW3B_PWRSTG[2:0] 8'b1111_1111 8'b0111_1111 1 1 1 1 1 FSLEXT_ THERM_ DISABLE PWRGD_ SHDWN_ DISABLE 1 1 1 RSVD RSVD RSVD 0 0 1 1 1 1 1 1 - - - - - - PWRGD_EN OTP_ SHDWN_EN 0 0 0 0 0 0 0 1 SW4_PWRSTG[2:0] 8'b0000_0001 PF0100 130 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 138. Extended Page 2 (continued) BITS[7:0] Address Register Name TYPE Default 7 8D 8E 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 I2C_WRITE_ADDRESS_TRAP[7:0] I2C WRITE ADDRESS TRAP R/W I2C TRAP PAGE R/W 8'b0000_0000 8'b0000_0000 0 0 0 0 LET_IT_ ROLL RSVD RSVD 0 0 0 0 I2C_TRAP_PAGE[4:0] 0 0 I2C_WRITE_ADDRESS_COUNTER[7:0] 8F I2C TRAP CNTR R/W 8'b0000_0000 0 0 SDA_DRV[1:0] 90 DO D1 D8 (79) IO DRV OTP AUTO ECC0 OTP AUTO ECC1 R/W R/W R/W E1 E2 E3 E4 E5 E6 E7 0 0 SDWNB_DRV[1:0] INTB_DRV[1:0] RESETBMCU_DRV[1:0] 8'b00xx_xxxx 0 0 x x x x x x - - - AUTO_ECC _BANK5 AUTO_ECC _BANK4 AUTO_ECC_ BANK3 AUTO_ECC _BANK2 AUTO_ECC_ BANK1 0 0 0 0 0 0 0 0 - - - AUTO_ECC_ BANK10 AUTO_ECC _BANK9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8'b0000_0000 8'b0000_0000 AUTO_ECC_ AUTO_ECCB AUTO_ECC_ BANK8 ANK7 BANK6 RSVD Reserved - 8'b0000_0000 0 D9 (79) 0 0 0 0 RSVD Reserved OTP ECC CTRL1 OTP ECC CTRL2 OTP ECC CTRL3 OTP ECC CTRL4 OTP ECC CTRL5 OTP ECC CTRL6 OTP ECC CTRL7 - R/W R/W R/W R/W R/W R/W R/W 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 0 0 ECC1_EN_ TBB ECC1_CALC _CIN 0 0 ECC2_EN_ TBB ECC2_CALC _CIN 0 0 ECC3_EN_ TBB ECC3_CALC _CIN 0 0 ECC4_EN_ TBB ECC4_CALC _CIN 0 0 ECC5_EN_ TBB ECC5_CALC _CIN 0 0 ECC6_EN_ TBB ECC6_CALC _CIN 0 0 ECC7_EN_ TBB ECC7_CALC _CIN 0 0 0 0 ECC1_CIN_TBB[5:0] 0 0 0 0 ECC2_CIN_TBB[5:0] 0 0 0 0 ECC3_CIN_TBB[5:0] 0 0 0 0 ECC4_CIN_TBB[5:0] 0 0 0 0 ECC5_CIN_TBB[5:0] 0 0 0 0 ECC6_CIN_TBB[5:0] 0 0 0 0 ECC7_CIN_TBB[5:0] 0 0 0 0 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 131 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 138. Extended Page 2 (continued) BITS[7:0] Address E8 E9 EA F1 F2 F3 F4 F5 F6 F7 F8 F9 FA Register Name OTP ECC CTRL8 OTP ECC CTRL9 OTP ECC CTRL10 OTP FUSE CTRL1 OTP FUSE CTRL2 OTP FUSE CTRL3 OTP FUSE CTRL4 OTP FUSE CTRL5 OTP FUSE CTRL6 OTP FUSE CTRL7 OTP FUSE CTRL8 OTP FUSE CTRL9 OTP FUSE CTRL10 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 8'b0000_0000 8'b0000_0000 8'b0000_0000 7 6 5 4 ECC8_EN_ TBB ECC8_CALC _CIN 0 0 ECC9_EN_ TBB ECC9_CALC _CIN 0 0 ECC10_EN_ TBB ECC10_CAL C_CIN 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 3 2 1 0 0 0 0 0 0 0 ECC8_CIN_TBB[5:0] 0 0 0 0 ECC9_CIN_TBB[5:0] 0 0 0 0 ECC10_CIN_TBB[5:0] 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 8'b0000_0000 0 0 ANTIFUSE1_ ANTIFUSE1_ ANTIFUSE1_ EN LOAD RW 0 0 0 ANTIFUSE2_ ANTIFUSE2_ ANTIFUSE2_ EN LOAD RW 0 0 0 ANTIFUSE3_ ANTIFUSE3_ ANTIFUSE3_ EN LOAD RW 0 0 0 ANTIFUSE4_ ANTIFUSE4_ ANTIFUSE4_ EN LOAD RW 0 0 0 ANTIFUSE5_ ANTIFUSE5_ ANTIFUSE5_ EN LOAD RW 0 0 0 ANTIFUSE6_ ANTIFUSE6_ ANTIFUSE6_ EN LOAD RW 0 0 0 ANTIFUSE7_ ANTIFUSE7_ ANTIFUSE7_ EN LOAD RW 0 0 0 ANTIFUSE8_ ANTIFUSE8_ ANTIFUSE8_ EN LOAD RW 0 0 0 ANTIFUSE9_ ANTIFUSE99 ANTIFUSE9_ EN _LOAD RW 0 0 0 ANTIFUSE10 ANTIFUSE10 ANTIFUSE10 _EN _LOAD _RW 0 0 0 BYPASS1 0 BYPASS2 0 BYPASS3 0 BYPASS4 0 BYPASS5 0 BYPASS6 0 BYPASS7 0 BYPASS8 0 BYPASS9 0 BYPASS10 0 Notes 79. Do not write in reserved registers. PF0100 132 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications Introduction 7 Typical Applications 7.1 Introduction Figure 35 provides a typical application diagram of the PF0100 PMIC together with its functional components. For details on component references and additional components such as filters, refer to the individual sections. 7.1.1 Application Diagram VIN1 VIN1 2.2uF VGEN1 4.7uF VGEN2 VGEN1 100mA Vin SW1A/B Single/Dual 2500 mA Buck VGEN2 250mA VIN2 1.0uF O/P Drive 4.7uF SW1AIN 1.0uH SW1ALX 2 x22uF SW1BLX SW1BIN 4.7uF Vin VGEN3 100mA VGEN3 SW1C Output 1.0uH SW1CLX 4.7uF SW1C 1750 mA Buck VGEN4 350mA VGEN4 VIN3 1.0uF O/P Drive SW1CIN SW1CFB Core Control logic VIN3 3 x 22uF 4.7uF Vin SW1VSSSNS VGEN5 100mA 2.2uF SW2 Output VGEN5 2.2uF SW2 2000 mA Buck VGEN6 200mA VGEN6 Supplies Control SW2IN SW2IN CONTROL I2C Interface SW3A/B Single/Dual DDR 2500 mA Buck O/P Drive O/P Drive 4.7uF SW3AIN 1.0uH SW3ALX SDA 1.0uH SW3BIN SW3BFB DVS CONTROL 2 x 22uF SW3BLX SCL To MCU 3 x 22uF 4.7uF SW3A Output Vin VDDIO 0.1uF Vin SW3AFB VDDOTP VDDIO O/P Drive SW2FB OTP 1.0uH SW2LX Initialization State Machine VDDOTP 4.7k O/P Drive VIN2 2.2uF 4.7k SW1AB Output SW1FB PF0100 1.0uF 2 x 22uF 4.7uF Vin SW3B Output SW3VSSSNS DVS Control SW4FB SW4 Output Vin 1uF I2C Register map VCOREDIG 220nF VCOREREF 1uF VCORE SW4 1000 mA Buck Trim-In-Package 1.0uH SW4LX Vin GNDREF1 2.2uH Reference Generation SWBSTLX Clocks and resets SWBST 600 mA Boost GNDREF 1uF 4.7uF SW4IN O/P Drive O/P Drive SWBSTIN Vin 3 x 22uF 10uF SWBST Output 2 x 22uF SWBSTFB 2.2uF VREFDDR VSW3A VINREFDDR Clocks 100nF 32kHz and 16MHz VHALF Package Pin Legend Output Pin 100nF Input Pin Bi-directional Pin Vin VIN 1uF LICELL 100nF Li Cell Charger Best of Supply VSNVS VSW2 100k 100k VSW2 INTB 100k VSW2 SDWNB STANDBY RESETBMCU 100k VSW2 PWRON 0.47uF ICTEST VSNVS Coin Cell Battery To/From AP Figure 35. Typical Application Schematic PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 133 Typical Applications Introduction 7.1.2 Bill of Material The following table provides a complete list of the recommended components on a full featured system using the PF0100 Device for -40 C to 85 C applications. Components are provided with an example part number; equivalent components may be used. Table 139. Bill of Material -40 C to 85 C Applications (80) Value Qty Description Part# Manufacturer Component/Pin PMIC 1 Power management IC MMPF0100 Freescale BUCK, SW1AB - (0.300-1.875 V), 2.5 A 1.0 H 1 2.5 x 2 x 1.2 ISAT = 3.4 A for 10% drop, DCRMAX = 49 m DFE252012R-H-1R0M TOKO INC. Output Inductor 22 H 4 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance 4.7 F 2 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance 0.1 F 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance BUCK, SW1C - (0.300-1.875 V), 2.0 A 1.0 H 1 2.5 x 2 x 1.2 ISAT = 3.0 A for 10% drop, DCRMAX = 59 m DFE252012C-1R0M TOKO INC. Output Inductor 22 F 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance 4.7 F 1 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance 0.1 F 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance BUCK, SW2 - (0.400-3.300 V), 2.0 A 1.0 H 1 2.5 x 2 x 1.2 ISAT = 3.0 A for 10% drop, DCRMAX = 59 m DFE252012C-1R0M TOKO INC. Output Inductor 22 F 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance 4.7 F 1 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance 0.1 F 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance BUCK, SW3AB - (0.400-3.300 V), 2.5 A 1.0 H 1 2.5 x 2 x 1.2 ISAT = 3.4 A for 10% drop, DCRMAX = 49 m DFE252012R-1R0M TOKO INC. Output Inductor 22 F 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance 4.7 F 2 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance 0.1 F 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance BUCK, SW4 - (0.400-3.300V), 1.0 A 1.0 H 1 2 x 1.6 x 0.9 ISAT = 2.0 A for 30% drop, DCRMAX = 80 m LQM2MPN1R0MGH Murata Output Inductor 22 F 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance 4.7 F 2 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance 0.1 F 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance PF0100 134 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications Introduction Table 139. Bill of Material -40 C to 85 C Applications (continued) (80) Value Qty Description Part# Manufacturer Component/Pin BOOST, SWBST - 5.0 V, 600 MA 2.2 H 1 2 x 1.6 x 1 ISAT = 2.4 A for 10% drop DFE201610E-2R2M TOKO INC. Output Inductor 22 F 2 10 V X5R 0603 GRM188R61A226ME15D Murata Output capacitance 10 F 3 10 V X5R 0402 GRM155R61A106ME11 Murata Input capacitance 2.2 F 1 10 V X5R 0201 GRM033R61A225ME47 Murata Input capacitance 0.1 F 1 10 V X5R 0201 GRM033R61A104KE84 Murata Input capacitance 1.0 A 1 DIODE SCH PWR RECT 1.0 A 20V SMT MBR120LSFT3G ON Semiconductor Schottky Diode LDO, VGEN1, 2, 3, 4, 5, 6 4.7 F 1 10 V X5R 0402 GRM155R61A475MEAA Murata VGEN2,4 Output Capacitors 2.2 F 1 10 V X5R 0201 GRM033R61A225ME47 Murata VGEN1,3,5,6 Output Capacitors 1.0 F 1 10 V X5R 0402 GRM033R61A105ME44 Murata VGEN1,2,3,4,5,6 Input Capacitors MISCELLANEOUS 1.0 F 1 10 V X5R 0402 GRM033R61A105ME44 Murata VCORE, VCOREDIG, VREFDDR, VINREFDDR, VIN Capacitors 0.22 F 1 10 V X5R 0201 GRM033R61A224ME90 Murata VCOREREF Output Capacitor 0.47 F 1 10 V X5R 0201 GRM033R61A474ME90 Murata VSNVS Output Capacitor 0.1 F 1 10 V X5R 0201 GRM033R61A104KE84 Murata VHALF, VINREFDDR, VDDIO, LICELL Capacitors 100 k 2 RES MF 100 k 1/16 W 1% 0402 RC0402FR-07100KL Yageo America Pull-up resistors 4.7 k 2 RES MF 4.70K 1/20W 1% 0201 RC0201FR-074K7L Yageo America I2C Pull-up resistors Notes 80. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 135 Typical Applications Introduction The following table provides a complete list of the recommended components on a full featured system using the PF0100 Device for -40 C to 105 C applications. Components are provided with an example part number; equivalent components may be used. Table 140. Bill of Material -40 C to 105 C Applications (81) Value Qty Description Part# Manufacturer Component/Pin PMIC 1 Power management IC MMPF0100 Freescale BUCK, SW1AB - (0.300-1.875 V), 2.5 A 1.0 H 1 2.5 x 2 x 1.2 ISAT = 3.4 A for 10% drop DCRMAX = 49 m DFE252012R-H-1R0M TOKO INC. Output Inductor 22 H 4 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance 4.7 F 2 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance BUCK, SW1C - (0.300-1.875 V), 2.0 A 1.0 H 1 2 x 1.6 x 1 ISAT = 2.9 A for 10% drop DFE201610E-1R0M TOKO INC. Output Inductor 22 F 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance 4.7 F 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance BUCK, SW1ABC - (0.300-1.875 V), 4.5 A 1.0 H 1 4.2 x 4.2 x 2 ISAT = 5.1 A for 10% drop, DCRMAX = 29 m FDSD0420-H-1R0M TOKO INC. Output Inductor 22 F 6 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance 4.7 F 2 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance BUCK, SW2 - (0.400-3.300 V), 2.0 A 1.0 H 1 2 x 1.6 x 1 ISAT = 2.9 A for 10% drop DFE201610E-1R0M TOKO INC. Output Inductor 22 F 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance 4.7 F 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance BUCK, SW3AB - (0.400-3.300 V), 2.5 A 1.0 H 1 2 x 1.6 x 1 ISAT = 2.9 A for 10% drop DFE201610E-1R0M TOKO INC. Output Inductor 22 F 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance 4.7 F 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance PF0100 136 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications Introduction Table 140. Bill of Material -40 C to 105 C Applications (continued) (81) Value Qty Description Part# Manufacturer Component/Pin BUCK, SW4 - (0.400-3.300V), 1.0 A 1.0 H 1 2 x 1.6 x 1 ISAT = 2.9 A for 30% drop DFE201610E-1R0M Murata Output Inductor 22 F 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance 4.7 F 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance BOOST, SWBST - 5.0 V, 600 MA 2.2 H 1 2 x 1.6 x 1 ISAT = 2.4 A for 10% drop DFE201610E-2R2M TOKO INC. Output Inductor 22 F 2 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance 10 F 3 10 V X7T 0603 GRM188D71A106MA73 Murata Input capacitance 2.2 F 1 10 V X7S 0402 GRM155C71A225KE11 Murata Input capacitance 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance 1.0 A 1 DIODE SCH PWR RECT 1A 20V SMT MBR120LSFT3G ON Semiconductor Schottky Diode LDO, VGEN1, 2, 3, 4, 5, 6 4.7 F 1 10 V X7S 0603 GRM188C71A475KE11 Murata VGEN2,4 Output Capacitors 2.2 F 1 10 V X7S 0402 GRM155C71A225KE11 Murata VGEN1,3,5,6 Output Capacitors 1.0 F 1 10 V X7S 0402 GRM155C71A105KE11 Murata VGEN1,2,3,4,5,6 Input Capacitors MISCELLANEOUS 1.0 F 1 10 V X7S 0402 GRM155C71A105KE11 Murata VCORE, VCOREDIG, VREFDDR, VINREFDDR, VIN Capacitors 0.22 F 1 10 V X7R 0402 GRM155R71A224KE01 Murata VCOREREF Output Capacitor 0.47 F 1 10 V X7R 0402 GRM155R71A474KE01 Murata VSNVS Output Capacitor 0.1 F 1 10 V X7S 0201 GRM033C71A104KE14 Murata VHALF, VINREFDDR, VDDIO, LICELL Capacitors 100 k 2 RES MF 100 k 1/16 W 1% 0402 RC0402FR-07100KL Yageo America Pull-up resistors 4.7 k 2 RES MF 4.70K 1/20W 1% 0201 RC0201FR-074K7L Yageo America I2C Pull-up resistors Notes 81. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 137 Typical Applications PF0100 Layout Guidelines 7.2 PF0100 Layout Guidelines 7.2.1 General Board Recommendations 1. It is recommended to use an eight layer board stack-up arranged as follows: * High current signal * GND * Signal * Power * Power * Signal * GND * High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing. 7.2.2 Component Placement It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output capacitors. 7.2.3 General Routing Requirements 1. Some recommended things to keep in mind for manufacturability: * Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole * Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper * Minimum allowed spacing between line and hole pad is 3.5 mils * Minimum allowed spacing between line and line is 3.0 mils 2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be also shielded. 3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node (i.e. SW1ALX, SW1BLX, SW1CLX, SW2LX, SW3ALX, SW3BLX, SW4LX, and SWBSTLX). 5. Make sure that all components related to a specific block are referenced to the corresponding ground. PF0100 138 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications PF0100 Layout Guidelines 7.2.4 Parallel Routing Requirements 1. I2C signal routing * CLK is the fastest signal of the system, so it must be given special care. * To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length. Figure 36. Recommended Shielding for Critical Signals * These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane. * Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 139 Typical Applications PF0100 Layout Guidelines 7.2.5 Switching Regulator Layout Recommendations 1. Per design, the switching regulators in PF0100 are designed to operate with only one input bulk capacitor. However, it is recommended to add a high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins. 2. Make high-current ripple traces low-inductance (short, high W/L ratio). 3. Make high-current traces wide or copper islands. 4. Make high-current traces symetrical for dual-phase regulators (SW1, SW3). VIN SWxIN CIN_HF Driver Controller CIN SWx SWxLX L COUT Compensation SWxFB Figure 37. Generic Buck Regulator Architecture Figure 38. Layout Example for Buck Regulators PF0100 140 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications Thermal Information 7.3 Thermal Information 7.3.1 Rating Data The thermal rating data of the packages has been simulated with the results listed in Table 6. Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RJA or JA (Theta-JA) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RJMA or JMA (ThetaJMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org. 7.3.2 Estimation of Junction Temperature An estimation of the chip junction temperature TJ can be obtained from the equation: TJ = TA + (RJA x PD) with: TA = Ambient temperature for the package in C RJA = Junction to ambient thermal resistance in C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RJA and the value obtained on a four layer board RJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RJB x PD) with TB = Board temperature at the package perimeter in C RJB = Junction to board thermal resistance in C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See Functional Block Requirements and Behaviors for more details on thermal management. PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 141 Packaging Packaging Dimensions 8 Packaging 8.1 Packaging Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing's document number. See the Thermal Characteristics section for specific thermal characteristics for each package. Table 141. Package Drawing Information Package Suffix Package Outline Drawing Number 56 QFN 8x8 mm - 0.5 mm pitch. E-Type (full lead) 56 QFN 8x8 mm - 0.5 mm pitch. WF-Type (wettable flank) EP 98ASA00405D ES 98ASA00589D PF0100 142 Analog Integrated Circuit Device Data Freescale Semiconductor Packaging Packaging Dimensions PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 143 Packaging Packaging Dimensions PF0100 144 Analog Integrated Circuit Device Data Freescale Semiconductor Packaging Packaging Dimensions PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 145 Packaging Packaging Dimensions PF0100 146 Analog Integrated Circuit Device Data Freescale Semiconductor Packaging Packaging Dimensions PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 147 Packaging Packaging Dimensions PF0100 148 Analog Integrated Circuit Device Data Freescale Semiconductor Reference Section Reference Documents 9 Reference Section 9.1 Reference Documents Table 142. PF0100 Reference Documents Reference AN4536 Description MMPF0100 OTP Programming Instructions PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 149 Revision History Reference Documents 10 Revision History REVISION DATE 1.0 7/2011 * Preliminary specification release 2.0 8/2012 * NPI phase: prototype major updates throughout cycle 3.0 10/2012 * Initial production release 4.0 5/2013 5.0 7/2013 * * * * * * * * * * * * * * * * * 6.0 8/2013 7.0 12/2013 DESCRIPTION OF CHANGES * * * * * * * * * * * * * 8.0 4/2014 Table 4. Added recommended pin connection when regulators are unused Update Table 9. Current Consumption summary Table 10. Removed VREFDDR_VOLT row Removed automatic fuse programming feature Updated Max frequency specification for the 16 MHz clock to 17.2 MHz Table 17. Added specification for derived 2.0 Mhz clock Added Clock adjustment Table 22. Updated VREFDDR minimum Current limit specification Updated Block diagram for all Switching Regulators Updated current limit and overcurrent protection minimum specification on LDOS Table 111. Update VTH0 and VTL0 specification on VSNVS Updated Table 137, Address FF Updated Table 138, address D8 and D9 Update Figure 35. Typical application diagram Removed Part Identification section Added part numbers to the ordering information for the MMPF0100A Added corrections and notes to the document to accomodate the new part numbers, where identified by MMPF0100A VIN Threshold (Coin Cell Powered to VIN Powered) Max. changed to 3.1 Removed LICELL connection to VIN on PF0100A Removed 4.7 F LICELL bypass capacitor as coin cell replacement Updated typical and max Off Current Add bypass capacitor in VDDIO Added industrial part numbers PMPF0100xxANES Added parts F3 and F4 Added Table 3, Ambient Temperature Range and updated specification headers accordingly. Increased max standby and sleep currents on Extended Industrial parts. Update output accuracy on SW1A/B, SW1C, SW2, SW3A/B and SW4. Corrected the default value on DEVICEID register, bit4 (unused) from 0 to 1. Corrected default register values on Table 118. Added VDDIO capacitor to Miscellaneous in the BOM * Corrected VDDOTP maximum rating * * * * * * * * Corrected SWBSTFB maximum rating Corrected inductor Isat for SW1ABC single phase mode from 4.5 A to 6.0 A Added note to clarify SWBST default operation in Auto mode Corrected default value of bits in SILICONREVID register in Table 136 Changed VSNVS current limit for PF0100A Noted that voltage settings 0.6V and below are not supported VSNVS Turn On Delay (td1) spec corrected from 15 ms to 5.0 ms Updated per GPCN 16298 6/2014 * Corrected GPCN number in the revision history table (16220 changed to 16298) 9.0 7/2014 10.0 7/2015 * * * * * Updated VTL1, VTH1, and VSNVSCROSS threshold specifications Added F6 part Changes documented in GPCN 16369 Added new part numbers MMPF0100F9ANES and MMPF0100FAANES to Table 1 Updated Table 10 PF0100 150 Analog Integrated Circuit Device Data Freescale Semiconductor Revision History Reference Documents REVISION DATE 11.0 8/2015 * Removed MMPF0100F3EP and MMPF0100F4EP from Orderable Parts table 9/2015 * * * * * * * * * * * * * * 12.0 DESCRIPTION OF CHANGES Updated Table 53 Updated Table 62 Updated Table 77 Updated Table 86 Fixed typo in Table 138 Updated Table 139 Added Table 140 Corrected the default register value for SW1ABMODE in Table 46 Corrected the default register value for SW1CMODE in Table 51 Corrected the default register value for SW2MODE in Table 60 Corrected the default register value for SW3AMODE in Table 70 Corrected the default register value for SW3BMODE in Table 75 Corrected the default register value for SW4MODE in Table 84 Updated Figure 35 PF0100 Analog Integrated Circuit Device Data Freescale Semiconductor 151 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. 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Document Number: MMPF0100 Rev. 12.0 9/2015 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Freescale Semiconductor: MMPF0100F0EP KITPF0100EPEVBE MMPF0100NPEP MMPF0100F0EPR2 MMPF0100F2EP MMPF0100NPEPR2 MMPF0100F1EP MMPF0100F1EPR2 MMPF0100F2EPR2 MMPF0100F0AEP MMPF0100F0AEPR2 MMPF0100F1AEPR2 MMPF0100F2AEP MMPF0100F1AEP MMPF0100F2AEPR2 MMPF0100F4AEP MMPF0100F3ANESR2 MMPF0100NPAEPR2 MMPF0100F3AEP MMPF0100F3ANES MMPF0100F3AEPR2 MMPF0100NPANESR2 MMPF0100F4ANESR2 MMPF0100F0ANESR2 MMPF0100NPANES MMPF0100F4AEPR2 MMPF0100F0ANES MMPF0100NPAEP MMPF0100F4ANES MMPF0100F6ANES MMPF0100F6AEPR2 MMPF0100F6ANESR2 MMPF0100F6AEP