2100 MHz to 2600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6603 The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. FEATURES Rx mixer with integrated fractional-N PLL RF input frequency range: 1100 MHz to 3200 MHz Internal LO frequency range: 2100 MHz to 2600 MHz Input P1dB: 14.8 dBm Input IP3: 28.5 dBm IIP3 optimization via external pin SSB noise figure IP3SET pin open: 14.3 dB IP3SET pin at 3.3 V: 15.6 dB Voltage conversion gain: 6.7 dB Matched 200 IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm x 6 mm LFCSP The loop filter output is then applied to an integrated VCO. The VCO output at 2 x fLO is applied to an LO divider, as well as to a programmable PLL divider. The programmable PLL divider is controlled by a sigma-delta (-) modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047. The active mixer converts the single-ended 50 RF input to a 200 differential IF output. The IF output can operate up to 500 MHz. The ADRF6603 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm x 6 mm LFCSP with an exposed paddle. Performance is specified over the -40C to +85C temperature range. APPLICATIONS Table 1. Cellular base stations GENERAL DESCRIPTION Part No. ADRF6601 The ADRF6603 is a high dynamic range active mixer with integrated phase-locked loop (PLL) and voltage controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate a fLO input to the mixer. The reference input can be divided or multiplied and then applied to the PLL phase frequency detector (PFD). ADRF6602 ADRF6603 ADRF6604 Internal LO Range 750 MHz 1160 MHz 1550 MHz 2150 MHz 2100 MHz 2600 MHz 2500 MHz 2900 MHz 3 dB RFIN Balun Range 300 MHz 2500 MHz 1000 MHz 3100 MHz 1100 MHz 3200 MHz 1200 MHz 3600 MHz 1 dB RFIN Balun Range 450 MHz 1600 MHz 1350 MHz 2750 MHz 1450 MHz 2850 MHz 1600 MHz 3200 MHz FUNCTIONAL BLOCK DIAGRAM VCC1 VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO 1 10 17 22 27 34 NC NC 32 33 ADRF6603 INTERNAL LO RANGE 2100MHz TO 2600MHz LODRV_EN 36 LON 37 BUFFER LOP 38 BUFFER PLL_EN 16 FRACTION MODULUS REG CLK 13 SPI INTERFACE LE 14 2:1 MUX INTEGER REG REF_IN 6 /2 /4 N COUNTER 21 TO 123 MUX TEMP SENSOR 7 2.5V LDO 9 DECL2P5 VCO LDO 40 DECLVCO VCO CORE PRESCALER /2 29 IP3SET CHARGE PUMP 250A, 500A (DEFAULT), 750A, 1000A - PHASE + FREQUENCY DETECTOR MUXOUT 8 4 DECL3P3 26 RF IN THIRD-ORDER FRACTIONAL INTERPOLATOR x2 DIV BY 2, 1 2 11 15 20 21 23 24 25 28 30 31 35 5 RSET GND 3 39 18 19 CP VTUNE IFP IFN 08547-001 DATA 12 3.3V LDO Figure 1. Rev. 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ADRF6603 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 RF Specifications .......................................................................... 3 Synthesizer/PLL Specifications ................................................... 4 Register 3--- Modulator Dither Control (Default: 0x10000B) ................................................................... 17 Register 4--PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)................................................... 18 Register 5--PLL Enable and LO Path Control (Default: 0x0000E5) ................................................................... 19 Register 6--VCO Control and VCO Enable (Default: 0x1E2106) ................................................................... 19 Logic Input and Power Specifications ....................................... 4 Register 7--Mixer Bias Enable and External VCO Enable (Default: 0x000007).................................................................... 19 Timing Characteristics ................................................................ 5 Theory of Operation ...................................................................... 20 Absolute Maximum Ratings............................................................ 6 Programming the ADRF6603................................................... 20 ESD Caution .................................................................................. 6 Initialization Sequence .............................................................. 20 Pin Configuration and Function Descriptions ............................. 7 LO Selection Logic ..................................................................... 21 Typical Performance Characteristics ............................................. 9 Applications Information .............................................................. 22 RF Frequency Sweep .................................................................... 9 Basic Connections for Operation ............................................. 22 IF Frequency Sweep ................................................................... 10 AC Test Fixture ............................................................................... 23 Spurious Performance................................................................ 15 Evaluation Board ............................................................................ 24 Register Structure ........................................................................... 16 Evaluation Board Control Software ......................................... 24 Register 0--Integer Divide Control (Default: 0x0001C0)..... 16 Schematic and Artwork ............................................................. 26 Register 1--Modulus Divide Control (Default: 0x003001) .. 16 Evaluation Board Configuration Options ............................... 28 Register 2--Fractional Divide Control (Default: 0x001802) .................................................................... 17 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29 REVISION HISTORY 11/10--Rev. 0 to Rev. A Changes to Features and General Description ............................. 1 Changes to Table 1 ............................................................................ 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 and Table 4 ....................................................... 4 Changes to Table 6 ............................................................................ 6 Change to Table 7, Pin 36 Description .......................................... 8 Changes to Typical Performance Characteristics Section ........... 9 Added Spurious Performance Section ......................................... 15 Changes to Programming the ADRF6603 Section .................... 20 Changes to Figure 46...................................................................... 22 Added AC Test Fixture Section and Figure 47; Renumbered Sequentially ............................................................. 23 Changes to Evaluation Board Control Software Section; Changes to Figure 48...................................................................... 24 Changes to Figure 49...................................................................... 25 Changes to Figure 50...................................................................... 26 1/10--Revision 0: Initial Version Rev. A | Page 2 of 32 ADRF6603 SPECIFICATIONS RF SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted. Table 2. Parameter INTERNAL LO FREQUENCY RANGE RF INPUT FREQUENCY RANGE RF INPUT AT 2140 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO-to-IF Leakage RF INPUT AT 2400 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO-to-IF Leakage RF INPUT AT 2650 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO-to-IF Leakage IF OUTPUT Voltage Conversion Gain IF Bandwidth Output Common-Mode Voltage Gain Flatness Gain Variation Output Swing Differential Output Return Loss LO INPUT/OUTPUT (LOP, LON) Frequency Range Output Level (LO as Output) Input Level (LO as Input) Input Impedance Test Conditions/Comments 3 dB RF input range Min 2100 1100 Relative to 50 (can be improved with external match) -5 dBm each tone (10 MHz spacing between tones) -5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1x LO frequency, 50 termination at the RF port Relative to 50 (can be improved with external match) -5 dBm each tone (10 MHz spacing between tones) -5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1x LO frequency, 50 termination at the RF port Relative to 50 (can be improved with external match) -5 dBm each tone (10 MHz spacing between tones) -5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1x LO frequency, 50 termination at the RF port Differential 200 load Small signal 3 dB bandwidth External pull-up balun or inductors required Over frequency range, any 5 MHz/50 MHz Over full temperature range Differential 200 load Measured through 4:1 balun Externally applied 1x LO input, internal PLL disabled Typ -6 Rev. A | Page 3 of 32 Unit MHz MHz <(-20) 14.9 55.3 29.3 15.6 14.4 -43 dB dBm dBm dBm dB dB dBm -16 14.9 55.1 28.6 15.8 14.2 -43 dB dBm dBm dBm dB dB dBm -11 14.7 52.1 28.1 15.8 14.5 -44 dB dBm dBm dBm dB dB dBm 6.7 500 5 0.2/1.0 1.2 2 -15 dB MHz V dB dB V p-p dB 250 1x LO into a 50 load, LO output buffer enabled Max 2600 3200 6000 -7 0 50 +6 MHz dBm dBm ADRF6603 SYNTHESIZER/PLL SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25C; fREF = 153.6 MHz; fREF power = 4 dBm; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted. Table 3. Parameter SYNTHESIZER SPECIFICATIONS Frequency Range Figure of Merit 1 Reference Spurs PHASE NOISE Integrated Phase Noise PFD Frequency REFERENCE CHARACTERISTICS REF_IN Input Frequency REF_IN Input Capacitance MUXOUT Output Level MUXOUT Duty Cycle CHARGE PUMP Pump Current Output Compliance Range 1 Test Conditions/Comments Synthesizer specifications referenced to 1x LO Internally generated LO PREF_IN = 0 dBm fPFD = 38.4 MHz fPFD/4 fPFD >fPFD fLO = 2100 MHz to 2600 MHz, fPFD = 38.4 MHz 1 kHz to 10 kHz offset 100 kHz offset 500 kHz offset 1 MHz offset 5 MHz offset 10 MHz offset 20 MHz offset 1 kHz to 40 MHz integration bandwidth Min Typ Max Unit 2600 -222 MHz dBc/Hz/Hz -107 -82 -85 dBc dBc dBc -88 -99.5 -120 -128 -142 -148 -150 0.42 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz rms MHz 2100 20 40 REF_IN, MUXOUT pins 12 160 4 VOL (lock detect output selected) VOH (lock detect output selected) 0.25 2.7 50 Programmable to 250 A, 500 A, 750 A, 1 mA 500 1 MHz pF V V % A V 2.8 The figure of merit (FOM) is computed as phase noise (dBc/Hz) - 10Log10(fPFD) - 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz, and fREF power = 10 dBm (500 V/s slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset. LOGIC INPUT AND POWER SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted. Table 4. Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Range Supply Current Test Conditions/Comments CLK, DATA, LE Min Typ 1.4 0 Max Unit 3.3 0.7 V V A pF 5.25 V mA mA mA mA mA 0.1 5 VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins 4.75 PLL only External LO mode (internal PLL disabled, LO output buffer off, IP3SET pin = 3.3 V) Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) Power-down mode Rev. A | Page 4 of 32 5 97 164 274 261 30 ADRF6603 TIMING CHARACTERISTICS VCC2 = 5 V 5%. Table 5. Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Description LE setup time DATA-to-CLK setup time DATA-to-CLK hold time CLK high duration CLK low duration CLK-to-LE setup time LE pulse width Timing Diagram t4 t5 CLK t2 DATA DB23 (MSB) t3 DB22 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) t1 DB0 (LSB) (CONTROL BIT C1) t7 08547-002 t6 LE Figure 2. Timing Diagram Rev. A | Page 5 of 32 ADRF6603 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Supply Voltage, VCC1, VCC2, VCC_LO, VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE, LODRV_EN, PLL_EN VTUNE IFP, IFN RFIN LOP, LON, REF_IN JA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating -0.5 V to +5.5 V -0.3 V to +3.6 V 0 V to 3.3 V -0.3 V to VCC_V2I + 0.3 V 16 dBm 13 dBm 35C/W 150C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. A | Page 6 of 32 ADRF6603 40 39 38 37 36 35 34 33 32 31 DECLVCO VTUNE LOP LON LODRV_EN GND VCC_LO NC NC GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADRF6603 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 GND IP3SET GND VCC_V2I RFIN GND GND GND VCC_MIX GND NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. 08547-003 GND 11 DATA 12 CLK 13 LE 14 GND 15 PLL_EN 16 VCC_LO 17 IFP 18 IFN 19 GND 20 VCC1 1 DECL3P3 2 CP 3 GND 4 RSET 5 REF_IN 6 GND 7 MUXOUT 8 DECL2P5 9 VCC2 10 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic VCC1 2 3 4, 7, 11, 15, 20, 21, 23, 24, 25, 28, 30, 31, 35 5 DECL3P3 CP GND RSET Description Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Decoupling Node for 3.3 V LDO. Connect a 0.1 F capacitor between this pin and ground. Charge Pump Output Pin. Connect to VTUNE through the loop filter. Ground. Connect these pins to a low impedance ground plane. Charge Pump Current. The nominal charge pump current can be set to 250 A, 500 A, 750 A, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally adjusted according to the following equation: 217.4 x I CP R SET = I NOMINAL 6 REF_IN 8 MUXOUT 9 10 DECL2P5 VCC2 12 13 DATA CLK 14 LE 16 PLL_EN - 37.8 Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dcbiased and should be ac-coupled. Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register. Decoupling Node for 2.5 V LDO. Connect a 0.1 F capacitor between this pin and ground. Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the eight registers. The relevant latch is selected by the three control bits of the 24-bit word. PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be used to switch modes. Rev. A | Page 7 of 32 ADRF6603 Pin No. 17, 34 Mnemonic VCC_LO 18, 19 22 IFP, IFN VCC_MIX 26 27 RFIN VCC_V2I 29 32, 33 36 IP3SET NC LODRV_EN 37, 38 LON, LOP 39 VTUNE 40 DECLVCO EPAD Description Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes. Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. RF Input (Single-Ended, 50 ). Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open. No Connection. LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. External LO drive frequency must be 1x LO. This pin has an internal 100 k pull down resistor. Local Oscillator Input/Output. The internally generated 1x LO is available on these pins. When internal LO generation is disabled, an external 1x LO can be applied to these pins. VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.5 V to 2.5 V. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 F capacitor between this pin and ground. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. Rev. A | Page 8 of 32 ADRF6603 TYPICAL PERFORMANCE CHARACTERISTICS RF FREQUENCY SWEEP CDAC = 0x1, internally generated high-side LO, RFIN = -5 dBm, fIF = 140 MHz, unless otherwise noted. 5 4 IP3SET = OPEN IP3SET = 3.3V 40 TA = +85C TA = +25C TA = -40C IP3SET = OPEN IP3SET = 3.3V TA = +85C TA = +25C TA = -40C 35 3 INPUT IP3 (dBm) GAIN (dB) 2 1 0 -1 30 25 -2 20 -3 RF FREQUENCY (MHz) 15 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 08547-104 -5 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 RF FREQUENCY (MHz) Figure 4. Gain vs. RF Frequency 90 IP3SET = OPEN IP3SET = 3.3V Figure 7. Input IP3 vs. RF Frequency 20 TA = +85C TA = +25C TA = -40C 19 IP3SET = OPEN IP3SET = 3.3V TA = +85C TA = +25C TA = -40C 18 INPUT P1dB (dBm) INPUT IP2 (dBm) 80 08547-107 -4 70 60 50 17 16 15 14 13 12 40 20 18 14 12 10 8 6 4 TA = +85C TA = +25C TA = -40C 0 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 RF FREQUENCY (MHz) 08547-106 NOISE FIGURE (dB) 16 IP3SET = OPEN IP3SET = 3.3V RF FREQUENCY (MHz) Figure 8. Input P1dB vs. RF Frequency Figure 5. Input IP2 vs. RF Frequency 2 10 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 Figure 6. Noise Figure vs. RF Frequency Rev. A | Page 9 of 32 08547-108 RF FREQUENCY (MHz) 08547-105 11 30 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 ADRF6603 IF FREQUENCY SWEEP CDAC = 0x1, internally generated swept low-side LO, fRF = 1960 MHz, RFIN = -5 dBm, unless otherwise noted. 5 4 IP3SET = OPEN IP3SET = 3.3V 45 TA = +85C TA = +25C TA = -40C 40 IP3SET = OPEN IP3SET = 3.3V TA = +85C TA = +25C TA = -40C 3 35 INPUT IP3 (dBm) GAIN (dB) 2 1 0 -1 30 25 20 -2 15 -3 IF FREQUENCY (MHz) 5 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 08547-109 -5 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 IF FREQUENCY (MHz) Figure 12. Input IP3 vs. IF Frequency, RFIN = -5 dBm Figure 9. Gain vs. IF Frequency 90 IP3SET = OPEN IP3SET = 3.3V 20 TA = +85C TA = +25C TA = -40C 18 IP3SET = OPEN IP3SET = 3.3V TA = +85C TA = +25C TA = -40C 16 INPUT P1dB (dBm) INPUT IP2 (dBm) 80 08547-112 10 -4 70 60 50 14 12 10 8 6 4 40 IF FREQUENCY (MHz) Figure 10. Input IP2 vs. IF Frequency, RFIN = -5 dBm 20 18 14 12 10 8 6 4 TA = +85C TA = +25C TA = -40C IF FREQUENCY (MHz) 08547-111 NOISE FIGURE (dB) 16 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 IF FREQUENCY (MHz) Figure 13. Input P1dB vs. IF Frequency IP3SET = OPEN IP3SET = 3.3V 2 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 Figure 11. Noise Figure vs. IF Frequency Rev. A | Page 10 of 32 08547-113 30 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 08547-110 2 ADRF6603 0 TA = +85C TA = +25C TA = -40C -10 -2 -4 -15 RETURN LOSS (dB) -20 -25 -30 -35 -40 -8 -10 -12 -14 -45 -16 -50 LO FREQUENCY (MHz) Figure 14. LO-to-IF Feedthrough vs. LO Frequency, LO Output Turned Off, CDAC = 0x0 -20 -25 IP3SET = OPEN IP3SET = 3.3V -20 1900 08547-114 -60 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 2100 2200 2300 2400 2500 2600 2700 2800 LO FREQUENCY (MHz) Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun) TA = +85C TA = +25C TA = -40C -30 2000 08547-117 -18 -55 350 3.5 300 3.0 -35 -40 RESISTANCE 250 RESISTANCE () LO-TO-RF LEAKAGE (dBm) -6 -45 -50 -55 -60 -65 -70 2.5 200 2.0 150 1.5 CAPACITANCE 100 1.0 50 0.5 CAPACITANCE (pF) LO-TO-IF FEEDTHROUGH (dBm) 0 IP3SET = OPEN IP3SET = 3.3V -5 -75 -80 -85 2300 2400 2500 2600 LO FREQUENCY (MHz) 0 50 Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off 150 200 250 300 350 400 450 0 500 IF FREQUENCY (MHz) Figure 18. IF Differential Output Impedance (R Parallel C Equivalent) 35 0 -5 IP3SET = OPEN IP3SET = 3.3V 30 NOISE FIGURE (dB) -10 -15 -20 -25 -30 -35 25 20 15 -45 1900 2000 2100 2200 2300 2400 2500 2600 2700 RF FREQUENCY (MHz) 2800 10 -60 -50 -40 -30 -20 -10 CW BLOCKER LEVEL (dBm) Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level, LO Frequency = 2105 MHz, RF Frequency = 1965 MHz Figure 16. RF Input Return Loss vs. RF Frequency Rev. A | Page 11 of 32 0 08547-119 -40 08547-116 RETURN LOSS (dB) 100 08547-118 2200 08547-115 -90 2100 ADRF6603 0 IP3SET = OPEN IP3SET = 3.3V -5 -10 TA = +85C TA = +25C TA = -40C 4.5 4.0 -15 VTUNE VOLTAGE (V) -20 -25 -30 -35 -40 3.5 3.0 2.5 2.0 1.5 -45 1.0 -50 0.5 -55 2000 2100 2200 2300 2400 2500 2600 2700 2800 LO FREQUENCY (MHz) 0 2100 08547-120 -60 1900 2200 Figure 20. RF-to-IF Isolation vs. RF Frequency, High-Side LO, IF = 140 MHz, LO Output Turned Off -2 IP3SET = OPEN IP3SET = 3.3V 2400 2500 2600 Figure 23. VTUNE vs. LO Frequency 350 TA = +85C TA = +25C TA = -40C -4 IP3SET = OPEN IP3SET = 3.3V TA = +85C TA = +25C TA = -40C 300 SUPPLY CURRENT (mA) LO OUTPUT AMPLITUDE (dBm) -3 2300 LO FREQUENCY (MHz) 08547-123 RF-TO-IF ISOLATION (dB) 5.0 TA = +85C TA = +25C TA = -40C -5 -6 -7 -8 -9 250 200 150 -10 LO FREQUENCY (MHz) 100 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 08547-121 -12 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 21. LO Output Amplitude vs. LO Frequency Figure 24. Supply Current vs. LO Frequency 2.5 20 2.4 15 IP3SET = OPEN IP3SET = 3.3V 2.3 2.2 VPTAT VOLTAGE (V) 10 5 0 -5 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 -10 1.3 1.2 -15 0 50 100 150 TIME (s) 200 250 1.0 -55 Figure 22. Frequency Deviation from 2140 MHz vs Time (Demonstrates LO Frequency Settling Time from 2150 MHz to 2140 MHz) -35 -15 5 25 45 TEMPERATURE (C) 65 85 105 08547-125 1.1 -20 08547-122 FREQUENCY DEVIATION FROM 2140MHz (MHz) 08547-124 -11 Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open) Rev. A | Page 12 of 32 ADRF6603 Complementary cumulative distribution function (CCDF), fRF = 2140 MHz, fIF = 140 MHz. 70 60 50 40 30 20 80 70 60 50 40 30 20 TA = +85C TA = +25C TA = -40C 10 10 -0.5 0 0.5 1.0 1.5 2.0 GAIN (dB) 0 20 08547-126 0 -1.0 22 24 DISTRIBUTION PERCENTAGE (%) DISTRIBUTION PERCENTAGE (%) 60 50 40 30 20 10 50 55 60 65 70 70 60 50 40 30 IP3SET = OPEN IP3SET = 3.3V 20 TA = +85C TA = +25C TA = -40C INPUT IP2 (dBm) 0 08547-127 45 9 10 11 100 90 DISTRIBUTION PERCENTAGE (%) 80 70 60 50 40 30 20 TA = +85C TA = +25C TA = -40C 15 NOISE FIGURE (dB) 15 16 17 18 16 17 80 70 60 50 40 30 20 TA = +85C TA = +25C TA = -40C 10 18 08547-128 10 14 14 IP3SET = OPEN IP3SET = 3.3V 90 13 13 Figure 30. Input P1dB IP3SET = OPEN 12 12 INPUT P1dB (dBm) Figure 27. Input IP2 0 11 36 80 10 0 40 DISTRIBUTION PERCENTAGE (%) 34 90 70 100 32 100 TA = +85C TA = +25C TA = -40C 80 30 Figure 29. Input IP3 IP3SET = OPEN IP3SET = 3.3V 90 28 INPUT IP3 (dBm) Figure 26. Gain 100 26 08547-129 DISTRIBUTION PERCENTAGE (%) TA = +85C TA = +25C TA = -40C 80 IP3SET = OPEN IP3SET = 3.3V 90 08547-130 90 DISTRIBUTION PERCENTAGE (%) 100 IP3SET = OPEN IP3SET = 3.3V 0 -55 -53 -51 -49 -47 -45 -43 -41 -39 -37 LO FEEDTHROUGH (dBm) Figure 31. LO Feedthrough to IF, LO Output Turned Off Figure 28. Noise Figure Rev. A | Page 13 of 32 -35 08547-131 100 ADRF6603 Measured at IF output, CDAC = 0x1, IP3SET = open, internally generated high-side LO, fREF = 153.6 MHz, fPFD = 38.4 MHz, RFIN = -5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted. 1.0 -80 TA = +85C TA = +25C TA = -40C -100 -110 -120 LO FREQUENCY = 2115.2MHz -130 -140 -150 0.8 0.7 0.6 0.5 0.4 0.3 0.2 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 35. Integrated Phase Noise vs. LO Frequency Figure 32. Phase Noise vs. Offset Frequency -75 -80 2x PFD FREQUENCY 4x PFD FREQUENCY TA = +85C TA = +25C TA = -40C OFFSET = 1kHz PHASE NOISE (dBc/Hz) -90 -85 -90 -95 -100 -100 OFFSET = 100kHz -110 -120 -130 OFFSET = 5MHz -140 -105 -150 -110 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 -160 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) 08547-133 SPURRS LEVEL (dBc) -80 Figure 33. PLL Reference Spurs vs. LO Frequency (2x PFD and 4x PFD) -75 08547-135 0.1 08547-132 -160 1k TA = +85C TA = +25C TA = -40C 0.9 LO FREQUENCY (MHz) Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps) -80 TA = +85C TA = +25C TA = -40C 3x PFD FREQUENCY 1x PFD FREQUENCY -80 TA = +85C TA = +25C TA = -40C 08547-136 PHASE NOISE (dBc/Hz) -90 INTEGRATED PHASE NOISE (rms) LO FREQUENCY = 2595.2MHz -90 PHASE NOISE (dBc/Hz) -85 -90 -95 -100 -110 -120 OFFSET = 1MHz -130 -140 0.25x PFD FREQUENCY -150 -110 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 -160 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) 08547-134 -105 Figure 34. PLL Reference Spurs vs. LO Frequency (0.25x PFD, 1x PFD, and 3x PFD) Rev. A | Page 14 of 32 TA = +85C TA = +25C TA = -40C LO FREQUENCY (MHz) Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps) 08547-137 SPURRS LEVEL (dBc) OFFSET = 10kHz -100 ADRF6603 SPURIOUS PERFORMANCE (N x fRF) - (M x fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious products were measured in dB relative to the carrier (dBc) from the IF output power level. All spurious components greater than -125 dBc are shown. LO = 2280 MHz, RF = 2140 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm. N 0 -114.35 -20.79 -58.20 0 1 2 3 4 5 6 7 1 -45.19 0.0 -61.95 -71.79 M 2 -36.94 -67.43 -78.15 -91.89 -107.79 3 -52.11 -85.93 -67.46 -110.27 -107.88 4 -93.10 -105.88 -107.87 -112.41 -107.71 -108.62 LO = 2540 MHz, RF = 2400 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm. N 0 -113.65 -18.91 -59.08 0 1 2 3 4 5 6 7 1 -47.04 0.0 -60.49 -77.54 M 2 -36.36 -65.01 -69.27 -89.56 -108.79 3 -56.24 -89.85 -68.39 -110.65 -108.85 4 -94.25 -109.30 -111.94 -111.54 -108.89 LO = 2650 MHz, RF = 2510 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm. N 0 1 2 3 4 5 6 7 0 -111.38 -17.70 -58.49 1 -46.57 0.0 -75.49 -81.35 M 2 -36.03 -65.70 -72.27 -89.18 -106.13 Rev. A | Page 15 of 32 3 -54.37 -71.05 -68.23 -106.74 -107.26 4 -95.32 -103.38 -112.72 -105.45 -110.74 ADRF6603 REGISTER STRUCTURE This section provides the register maps for the ADRF6603. The three LSBs determine the register that is programmed. REGISTER 0--INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0) DIVIDE MODE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 0 0 0 0 0 0 0 0 0 0 0 INTEGER DIVIDE RATIO CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) 0 0 DM DIVIDE MODE 0 FRACTIONAL (DEFAULT) 1 INTEGER DB1 ID6 ID5 ID4 ID3 ID2 ID1 ID0 INTEGER DIVIDE RATIO 0 0 1 0 1 0 1 21 (INTEGER MODE ONLY) 0 0 1 0 1 1 0 22 (INTEGER MODE ONLY) 0 0 1 0 1 1 1 23 (INTEGER MODE ONLY) 0 0 1 1 0 0 0 24 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 56 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 119 1 1 1 1 0 0 0 120 (INTEGER MODE ONLY) 1 1 1 1 0 0 1 121 (INTEGER MODE ONLY) 1 1 1 1 0 1 0 122 (INTEGER MODE ONLY) 1 1 1 1 0 1 1 123 (INTEGER MODE ONLY) DB0 08547-004 RESERVED Figure 38. Register 0--Integer Divide Control Register Map REGISTER 1--MODULUS DIVIDE CONTROL (DEFAULT: 0x003001) MODULUS VALUE 0 0 0 0 0 0 0 0 0 0 MD10 CONTROL BITS DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 MD9 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1) MD8 MD7 DB1 DB0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MODULUS VALUE 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 2 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 0 0 0 0 0 0 1536 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1 1 1 2047 Figure 39. Register 1--Modulus Divide Control Register Map Rev. A | Page 16 of 32 08547-005 RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 ADRF6603 REGISTER 2--FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802) RESERVED 0 0 0 0 0 0 0 FD10 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 FD9 FD6 FD5 FD4 FD3 FD2 FD1 FD0 FD8 FD7 DB2 DB1 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 FRACTIONAL VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 0 0 0 0 0 0 0 0 768 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... DB0 C3(0) C2(1) C1(0) 08547-006 0 CONTROL BITS FRACTIONAL VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 <MDR FRACTIONAL VALUE MUST BE LESS THAN MODULUS Figure 40. Register 2--Fractional Divide Control Register Map REGISTER 3--- MODULATOR DITHER CONTROL (DEFAULT: 0x10000B) DITHER DITHER RESTART VALUE CONTROL BITS ENABLE DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1) DITH1 0 0 DITH0 0 1 DITHER MAGNITUDE 15 (DEFAULT) 7 1 0 3 1 1 1 (RECOMMENDED) DEN 0 1 DITHER ENABLE DISABLE ENABLE (DEFAULT, RECOMMENDED) DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 DITHER RESTART VALUE 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0x00001 (DEFAULT) ... ... 0x1FFFF 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 Figure 41. Register 3--- Modulator Dither Control Register Map Rev. A | Page 17 of 32 0 ... ... 1 1 ... ... 1 08547-007 DB23 0 DITHER MAGNITUDE DB22 DB21 DITH1 DITH0 ADRF6603 REGISTER 4--PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4) REF OUPUT MUX SELECT DB23 DB22 CP INPUT REF CURRENT REF PATH SOURCE DB21 DB20 DB19 RMS2 RMS1 RMS0 RS1 RS0 PFD PHASE OFFSET MULTIPLIER PFD POL CP CURRENT CP CP SRC CONTROL DB8 PFD EDGE DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB6 DB5 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PFD ANTI BACKLASH DELAY DB4 DB3 CONTROL BITS DB2 DB1 DB0 PAB1 PAB0 C3(1) C2(0) C1(0) PAB0 PAB1 PFD ANTI BACKLASH DELAY 0 0 0ns (DEFAULT) 0 1 0.5ns 1 0 0.75ns 1 1 0.9ns PE1 0 1 PE0 REFERENCE PATH EDGE SENSITIVITY 0 1 FALLING EDGE RISING EDGE (DEFAULT) DIVIDER PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE (DEFAULT) CPC1 CPC0 CHARGE PUMP CONTROL 0 0 1 1 0 1 0 1 BOTH ON PUMP DOWN PUMP UP TRISTATE (DEFAULT) CPS CHARGE PUMP CONTROL SOURCE 0 1 CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) CONTROL FROM PFD (DEFAULT) CPP1 CPP0 CHARGE PUMP CURRENT 0 0 1 1 0 1 0 1 250A 500A (DEFAULT) 750A 1000A CPB4 CPB3 CPB2 CPB1 CPB0 PFD PHASE OFFSET MULTIPLIER 0 0 0 0 1 1 CPM 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 CPBD PFD PHASE OFFSET POLARITY 0 1 NEGATIVE POSITIVE (DEFAULT) 0 x 22.5/ICPMULT 1 x 22.5/ICPMULT 6 x 22.5/ICPMULT (RECOMMENDED) 10 x 22.5/ICPMULT (DEFAULT) 16 x 22.5/ICPMULT 31 x 22.5/ICPMULT CHARGE PUMP CURRENT REFERENCE SOURCE INTERNAL (DEFAULT) EXTERNAL RS0 INPUT REFERENCE RS1 PATH SOURCE 0 0 1 1 0 1 0 1 2x REFIN REFIN (DEFAULT) 0.5x REFIN 0.25x REFIN RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOCK DETECT (DEFAULT) VPTAT REFIN (BUFFERED) 0.5x REFIN (BUFFERED) 2x REFIN (BUFFERED) TRISTATE RESERVED RESERVED 08547-008 0 0 0 0 1 1 1 1 Figure 42. Register 4--PLL Charge Pump, PFD, and Reference Path Control Register Map Rev. A | Page 18 of 32 ADRF6603 REGISTER 5--PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5) CAP DAC RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 0 0 CD3 0 CD2 CD1 CD0 PLL EN RES LO DIV1 LO EXT DB7 DB6 DB5 DB4 LDV2 PLEN LDV1 LXL LO DRV CONTROL BITS DB3 DB2 DB1 DB0 LDRV C3(1) C2(0) C1(1) CD3 CD2 CD1 CD0 CAPACITOR DAC CONTROL FOR IIP3 OPTIMIZATION LO OUTPUT DRIVER LDRV ENABLE 0 ... 1 0 ... 1 0 ... 1 0 ... 1 MIN ... MAX 0 1 DRIVER OFF (DEFAULT) DRIVER ON EXTERNAL LO DRIVE LXL ENABLE (PIN 37, PIN 38) 0 1 INTERNAL LO OUTPUT (DEFAULT) EXTERNAL LO INPUT DIVIDE-BY-2 IN LO CHAIN ENABLE 0 1 DIVIDE BY 1 DIVIDE BY 2 (DEFAULT) PLEN PLL ENABLE 0 1 DISABLE ENABLE (DEFAULT) 08547-009 LDV1 Figure 43. Register 5--PLL Enable and LO Path Control Register Map REGISTER 6--VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106) CHARGE 3.3V VCO PUMP LDO VCO LDO VCO ENABLE ENABLE ENABLE ENABLE SWITCH DB23 DB22 DB21 0 0 0 DB20 CPEN DB19 L3EN DB18 LVEN VCO AMPLITUDE DISABLE ENABLE (DEFAULT) L3EN 3.3V LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT) LVEN VCO LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT) VCO BAND SELECT FROM SPI CONTROL BITS DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0) CPEN CHARGE PUMP ENABLE 0 1 VCO BW SW CTRL VC[5:0] VCO AMPLITUDE VBS[5:0] VCO BAND SELECT FROM SPI 0x00 .... 0x18 .... 0x2B .... 0x3F 0x00 0x01 .... 0x3F DEFAULT 0x20 0 .... 24 (DEFAULT) .... 43 .... 63 (RECOMMENDED) VCO SW VCO SWITCH CONTROL FROM SPI 0 1 REGULAR (DEFAULT) BAND CAL VCO EN VCO ENABLE 0 1 DISABLE ENABLE (DEFAULT) VBSRC VCO BW CAL AND SW SOURCE CONTROL 0 1 BAND CAL (DEFAULT) SPI 08547-010 RESERVED Figure 44. Register 6--VCO Control and VCO Enable Register Map REGISTER 7--MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007) RES MIXER XVCO B_EN RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 0 XVCO MBE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONTROL BITS DB4 DB3 DB2 DB1 DB0 0 0 C3(1) C2(1) C1(1) MBE MIXER BIAS ENABLE ENABLE (DEFAULT) 0 DISABLE 1 EXTERNAL VCO INTERNAL VCO (DEFAULT) EXTERNAL VCO 08547-011 XVCO 0 1 Figure 45. Register 7--Mixer Bias Enable and External VCO Enable Register Map Rev. A | Page 19 of 32 ADRF6603 THEORY OF OPERATION The ADRF6603 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer optimization functions, as well as allowing for an externally applied LO or VCO. The mixer core within the ADRF6603 is the next generation of an industry-leading family of mixers from Analog Devices, Inc. The RF input is converted to a current and then mixed down to IF using high performance NPN transistors. The mixer output currents are transformed to a differential output. The high performance active mixer core results in an exceptional IIP3 and IP1dB, with a very low output noise floor for excellent dynamic range. Over the specified frequency range, the ADRF6603 typically provides IF input P1dB of 14.6 dBm and IIP3 of 27 dBm. Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC (CDAC), which is programmable via the SPI port, and by using a resistor to a 5 V supply from the IP3SET pin (Pin 29). Adjustment of the capacitor DAC allows increments in phase shift at internal nodes in the ADRF6603, thus allowing cancellation of third-order distortion with no change in supply current. Connecting a resistor to a 5 V supply from the IP3SET pin increases the internal mixer core current, thereby improving overall IIP2 and IIP3, as well as IP1dB. Using the IP3SET pin for this purpose increases the overall supply current. The fractional divide function of the PLL allows the frequency multiplication value from REF_IN to LO output to be a fractional value rather than be restricted to an integer value as in traditional PLLs. In operation, this multiplication value is INT + (FRAC/MOD), where INT is the integer value, FRAC is the fractional value, and MOD is the modulus value, all programmable via the SPI port. In other fractional-N PLL designs, fractional multiplication is achieved by periodically changing the fractional value in a deterministic way. The disadvantage of this approach is often spurious components close to the fundamental signal. In the ADRF6603, a - modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function. PROGRAMMING THE ADRF6603 The ADRF6603 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Table 8. Table 8. ADRF6603 Register Functions Register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Function Integer divide control for the PLL Modulus divide control for the PLL Fractional divide control for the PLL - modulator dither control PLL charge pump, PFD, reference path control PLL enable and LO path control VCO control and VCO enable Mixer bias enable and external VCO enable Note that internal calibration for the PLL must be run when the ADRF6603 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 should always be programmed last and in this order: Register 0, Register 1, Register 2. To program the frequency of the ADRF6603, the user typically programs only Register 0, Register 1, and Register 2. However, if registers other than these are programmed first, a short delay should be inserted before programming Register 0. This delay ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated. Software is available on the ADRF6603 product page under the Evaluation Boards & Development Kits section that allows easy programming from a PC running Windows XP or Vista. INITIALIZATION SEQUENCE To ensure proper power-up of the ADRF6603, it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V 0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions. To ensure that the PLL is reset after power-up, follow this procedure: 1. 2. Disable the PLL by setting the PLEN bit to 0 (Register 5, Bit DB6). After a delay of >100 ms, set the PLEN bit to 1 (Register 5, Bit DB6). After this procedure is followed, the other registers should be programmed in this order: Register 7, Register 6, Register 4, Register 3, Register 2, Register 1. Then, after a delay of >100 ms, Register 0 should be programmed. Rev. A | Page 20 of 32 ADRF6603 LO SELECTION LOGIC The downconverting mixer in the ADRF6603 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer. The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Table 9. Table 9. LO Selection Logic Pin 16 (PLL_EN) 0 0 1 1 1 1 1 Pins 1 Pin 36 (LODRV_EN) X X X 0 X 1 Register 5 Bits1 Bit DB6 (PLEN) Bit DB3 (LDRV) 0 X 1 X 0 X 1 0 1 1 1 X X = don't care. Rev. A | Page 21 of 32 Output Buffer Disabled Disabled Disabled Disabled Enabled Enabled Outputs LO External External External Internal Internal Internal ADRF6603 APPLICATIONS INFORMATION be ac-coupled and terminated with a 50 resistor as shown in Figure 46. The reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin. BASIC CONNECTIONS FOR OPERATION Figure 46 shows the schematic for the ADRF6603 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 F capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 46. The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Evaluation Board Configuration Options section. The RF input is internally ac-coupled and needs no external bias. The IF outputs are open collector, and a bias inductor is required from these outputs to VCC. Operation with an external VCO is also possible. In this case, the loop filter components should be referred to ground. The output of the loop filter is connected to the input voltage pin of the external VCO. The output of the VCO is brought back into the device on the LOP and LON pins, using a balun if necessary. The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF_IN pin, which should 1 2 3 4 5 6 VCC S2 R53 10k (0402) VCC RED +5V C19 0.1F (0402) C9 0.1F (0402) C33 OPEN (0402) R51 OPEN (0402) R6 0 (0402) C8 100pF (0402) R26 0 (0402) C24 100pF (0402) R25 0 (0402) C22 100pF (0402) R24 0 (0402) C21 100pF (0402) R17 0 (0402) C18 100pF (0402) R7 0 (0402) C10 100pF (0402) C32 OPEN (0402) R50 OPEN (0402) VCC_V2I LO IN/OUT LON 3 4 C5 1nF LOP 1 (0402) 5 T8 TC1-1-13+ REF_IN R70 49.9 (0402) VCC1 10 1 16 13 12 14 DECL2P5 9 37 DIVIDER /2 BUFFER 38 BUFFER FRACTION REG MODULUS 2:1 MUX INTEGER REG 2 DIV BY 2, 1 ADRF6603 26 THIRD-ORDER FRACTIONAL INTERPOLATOR x2 N COUNTER 21 TO 123 6 /2 MUXOUT R16 0 (0402) VCC2 17 C16 R18 100pF 0 (0402) (0402) C17 0.1F (0402) C42 10F (0603) DECL3P3 C12 R8 100pF 0 (0402) (0402) C11 0.1F (0402) C41 OPEN (0603) SPI INTERFACE TEMP SENSOR 8 4 7 11 15 20 21 23 24 25 38 30 31 35 RSET R2 R37 OPEN 0 (0402) (0402) CP TEST POINT (ORANGE) R38 0 (0402) C14 22pF (0603) 29 3 5 39 CP 40 18 R10 3k (0603) C15 2.7nF (1206) C2 OPEN (0402) C13 6.8pF (0603) R1 0 (0402) C40 22pF (0603) R63 OPEN (0402) 1 4 2 R59 0 (0402) 3 5 RFOUT R43 0 (0402) C29 0.1F (0402) R12 0 (0402) C1 100pF (0402) Figure 46. Basic Connections for Operation of the ADRF6603 Rev. A | Page 22 of 32 IFN VCC +5V VTUNE C27 0.1F (0402) 19 VTUNE DECLVCO IFP R62 0 (0402) RFIN IP3SET R27 0 (0402) R9 10k R65 10k (0402) (0402) R11 OPEN (0402) C43 10F (0603) R28 0 (0402) CHARGE PUMP 250A, 500A (DEFAULT), 750A, 1000A - PHASE + FREQUENCY DETECTOR RFIN VCO CORE PRESCALER /2 MUX /4 REFOUT VCC_LO 22 36 C6 1nF (0402) C31 1nF (0402) REF_IN VCC_MIX 27 LE C20 0.1F (0402) DATA C23 0.1F (0402) 34 LODRV_EN R52 OPEN (0402) C25 0.1F (0402) CLK VCC_LO R56 0 (0402) C34 OPEN (0402) C7 0.1F (0402) PLL_EN VCC1 RED R55 OPEN (0402) S1 OPEN P1 9-PIN DSUB 9 R36 0 R30 (0402) 0 R57 (0402) 0 (0402) R35 0 (0402) R19 0 R20 (0402) 0 (0402) R54 10k (0402) 8 7 08547-024 A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms for a sine wave input) results in an IF output power of 4.7 dBm. ADRF6603 AC TEST FIXTURE Characterization data for the ADRF6603 was taken under very strict test conditions. All possible techniques were used to achieve optimum accuracy and to remove degrading effects of the signal generation and measurement equipment. Figure 47 shows the typical AC test set up used in the characterization of the ADRF6603. ADRF6603 CHARACTERIZATION RACK DIAGRAM. ALL INSTRUMENTS ARE CONTROLLED BY A LAB COMPUTER VIA A USB TO GPIB CONTROLLER, DAISY CHAINED TO EACH INDIVIDUAL INSTRUMENT. RF1 AGILENT N5181A HP 11636A POWER DIVIDER RF2 AGILENT N5181A REF_IN AGILENT N5181A RFIN REF_IN ADRF6603 EVALUATION BOARD 9-PIN CONTROLLER DSUB AND 10-PIN DC HEADER IF_OUT ROHDE & SCHWARTZ FSEA30 AGILENT 34401A SET TO IDC (SET FOR SUPPLY CURRENT) GND VIA 10-PIN DC HEADER 5V dc VIA 10-PIN DC HEADER 3.3V dc VIA 10-PIN DC HEADER AGILENT 34980A WITH THREE 34921 MODULES AND ONE 34950 MODULE AGILENT E3631A 25V SET TO 3.3V, 6V SET TO 5V. RETURNS ARE JUMPERED TOGETHER Figure 47. ADRF6603 AC Test Setup Rev. A | Page 23 of 32 08547-047 5V dc MEASURED FOR SUPPLY CURRENT ADRF6603 EVALUATION BOARD Figure 50 shows the schematic of the RoHS-compliant evaluation board for the ADRF6603. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material. The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6--VCO Control and VCO Enable (Default: 0x1E2106) section). To connect the evaluation board to a USB port, a USB adapter board (EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices. This board connects to the PC using a standard USB cable with a USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6603 evaluation board. Additional configuration options for the evaluation board are described in Table 10. EVALUATION BOARD CONTROL SOFTWARE The evaluation board can be connected to the PC using a PC parallel port or a USB port. These options are selectable from the opening menu of the software interface (see Figure 48). The evaluation board is shipped with a 25-pin parallel port cable for connection to the PC parallel port. 08547-048 Software to program the ADRF6603 is available for download on the ADRF6603 product page under the Evaluation Boards & Development Kits section. To install the software 1. Download and extract the zip file: ADRF6x0x_3p0p0_XP_install.exe file. 2. Follow the instructions in the read me file. Figure 48. Control Software Opening Menu Figure 49 shows the main menu of the control software with the default settings displayed. Rev. A | Page 24 of 32 08547-049 ADRF6603 Figure 49. Main Screen of the ADRF6603 Evaluation Board Software Rev. A | Page 25 of 32 3P3V_LDO AGND AGND AGND REFIN R70 49.9 AGND AGND OSC_3P3V 1000PF C31 10PF 22000PF C3 C4 0 AGND 100PF 0.1UF OSC_3P3V 1 R15 C12 C11 10UF 0 R8 C41 3P3V1 1 AGND 100PF AGND C10 0.1UF 0 R7 C9 VCC4 1 VCC 0 22PF C14 DNI R11 0 R37 0 R16 AGND 2P5V_LDO REFOUT DNI R49 VCO_LDO 1 VCC AGND C42 10UF P1-1 10UF C13 6.8PF 100PF AGND 0.1UF AGND C19 0 C18 AGND AGND R17 100PF 0.1UF VCC2 1 22PF C40 R2 R72 R62 R50 1K DNI CLK DNI 1 0 40 39 37 R55 10K 36 DATA 1 LE 34 32 31 R54 10K 29 26 OUTPUT_EN AGND AGND C20 0.1UF C21 100PF 0 R24 AGND IP3SET AGND VCC_LO VCC_LO1 1 E-PAD PAD GNDRF 21 VCCBB 22 GNDRF 23 NC 24 RFRTN 25 RFIN VCCRF 27 GNDRF 28 IP3SET GNDRF 30 AGND AGND C7 VCC_LO 1 P1-T7 0.1UF 0 R6 4 2 AGND C8 NC 5 100PF T8 AGND 20 19 18 VCC AGND 1 VCC5 R53 10K 33 17 3 2 AGND 100PF DNI C34 AGND 100PF DNI 16 AGND R56 10K AGND AGND 15 14 Z1 35 3 LO_EXTERN P3-T7 1 P4-T7 P4-T7 AGND AGND LO VCC R58 DNI VCC AGND L2 TBD TBD AGND C23 DNI C36 DNI C35 0 0 R48 0 R47 VCC_BB1 1 VCC_BB 0.1UF L1 0 VCC_LO 0 R32 IFP AGND IFN AGND VCC_BB VCC 1 VCC R68 AGND 0 R67 0 DNI AGND RFIN VCC_RF IP3SET R28 AGND C25 C22 VCC_RF VCC_RF 1 0.1UF R25 R29 VCC_BB C24 AGND 0 R31 OUTPUT_EN 100PF 0 R26 AGND 100PF AGND TBD R60 C27 TBD 0.1UF R27 VCC_LO IP3SET 1 0 R69 0 10UF P3-T7 P3-T7 6 6A 5 5A 4 4A SNS1 SNS 0 T7 R43 AGND P4-T7 1 S2 R52 1K DNI R51 1K DNI 13 C33 12 11 100PF DNI C32 10 VCC 9 2P5_LDO 38 1NF VCC1 1 VCC C5 C6 1NF 8 REFOUT/LOCK 7 REFGND 6 REFIN 5 RSET 4 GNDCP 3 CPOUT 2 3P3_LDO 1 VCC 0 P1 AGND P1-1 1 R19 2 0 3 4 R30 5 0 6 P1-6 R57 7 0 R36 8 0 9 1 AMP745781-4 DIG_GND AGND C16 0 R18 10K R65 C17 2P5V 1 AGND AGND 100PF AGND C1 0.1UF 0 R1 R12 AGND C43 C2 R9 10K 2.7NF C15 AGND VCO_LDO R10 R71 R38 DNI 0 3K TBD 3 2 S1 CP 1 Y1 R14 VCO_LDO GNDDIG VCC_LO R63 100K VCO_IN DATA AGND OUTPUTEN 0 INBB R33 IPBB C28 R66 VTUNE LOP R35 VCO_LDO VCC_SENSE T3 AGND OUT VCC AGND VCC_SENSE AGND 3P3V_LDO 2P5V_LDO LO_EXTERN 4 1 P1-6 0 CLK 1 LON LE DNI R44 AGND 0.1UF C29 2 1 LOEXTEN GNDDIG GND R20 VCC_LO IFP 0 GNDBB 0 R34 Rev. A | Page 26 of 32 IFN Figure 50. Evaluation Board Schematic GNDBB GND 1 R59 0 J1 1 J1 2 J1 3 J1 4 J1 5 J1 6 J1 7 J1 8 J1 9 J1 10 GND1 GND2 1 1 AGND AGND VCC 6 TC4-1W 3 1 1A 2 2A 3 3A 08547-050 P1-T7 P1-T7 ADRF6603 SCHEMATIC AND ARTWORK 0 08547-012 08547-013 ADRF6603 Figure 51. Evaluation Board Layout (Bottom) Figure 52. Evaluation Board Layout (Top) Rev. A | Page 27 of 32 ADRF6603 EVALUATION BOARD CONFIGURATION OPTIONS Table 10. Component S1, R55, R56, R33 Description LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information). LO IN/OUT SMA Connector REFIN SMA Connector REFOUT SMA Connector LO input/output. An external 1x LO or 2x LO can be applied to this single-ended input connector. Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 . Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REFIN, 2x REFIN, REFIN/2, and REFIN/4; temperature sensor output voltage; and lock detect indicator. Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise. Loop filter. Loop filter components. CP Test Point R37, C14, R9, R10, C15, C13, R65, C40 R11, R12 R62, R63, VTUNE SMA Connector R2 RFIN SMA Connector T3 Loop filter return. When the internal VCO is used, the loop filter components should be returned to Pin 40 (DECLVCO) by installing a 0 resistor in R12. When an external VCO is used, the loop filter components can be returned to ground by installing a 0 resistor in R11. Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 resistor in R62. To use an external VCO, R62 should be left open. A 0 resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector. RSET pin. This pin is unused and should be left open. RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6603 is ac-coupled, so no bias is necessary. IF output. The differential IF output signals from the ADRF6603 (IFP and IFN) are converted to a single-ended signal by T3. Rev. A | Page 28 of 32 Default Condition/ Option Settings S1 = R55 = open (not installed), R56 = R33 = 0 , LODRV_EN = 0 V LO input Lock detect R12 = 0 (0402), R11 = open (0402) R62 = 0 (0402), R63 = open (0402) R2 = open (0402) R3 = R23 = open (0402) ADRF6603 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOT TOM VIEW) 21 20 11 10 0.25 MIN 4.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 40 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 072108-A PIN 1 INDICATOR 1.00 0.85 0.80 PIN 1 INDICATOR 31 30 Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF6603ACPZ-R7 ADRF6603-EVALZ 1 Temperature Range -40C to +85C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 29 of 32 Package Option CP-40-1 ADRF6603 NOTES Rev. A | Page 30 of 32 ADRF6603 NOTES Rev. A | Page 31 of 32 ADRF6603 NOTES (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08547-0-11/10(A) Rev. A | Page 32 of 32