MT58L32L32DT-10 - Micron - Datasheet.World

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (VDD)

• Separate +3.3V +0.3V/-0.165V isolated output

buffer supply (VDDQ)

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-lead TQFP package for high density, high speed

• Low capacitive bus loading

• x18, x32 and x36 options available

OPTIONS MARKING

• Timing (Access/Cycle/MHz)

3.5ns/6.0ns/166 MHz -6

4.2ns/7.5ns/133 MHz -7.5

5ns/10ns/100 MHz -10

• Configurations

64K x 18 MT58L64L18D

32K x 32 MT58L32L32D

32K x 36 MT58L32L36D

• Package

100-pin TQFP T

• Operating Temperature Range

Commercial (0ºC to +70ºC) None

Part Number Example:

MT58L64L18DT-10 IT

MT58L64L18D, MT58L32L32D,

MT58L32L36D

3.3V VDD, 3.3V I/O, Pipelined, Double-

Cycle Deselect

GENERAL DESCRIPTION

The Micron® SyncBurst™ SRAM family employs

high- speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

The MT58L64L18D and MT58L32L32/36D 1Mb

SRAMs integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM

core with advanced synchronous peripheral circuitry

and a 2-bit burst counter. All synchronous inputs pass

through registers controlled by a positive-edge-trig-

gered single clock input (CLK). The synchronous inputs

include all addresses, all data inputs, active LOW chip

enable (CE#), two additional chip enables for easy

depth expansion (CE2, CE2#), burst control inputs

(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and

global write (GW#).

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is also

a burst mode pin (MODE) that selects between inter-

leaved and linear burst modes. The data-out (Q), en-

abled by OE#, is also asynchronous. WRITE cycles can

be from one to two bytes wide (x18) or from one to four

bytes wide (x32/x36), as controlled by the write control

inputs.

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance

pin (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls

DQb pins and DQPb. During WRITE cycles on the x32

and x36 devices, BWa# controls DQa pins and DQPa;

BWb# controls DQb pins and DQPb; BWc# controls

DQc pins and DQPc; BWd# controls DQd pins and

DQPd. GW# LOW causes all bytes to be written. Parity

*JEDEC-standard MS-026 BHA (LQFP).

100-Pin TQFP*

1Mb SYNCBURST™

SRAM

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

FUNCTIONAL BLOCK DIAGRAM

64K x 18

ADDRESS

ADV#

CLK BINARY

COUNTER AND

LOGIC

CLR

ADSC#

16 16 14 16

CE#

ENABLE

OE#

SENSE

AMPS

64K x 9 x 2

MEMORY

ARRAY

ADSP#

MODE

CE2

CE2#

GW#

BWE#

PIPELINED

ENABLE

OUTPUT

REGISTERS

INPUT

REGISTERS

OUTPUT

BUFFERS

SA0, SA1, SA

BWb#

BWa#

BYTE “b”

WRITE REGISTER

BYTE “a”

WRITE REGISTER

SA0'

SA1'

SA0-SA1

DQs

DQPa

DQPb

BYTE “b”

WRITE DRIVER

BYTE “a”

WRITE DRIVER

NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and timing diagrams

for detailed information.

FUNCTIONAL BLOCK DIAGRAM

32K x 32/36

ADDRESS

ADV#

CLK BINARY

COUNTER

CLR

ADSP#

ADSC#

MODE

15 15 13 15

BWE#

GW#

CE#

CE2

CE2#

OE#

ENABLE

DQs

OUTPUT

REGISTERS

SENSE

AMPS

32K x 8 x 4

(x32)

32K x 9 x 4

(x36)

MEMORY

ARRAY

INPUT

REGISTERS

OUTPUT

BUFFERS

BWd#

BWc#

BYTE “d”

WRITE REGISTER

BYTE “c”

WRITE REGISTER

BYTE “b”

WRITE REGISTER

BYTE “a”

WRITE REGISTER

BYTE “a”

WRITE DRIVER

BYTE “b”

WRITE DRIVER

BYTE “c”

WRITE DRIVER

BYTE “d”

WRITE DRIVER

SA0, SA1, SA

BWb#

BWa#

SA0'

SA1'

SA0-SA1

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

GENERAL DESCRIPTION (continued)

pins are only available on the x18 and x36 versions.

The device incorporates an additional pipelined

enable register which delays turning off the output

buffer an additional cycle when a deselect is executed.

This feature allows depth expansion without penaliz-

ing system performance.

Micron’s 1Mb SyncBurst SRAMs operate from a

+3.3V power supply, and all inputs and outputs are

TTL-compatible. The device is ideally suited for

Pentium® and PowerPC pipelined systems and systems

that benefit from a very wide, high-speed data bus. The

device is also ideal in generic 16-, 18-, 32-, 36-, 64- and

72-bit-wide applications.

Please refer to the Micron Web site

(www.micron.com/mti/msp/html/sramprod.html) for

the latest data sheet.

* Pins 49 and 50 are reserved for address expansion.

**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.

TQFP PIN ASSIGNMENT TABLE

PIN # x18 x32/x36

1NC

NC/DQPc**

2NC DQc

3NC DQc

4VDDQ

5VSS

6NC DQc

7NC DQc

8DQb DQc

9DQb DQc

10 VSS

11 VDDQ

12 DQb DQc

13 DQb DQc

14 VDD

15 VDD

16 NC

17 VSS

18 DQb DQd

19 DQb DQd

20 VDDQ

21 VSS

22 DQb DQd

23 DQb DQd

24 DQPb DQd

25 NC DQd

PIN # x18 x32/x36 PIN # x18 x32/x36 PIN # x18 x32/x36

26 VSS

27 VDDQ

28 NC DQd

29 NC DQd

30 NC

NC/DQPd**

31 MODE

32 SA

33 SA

34 SA

35 SA

36 SA1

37 SA0

38 DNU

39 DNU

40 VSS

41 VDD

42 DNU

43 DNU

44 SA

45 SA

46 SA

47 SA

48 SA

49 NC/SA*

50 NC/SA*

76 VSS

77 VDDQ

78 NC DQb

79 NC DQb

80 SA

NC/DQPb**

81 SA

82 SA

83 ADV#

84 ADSP#

85 ADSC#

86 OE#

87 BWE#

88 GW#

89 CLK

90 VSS

91 VDD

92 CE2#

93 BWa#

94 BWb#

95 NC BWc#

96 NC BWd#

97 CE2

98 CE#

99 SA

100 SA

51 NC

NC/DQPa**

52 NC DQa

53 NC DQa

54 VDDQ

55 VSS

56 NC DQa

57 NC DQa

58 DQa

59 DQa

60 VSS

61 VDDQ

62 DQa

63 DQa

64 ZZ

65 VDD

66 NC

67 VSS

68 DQa DQb

69 DQa DQb

70 VDDQ

71 VSS

72 DQa DQb

73 DQa DQb

74 DQPa DQb

75 NC DQb

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

PIN ASSIGNMENT (TOP VIEW)

100-PIN TQFP

(D-1)

ADV#

ADSP#

ADSC#

OE#

BWE#

GW#

CLK

VSS

VDD

CE2#

BWa#

BWb#

CE2

CE#

100

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

VDDQ

VSS

DQPa

DQa

VSS

VDDQ

DQa

VSS

VDD

DQa

VDDQ

VSS

DQa

VSS

VDDQ

NC/SA*

DNU

VDD

VSS

DNU

SA0

SA1

MODE

VDDQ

VSS

DQb

VSS

VDDQ

DQb

VDD

VSS

DQb

VDDQ

VSS

DQb

DQPb

VSS

VDDQ

x18

ADV#

ADSP#

ADSC#

OE#

BWE#

GW#

CLK

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

CE#

100

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NC/DQPb**

DQb

DQa

NC/DQPa**

NC/SA*

DNU

SA0

SA1

MODE

NC/DQPc**

DQc

DQd

NC/DQPd**

x32/x36

* Pins 49 and 50 are reserved for address expansion.

**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

TQFP PIN DESCRIPTIONS

x18 x32/x36 SYMBOL TYPE DESCRIPTION

37 37 SA0 Input Synchronous Address Inputs: These inputs are registered and must

36 36 SA1 meet the setup and hold times around the rising edge of CLK.

32-35, 44-48, 32-35, 44-48, SA

80-82, 99, 81, 82, 99,

100 100

93 93 BWa # Input Synchronous Byte Write Enables: These active LOW inputs allow

94 94 BWb# individual bytes to be written and must meet the setup and hold

– 95 BWc# times around the rising edge of CLK. A byte write enable is LOW

– 96 BWd# for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb. For the x32 and x36 versions, BWa# controls DQa pins and

DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins

and DQPc; BWd# controls DQd pins and DQPd. Parity is only

available on the x18 and x36 versions.

87 87 BWE # Input Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold times around the

rising edge of CLK.

88 88 GW# Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit

WRITE to occur independent of the BWE# and BWx# lines and must

meet the setup and hold times around the rising edge of CLK.

89 89 CLK Input Clock: This signal registers the address, data, chip enable, byte

write enables and burst control inputs on its rising edge. All

synchronous inputs must meet setup and hold times around the

clock’s rising edge.

98 98 CE# Input Synchronous Chip Enable: This active LOW input is used to enable

the device and conditions the internal use of ADSP#. CE# is sampled

only when a new external address is loaded.

92 92 CE2# Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

64 64 ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in the

memory array is retained. When ZZ is active, all other inputs are

ignored.

97 97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable

the device and is sampled only when a new external address is

loaded.

86 86 OE# Input Output Enable: This

active LOW, asynchronous input enables the

data I/O output drivers.

83 83 ADV# Input Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after

the external address is loaded. A HIGH on this pin effectively causes

wait states to be generated (no address advance). To ensure use of

correct address during a WRITE cycle, ADV# must be HIGH at the

rising edge of the first clock after an ADSP# cycle is initiated.

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

TQFP PIN DESCRIPTIONS (continued)

x18 x32/x36 SYMBOL TYPE DESCRIPTION

84 84 ADSP# Input Synchronous Address Status Processor: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

85 85 ADSC# Input Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE# is LOW. ADSC# is also used to place the chip into power-down

state when CE# is HIGH.

31 31 MODE Input Mode: This input selects the burst sequence. A LOW on this pin

selects “linear burst.” NC or HIGH on this pin selects “interleaved

burst.” Do not alter input state while device is operating.

(a) 58, 59, (a) 52, 53, DQa Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”

62, 63, 68, 69, 56-59, 62, 63 Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;

72, 73 Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.

(b) 8, 9, 12, (b) 68, 69, DQb Input data must meet setup and hold times around the rising edge

13, 18, 19, 72-75, 78, 79 of CLK.

22, 23 (c) 2, 3, 6-9, DQc

12, 13

(d) 18, 19, DQd

22-25, 28, 29

74 51 NC/DQPa NC/ No Connect/Parity Data I/Os: On the x32 version, these pins are No

24 80 NC/DQPb I/O Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”

–1NC/DQPc parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte

–30 NC/DQPd “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.

14, 15, 41, 65, 14, 15, 41, 65, V

Supply Power Supply:

See DC Electrical Characteristics and Operating

91 91 Conditions for range.

4, 11, 20, 27, 4, 11, 20, 27, V

Q Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

54, 61, 70, 77 54, 61, 70, 77 Operating Conditions for range.

5, 10, 17, 21, 5, 10, 17, 21, V

Supply Ground:

GND.

26, 40, 55, 60, 26, 40, 55, 60,

67, 71, 76, 90 67, 71, 76, 90

38, 39, 42, 43 38, 39, 42, 43 DNU – Do Not Use: These signals may either be unconnected or wired to

GND to improve package heat dissipation.

1-3, 6, 7, 16, 16, 66 NC – No Connect: These signals are not internally connected and may be

25, 28-30, connected to ground to improve package heat dissipation.

51-53, 56, 57,

66, 75, 78, 79,

95, 96

49, 50 49, 50 NC/SA – No Connect: These pins are reserved for address expansion.

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X...X00 X...X01 X...X10 X...X11

X...X01 X...X00 X...X11 X...X10

X...X10 X...X11 X...X00 X...X01

X...X11 X...X10 X...X01 X...X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X...X00 X...X01 X...X10 X...X11

X...X01 X...X10 X...X11 X...X00

X...X10 X...X11 X...X00 X...X01

X...X11 X...X00 X...X01 X...X10

FUNCTION GW# BWE# BWa# BWb#

READ H H X X

READ H L H H

WRITE Byte “a” H L L H

WRITE Byte “b” H L H L

WRITE All Bytes H L L L

WRITE All Bytes L X X X

PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)

PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)

FUNCTION GW# BWE# BWa# BWb# BWc# BWd#

READ H H X X X X

READ H L H H H H

WRITE Byte “a” H L L H H H

WRITE All Bytes H LLLLL

WRITE All Bytes L X X X X X

NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

TRUTH TABLE

OPERATION ADDRESS CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE# CLK DQ

USED

Deselected Cycle, Power-Down None H X X L X L X X X L-H High-Z

Deselected Cycle, Power-Down None L X L L L X X X X L-H High-Z

Deselected Cycle, Power-Down None L H X L L X X X X L-H High-Z

Deselected Cycle, Power-Down None L X L L H L X X X L-H High-Z

Deselected Cycle, Power-Down None L H X L H L X X X L-H High-Z

SNOOZE MODE, Power-Down None X X X H XXXXXXHigh-Z

READ Cycle, Begin Burst Exte rnal L L H L L X X X L L-H Q

READ Cycle, Begin Burst Exte rnal L L H L L X X X H L-H High-Z

WRITE Cycle, Begin Burst Exte rnal L L H L H L X L X L-H D

READ Cycle, Begin Burst Exte rnal L L H L H L X H L L-H Q

READ Cycle, Begin Burst Exter nal L L H L H L X H H L-H High-Z

READ Cycle, Continue Burst Next X X X L H H L H L L-H Q

READ Cycle, Continue Burst Next X X X L H H L H H L-H High-Z

READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H High-Z

WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D

WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D

READ Cycle, Suspend Burst Current X X X L HHHHLL-HQ

READ Cycle, Suspend Burst Current X X X L HHHHHL-HHigh-Z

READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z

WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.

2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or

GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.

3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc

pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions.

DQPc and DQPd are only available on the x36 version.

4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held

HIGH throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more

byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing

diagram for clarification.

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD Supply Relative to Vss -0.5V to +4.6V

Voltage on VDDQ Supply

Relative to Vss .............................. -0.5V to +4.6V

VIN -0.5V to VDD + 0.5V

Storage Temperature (plastic) ............-55ºC to +150ºC

Junction Temperature**................................... +150ºC

Short Circuit Output Current...........................100mA

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

**Maximum junction temperature depends upon pack-

age type, cycle time, loading, ambient temperature and

airflow. See Micron Technical Note TN-05-14 for more

information.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0ºC ≤ TA ≤ +70ºC; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH 2.0 VDD + 0.3 V 1, 2

Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2

Input Leakage Current 0V ≤ VIN ≤ VDD ILI-1.0 1.0 µA 3

Output Leakage Current Output(s) disabled, ILO-1.0 1.0 µA

0V ≤ VIN ≤ VDD

Output High Voltage IOH = -4.0mA VOH 2.4 – V 1, 4

Output Low Voltage IOL = 8.0mA VOL – 0.4 V 1, 4

Supply Voltage VDD 3.135 3.6 V 1

Isolated Output Buffer Supply VDDQ 3.135 VDD V 1, 5

NOTE: 1. All voltages referenced to VSS (GND).

2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2 for I ≤ 20mA

Undershoot: VIL  -0.7V for t ≤ tKC/2 for I ≤ 20mA

Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms

3. MODE pin has an internal pull-up, and input leakage = ±10µA.

4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O

curves are available upon request.

5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

IDD OPERATING CONDITIONS AND MAXIMUM LIMITS

(0ºC ≤ TA ≤ +70ºC; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)

DESCRIPTION CONDITIONS SYMBOL TYP -6 -7.5 -10 UNITS NOTES

Power Supply Device selected; All inputs ≤ V

Current: or  V

; Cycle time 

KC MIN; I

100 340 280 225 mA 1, 2, 3

Operating V

= MAX; Outputs open

Power Supply Device selected; V

= MAX;

Current: Idle ADSC#, ADSP#, GW#, BWx#, ADV# I

30 85 70 65 mA 1, 2, 3

; All inputs ≤ V

+ 0.2 or  V

- 0.2;

Cycle time 

KC MIN

CMOS Standby Device deselected; V

= MAX;

All inputs ≤ V

+ 0.2 or  V

- 0.2; I

0.5 10 10 10 mA 2, 3

All inputs static; CLK frequency = 0

TTL Standby Device deselected; V

= MAX;

All inputs ≤ V

or  V

6 252525mA2, 3

All inputs static; CLK frequency = 0

Clock Running Device deselected; V

= MAX;

ADSC#, ADSP#, GW#, BWx#, ADV# I

30 85 70 65 mA 2, 3

; All inputs ≤ V

+ 0.2 or  V

- 0.2;

Cycle time 

KC MIN

NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means

device is active (not in power-down mode).

3. Typical values are measured at 3.3V, 25ºC and 10ns cycle time.

4. This parameter is sampled.

CAPACITANCE

DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES

Control Input Capacitance TA = 25ºC; f = 1 MHz; CI2.7 3.5 pF 4

Input/Output Capacitance (DQ) VDD = 3.3V CO45pF4

Address Capacitance CA2.5 3.5 pF 4

Clock Capacitance CCK 2.5 3.5 pF 4

TQFP THERMAL RESISTANCE

DESCRIPTION CONDITIONS SYMBOL TYP UNITS NOTES

Thermal Resistance Test conditions follow standard test methods θJA 40 ºC/W 4

(Junction to Ambient) and procedures for measuring thermal

Thermal Resistance impedance, per EIA/JESD51. θJC 8 ºC/W 4

(Junction to Top of Case)

MAX

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.

2. Measured as HIGH above VIH and LOW below VIL.

3. This parameter is measured with the output loading shown in Figure 2.

4. This parameter is sampled.

5. Transition is measured ±500mV from steady state voltage.

6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough

discussion on these parameters.

7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.

8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold

times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the

required setup and hold times.

9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold

times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at

each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 1) (0ºC ≤ TA ≤ +70ºC; VDD, VDDQ = +3.3V +0.3V/-0.165V)

-6 -7.5 -10

DESCRIPTION SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Clock

Clock cycle time tKC 6.0 7.5 10 ns

Clock frequency fKF 166 133 100 MHz

Clock HIGH time tKH 1.7 1.9 3.2 ns 2

Clock LOW time tKL 1.7 1.9 3.2 ns 2

Output Times

Clock to output valid tKQ 3.5 4.2 5.0 ns

Clock to output invalid tKQX 1.5 1.5 1.5 ns 3

Clock to output in Low-Z tKQLZ 1.5 1.5 1.5 ns 3, 4, 5, 6

Clock to output in High-Z tKQHZ 3.5 4.2 5.0 ns 3, 4, 5, 6

OE# to output valid tOEQ 3.5 4.2 5.0 ns 7

OE# to output in Low-Z tOELZ 0 0 0 ns 3, 4, 5, 6

OE# to output in High-Z tOEHZ 3.5 4.2 4.5 ns 3, 4, 5, 6

Setup Times

Address tAS 1.7 2.0 2.2 ns 8, 9

Address status (ADSC#, ADSP#) tADSS 1.7 2.0 2 .2 ns 8, 9

Address advance (ADV#) tAAS 1.7 2.0 2.2 ns 8, 9

Write signals tWS 1.7 2.0 2.2 ns 8, 9

(BWa#-BWd#, BWE#, GW#)

Data-in tDS 1.7 2.0 2.2 ns 8, 9

Chip enables (CE#, CE2#, CE2) tCES 1.7 2.0 2.2 ns 8, 9

Hold Times

Address tAH 0.5 0.5 0.5 ns 8, 9

Address status (ADSC#, ADSP#) tADSH 0.5 0. 5 0.5 ns 8, 9

Address advance (ADV#) tAAH 0.5 0.5 0.5 ns 8, 9

Write signals tWH 0.5 0.5 0.5 ns 8, 9

(BWa#-BWd#, BWE#, GW#)

Data-in tDH 0.5 0.5 0.5 ns 8, 9

Chip enables (CE#, CE2#, CE2) tCEH 0.5 0.5 0.5 ns 8, 9

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

Q50

V = 1.5V

Z = 50

Figure 1

Q351

317

5pF

+3.3V

Figure 2

LOAD DERATING CURVES

Micron 64K x 18, 32K x 32, or 32K x 36 SyncBurst

SRAM timing is dependent upon the capacitive loading

on the outputs.

Consult the factory for copies of I/O current versus

voltage curves.

AC TEST CONDITIONS

Input pulse levels ................. VIH = (VDD/2.2) + 1.5V

....................VIL = (VDD/2.2) - 1.5V

Input rise and fall times..................................... 1ns

Input timing reference levels ..................... VDD/2.2

Output reference levels ............................V DDQ/2.2

Output load ............................. See Figures 1 and 2

OUTPUT LOAD EQUIVALENT

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

SNOOZE MODE

SNOOZE MODE is a low-current, “power-down”

mode in which the device is deselected and current is

reduced to ISB2Z. The duration of SNOOZE MODE is

dictated by the length of time the ZZ pin is in a HIGH

state. After the device enters SNOOZE MODE, all inputs

except ZZ become gated inputs and are ignored.

The ZZ pin is an asynchronous, active HIGH input

that causes the device to enter SNOOZE MODE. When

the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed

after the setup time tZZ is met. Any READ or WRITE

operation pending when the device enters SNOOZE

MODE is not guaranteed to complete successfully.

Therefore, SNOOZE MODE must not be initiated until

valid pending operations are completed.

SNOOZE MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Current during SNOOZE MODE ZZ  VIH ISB2Z 10 mA

ZZ active to input ignored tZZ 2(tKC) ns 1

ZZ inactive to input sampled tRZZ 2(tKC) ns 1

ZZ active to snooze current tZZI 2(tKC) ns 1

ZZ inactive to exit snooze current tRZZI 0 ns 1

NOTE: 1. This parameter is sampled.

SNOOZE MODE WAVEFORM

tZZ

SUPPLY

CLK

tRZZ

ALL INPUTS

(except ZZ)

DON’T CARE

IISB2Z

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

READ TIMING

tKC

tKL

CLK

ADSP#

tADSH

tADSS

ADDRESS

tKH

OE#

ADSC#

CE#

(NOTE 2)

tAH

tAS

tCEH

tCES

GW#, BWE#,

BWa#-BWd#

QHigh-Z

tKQLZ tKQX

tKQ

ADV#

tOEHZ

tKQ

Single READ BURST READ

tOEQ

tOELZ tKQHZ

Burst wraps around

to its initial state.

tAAH

tAAS

tWH

tWS

tADSH

tADSS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1) Q(A3)Q(A2 + 3)

A2 A3

(NOTE 1)

Deselect

cycle.

(NOTE 3)

Burst continued with

new base address.

(NOTE 4)

ADV# suspends burst.

DON’T CARE UNDEFINED

NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When

CE# is HIGH, CE2# is HIGH and CE2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q

to be driven until after the following clock rising edge.

4. Outputs are disabled within two clock cycles after deselect.

-6 -7.5 -10

SYM MIN MAX MIN MAX MIN MAX UNITS

tAS 1.7 2.0 2.2 ns

tADSS 1.7 2.0 2.2 ns

tAAS 1.7 2.0 2.2 ns

tWS 1.7 2.0 2.2 ns

tCES 1.7 2.0 2.2 ns

tAH 0.5 0.5 0.5 ns

tADSH 0.5 0.5 0.5 ns

tAAH 0.5 0.5 0.5 ns

tWH 0.5 0.5 0.5 ns

tCEH 0.5 0.5 0.5 ns

READ TIMING PARAMETERS

-6 -7.5 -10

SYM MIN MAX MIN MAX MIN MAX UNITS

tKC 6.0 7.5 10 ns

fKF 166 133 100 MHz

tKH 1.7 1.9 3.2 ns

tKL 1.7 1.9 3.2 ns

tKQ 3.5 4.2 5.0 ns

tKQX 1.5 1.5 1.5 ns

tKQLZ 1.5 1.5 1.5 ns

tKQHZ 3.5 4.2 5.0 ns

tOEQ 3.5 4.2 5.0 ns

tOELZ 0 0 0 ns

tOEHZ 3.5 4.2 4.5 ns

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

WRITE TIMING

tKC

tKL

CLK

ADSP#

tADSH

tADSS

ADDRESS

tKH

OE#

ADSC#

CE#

(NOTE 2)

tAH

tAS

tCEH

tCES

BWE#,

BWa#-BWd#

High-Z

ADV#

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADSH

tADSS

tADSH

tADSS

tOEHZ

tAAH

tAAS

tWH

tWS

tDH

tDS

(NOTE 3)

(NOTE 1)

(NOTE 4)

GW#

tWH

tWS

(NOTE 5)

Byte write signals are ignored for first cycle when

ADSP# initiates burst.

ADSC# extends burst.

ADV# suspends burst.

DON’T CARE UNDEFINED

D(A1)

NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When

CE# is HIGH, CE2# is HIGH and CE2 is LOW.

3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/

output data contention for the time period prior to the byte write enable inputs being sampled.

4. ADV# must be HIGH to permit a WRITE to the loaded address.

5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or

GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.

WRITE TIMING PARAMETERS

-6 -7.5 -10

SYM MIN MAX MIN MAX MIN MAX UNITS

tKC 6.0 7.5 10 ns

fKF 166 133 100 MHz

tKH 1.7 1.9 3.2 ns

tKL 1.7 1.9 3.2 ns

tOEHZ 3.5 4.2 4.5 ns

tAS 1.7 2.0 2.2 ns

tADSS 1.7 2.0 2.2 ns

tAAS 1.7 2.0 2.2 ns

tWS 1.7 2.0 2.2 ns

-6 -7.5 -10

SYM MIN MAX MIN MAX MIN MAX UNITS

tDS 1.7 2.0 2.2 ns

tCES 1.7 2.0 2.2 ns

tAH 0.5 0.5 0.5 ns

tADSH 0.5 0.5 0.5 ns

tAAH 0.5 0.5 0.5 ns

tWH 0.5 0.5 0.5 ns

tDH 0.5 0.5 0.5 ns

tCEH 0.5 0.5 0.5 ns

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

READ/WRITE TIMING

tKC

tKL

CLK

ADSP#

tADSH

tADSS

ADDRESS

tKH

OE#

ADSC#

CE#

(NOTE 2)

tAH

tAS

tCEH

tCES

BWE#,

BWa#-BWd#

(NOTE 4)

QHigh-Z

ADV#

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWH

tWS

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

(NOTE 1)

tKQLZ

tKQ

Back-to-Back

WRITEs

(NOTE 5)

DON’T CARE UNDEFINED

NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When

CE# is HIGH, CE2# is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.

4. GW# is HIGH.

5. Back-to-back READs may be controlled by either ADSP# or ADSC#.

tADSS 1.7 2.0 2.2 ns

tWS 1.7 2.0 2.2 ns

tDS 1.7 2.0 2.2 ns

tCES 1.7 2.0 2.2 ns

tAH 0.5 0.5 0.5 ns

tADSH 0.5 0.5 0.5 ns

tWH 0.5 0.5 0.5 ns

tDH 0.5 0.5 0.5 ns

tCEH 0.5 0.5 0.5 ns

READ/WRITE TIMING PARAMETERS

-6 -7.5 -10

SYM MIN MAX MIN MAX MIN MAX UNITS

tKC 6.0 7.5 10 ns

fKF 166 133 100 MHz

tKH 1.7 1.9 3.2 ns

tKL 1.7 1.9 3.2 ns

tKQ 3.5 4.2 5.0 ns

tKQLZ 1.5 1.5 1.5 ns

tOELZ 0 0 0 ns

tOEHZ 3.5 4.2 4.5 ns

tAS 1.7 2.0 2.2 ns

-6 -7.5 -10

SYM MIN MAX MIN MAX MIN MAX UNITS

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

100-PIN PLASTIC TQFP (JEDEC LQFP)

14.00 ±0.10

20.10 ±0.10

0.62

22.10 +0.10

-0.15

16.00 +0.20

-0.05

PIN #1 ID

0.65

1.50 ±0.10

0.25

0.60 ±0.15 1.40 ±0.05

0.32 +0.06

-0.10

0.15 +0.03

-0.02

0.10 +0.10

-0.05

DETAIL A

1.00 (TYP)

GAGE PLANE

0.10

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micronsemi.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

SyncBurst is a trademark of Micron Technology, Inc.

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

REVISION HISTORY

Removed references to Industrial Temperature, Rev. 9/99 ........................................................................... July 17/01