Description
The A4983 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, eighth-, and
sixteenth-step modes, with an output drive capacity of up to
35 V and ±2 A. The A4983 includes a fixed off-time current
regulator which has the ability to operate in Slow or Mixed
decay modes.
The translator is the key to the easy implementation of the
A4983. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A4983 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The chopping control in the A4983 automatically selects the
current decay mode (Slow or Mixed). When a signal occurs at
the STEP input pin, the A4983 determines if that step results
in a higher or lower current in each of the motor phases. If
the change is to a higher current, then the decay mode is set
to Slow decay. If the change is to a lower current, then the
current decay is set to Mixed (set initially to a fast decay for
a period amounting to 31.25% of the fixed off-time, then to a
4983DS, Rev. 1
Features and Benefits
▪ Low RDS(ON) outputs
▪ Automatic current decay mode detection/selection
▪ Mixed and Slow current decay modes
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO
▪ Crossover-current protection
▪ 3.3 and 5 V compatible logic supply
▪ Very thin profile QFN package
▪ Thermal shutdown circuitry
DMOS Microstepping Driver with Translator
Continued on the next page…
Package: 28-pin QFN (suffix ET)
Typical Application Diagram
A4983
Approximate size
Microcontroller or
Controller Logic
STEP
VDD
VDD
MS1
MS2
MS3
DIR
RESET
ENABLE
SLEEP
REF ROSC
RS2
OUT2B
OUT2A
RS1
OUT1B
OUT1A
VBB
CP1VCPVREG
0.22 1.0F 1.0F F
CP2
VBB
VBB
A4983
DMOS Microstepping Driver with Translator
A4983
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
slow decay for the remainder of the off-time). This current decay
control scheme results in reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation. Internal circuit
protection includes: thermal shutdown with hysteresis, undervoltage
lockout (UVLO), and crossover-current protection. Special power-
on sequencing is not required.
The A4983 is supplied in a 5 mm × 5 mm × 0.90 nominal surface
mount QFN package with exposed thermal pad (suffix ET). The
package is lead (Pb) free (suffix –T), with 100% matte tin plated
leadframe.
Description (continued)
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 35 V
Output Current IOUT
±2 A
Duty Cycle < 20% ±2.5 A
Logic Input Voltage VIN –0.3 to 7 V
Sense Voltage VSENSE 0.5 V
Reference Voltage VREF 4V
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Selection Guide
Part Number Pb-free Package Packing
A4983SETTR-T Yes 28-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel
DMOS Microstepping Driver with Translator
A4983
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Functional Block Diagram
SENSE1
SENSE2
VREG
VCP
CP2
Control
Logic
DAC
VDD
PWM Latch
Blanking
Mixed Decay
DAC
STEP
DIR
RESET
MS1
PWM Latch
Blanking
Mixed Decay
Current
Regulator
CP1
Charge
Pump
RS2
RS1
VBB1
OUT1A
OUT1B
VBB2
OUT2A
OUT2B
0.1 MF
VREF
Translator
Gate
Drive DMOS Full Bridge
DMOS Full Bridge
0.1 MF
0.22 MF
OSC
ROSC
MS2
REF
ENABLE
SLEEP
MS3
DMOS Microstepping Driver with Translator
A4983
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
1Negative current is defined as coming out of (sourcing from) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3errI = (ITrip – IProg
) ⁄ IProg
, where IProg = %ITripMAX I TripMAX.
Characteristics Symbol Test Conditions Min. Typ.2Max. Units
Output Drivers
Load Supply Voltage Range VBB
Operating 8 – 35 V
During Sleep Mode 0 – 35 V
Logic Supply Voltage Range VDD Operating 3.0 – 5.5 V
Output On Resistance RDSON
Source Driver, IOUT = –1.5 A – 0.350 0.450
Sink Driver, IOUT = 1.5 A – 0.300 0.370
Body Diode Forward Voltage VF
Source Diode, IF = –1.5 A – – 1.2 V
Sink Diode, IF = 1.5 A – – 1.2 V
Motor Supply Current IBB
fPWM < 50 kHz – – 4 mA
Operating, outputs disabled – – 2 mA
Sleep Mode – – 10 A
Logic Supply Current IDD
fPWM < 50 kHz – – 8 mA
Outputs off – – 5 mA
Sleep Mode – – 10 A
Control Logic
Logic Input Voltage VIN(1) VDD0.7 ––V
VIN(0) ––
VDD0.3 V
Logic Input Current IIN(1) VIN = VDD0.7 –20 <1.0 20 A
IIN(0) VIN = VDD0.3 –20 <1.0 20 A
Microstep Select 2 RMS2 – 100 – k
Microstep Select 3 RMS3 – 100 – k
Input Hysteresis VHYS(IN) 150 300 500 mV
Blank Time tBLANK 0.7 1 1.3 s
Fixed Off-Time tOFF
OSC > 3 V 20 30 40 s
ROSC = 25 k23 30 37 s
Reference Input Voltage Range VREF 0–4V
Reference Input Current IREF –3 0 3 A
Current Trip-Level Error3errI
VREF = 2 V, %ITripMAX = 38.27% – – ±15 %
VREF = 2 V, %ITripMAX = 70.71% – – ±5 %
VREF = 2 V, %ITripMAX = 100.00% – – ±5 %
Crossover Dead Time tDT 100 475 800 ns
Protection
Thermal Shutdown Temperature TJ– 165 – °C
Thermal Shutdown Hysteresis TJHYS –15–°C
UVLO Enable Threshold UVLO VDD rising 2.35 2.7 3 V
UVLO Hysteresis UVHYS 0.05 0.10 – V
DMOS Microstepping Driver with Translator
A4983
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA Package ET; 4-layer PCB, based on JEDEC standard 32 ºC/W
*In still air. Additional thermal information available on Allegro Web site.
20 40 60 80 100 120 140 160 180
Temperature (°C)
Power Dissipation, P
D
(W)
0.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.0
1.5
Maximum Power Dissipation, PD(max)
(RθJA = 32 ºC/W)
DMOS Microstepping Driver with Translator
A4983
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Figure 1. Logic Interface Timing Diagram
STEP
tA
tD
tC
MS1, MS2, MS3,
RESET, or DIR
t
B
Table 1. Microstep Resolution Truth Table
MS1 MS2 MS3 Microstep Resolution Excitation Mode
L L L Full Step 2 Phase
H L L Half Step 1-2 Phase
L H L Quarter Step W1-2 Phase
H H L Eighth Step 2W1-2 Phase
H H H Sixteenth Step 4W1-2 Phase
Time Duration Symbol Typ. Unit
STEP minimum, HIGH pulse width tA1s
STEP minimum, LOW pulse width tB1s
Setup time, input change to STEP tC200 ns
Hold time, input change to STEP tD200 ns
DMOS Microstepping Driver with Translator
A4983
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Functional Description
Device Operation. The A4983 is a complete microstepping
motor driver with a built-in translator for easy operation with
minimal control lines. It is designed to operate bipolar step-
per motors in full-, half-, quarter-, eighth-, and sixteenth-step
modes. The currents in each of the two output full-bridges and
all of the N-channel DMOS FETs are regulated with fixed off-
time PWM (pulse width modulated) control circuitry. At each
step, the current for each full-bridge is set by the value of its
external current-sense resistor (RS1 and RS2), a reference volt-
age (VREF), and the output voltage of its DAC (which in turn is
controlled by the output of the translator).
At power-on or reset, the translator sets the DACs and the phase
current polarity to the initial Home state (shown in figures 2
through 6), and the current regulator to Mixed Decay Mode for
both phases. When a step command signal occurs on the STEP
input, the translator automatically sequences the DACs to the
next level and current polarity. (See table 2 for the current-level
sequence.) The microstep resolution is set by the combined
effect of inputs MS1, MS2, and MS3, as shown in table 1.
When stepping, if the new output levels of the DACs are lower
than their previous output levels, then the decay mode for the
active full-bridge is set to Mixed. If the new output levels of
the DACs are higher than or equal to their previous levels, then
the decay mode for the active full-bridge is set to Slow. This
automatic current decay selection improves microstepping
performance by reducing the distortion of the current waveform
that results from the back EMF of the motor.
If the logic circuits are pulled up to VDD, it is good practice to
use a high value pull-up resistor in order to limit current to the
logic inputs, should an overvoltage event occur. Logic inputs
include: MSx, SLEEP, DIR, ENABLE, RESET, and STEP.
RESET Input (RESET). The RESET input sets the trans-
lator to a predefined Home state (shown in figures 2 through
6), and turns off all of the FET outputs. All STEP inputs are
ignored until the RESET input is set to high.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current flow in each winding. The size of the
increment is determined by the combined state of inputs MS1,
MS2, and MS3.
Microstep Select (MS1, MS2, and MS3). Selects the
microstepping format, as shown in table 1. MS2 and MS3 have a
100 kΩ pull-down resistance. Any changes made to these inputs
do not take effect until the next STEP rising edge.
If the MSx pins are pulled up to VDD, it is good practice to use a
high value pull-up resistor in order to limit current to these pins,
should an overvoltage event occur.
Direction Input (DIR). This determines the direction of
rotation of the motor. When low, the direction will be clockwise
and when high, counterclockwise. Changes to this input do not
take effect until the next STEP rising edge.
Internal PWM Current Control. Each full-bridge is
controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, ITRIP
. Initially, a
diagonal pair of source and sink FET outputs are enabled and
current flows through the motor winding and the current sense
resistor, RSx. When the voltage across RSx equals the DAC out-
put voltage, the current sense comparator resets the PWM latch.
The latch then turns off either the source FETs (when in Slow
Decay Mode) or the sink and source FETs (when in Mixed
Decay Mode).
The maximum value of current limiting is set by the selection
of RSx and the voltage at the VREF pin. The transconductance
function is approximated by the maximum value of current
limiting, ITripMAX (A), which is set by
ITripMAX = VREF / ( 8 R S)
where RS is the resistance of the sense resistor (Ω) and VREF is
the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current sense
comparator in precise steps, such that
Itrip = (%ITripMAX / 100) × ITripMAX
(See table 2 for %ITripMAX at each step.)
Functional Description
DMOS Microstepping Driver with Translator
A4983
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The one shot off-time, tOFF, is deter-
mined by the selection of an external resistor connected from the
ROSC timing pin to ground. If the ROSC pin is tied to an external
voltage > 3 V, then tOFF defaults to 30 μs. The ROSC pin can be
safely connected to the VDD pin for this purpose. The value of
tOFF (μs) is approximately
tOFF ≈ ROSC ⁄ 825
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current
control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, tBLANK (μs), is approximately
tBLANK ≈ 1 μs
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
VREG (VREG). This internally-generated voltage is used
to operate the sink-side FET outputs. The VREG pin must be
decoupled with a 0.22 μF ceramic capacitor to ground. VREG
is internally monitored. In the case of a fault condition, the FET
outputs of the A4983 are disabled.
Enable Input (ENABLE). This input turns on or off all of the
FET outputs. When set to a logic high, the outputs are disabled.
When set to a logic low, the internal control enables the outputs as
required. The translator inputs STEP, DIR, MS1, MS2, and MS3,
as well as the internal sequencing logic, all remain active, indepen-
dent of the ENABLE input state.
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4983 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Sleep Mode (SLEEP). To minimize power consumption when
the motor is not in use, this input disables much of the internal
circuitry including the output FETs, current regulator, and charge
pump. A logic low on the SLEEP pin puts the A4983 into Sleep
mode. A logic high allows normal operation, as well as start-up
(at which time the A4983 drives the motor to the Home microstep
position). When emerging from Sleep mode, in order to allow the
charge pump to stabilize, provide a delay of 1 ms before issuing a
Step command.
If the SLEEP pin is pulled up to VDD, it is good practice to use
a high value pull-up resistor in order to limit current to the pin,
should an overvoltage event occur.
Mixed Decay Operation. The bridge can operate in Mixed
Decay mode, depending on the step sequence, as shown in figures
3 through 6. As the trip point is reached, the A4983 initially goes
into a fast decay mode for 31.25% of the off-time. tOFF. After that,
it switches to Slow Decay mode for the remainder of tOFF. A tim-
ing dagram for this feature appears on the next page.
Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed–off-time cycle, load current recir-
culates according to the decay mode selected by the control logic.
This synchronous rectification feature turns on the appropriate
FETs during current decay, and effectively shorts out the body
diodes with the low FET RDS(ON). This reduces power dissipation
significantly, and can eliminate the need for external Schottky
diodes in many applications. Synchronous rectification turns off
when the load current approaches zero (0 A), preventing reversal
of the load current. A timing dagram for this feature appears on
the next page.
DMOS Microstepping Driver with Translator
A4983
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
V
PHASE
I
OUT
I
OUT
t
+
–
0See Enlargement A
Enlargement A
t
SD
t
FD
t
off
Slow Decay
Mixed Decay
Fast Decay
I
PEAK
Symbol Characteristic
toff Device fixed off-time
IPEAK Maximum output current
tSD Slow decay interval
tFD Fast decay interval
IOUT Device output current
Current Decay Modes Timing Chart
DMOS Microstepping Driver with Translator
A4983
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Application Layout
Layout The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A4983 must be soldered directly onto the board. On the under-
side of the A4983 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB. Thermal vias
should not have any thermal relief and should be connected to
internal layers, if available, to maximize the dissipation area.
Grounding In order to minimize the effects of ground bounce
and offset issues, it is important to have a low impedance single-
point ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the groundplane directly under the A4983, that area
becomes an ideal location for a star ground point.
A low impedance ground will prevent ground bounce during
high current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below, illustrates how to create a star ground
under the device, to serve both as low impedance ground point
and thermal path.
PCB
Thermal Vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
Solder
A4983
V
BB
V
DD
PAD
1
A4983
C3
C6 R1
R2
R3
C1 C8
C2
C9C7 RS2RS1
R6
C4
OUT1B
NC
DIR
GND
REF
STEP
VDD
OUT2B
ENABLE
GND
CP1
CP2
VCP
NC
VREG
MS1
MS2
MS3
RESET
ROSC
SLEEP
VBB2
SENSE2
OUT2A
NC
OUT1A
SENSE1
VBB1
DMOS Microstepping Driver with Translator
A4983
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
0.00
100.00
92.39
70.71
38.27
–38.27
–70.71
–92.39
–100.00
0.00
100.00
92.39
70.71
38.27
–38.27
–70.71
–92.39
–100.00
Phase 2
IOUT2B
Direction = H
(%)
Phase 1
IOUT1A
Direction = H
(%)
Home Microstep Position
Slow Mixed Slow
Slow Mixed
Slow Mixed Slow MixedMixed
STEP
Slow
Figure 4. Decay Modes for Quarter-Step Increments
Figure 3. Decay Modes for Half-Step IncrementsFigure 2. Decay Mode for Full-Step Increments
Phase 2
IOUT2A
Direction = H
(%)
Phase 1
IOUT1A
Direction = H
(%)
STEP
Home Microstep Position
Home Microstep Position
100.00
70.71
–70.71
0.00
–100.00
100.00
70.71
–70.71
0.00
–100.00
Slow
Slow
Home Microstep Position
Home Microstep Position
100.00
70.71
–70.71
0.00
–100.00
100.00
70.71
–70.71
0.00
–100.00
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1A
Direction = H
(%)
STEP
Slow
Mixed
Slow
Mixed
Slow
Mixed
Mixed
Slow
Mixed
Slow
Mixed
Slow
Slow
DMOS Microstepping Driver with Translator
A4983
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Figure 5. Decay Modes for Eighth-Step Increments
Mixed Mixed
Slow Slow
Mixed Slow Mixed Slow
0.00
100.00
92.39
70.71
55.56
–55.56
83.15
–83.15
38.27
19.51
–19.51
–38.27
–70.71
–92.39
–100.00
0.00
100.00
92.39
70.71
55.56
–55.56
83.15
–83.15
38.27
19.51
–19.51
–38.27
–70.71
–92.39
–100.00
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1A
Direction = H
(%)
Home Microstep Position
STEP
DMOS Microstepping Driver with Translator
A4983
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Figure 6. Decay Modes for Sixteenth-Step Increments
MixedSlow MixedSlow
MixedSlow Slow
Slow
100.00
95.69
88.19
83.15
–83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
0.00
–100.00
–95.69
–88.19
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.8
100.00
95.69
88.19
83.15
–83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
0.00
–100.00
–95.69
–88.19
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.8
Phase 2
IOUT2B
Direction = H
(%)
Phase 1
IOUT1A
Direction = H
(%)
Home Microstep Position
Mixed
STEP
DMOS Microstepping Driver with Translator
A4983
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Full
Step
#
Half
Step
#
1/4
Step
#
1/8
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
Full
Step
#
Half
Step
#
1/4
Step
#
1/8
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
1 1 1 1 100.00 0.00 0.0 5 9 17 33 –100.00 0.00 180.0
2 99.52 9.80 5.6 34 –99.52 –9.80 185.6
2 3 98.08 19.51 11.3 18 35 –98.08 –19.51 191.3
4 95.69 29.03 16.9 36 –95.69 –29.03 196.9
2 3 5 92.39 38.27 22.5 10 19 37 –92.39 –38.27 202.5
6 88.19 47.14 28.1 38 –88.19 –47.14 208.1
4 7 83.15 55.56 33.8 20 39 –83.15 –55.56 213.8
8 77.30 63.44 39.4 40 –77.30 –63.44 219.4
1 2 3 5 9 70.71 70.71 45.0 3 6 11 21 41 –70.71 –70.71 225.0
10 63.44 77.30 50.6 42 –63.44 –77.30 230.6
6 11 55.56 83.15 56.3 22 43 –55.56 –83.15 236.3
12 47.14 88.19 61.9 44 –47.14 –88.19 241.9
4 7 13 38.27 92.39 67.5 12 23 45 –38.27 –92.39 247.5
14 29.03 95.69 73.1 46 –29.03 –95.69 253.1
8 15 19.51 98.08 78.8 24 47 –19.51 –98.08 258.8
16 9.80 99.52 84.4 48 –9.80 –99.52 264.4
3 5 9 17 0.00 100.00 90.0 7 13 25 49 0.00 –100.00 270.0
18 –9.80 99.52 95.6 50 9.80 –99.52 275.6
10 19 –19.51 98.08 101.3 26 51 19.51 –98.08 281.3
20 –29.03 95.69 106.9 52 29.03 –95.69 286.9
6 11 21 –38.27 92.39 112.5 14 27 53 38.27 –92.39 292.5
22 –47.14 88.19 118.1 54 47.14 –88.19 298.1
12 23 –55.56 83.15 123.8 28 55 55.56 –83.15 303.8
24 –63.44 77.30 129.4 56 63.44 –77.30 309.4
2 4 7 13 25 –70.71 70.71 135.0 4 8 15 29 57 70.71 –70.71 315.0
26 –77.30 63.44 140.6 58 77.30 –63.44 320.6
14 27 –83.15 55.56 146.3 30 59 83.15 –55.56 326.3
28 –88.19 47.14 151.9 60 88.19 –47.14 331.9
8 15 29 –92.39 38.27 157.5 16 31 61 92.39 –38.27 337.5
30 –95.69 29.03 163.1 62 95.69 –29.03 343.1
16 31 –98.08 19.51 168.8 32 63 98.08 –19.51 348.8
32 –99.52 9.80 174.4 64 99.52 –9.80 354.4
DMOS Microstepping Driver with Translator
A4983
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Terminal List Table
Name Number Description
CP1 4 Charge pump capacitor terminal
CP2 5 Charge pump capacitor terminal
VCP 6 Reservoir capacitor terminal
VREG 8 Regulator decoupling terminal
MS1 9 Logic input
MS2 10 Logic input
MS3 11 Logic input
RESET 12 Logic input
ROSC 13 Timing set
SLEEP 14 Logic input
VDD 15 Logic supply
STEP 16 Logic input
REF 17 Gm reference voltage input
GND 3, 18 Ground*
DIR 19 Logic input
OUT1B 21 DMOS Full Bridge 1 Output B
VBB1 22 Load supply
SENSE1 23 Sense resistor terminal for Bridge 1
OUT1A 24 DMOS Full Bridge 1 Output A
OUT2A 26 DMOS Full Bridge 2 Output A
SENSE2 27 Sense resistor terminal for Bridge 2
VBB2 28 Load supply
OUT2B 1 DMOS Full Bridge 2 Output B
ENABLE 2 Logic input
NC 7, 20, 25 No connection
PAD – Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane
under the device.
PAD
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
VBB2
SENSE2
OUT2A
NC
OUT1A
SENSE1
VBB1
VREG
MS1
MS2
MS3
RESET
ROSC
SLEEP
OUT1B
NC
DIR
GND
REF
STEP
VDD
OUT2B
ENABLE
GND
CP1
CP2
VCP
NC
Pin-out Diagram
DMOS Microstepping Driver with Translator
A4983
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ET Package, 28-Pin QFN with Exposed Thermal Pad
0.25 +0.05
–0.07
0.55 +0.20
–0.10
0.50 0.90 ±0.10
C0.08
29X SEATING
PLANE C
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
28
2
1
A
28
1
2
PCB Layout Reference View
B3.15
3.15
3.15
3.15
0.30
1
28 0.50
1.15
4.80
4.80
C
5.00 ±0.15
5.00 ±0.15
D
DCoplanarity includes exposed thermal pad and terminals
Copyright ©2007-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
