NCP1594A, NCP1594B Buck Converter High-Efficiency, Synchronous 4 A, 6 A, 2 MHz The NCP1594 is a high-output-current synchronous PWM converter that integrates two N-channel Power MOSFETs. The NCP1594 utilizes externally compensated voltage mode control to provide good transient response, ease of implementation, and excellent loop stability. It regulates input voltages from 2.9 V to 6.0 V down to an output voltage as low as 0.6 V and is able to supply up to 4.0 A of load current (NCP1594A). Please contact factory for NCP1594B which supports 6.0 A load current. The NCP1594 includes an internal soft-start to limit inrush current. Other features include cycle-by-cycle current limit, 92% max duty cycle, short-circuit protection, and thermal shutdown. Features * Wide Input Voltage Range from 2.9 V to 6.0 V * Nine Preset Output Voltages (0.6 V, 0.7 V, 0.8 V, 1.0 V, 1.2 V, 1.5 V, www.onsemi.com MARKING DIAGRAM 24 PIN WQFN MT SUFFIX CASE 510BC x = A or B A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) 1.8 V, 2.0 V, and 2.5 V) PIN CONNECTIONS PGND PGND IN 1 18 PGND VDD 2 17 PGND CTL1 3 16 LX CTL2 4 15 LX REFIN 5 14 LX SS 6 13 BST NCP1594 9 10 11 12 (Top View) PWRGD FREQ 8 OUT 7 FB Telecom and Networking Power Management Computing Power Management Datacom Power Management Point of Load ASIC/CPU/DSP Core and I/O Voltages DDR Termination Voltage IN * * * * * * MODE GND Typical Applications 24 23 22 21 20 19 COMP * * * * * IN * * EN * Adjustable Output Voltage Down to 0.6 V * Adjustable 500 kHz to 2 MHz Switching Frequency * Externally Adjustable Soft-Start and Able to Start Up with Pre-Biased Output Load Selectable Forced PWM with and without Pre-biased Startup Compatible with Ceramic, Polymer, and Electrolytic Output Capacitors Cycle-by-Cycle Current Limiting Hiccup Mode Short-Circuit Protection Over Temperature Protection This is a 24 Pin 4 x 4 mm 0.5P WQFN Pb-Free Device These are Pb-Free Devices 1 NCP 1594x ALYWG G ORDERING INFORMATION Package Shipping NCP1594AMNTXG WQFN-24 (Pb-Free) 4000 / Tape & Reel NCP1594BMNTXG WQFN-24 (Pb-Free) 4000 / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2016 August, 2019 - Rev. 1 1 Publication Order Number: NCP1594/D NCP1594A, NCP1594B EN INPUT 2.9V~5.5V BST IN 0.1uF 0.47uH OUTPUT 1.8V / 6A LX 22uF 22uF PGND PGND CTL1 CTL2 OUT VDD 2.2uF NCP1594 GND FB 20k 158 560pF 2.67k 1500pF PWRGD COMP MODE FREQ REFIN SS 33pF 0.022uF 49.9k 1 MODE 2 VDD 3 CTL1 4 CTL2 6 SS 5 REFIN Figure 1. Functional Block Diagram VOLTAGE- CONTROL CIRCUITRY EN GND VOLTAGE REFERENCE SOFT-START 8 SHUTDOWN CONTROL IN COMP COMP CLAMPS 9 BIAS GENERATOR THERMAL SHUTDOWN FB ERROR AMPLIFIER PWM COMPARATOR 24 23 3.3V LDO UVLO CIRCUITRY MODE 7 IN CURRENT-LIMIT COMPARATOR 22 BST SWITCH OUT 8k PGND SHDN FB 13 CURRENT-LIMIT COMPARATOR PGND 0.9 x V REFIN PGND PWRGD PGND LX 12 IN OSCILLATOR LX FREQ 21 1Vp-p BST 11 IN LX 10 CONTROL LOGIC 14 15 16 17 18 Figure 2. Functional Block Diagram www.onsemi.com 2 20 19 NCP1594A, NCP1594B PIN DESCRIPTION Pin NO. Symbol 1 MODE Descriptions 2 VDD 3.3 V LDO Output. Supply input for the internal analog core. Connect a low-ESR, ceramic capacitor with a minimum value of 2.2 mF from VDD to GND. 3 CTL1 4 CTL2 Preset Output-Voltage Selection Inputs. CTL1 and CTL2 set the output voltage to one of nine preset voltages. See Table 1 for details 5 REFIN 6 SS Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. Minimum capacitance is 1 nF. 7 GND Analog Ground Connection. Connect GND and PGND together at one point near the input bypass capacitor return terminal. 8 COMP Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to FB and OUT. COMP is internally pulled to GND when the IC is in shutdown/hiccup mode. 9 FB 10 OUT Output-Voltage Sense. Connect to the converter output. Leave OUT unconnected when an external resistive divider is used. 11 FREQ Oscillator Frequency Select. Connect a precision resistor from FREQ to GND to select the switching frequency. 12 PWRGD Open-Drain, Power-Good Output. PWRGD is high impedance when VFB rises above 92.5% (typ) of VREFIN and VREFIN is above 0.54 V. PWRGD is internally pulled low when VFB falls below 90% (typ) of VREFIN or VREFIN is below 0.54 V. PWRGD is internally pulled low when the IC is in shutdown mode, VDD is below the internal UVLO threshold, or the IC is in thermal shutdown. 13 BST High-Side MOSFET Driver Supply. Internally connected to IN through a P-MOS switch Bypass BST to LX with a 0.1 mF capacitor. 14-16 LX Inductor Connection. All LX pins are internally shorted together. Connect all LX pins to the switched side of the inductor. LX is high impedance when the IC is in shutdown mode. 17-20 PGND 21-23 IN Input Power Supply. Input supply range is from 2.9 V to 6.0 V. Bypass IN to PGND with a 22 mF ceramic capacitor. 24 EN Enable Input. Logic input to enable/disable the NCP1594. -- EP Exposed Pad. Solder EP to a large contiguous copper plane connected to PGND to optimize thermal performance. Do not use EP as a ground connection for the device. Mode selection input. Input bias on this pin sets Forced PWM or Forced PWM with pre-biased startup External Reference Input. Connect REFIN to SS to use the internal 0.6 V reference. Connecting REFIN to an external voltage forces FB to regulate to the voltage applied to REFIN. REFIN is internally pulled to GND when the IC is in shutdown/hiccup mode. Feedback Input. Connect FB to the center tap of an external resistive divider from the output to GND to set the output voltage from 0.6 V to 90% of VIN. Connect FB through an RC network to the output when using CTL1 and CTL2 to select any of nine preset voltages. Power Ground. Connect all PGND pins externally to the power ground plane. Connect all PGND pins together near the IC. www.onsemi.com 3 NCP1594A, NCP1594B ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit IN,PGND 7 -0.3 V VDD the lower of 7 V or (VIN + 0.3) -0.3 V (VDD + 0.3) -0.3 V 7 -0.3 V BST 14 -0.3 V BST to LX BST,LX 7 -0.3 V PGND to GND PGND 0.3 -0.3 V LX the lower of 7 V or (VIN + 0.3) -0.3 the lower of +7 V or (VIN + 1) (t < 50 ns) -1.0 V (t < 50 ns) 8.5 V(t < 10 ns) -2.5 V (t < 10 ns) V 4/6 A Power Supply to GND VDD to GND COMP, FB, MODE, REFIN, CTL1, CTL2, SS, FREQ to GND OUT, EN to GND BST to GND LX to PGND ILX(rms) (NCP1594A/B) VDD Output Short Circuit Duration Continuous Converter Output Short Circuit Duration Continuous Continuous Power Dissipation (Note 1) PD 2222 mW Operating Ambient Temperature Range (Note 2) TA -40 to +85 C Operating Junction Temperature Range (Note 2) TJ -40 to +125 C TJ(MAX) +150 C Storage Temperature Range Tstg -65 to +150 C Thermal Characteristics (Note 1) RqJA RqJC 36 6 C/W Maximum Junction Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The maximum package power dissipation limit must not be exceeded. PD + T J(max) * T A R qJA 2. Rth_JA measured on approximately 1x1 in sq of 1 oz. Copper FR-4 or G-10 board. ELECTRICAL CHARACTERISTICS (VIN = VEN = 5 V, CVDD = 2.2 mF, TA = TJ = -40C to 85C, typical values are at TA = 25C, circuit of Figure 1, unless other noted) Parameter Symbol Conditions Min Typ Max Unit 6.0 V mA INPUT POWER SUPPLY IN Voltage Range VIN IN Supply Current IIN Total Shutdown Current from IN ISD 2.9 FSW = 1 MHz, no load (NCP1594A) VIN = 3.3 V 4.7 8 VIN = 5 V 5.0 8.5 FSW = 1 MHz, no load (NCP1594B) VIN = 3.3 V 4.9 8 VIN = 5 V 5.2 8.5 VIN = 5 V, VEN = 0 V 10 20 VIN = VDD = 3.3 V, VEN = 0 V 45 www.onsemi.com 4 mA NCP1594A, NCP1594B ELECTRICAL CHARACTERISTICS (VIN = VEN = 5 V, CVDD = 2.2 mF, TA = TJ = -40C to 85C, typical values are at TA = 25C, circuit of Figure 1, unless other noted) Parameter Symbol Conditions Min Typ Max Unit 2.6 2.8 V 3.3V LDO (VDD) VDD_R VDD Undervoltage Lockout Threshold VDD_F VDD rising LX starts/stops switching 2.35 Minimum glitch-width rejection TDD VDD Output Voltage VDD falling VDD VIN = 5 V, IVDD = 0 to 10 mA VDD Dropout VDD_DRP VIN = 2.9 V, IVDD = 10 mA VDD Current Limit IDD_LMT VIN = 5 V, VDD = 0 V IBST PWM Comparator Propagation Delay TD_PWM PWM Peak-to-Peak Ramp Amplitude 3.1 25 2.55 V 10 ms 3.3 3.5 V 0.08 V 40 mA VBST = VIN = 5 V, VLX = 0 or 5 V, VEN = 0 V 0.025 mA 10 mV overdrive 20 ns RAMP 1 V RAMP_OS 0.8 V BST BST Supply Current PWM COMPARATOR PWM Valley Amplitude ERROR AMPLIFIER COMP Clamp Voltage, High COMP_H VIN = 2.9 V to 5 V, VFB = 0.5 V, VREFIN = 0.6 V 2 V COMP Clamp Voltage, Low COMP_L VIN = 2.9 V to 5 V, VFB = 0.7 V, VREFIN = 0.6 V 0.7 V COMP Slew Rate COMP_SL VFB step from 0.5 V to 0.7 V in 10 ns 1.6 V/ms COMP Shutdown Resistance COMP_RS From COMP to GND, VIN = 3.3 V, VCOMP = 100 mV, VEN = VSS = 0 V 6 W Internally Preset Output Voltage Accuracy VR VREFIN = VSS, MODE = GND -1 FB Set-Point Value FB CTL1 = CTL2 = GND, MODE = GND 0.594 FB to OUT Resistor RFB All VID settings except CTL1 = CTL2 = GND 5.5 Open-Loop Voltage Gain Error-Amplifier Unity-Gain Bandwidth Error-Amplifier Common-Mode Input Range Error-Amplifier Maximum Output Current FB Input Bias Current +1 % 0.6 0.606 V 8 10.5 kW GAIN_EA 115 dB BW_EA 28 MHz VCOM_EA IMAX_EA IFB VDD = 2.9 V to 3.5 V VCOMP = 1 V, VREFIN = 0.6 V 0 VFB = 0.7 V, sinking 1 VFB = 0.5 V, sourcing -1 2 V mA CTL1 = CTL2 = GND -125 VCTL = 0 V -7.2 VCTL = VDD 7.2 nA CTL CTL Input Bias Current ICTL www.onsemi.com 5 mA NCP1594A, NCP1594B ELECTRICAL CHARACTERISTICS (VIN = VEN = 5 V, CVDD = 2.2 mF, TA = TJ = -40C to 85C, typical values are at TA = 25C, circuit of Figure 1, unless other noted) Parameter Symbol Conditions Min Typ Max Unit CTL CTL Input Threshold Hysteresis Low, falling 0.8 Open VDD/2 High, rising VDD - 0.8 All VID transitions 50 mV VREFIN = 0.6 V -185 nA VTH_CTL VHS_CTL V REFIN REFIN Input Bias Current REFIN Offset Voltage IREFIN VOS_REFIN VREFIN = 0.9 V, FB shorted to COMP -4.5 +4.5 mV LX (All Pins Combined) VIN = VBST - VLX = 3.3 V 42 VIN = VBST - VLX =5V 31 VIN = VBST - VLX = 3.3 V 35 VIN = VBST - VLX =5V 26 ILX = 2 A (NCP1594A) VIN = 3.3 V 30 VIN = 5 V 24 ILX = 2 A (NCP1594B) VIN = 3.3 V 25 VIN = 5 V 20 ILX = -2 A (NCP1594A) LX On-Resistance, High Side Rds_H ILX = -2 A (NCP1594B) LX On-Resistance, Low Side Rds_L ILIM_H High-side sourcing (NCP1594A) ILIM_L Low-side sinking (NCP1594A) ILIM_H High-side sourcing (NCP1594B) ILIM_L Low-side sinking (NCP1594B) ILK_LX VIN = 5 V, VEN = 0 V FSW VIN = 2.9 V to 6.0 V LX Current-Limit Threshold LX Leakage Current LX Switching Frequency Switching Frequency Range LX Minimum Off-Time LX Maximum Duty Cycle DMAX LX Minimum Duty Cycle DMIN Average Short-Circuit IN Supply Current IST mW 5.7 mW 42 35 mW 7 A 9 11 11 VLX = 0 V -0.01 VLX = 5 V 0.01 mA RFREQ = 49.9 kW 0.9 1 1.1 RFREQ = 23.6 kW 1.8 2 2.2 500 RFREQ = 49.9 kW 92 5 OUT connected to GND, VIN = 5 V (NCP1594A) 0.15 OUT connected to GND, VIN = 5 V (NCP1594B) 0.35 www.onsemi.com MHz 2000 kHz 78 ns 95 RFREQ = 49.9 kW 6 45 7 FSW TOFF_MIN mW 54 % 15 % A NCP1594A, NCP1594B ELECTRICAL CHARACTERISTICS (VIN = VEN = 5 V, CVDD = 2.2 mF, TA = TJ = -40C to 85C, typical values are at TA = 25C, circuit of Figure 1, unless other noted) Parameter Symbol Conditions Min NCP1594A 4 NCP1594B 6 Typ Max Unit LX (All Pins Combined) RMS LX Output Current IRMS A ENABLE EN Input Logic-Low Threshold EN_L EN falling EN Input Logic-High Threshold EN_H EN rising IEN VEN = 0 or 5 V, VIN = 5 V 0.01 MODE_L Logic-low, falling 26 MODE Input-Logic Threshold MODE_M Logic VDD/2 or open, rising 50 MODE_H Logic-high, rising 74 MODE Input-Logic Hysteresis MODE_HSY MODE falling 5 %VDD IMODE MODE = GND -5 mA ISS VSS = 0.45V, VREFIN = 0.6 V, sourcing Thermal-Shutdown Threshold TSD Rising Thermal-Shutdown Hysteresis TSD_HSY EN Input Current 0.9 1.5 V V mA MODE MODE Input Bias Current %VDD SS SS Current 6.7 8 9.3 mA THERMAL SHUTDOWN 150 C 25 C POWER GOOD (PWRGD) VFB falling, VREFIN = 0.6 V PG_H VFB rising, VREFIN = 0.6 V 92.5 TPG VFB rising or falling 48 PWRGD Output-Voltage Low VPG_L IPWRGD = 4 mA 0.03 PWRGD Leakage Current ILK_PG VIN = VPWRGD = 5 V, VFB = 0.7 V, VREFIN = 0.6 V 0.01 mA TCBLK 112 Clock Cycles TRST 896 Clock Cycles Power-Good Threshold Voltage Power-Good Edge Deglitch 88 90 92 % VREFIN PG_L Clock Cycles 0.1 V HICCUP OVERCURRENT LIMIT Current-Limit Startup Blanking Autoretry Restart Time FB Hiccup Threshold VTH_HCP VFB falling 70 %VREFIN Hiccup Threshold Blanking Time TBLK_HCP VFB falling 28 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 7 NCP1594A, NCP1594B Table 1. CTL1 AND CTL2 OUTPUT VOLTAGE SELECTION CTL1 CTL2 VOUT (V) VOUT (V) When Using External REFIN GND GND 0.6 REFIN* or REFIN < VOUT < 0.9 x VIN** VDD VDD 0.7 REFIN x (7/6) GND Unconnected 0.8 REFIN x (4/3) GND VDD 1.0 REFIN x (5/3) Unconnected GND 1.2 REFIN x 2 Unconnected Unconnected 1.5 REFIN x 2.5 Unconnected VDD 1.8 REFIN x 3 VDD GND 2.0 REFIN x (10/3) VDD Unconnected 2.5 REFIN x (25/6) *Install an 8.06 kWresistor at R3 and do not install a resistor at R4 (see Figure 3). **Install R3 and R4 following the equation in the Compensation Design section. OUT 1.8V 0.47uH 22uF 0.1uF VDD 13 20k BST 14 LX 15 LX 16 LX 17 PGND PGND 18 19 PGND PWRGD 12 20 PGND FREQ 11 21 IN R3 (For external adjstable voltage) 49.9k 158 IN FB 9 23 IN COMP 8 24 EN GND 7 560pF 2.67k 1500pF CTL2 REFIN SS 33pF CTL1 0.1uF 22 VDD 2.9V TO 6.0V MODE INPUT 22uF OUT 10 NCP1594 1 2 3 4 5 6 R4 (For external adjstable voltage) 2.2uF 0.022uF Figure 3. Typical Application Schematic. www.onsemi.com 8 NCP1594A, NCP1594B DETAILED DESCRIPTION The NCP1594 high-efficiency, voltage-mode switching regulator delivers up to 4 A of output current. The NCP1594 provides output voltages from 0.6 V to 0.9 x VIN from 2.9 V to 6.0 V input supplies, making it ideal for on-board point-of-load applications. The output voltage accuracy is better than 1% over load, line, and temperature. The NCP1594 features a wide switching frequency range, allowing the user to achieve all-ceramic-capacitor designs and fast transient responses (see Figure 1). The high operating frequency minimizes the size of external components. The NCP1594 is available in a small (4 mm x 4 mm), Pb-Free, 24-pin thin QFN package. The REFIN function makes the NCP1594 an ideal candidate for DDR and tracking power supplies. Using internal low-RDS(on) (20 mW / 24 mW, NCP1594A/B for the low-side n-channel MOSFET and 26 mW / 31 mW NCP1594A/B for the high-side n-channel MOSFET) maintains high efficiency at both heavy-load and high-switching frequencies. The NCP1594 employs voltage-mode control architecture with a high bandwidth (28 MHz) error amplifier. The voltage-mode control architecture allows up to 2 MHz switching frequency, reducing board area. The op-amp voltage-error amplifier works with type III compensation to fully utilize the bandwidth of the high-frequency switching to obtain fast transient response. Adjustable soft-start time provides flexibilities to minimize input startup inrush current. An open-drain, power-good (PWRGD) output goes high when VFB reaches 92.5% of VREFIN and VREFIN is greater than 0.54 V. The NCP1594 provides options for regular PWM, or PWM mode with monotonic startup into prebiased output. limit, the high-side MOSFET turns off and the synchronous rectifier turns on. The synchronous rectifier remains on until the inductor current falls below the low-side current limit. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. The NCP1594 uses a hiccup mode to prevent overheating during short-circuit output conditions. During current limit, if VFB drops below 70% of VREFIN and stays below this level for 12 ms or more, the NCP1594 enters hiccup mode. The high-side MOSFET and the synchronous rectifier are turned off and both COMP and REFIN are internally pulled low. If REFIN and SS are connected together, both are pulled low. The part remains in this state for 896 clock cycles and then attempts to restart for 112 clock cycles. If the fault causing current limit has cleared, the part resumes normal operation. Otherwise, the part reenters hiccup mode again. Soft-Start and REFIN The NCP1594 utilizes an adjustable soft-start function to limit inrush current during startup. An 8 mA (typ) current source charges an external capacitor connected to SS. The soft-start time is adjusted by the value of the external capacitor from SS to GND. The required capacitance value is determined as: C+ 8 mA t SS 0.6 V (eq. 1) where tSS is the required soft-start time in seconds. The NCP1594 also features an external reference input (REFIN). The IC regulates FB to the voltage applied to REFIN. The internal soft-start is not available when using an external reference. A method of soft-start when using an external reference is shown in Figure 2. Connect REFIN to SS to use the internal 0.6 V reference. Use a capacitor of 1 nF minimum value at SS. Controller The controller logic block determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the PWM comparator and generates the driver signals for both high-side and low-side MOSFETs. The break-before-make logic and the timing for charging the bootstrap capacitors are calculated by the controller logic block. The error signal from the voltage-error amplifier is compared with the ramp signal generated by the oscillator at the PWM comparator and, thus, the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the VCOMP signal or the current-limit threshold is exceeded. The low-side switch is then turned on for the remainder of the oscillator cycle. Figure 4. Soft-start with External Reference Undervoltage Lockout (UVLO) The UVLO circuitry inhibits switching when VDD is below 2.55 V (typ). Once VDD rises above 2.6 V (typ), UVLO clears and the soft-start function activates. A 50 mV hysteresis is built in for glitch immunity. Current Limit The internal, high-side MOSFET has a typical 7 A peak current-limit threshold for the NCP1594A and 11 A for the NCP1594B. When current flowing out of LX exceeds this www.onsemi.com 9 NCP1594A, NCP1594B Bootstrap (BST) and CTL2 are trilevel inputs: VDD, unconnected, and GND. An 8.06 kW resistor must be connected between VOUT and FB when CTL1 and CTL2 are connected to GND. The logic states of CTL1 and CTL2 should be programmed only before power-up. Once the part is enabled, CTL1 and CTL2 should not be changed. If the output voltage needs to be reprogrammed, cycle power or EN and reprogram before enabling. The output voltage can be programmed continuously from 0.6 V to 90% of VIN by using a resistor-divider network from VOUT to FB to GND as shown in Figure 3a. CTL1 and CTL2 must be connected to GND. The gate-drive voltage for the high-side, n-channel switch is generated by a flying-capacitor boost circuit. The capacitor between BST and LX is charged from the VIN supply while the low-side MOSFET is on. When the low-side MOSFET is switched off, the voltage of the capacitor is stacked above LX to provide the necessary turn-on voltage for the high-side internal MOSFET. Frequency Select (FREQ) The switching frequency is resistor programmable from 500 kHz to 2 MHz. Set the switching frequency of the IC with a resistor (RFREQ) connected from FREQ to GND. RFREQ is calculated as: R FREQ + 50 kW 0.95 ms 1 * 0.05 ms fS Shutdown Mode Drive EN to GND to shut down the IC and reduce quiescent current to 10 mA (typ). During shutdown, the LX is high impedance. Drive EN high to enable the NCP1594. (eq. 2) Where fS is the desired switching frequency in Hertz. Thermal Protection Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds TJ = +165C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 20C, causing a pulsed output during continuous overload conditions. The soft-start sequence begins after recovery from a thermal-shutdown condition. Power-Good Output (PWRGD) PWRGD is an open-drain output that goes high impedance when VFB is above 0.925 x VREFIN and VREFIN is above 0.54 V for at least 48 clock cycles. PWRGD pulls low when VFB is below 90% of VREFIN or VREFIN is below 0.54 V for at least 48 clock cycles. PWRGD is low when the IC is in shutdown mode, VDD is below the internal UVLO threshold, or the IC is in thermal shutdown mode. Programming the Output Voltage (CTL1, CTL2) As shown in Table 1, the output voltage is pin programmable by the logic states of CTL1 and CTL2. CTL1 APPLICATIONS INFORMATION IN and VDD Decoupling Output-Capacitor Selection To decrease the noise effects due to the high switching frequency and maximize the output accuracy of the NCP1594, decouple IN with a 22 mF capacitor from IN to PGND. Also, decouple VDD with a 2.2 mF low-ESR ceramic capacitor from VDD to GND. Place these capacitors as close as possible to the IC. The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor's ESR, and the voltage drop due to the capacitor's ESL. Estimate the output-voltage ripple due to the output capacitance, ESR, and ESL: Inductor Selection Choose an inductor with the following equation: L+ V OUT fS V IN VIN * VOUT LIR I OUTMAX (eq. 4) V RIPPLE + V RIPPLEC ) V RIPPLEESR ) V RIPPLEESL (eq. 3) where the output ripple due to output capacitance, ESR, and ESL is: where LIR is the ratio of the inductor ripple current to full load current at the minimum duty cycle. Choose LIR between 20% to 40% for best performance and stability. Use an inductor with the lowest possible DC resistance that fits in the allotted dimensions. Powdered iron ferrite core types are often the best choice for performance. With any core material, the core must be large enough not to saturate at the current limit of the NCP1594. V RIPPLEC + I P-P 8 C OUT V RIPPLEESR + I P- www.onsemi.com 10 ESR fS (eq. 5) (eq. 6) NCP1594A, NCP1594B V RIPPLEESL + V RIPPLEESL + I P- t ON I P-P t ON ESR ESL requirement imposed by the switching currents. The RMS input ripple current is given by: (eq. 7) VOUT I RIPPLE + I LOAD (eq. 8) or V IN * VOUT (eq. 11) V IN Where IRIPPLE is the RMS ripple current. V RIPPLEESL + I P-P t OFF Compensation Design ESL The power transfer function consists of one double pole and one zero. The double pole is introduced by the inductor L and the output capacitor CO. The ESR of the output capacitor determines the zero. The double pole and zero frequencies are given as follows: or whichever is larger. The peak-to-peak inductor current (IP-P) is: I P-P + V IN * V OUT fS V OUT V IN L (eq. 9) f P1_LC + f P2_LC + Use these equations for initial output-capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output-voltage ripple. Since the inductor ripple current is a factor of the inductor value, the output-voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors. Load-transient response depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x DILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design section for more details. f Z_ESR + The input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the IC. The total input capacitance must be equal or greater than the value given by the following equation to keep the input-ripple voltage within specification and minimize the high-frequency ripple current being fed back to the input source: D TS I OUT V IN-RIPPLE L 2p CO 1 ESR R )ESR O R )R CO O L (eq. 13) where RL is equal to the sum of the output inductor's DCR (DC resistance) and the internal switch resistance, RDS(on). A typical value for RDS(on) is 20 mW (low-side MOSFET) and 26 mW (high-side MOSFET). RO is the output load resistance, which is equal to the rated output voltage divided by the rated output current. ESR is the total equivalent series resistance of the output capacitor. If there is more than one output capacitor of the same type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single output capacitor divided by the total number of output capacitors. The high switching frequency range of the NCP1594 allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher than the unity-gain crossover frequency, fC, and the zero cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. The double pole produces a gain drop of 40 dB/decade and a phase shift of 180. The compensation network error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. Therefore, use type III compensation as shown in Figures 3 and 4. Type III compensation possesses three poles and two zeros with the first pole, fP1_EA, located at zero frequency (DC). Locations of other poles and zeros of the type III compensation are given by: Input-Capacitor Selection C IN_MIN + 2p (eq. 12) 1 (eq. 10) f Z1_EA + voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage. D is the duty cycle (VOUT/VIN) and TS is the switching period (1/fS). The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. The input capacitor must meet the ripple current f Z2_EA + f P3_EA + www.onsemi.com 11 2p 1 R1 C1 2p 1 R3 C3 2p 1 R1 C2 (eq. 14) (eq. 15) (eq. 16) NCP1594A, NCP1594B f P2_EA + 2p 1 R2 (eq. 17) C3 R1 + The above equations are based on the assumptions that C1 >> C2 and R3 >> R2 are true in most applications. Placements of these poles and zeros are determined by the frequencies of the double pole and ESR zero of the power transfer function. It is also a function of the desired close-loop bandwidth. The following section outlines the step-by-step design procedure to calculate the required compensation components for the NCP1594. When the output voltage of the NCP1594 is programmed to a preset voltage, R3 is internal to the IC and R4 does not exist (Figure 3b). When externally programming the NCP1594 (Figure 3a), the output voltage is determined by: R4 + 0.6 R3 VOUT * 0.6 for V OUT u 0.6 V C3 + V REFIN C1 + 2 p R3 V V R O ) ESR CO RL ) RO CO ESR C3 (eq. 21) (eq. 22) (eq. 23) p 1 R1 fS (eq. 24) The above equations (Equation 12 - 24) provide application compensation when the zero-cross frequency is significantly higher than the double-pole frequency. When the zero-cross frequency is near the double-pole frequency, the actual zero cross frequency is higher than the calculated frequency. In this case, lowering the value of R1 reduces the zero cross frequency. Also, set the third pole of the type III compensation close to the switching frequency if the zero-cross frequency is above 200 kHz to boost the phase margin. The recommended range for R3 is 2 kW to 10 kW. Note that the loop compensation remains unchanged if only R4's resistance is altered to set different outputs. if using and external VREFIN, and VOUT > VREFIN. For a 0.6 V output, or for VOUT = VREFIN, connect an 8.06 kW resistor from FB to VOUT. The zero-cross frequency of the close-loop, fC, should be between 10% and 20% of the switching frequency, fS. A higher zero cross frequency results in faster transient response. Once fC is chosen, C1 is calculated from the following equation: 1.5625 R3 C2 + (eq. 19) VOUT * VREFIN L 1 0.8 RL ) RO Set the third compensation pole at half of the switching frequency. Calculate C2 as follows: (eq. 18) R3 C1 R O ) ESR CO R2 + or: R4 + 0.8 L 1 IN P-P 1 ) R R L O (eq. 20) fC where VP-P is the ramp peak-to-peak voltage (1 V typ). Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the type III compensation less than the LC double-pole frequency to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency. Hence: Figure 5. Type 3 Compensation MODE SELECTION on first, charging the bootstrap capacitor to provide the gate-drive voltage for the high side switch. The low-side switch turns off either at the end of the clock period or once the low-side switch sinks 0.875 A/1.35 A (NCP1594A/NCP1594B respectively) current (typ), whichever occurs first. If the low-side switch is turned off before the end of the clock period, the high-side switch is turned on for the remaining part of the time interval until the inductor current reaches 0.58A/0.9A The NCP1594 features a mode selection input (MODE) that enables users to select a functional mode for the device (See Table 2). Forced-PWM Mode Connect MODE to GND to select forced-PWM mode. In forced-PWM mode, the NCP1594 operates at a constant switching frequency (set by the resistor at FREQ terminal) with no pulse skipping. PWM operation starts after a brief settling time when EN goes high. The low side switch turns www.onsemi.com 12 NCP1594A, NCP1594B (NCP1594A/NCP1594B respectively), or the end of clock cycle is encountered. Starting from the first PWM activity, the sink current threshold is increased through an internal 4-step DAC to reach the current limit of 7 A/11 A (NCP1594A/NCP1594B respectively), after 128 clock periods. This is done to help a smooth recovery of the regulated voltage even in the case of an accidental prebiased output with the forced-PWM mode selection. Table 2. MODE SELECTION Mode Connection Operation Mode GND Forced PWM Unconnected or VDD/2 Forced PWM. Soft-start into a prebiased output (monotonic startup) PCB Layout Considerations and Thermal Performance Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the NCP1594 EV kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB layout: 1. Connect input and output capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 2. Place capacitors on VDD, IN, and SS as close as possible to the IC and its corresponding pin using direct traces. Keep power ground plane (connected to PGND) and signal ground plane (connected to GND) separate. 3. Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors. 4. Connect IN, LX, and PGND separately to a large copper area to help cool the IC to further improve efficiency and long-term reliability. 5. Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close as possible to the IC. 6. Route high-speed switching nodes, such as LX, away from sensitive analog areas (FB, COMP). Soft-Starting Into a Prebiased Output Mode (Monotonic Startup) When MODE is left unconnected or biased to VDD/2, the NCP1594 soft-starts into a prebiased output without discharging the output capacitor. This type of operation is also termed monotonic startup. See the Starting Into Prebiased Output waveforms in the Typical Operating Characteristics section for an example. In monotonic startup mode, both low-side and high side switches remain off to avoid discharging the prebiased output. PWM operation starts when the FB voltage crosses the SS voltage. As in forced-PWM mode, the PWM activity starts with the low-side switch turning on first to build the bootstrap capacitor charge. The NCP1594 is also able to start into prebiased with the output above the nominal set point without abruptly discharging the output, thanks to the sink current control of the low-side switch through a 4-step DAC in 128 clock cycles. Monotonic startup mode automatically switches to forced-PWM mode 4096 clock cycles delay after the voltage at FB increases above 92.5% of VREFIN. The additional delay prevents an early transition from monotonic startup to forced-PWM mode during soft-start when a prolonged time constant external REFIN voltage is applied. The maximum allowed soft-start time is 2ms when an external reference is applied at REFIN in the case of starting up into prebiased output. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WQFN24, 4x4, 0.5P CASE 510BP ISSUE O DATE 03 FEB 2016 SCALE 2:1 II II II A B D PIN ONE REFERENCE 0.10 C 2X L (R0.125) E DETAIL A OPTIONAL CONSTRUCTION 0.10 C TOP VIEW 2X (A3) A 0.10 C 0.08 C NOTE 4 SIDE VIEW A1 C SEATING PLANE DIM A A1 A3 b D D2 E E2 e L 24X L 7 13 E2 1 24 24X e e/2 b 0.10 C A B 0.05 C BOTTOM VIEW NOTE 3 SOLDERING FOOTPRINT* 4.30 24X MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 3.90 4.10 2.44 2.64 3.90 4.10 2.44 2.64 0.50 BSC 0.30 0.50 GENERIC MARKING DIAGRAM* 1 D2 DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. XXXXXX XXXXXX ALYWG G XXXXXX= Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. 0.58 2.70 1 2.70 4.30 PKG OUTLINE 24X 0.32 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 98AON08748G Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped "CONTROLLED COPY" in red. NEW STANDARD: (c) Semiconductor Components Industries, LLC, 2002 Case Outline Number: http://onsemi.com WQFN24, 4X4, 0.5P DESCRIPTION: October, 2002 - Rev. 0 PAGE 1 OFXXX 2 1 DOCUMENT NUMBER: 98AON08748G PAGE 2 OF 2 ISSUE REVISION DATE O THIS IS A CUSTOM VERSION OF CASE 510BC TO MEET CUSTOMER'S SPECIAL REQUIREMENT OF LEAD CONSTRUCTION OPTION. REQ. BY J. LIU. 03 FEB 2016 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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