CY7C024AV-25AC - Cypress Semiconductor

3.3V 4K/8 K/16K x 16/18 Dual-Port Static RAM

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-06052 Rev. ** Revised September 21, 2001

25/0251

Features

• True dual-ported memory cells which allow simulta-

neous access of the same memory location

• 4/8/16K x 16 organiza tion (CY7 C024 AV/025AV/026AV)

• 4/8K x 18 organization (CY7C0241AV/0251AV)

• 16K x 18 organization (CY7C036AV)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 20 and 25 ns

• Low operating power

—Active: ICC = 115 mA (typical)

—Standby: ISB3 = 10 µA (typical)

•Fully asynchro nous operation

•Automatic power-down

•Expandable data bus to 32/36 bits or more using Master/

Slave chip select when using more than one device

•On-chip arbitration logic

•Semaphores included to permit software handshaking

between ports

•INT flag for port-to-port communication

•Separate upper-byte and lower-byte control

•Pin select for Master or Slave

•Commercial and indus trial tem peratu re ranges

•Available in 100-pin TQFP

•Pin-compatible and functionally equivalent to

IDT70V24, 70V25, and 7V0261.

Notes:

1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.

2. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.

3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.

4. BUSY is an output in master mode and an input in slave mode.

R/WL

OEL

I/O8/9L–I/O15/17L I/O

Control

Address

Decode

A0L–A11/12/13L

CEL

OEL

R/WL

BUSYL

I/O

Control

CEL

Interrupt

Semaphore

Arbitration

SEML

INTL

M/S

UBL

LBL

I/O0L–I/O7/8L

R/WR

OER

I/O8/9L–I/O15/17R

CER

UBR

LBR

I/O0L–I/O7/8R

UBL

LBL

Logic Block Diagram

A0L–A11/1213L True Dua l-Ported

RAM Array

A0R–A11/12/13R

CER

OER

R/WR

BUSYR

SEMR

INTR

UBR

LBR

Address

Decode A0R–A11/12/13R

[1] [1]

[2] [2]

[4] [4]

12/13/14

8/9

12/13/14

8/9

12/13/14 12/13/14

[3]

For the most recent information, visit the Cypress web site at www.cypress.com

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 2 of 19

Functional Description

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV /

036AV are low-power CMOS 4K, 8K, and 16K x16/18 dual-

port stati c RAMs. Various arbitration schemes are included on

the dev ic es to h andle situations w he n m ul tip le pro ce ss ors a c-

cess the same piece of data. Two ports are provided, permit-

ting independent, asynchronous access for reads and writes

to any l ocation in memory . The devices can be utilized as stan-

dalone 1 6/18-bit dual -port static RAMs or multi ple devices can

be combined in order to function as a 32/36-bit or wider mas-

ter/sl ave dual -por t sta tic RAM. An M/S pi n is pr ov ided for i m-

plementing 32/36-bit or wider memor y applications with out the

need for separate master and slave devices or additional dis-

crete logic. Application areas include interprocessor/multipro-

cessor designs, communications status buffering, and dual-

port video/graphics memory.

Each port has independent control pins: Chip Enable (CE),

Read or Write Enable (R/W), and Output Enable (OE). Two

flags are provided on each port (BUSY and INT). BUSY sig-

nals that the port is trying to access the same location currently

being ac cess ed by the oth er port. Th e Interru pt flag (INT) p er-

mits communication between ports or systems by means of a

mail box. The semaphores are used to pass a flag, or token,

from one port to the other to indicate that a shared resou rce is

in use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared re-

source is in use. An automatic power-down feature is con-

trolled independently on each port by a Chip Select (CE) pin.

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV are available in 100-pin Thin Quad Plastic Flatpacks

(TQFP).

Pin Configurations

Notes:

5. A12L on the CY7C025AV.

6. A12R on the CY7C025AV.

Top View

100-Pin TQFP

100 99 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

A5L

A4L

INTL

A2L

A0L

BUSYL

GND

INTR

A0R

A1L

I/O10L

I/O11L

I/O15L

VCC

GND

I/O1R

I/O2R

VCC

9091

A3L

M/S

BUSYR

I/O14L

GND

I/O12L

I/O13L

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

83 82 81 80 79 78 77 76

43 44 45 46 4748 49 50

I/O

GND

I/O

SEM

11L

10L

I/O0R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

R/W

GND

SEM

11R

10R

CY7C024AV (4K x 16)

R/W

[5]

[6]

CY7C025AV (8K x 16)

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 3 of 19

Pin Configurations (continued)

Notes:

7. A12L on the CY7C0251AV.

8. A12R on the CY7C0251AVC.

Top View

100-Pin TQFP

100 99 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

A5L

A4L

INTL

A2L

A0L

BUSYL

GND

INTR

A0R

A1L

I/O11L

I/O12L

I/O16L

VCC

GND

I/O1R

I/O2R

VCC

9091

A3L

M/S

BUSYR

I/O15L

GND

I/O13L

I/O14L

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

83 82 81 80 79 78 77 76

43 44 45 46 47 48 49 50

I/O

10L

GND

I/O

SEM

11L

10L

I/O0R

I/O

16R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

R/W

GND

SEM

11R

10R

CY7C0241AV (4K x 18)

I/O8L

I/O17L

I/O8R

I/O17R

R/W

[8] [7]

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A6L

A5L

A4L

INTL

A2L

A0L

GND

M/S

A0R

A1R

A1L

A3L

BUSYR

INTR

A2R

A3R

A4R

A5R

BUSYL

CY7C026AV (16K x 16)

I/O10L

I/O11L

I/O15L

I/O13L

I/O14L

GND

I/O0R

VCC

I/O3R

GND

I/O12L

I/O1R

I/O2R

I/O4R

I/O5R

I/O6R

VCC

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O0L

I/O2L

I/O1L

VCC

R/WL

UBL

LBL

GND

I/O3L

SEML

CEL

A113L

A12L

A11L

A10L

A9L

A8L

A7L

OEL

34 35 36 424139 403837 43 44 45 5048 494746

A6R

A7R

A8R

A9R

A10R

A11R

CER

A13R

UBR

GND

R/WR

GND

I/O14R

LBR

A12R

OER

I/O15R

I/O13R

I/O12R

I/O11R

I/O10R

I/O9R

I/O8R

I/O7R

SEMR

3332313029282726

CY7C0251AV (8K x 18)

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 4 of 19

Pin Configurations (continued)

Selection Guide

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

-20

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

-25

Maximum Access Time (ns) 20 25

Typical Operating Current (mA) 120 115

T ypical Stand by Current for ISB1 (mA) (Both ports TTL

Level) 35 30

Typical Standby Current for ISB3 (µA)

(Both ports CMOS Level) 10 10

Top View

100-Pin TQFP

100 99 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

A5L

A4L

INTL

A2L

A0L

BUSYL

GND

INTR

A0R

A1L

I/O11L

I/O12L

I/O16L

VCC

GND

I/O1R

I/O2R

VCC

9091

A3L

M/S

BUSYR

I/O15L

GND

I/O13L

I/O14L

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

83 82 81 80 79 78 77 76

43 44 45 46 4748 49 50

I/O

10L

GND

I/O

SEM

11L

10L

I/O0R

I/O

16R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

R/W

GND

SEM

11R

10R

I/O8L

I/O17L

I/O8R

I/O17R

R/W

CY7C036AV (16K x 18)

A13L

A13R

12L

12R

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 5 of 19

Maximum Ratings

(Above w hi ch the useful life m ay be im pai red. For user guide-

lines, not tes ted .)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +4.6V

DC Voltage Applied to

Outputs in High Z State ...........................–0.5V to VCC+0.5V

DC Input Voltage[9] ..................................–0.5V to VCC+0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... >2001V

Latch-Up Current.................................................... >200 mA

Notes:

9. Pulse width < 20 ns.

10. Industrial parts are available in CY7C026AV and CY7C036AV only.

Pin Definitions

Left Port Right Port Description

CELCERChip Enable

R/WLR/WRRead/Write Enable

OELOEROutput Enable

A0L–A13L A0R–A13R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K)

I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output

SEML SEMRSemaphore Enable

UBLUBRUpper Byte Select (I/O8–I/O15 for x 16 devices; I/O9–I/O17 for x18 devices)

LBLLBRLower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)

INTLINTRInterrupt Flag

BUSYLBUSYRBusy Flag

M/S Master or Slave Select

VCC Power

GND Ground

NC No Connect

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 3.3V ± 300 mV

Industrial[10] –40°C to +85°C 3.3V ± 300 mV

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 6 of 19

Notes:

11. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except outp ut enable). f = 0 means no addres s or control line s change. This applies only to inputs at CMOS level standby ISB3.

12. Tested initially and after any design or process changes that may affect these parameters.

Electrical Characteristics Ov er the Op erating Range

Parameter Description

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Unit

-20 -25

Min. Typ. Max. Min. Typ. Max.

VOH Output HIGH Voltage (VCC=3.3V) 2.4 2.4 V

VOL Output LOW Voltage 0.4 0.4 V

VIH Input HIGH Voltage 2.0 2.0 V

VIL Input LOW Voltage 0.8 0.8 V

IOZ Output Lea ka ge Cu rren t –10 10 –10 10 µA

IIX Input Leakage Current –10 10 –10 10 µA

ICC Operati ng Curren t (VCC = Max., IOUT =0

mA) Outputs Disa bled Com’l. 120 175 115 165 mA

Ind.[10] 135 185 mA

ISB1 Stand by Current (Both Ports TTL Level )

CEL & CER ≥ VIH, f = fMAX Com’l. 35 45 30 40 mA

Ind.[10] 40 50 mA

ISB2 Stand by Current (One Port TTL Level )

CEL | CER ≥ VIH, f = fMAX Com’l. 75 110 65 95 mA

Ind.[10] 75 105 mA

ISB3 Standby Current (Both Ports CMOS Level)

CEL & CER ≥ VCC−0.2V, f = 0 Com’l. 10 500 10 500 µA

Ind.[10] 10 500 µA

ISB4 Stand by Current (One Port CMOS Level)

CEL | CER ≥ VIH, f = fMAX[11] Com’l. 70 95 60 80 mA

Ind.[10] 70 90 mA

Capacitance[12]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 3.3V 10 pF

COUT Output Capacitance 10 pF

AC Test Loads and Waveforms

3.0V

GND 90% 90%

10%

3ns 3ns

10%

ALL INPUTPULSES

(a) Normal Load (Load 1)

R1 = 590Ω

3.3V

OUTPUT

R2 = 435Ω

C= 30pF

VTH =1.4V

OUTPUT

C= 30pF

(b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2)

R1 = 590Ω

R2 = 435Ω

3.3V

OUTPUT

C= 5pF

RTH = 250Ω

≤≤

including scope and jig)

(Used for tLZ, tHZ, tHZWE, & tLZWE

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 7 of 19

Switching Characteristics Over the Operating Range[13]

Parameter Description

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Unit

-20 -25

Min. Max. Min. Max.

READ CYCLE

tRC Read Cycle Time 20 25 ns

tAA Address to Data Valid 20 25 ns

tOHA Output Hold From Address Change 3 3 ns

tACE[14] CE LOW to Data Valid 20 25 ns

tDOE OE LOW to Data Valid 12 13 ns

tLZOE[15, 1 6, 17] OE Low to Low Z 3 3 ns

tHZOE[15, 16, 17] OE HIGH to High Z 12 15 ns

tLZCE[15 , 16, 17] CE LOW to Low Z 3 3 ns

tHZCE[15, 16, 17] CE HIGH to High Z 12 15 ns

tPU[17] CE LOW to Power-Up 0 0 ns

tPD[17] CE HIGH to Power-Down 20 25 ns

tABE[14] Byte Enable Access Time 20 25 ns

WRITE CYCLE

tWC Write Cycle Time 20 25 ns

tSCE[14] CE LOW to Write End 15 20 ns

tAW Address Valid to Write End 15 20 ns

tHA Address Hold From Write End 0 0 ns

tSA[14] Address Set-Up to Write Start 0 0 ns

tPWE Write Pulse Widt h 15 20 ns

tSD Data Set-Up to Write End 15 15 ns

tHD Data Hold From Write End 0 0 ns

tHZWE[16, 17] R/W LOW to High Z 12 15 ns

tLZWE[16, 17] R/W H IGH t o Lo w Z 3 0 ns

tWDD[18] Write Pulse to Data Delay 45 50 ns

tDDD[18] Write Data Valid to Read Data Valid 30 35 ns

Notes:

13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V , and output loading of the specified

IOI/IOH and 30-pF l oad capac itan ce.

14. To access RAM, CE=L, UB =L, SEM=H. To access semaphore, CE=H a nd SEM=L. Either condition must be valid for the en tire tSCE time.

15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE a nd tHZOE is less than tLZOE.

16. Test conditions used are Load 3.

17. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing

with Busy waveform.

18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 8 of 19

Data Retention Mode

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV are designed with battery backup in mind. Data reten-

tion volta ge and su pply cu rrent are guarante ed over tem pera-

ture. The follow i ng rule s ens ure data retenti on :

1. Chip Enable (CE) must be held HIGH during data retention, with-

in VCC to VCC – 0.2V.

2. CE must be kept between VCC – 0.2V and 70% of VCC

during the power-up and power-down transitions.

3. The RAM can begin operation >tRC a fter VCC reaches the

minimum operating voltage (3.0 volts).

Notes:

19. Test conditions used are Load 2.

20. tBDD is a c alculat ed param eter a nd is t he great er of tWDD–tPWE (actual) or t DDD–tSD (actual).

21. CE = VCC, Vin = GND to VCC, T A = 25°C. Thi s paramet er is guaran teed b ut not te sted.

BUSY TIMING[19]

tBLA BUSY LOW from Address Match 20 20 ns

tBHA BUSY HIGH from Address Mismatch 20 20 ns

tBLC BUSY LOW from CE LOW 20 20 ns

tBHC BUSY HIGH from CE HIGH 17 17 ns

tPS Port Set-Up for Priority 5 5 ns

tWB R/W HIGH a fter BU SY (Sl ave) 0 0 ns

tWH R/W HIGH a fter BU SY HIGH (Slave ) 15 17 ns

tBDD[20] BUSY HIGH to Data Valid 20 25 ns

INTERRUPT TIMING[19]

tINS INT Set T i me 20 20 ns

tINR INT Reset Time 20 20 ns

SEMAPHORE TIMING

tSOP SEM Flag Update Pulse (OE or SEM)10 12 ns

tSWRD SEM Flag Write to Read Time 5 5 ns

tSPS SEM Flag Contenti on Win dow 5 5 ns

tSAA SEM Address Access Time 20 25 ns

Switching Characteristics Over the Operating Range[13] (continued)

Parameter Description

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Unit

-20 -25

Min. Max. Min. Max.

Timing

Parameter Test Conditions[21] Max. Unit

ICCDR1 @ VCCDR = 2V 50 µA

Data Retention Mode

3.0V 3.0V

VCC > 2.0V

VCC to VCC –0.2V

VCC

tRC

VIH

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 9 of 19

Switching Waveforms

Notes:

22. R/W is HIGH for read c ycles.

23. Device is continuously selected CE = VIL and UB or LB = VIL. This wavef orm ca nnot b e used for semap hore rea ds.

24. OE = VIL.

25. Address v a lid prior to or coincident with CE t ransiti on LOW.

26. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

tRC

tAA

tOHA

DATA VALIDPREVIO U S D ATA VALID

DATA OUT

ADDRESS

tOHA

Read Cycl e No.1 (Either Port Addr ess Access)[ 22, 23, 24 ]

tACE

tLZOE

tDOE

tHZOE

tHZCE

DATA VALID

tLZCE

tPU tPD

ISB

ICC

DATA OUT

CE and

LB or UB

CURRENT

Read Cycle No.2 (Either Port CE/OE Access)[22, 25, 26]

UB or LB

DATAOUT

tRC

ADDRESS

tAA tOHA

tLZCEtABE

tHZCE

tACE

tLZCE

Read Cycle No. 3 (Either Port)[22, 24, 25, 26]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 10 of 19

Notes:

27. R/W must be HIGH duri ng all address tran sitions .

28. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.

29. tHA is measur ed from the e arlier o f CE or R/W or (SEM or R/W) going HIGH at the end of write cyc le.

30. If OE i s LOW during a R/W controll ed write cycle, t he write p ulse widt h must b e the larger of tPWE or (tHZWE + tSD) to a llow the I/O dri vers to tu rn off and data to be p laced on

the bus for the requi red tSD. If OE is HIGH duri ng an R/W contr olled write cycle, this requi rement does not apply and t he writ e pul se ca n be as s hort a s the speci fied t PWE.

31. To access RAM, CE = VIL, SEM = VIH.

32. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.

To access lower byte, CE = VIL, LB = VIL, SEM = VIH.

33. Transition is measured ±500 mV from steady state with a 5-pF load (includi ng scope and jig). This para meter is sampled and not 100% tested.

34. During this period, the I/O pins are in the output state, and input signals must not be applied.

35. If the CE or SEM LOW trans ition occurs simultaneously with or after the R/W LOW transi tion, the outputs remain in the high-i mpedance st ate.

Switching Waveforms (continued)

tAW

tWC

tPWE

tHD

tSD

tHA

R/W

DATAOUT

DATA IN

ADDRESS

tHZOE

tSA

tHZWE tLZWE

Write Cycle No.1: R/W Controlled Timing[27, 28, 29, 30]

[33]

[30]

[31, 32]

NOTE 34 NOTE 34

tAW

tWC

tSCE

tHD

tSD

tHA

R/W

DATA IN

ADDRESS

tSA

Write Cycle No. 2: CE Controlled Timing[27, 28, 29, 35]

[31, 32]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 11 of 19

Notes:

36. CE = HIGH for the duration of the above timing (both write and read cycle).

37. I/O0R = I/O0L = LO W (re quest sema phore); CER = CEL = HIGH.

38. Semaphores are reset (available to both ports) at cycle start.

39. If tSPS is viol ated, t he sema phore w ill d efinite ly be ob taine d by o ne side or the other, but which s ide will get the s emaphore is unp redictable.

Switching Waveforms (continued)

tSOP

tSAA

VALID ADRESS VALID ADRESS

tHD

DATAIN VALID DATAOUT VALID

tOHA

tAW tHA tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITE CYCLE READ CYCLE

R/W

I/O0

SEM

A0–A2

Semaphore Read After Write Timing, Either Side[36]

MATCH

tSPS

A0L–A2L

MATCH

R/WL

SEML

A0R–A2R

R/WR

SEMR

Timing Diagram of Semaphore Contention[37, 38, 39]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 12 of 19

Note:

40. CEL = CER = LOW.

Switching Waveforms (continued)

VALID

tDDD

tWDD

MATCH

R/WR

DATA INR

DATAOUTL

tWC

ADDRESSR

tPWE

VALID

tSD tHD

ADDRESSL

tPS

tBLA tBHA

tBDD

BUSYL

Timing Diagram of Read with BUSY (M/S=HIGH)[40]

tPWE

R/W

BUSY tWB tWH

Write Timing with Busy Input (M/S=LOW)

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 13 of 19

Note:

41. If tPS is violated, the busy signal will be ass erted on one side or the other , but there is no guaran tee to which side BUSY will be asserted.

Switching Waveforms (continued)

ADDRESS MATCH

tPS

tBLC tBHC

ADDRESS MATCH

tPS

tBLC tBHC

CERValidFirst:

ADDRESSL,R

BUSYR

CEL

CER

BUSYL

CER

CEL

ADDRESSL,R

Busy Timing Diagram No.1 (CE Arbitration)[41]

CELValid First:

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDR ES S MI SMATCH

tRC or tWC

tBLA tBHA

ADDRESSR

ADDRESS MATCH ADDR ES S MI SMATCH

tPS

ADDRESSL

BUSYL

tRC or tWC

tBLA tBHA

ADDRESSR

Right AddressValid First:

Busy Timing Diagram No.2 (Address Arbitration)[41]

Left Address Valid First:

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 14 of 19

Notes:

42. tHA depen ds on which enable pin (CEL or R/WL) is deasse rted f irst.

43. tINS or tINR depends on w hich en able pin (CE L or R/WL) is asserted la st.

Switching Waveforms (continued)

Interrupt Timing Diagrams

WRITE 1FFF (OR 1/3FFF)

tWC

Right SideClearsINTR:

tHA

READ 7FFF

tRC

tINR

WRITE 1FFE (OR 1/3FFE)

tWC

Right Side Sets INTL:

Left Side Sets INTR:

Left SideClears INTL:

READ 7FFE

tINR

tRC

ADDRESSR

CE L

R/WL

INTL

OE L

ADDRESSR

R/WR

CER

INTL

ADDRESSR

CER

R/WR

INTR

OER

ADDRESSL

R/WL

CEL

INTR

tINS

tHA

tINS

(OR 1/3FFF)

OR 1/3FFE)

[42]

[43]

[42]

[43]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 15 of 19

Architecture

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV consist of an array of 4K, 8K, and 16K words of 16 and

18 bits each of dual-port RAM cells, I/O and address lines, and

control signals (CE, OE, R/ W). T hes e c ont rol pin s pe r mit ind e-

pendent access for reads or writes to any location in memory.

To handle simultaneous writes/reads to the same location, a

BUSY pin is provided on each port. T wo Interrupt (INT) pins can

be utilized for port-to-port communication. Two Semaphore

(SEM) control pins are used for allocating shared resources.

With the M/S pin, the devices can function as a master (BUSY

pins are outputs) or as a slave (BUSY pins are inputs). The

devices also have an automatic power-down feature controlled

by CE. Each port is provided with its own output enable control

(OE), which allows data to be read from the device.

Functional Description

Wr ite Ope ration

Data must be set up for a duration of tSD before the rising edge

of R/W in order to guarantee a valid write. A write operation is

controlled by either the R/W pin (see Write Cycle No. 1 wave-

form) or the CE pin (see Write Cycle No. 2 waveform). Required

inputs for non-contention operations are summarized in Table 1.

If a location is being written to by one port and the opposite

port attempts to read that location, a port-to-port flowthrough

delay m us t occur be fore the d ata i s rea d on the ou tpu t; oth er-

wise the data read is not deterministic. Data will be valid o n the

port tDDD after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE

and CE pin s. Dat a will be av ailabl e tACE after CE or tDOE af ter

OE is asserted. If the user wishes to access a sema phore flag,

then the SEM pin must be asserted instead of the CE pin, and

OE must also be asserted.

Interrupts

The upper two memory locations may be used for message

passing. The highest memory location (FFF for the

CY7C024AV/41AV, 1FFF for the CY7C025AV/51AV, 3FFF for

the CY7 C026A V/ 36A V) i s the mailb ox for the rig ht port and th e

second-highest memory location (FFE for the CY7C024AV/

41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the

CY7C026AV/36AV) is the mailbox for the left port. When one

port writes to the other port’s mailbox, an interrupt is generated

to the owner. The interrupt is reset when the owner reads the

contents of the mailbox. The message is user defined.

Each port can read the other port’s mailbox without resetting

the interrupt. The active state of the busy signal (to a port)

prevents the port f rom s etting the i nterrupt to th e wi nning port.

Also, an ac ti v e busy t o a p o rt p rev en t s t ha t p or t fr om r ead i ng

its own mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not con-

nect the interrupt pin to the processor’s interrupt request input pin.

The operation of the interrupts and their interaction with Busy

are summarized in Table 2.

Busy

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV provide on-chip arbitration to resolve simultaneous

memory location access (contention). If both ports’ CEs are

asserte d and an ad dress m atch oc curs wit hin t PS of each ot h-

er, the busy logic will determine which port has access. If tPS

is violated, one port will definitely gain permission to the loca-

tion, but it is not predictable which port will get that permission.

BUSY will be asserted tBLA after an address match or tBLC

after CE is taken LOW.

Master/Slave

A M/S pin is provided in order to expand the word width by

configuring the device as either a master or a slave. The BUSY

output of the master is connected to the BUSY input of the

slave. This will allow the dev ice to i nterface t o a master device

with no external co mponents. W riting to slave devices must be

delayed until after the BUSY input has settled (tBLC or tBLA),

otherwise, the sla ve chip may begin a write cy cle during a con-

tention situation. When tied HIGH, the M/S pin allows the de-

vice to be used as a master and, therefore, the BUSY line is

an outpu t. BUSY ca n then be us ed to se nd the arbitra tion ou t-

come to a slave.

Semaphore Operation

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV provide eight semaphore latches, which are separate

from the dual-port memory locations. Semaphores are used to

reser ve resource s that are shar ed between the two ports. The

state o f the sem aphore indi cates that a res our ce i s in use. For

example, if the left port wants to request a given resource, it

sets a lat ch by writing a zero to a sem aphore loc ation. The le ft

port then verifies its success in setting the latch by reading it.

After writi ng to the semap hore, SEM or OE mu st be deasse rt-

ed for tSOP before attempting to read the semaphore. The

semaphore value will be available tSWRD + tDOE after the rising

edge of the semaphore write. If the left port was successful

(reads a z ero), it assu mes cont rol of the sha red resourc e, oth-

erwise (rea ds a o ne) it a ss um es the righ t p ort h as control and

continues to poll the semaphore. When the right side has re-

linquis hed control of the semaphor e (by writing a one), the le ft

side wil l succeed in ga ining control o f the semaphore. If the left

side no longer requires the semaphore, a one is written to

cancel its request.

Semapho res are a ccesse d by as sertin g SEM LOW. The SEM

pin functions as a chip select for the semaphore latches (CE

must remain HIGH during SEM LOW). A0–2 represents the

semaph ore add res s. OE and R/W are used in the sam e man-

ner as a normal memory access. When writing or reading a

semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O0 is used. If a zero is

written to the left port of an available semaphore, a one will

appear a t the same semaphore a ddress on th e right port. Th at

semaphore can now only be modified by the side showing zero

(the left port in this c ase). If the lef t port n ow relinqu ishes co n-

trol by writing a one to the semaphore, the semaphore will be

set to one for both sides. However , if the right port had request-

ed the semaphore (written a zero) while the left port had con-

trol, the right port would immediately own the semaphore as

soon as the l eft p ort rel ea sed it. Tabl e 3 shows sample sema-

phore operations.

When reading a semaphore, all sixteen/eighteen data lines

output the semaphore value. The read value is latched in an

output register to pre ven t the se ma pho re fro m c ha ngi ng s ta te

during a write from the other port. If both ports attempt to ac-

cess the semaphore within tSPS of each oth er, the sema phore

will d efinite ly be obtain ed by one si de or th e ot her, but the re i s

no guarantee which side will control the semaphore.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 16 of 19

Table 1. Non-Contending Read/Write

Inputs Outputs

CE R/W OE UB LB SEM I/O9–I/O17 I/O0–I/O8Operation

H X X X X H High Z High Z Deselected: Power-Down

X X X H H H High Z High Z Deselected: Power-Down

L L X L H H Data In Hi gh Z Write to Upper Byte Only

L L X H L H High Z Data In Write to Lower Byte Only

L L X L L H Data In Data In Write to Both Bytes

L H L L H H Data Out High Z Read Upper Byte Only

L H L H L H High Z Data Out Read Lower Byte Only

L H L L L H Data Out Data Out Read Both Bytes

X X H X X X High Z High Z Outputs Disable d

H H L X X L Data Out Data Out Read Data in Semaphore Flag

X H L H H L Data Out Data Out Read Data in Semaphore Flag

H X X X L Data In Data In Write DIN0 into Semaphore Flag

X X H H L Data In Data In Write DIN0 into Semaphore Flag

L X X L X L Not Allowed

L X X X L L Not Allowed

Table 2. Interrupt Operati on Example (assumes BUSYL=BUSYR=HIGH)[44]

Left Port Right Port

Function R/WLCELOELA0L–13LINTLR/WRCEROERA0R–13R INTR

Set Right IN TR Flag L L X FFF[47] X X X X X L[46]

Reset Right INTR Flag X X X X X X L L FFF (or 1/3FFF) H[45]

Set Left IN TL Flag X X X X L[45] L L X 1FFE (or 1/

3FFE) X

Reset Left INTL Flag X L L 1FFE[47] H[46] X X X X X

Table 3. Semaphore Operation Example

Function I/O0–I/O17 Left I/O0–I/O17 Right Status

No action 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left Port has semaphore token

Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore

Left port writes 1 to semaphore 1 0 Right port obtains semaphore token

Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore

Right port writes 1 to semaphore 0 1 Left port obtains semaphor e token

Left port writes 1 to semaphore 1 1 Semaphore free

Right port writes 0 to semaphore 1 0 Right port has semaphore token

Right port writes 1 to semaphore 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left port has semaphore token

Left port writes 1 to semaphore 1 1 Semaphore free

Notes:

44. See Functional Description for specific highest memory locations by device.

45. If BU SYR=L, then no change.

46. If BU SYL=L, then no change.

47. See Functional Description for specific addresses by device.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 17 of 19

Ordering Information

4K x16 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C024AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C024AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

8K x16 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C025AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C025AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

16K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C026AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C026AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C026AV-25AI A100 100-Pin Thin Quad Fl at Pack Industrial

4K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C0241AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C0241AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

8K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C0251AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C0251AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

16K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C036AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C036AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C036AV-25AI A100 100-Pin Thin Quad Fl at Pack Industrial

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 18 of 19

of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagram

100-Pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-B

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. ** Page 19 of 19

Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18

Dual Port Static RAM

Document Number: 38-06052

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 110204 11/11/01 SZV Change from Spec number: 38-00838 to 38-06052