2002 Microchip Technology Inc. DS39025F-page 1
MPIC16F87X
This document includes the programming
specifications for the following devices:
1.0 PROGRAMMING THE
PIC16F87X
The PIC16 F87X is progra mmed using a seria l metho d.
The Serial mode will allow the PIC16F87X to be pro-
grammed while in the user’s system. This allows for
increased design flexibility. This programming specifi-
cation applies to PIC16F87X devices in all packages.
1.1 Programming Algorit hm
Requirements
The programming algorithm used depends on the
operating voltage (VDD) of the PIC16F87X device.
Algorithm 1 is designed for a VDD range of
2.2V ≤VDD < 5.5V. Algorithm 2 is for a range of
4.5V ≤VDD ≤5.5V. Either algorithm can be used with
the two available pr ogramming entry me thods. The firs t
method follows the normal Microchip Programming
mode ent ry of applyi ng a VPP volt age of 13V ± .5V. The
second method, called Low Voltage ICSPTM or LVP for
short, applies VDD to MCLR and uses the I/O pin RB3
to enter Programming mode. When RB3 is driven to
VDD from ground, the PIC16F87X device enters
Programming mode.
1.2 Programming Mode
The Programming mode for the PIC16F87X allows pro-
grammi ng of user pr ogram memo ry , dat a memory, spe-
cial locations used for ID, and the configuration word.
Pin Di agram
•PIC16F870 •PIC16F874
•PIC16F871 •PIC16F876
•PIC16F872 •PIC16F877
•PIC16F873
PDIP, SOIC
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F877/874/871 PIC16F876/873/872/870
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
EEPROM Me mory Programming Spec ification
PIC16F87X
DS39025F-page 2 2002 Microchip Technology Inc.
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F87X
Pin Name During Programming
Function Pin Type Pin Description
RB3 PGM I Low voltage ICSP programming input if LVP
configuration bit equals 1
RB6 CLOCK I Clock input
RB7 DATA I/O Data input/output
MCLR VTEST MODE P* Program Mode Select
VDD VDD P Pow er Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
* In the PIC 16F87X, the pro gramming high vol tage is inte rnally generat ed. To acti vate the Programmi ng mode, high
voltage needs t o be applie d to the MCLR input. Since the MCLR is used for a leve l source, t his means that MC LR
does not draw any significant current.
2002 Microchip Technology Inc. DS39025F-page 3
PIC16F87X
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). In Programming mode, the program
memory space extends from 0x0000 to 0x3FFF, with
the first half (0x0000-0x1FFF) being user program
memory and the second half (0x2000-0x3FFF) being
configuration memory. The PC will increment from
0x0000 to 0x1FFF and wrap to 0x0000, 0x2000 to
0x3FFF and wrap around to 0x2000 (not to 0x0000).
Once i n configuratio n memory , t he highest bi t of the PC
stays a ‘1’, thus always pointing to the configuration
memory. The only way to point to user program mem-
ory is to reset the part and re-enter Program/Verify
mode, as described in Section 2.4.
In the configuration memory space, 0x2000-0x200F
are physically implemented. However, only locations
0x2000 through 0x2007 are available. Other locations
are reserved. Locations beyond 0x200F will physically
acce ss user mem ory (s ee Fig ure 2-1).
2.2 Data EEPROM Memory
The EEPROM data memory space is a separate block
of high endurance memory that the user accesses
using a special sequence of instructions. The amount
of data EEPROM memory depends on the device and
is sh own below in numb er of bytes.
The content s of dat a EEPROM memory have th e capa-
bility to be embedded in to the HEX file.
The progra mmer should be able to read data EEPROM
information from a HEX file and conversely (as an
option), write data EEPROM contents to a HEX file,
along w ith prog ram memo ry inform ation and configu ra-
tion bit inform ati on.
The 256 data memory locations are logically mapped
starting at address 0x2100. The format for data mem-
ory storage is one data byte per address location, LSB
aligned.
2.3 ID Locations
A user may store identification information (ID) in four
ID locat ion s. The ID locations are mapped in [0x 20 00 :
0x2003]. It is recommended that the user use only the
four Least Significant bits of each ID location. In some
devices, the ID locations read out in an unscrambled
fashion after code protection is enabled. For these
device s, it is recommended that ID location is written as
“11 1111 1000 bbbb” where ‘bbbb’ is ID information.
In other devices, the ID locations read out normally,
even after code protection. To understand how the
devices behave, refer to Table 5-1.
To understand the scrambling mechanism after code
protecti on, refe r to Sect ion 4.0.
Device # of Bytes
PIC16F870 64
PIC16F871 64
PIC16F872 64
PIC16F873 128
PIC16F874 128
PIC16F876 256
PIC16F877 256
PIC16F87X
DS39025F-page 4 2002 Microchip Technology Inc.
TABLE 2-1: PROGRAM MEMORY MAPPING
2K words 4K words 8K words
Implemented Implemented Implemented
Implemented Implemented Implemented
Implemented Implemented
Implemented Implemented
Reserved Implemented
Reserved Implemented
Implemented
Implemented
Reserved Reserved Reserved
Reserved Reserved Reserved
ID Location
ID Location
ID Location
ID Location
Reserved
Reserved
Device ID
Configuration Word
2000h
2001h
2002h
2003h
2004h
2005h
2006h
2007h
0h
1FFh
3FFh
400h
7FFh
800h
BFFh
C00h
FFFh
1000h
1FFFh
2008h
2100h
3FFFh
2002 Microchip Technology Inc. DS39025F-page 5
PIC16F87X
2.4 Program/Verify Mode
The Program/Verify mode is entered by holding pins
RB6 and RB7 l ow, w hile r aisin g MCLR pin from VIL to
VIHH (high voltage). In this mode, the state of the RB3
pin does not effect programming. Low voltage ICSP
Programm ing mo de is en tered by rais ing RB 3 from VIL
to VDD and then applying VDD to MCLR. Once in this
mode, the u se r p rog ram m em ory and t he co nfiguration
memory can be accessed and programmed in serial
fashion . The mode of oper ation is serial , and the mem-
ory that is accessed is the user program memory. RB6
and RB7 are Schmitt Trigger Inputs in this mode.
The seque nce that enters the de vice in to the Program -
ming/Verify mode place s all other log ic into the RESET
state (the MCLR pin was initially at VIL). This means
that all I/O are in the RESET state (high impedance
inputs).
The normal sequence for programming is to use the
load data command to set a value to be written at the
selected address. Issue the begin programming com-
mand followed by read data command to verify, and
then increment the address.
A device RESET will clear the PC and set the address
to 0. The “increment ad dress” com m and will incre me nt
the PC. The “load configuration” co mman d wil l se t the
PC to 0x2000. The available commands are shown in
Table 2-2.
2.4.1 LOW VOLTAGE ICSP
PROGRAMMING MODE
Low voltage ICSP Programming mode allows a
PIC16 F87 X devi ce to be pro gra mmed usin g VDD only.
Howeve r , when th is mode is ena bled by a co nfiguratio n
bit (LVP), the PIC16F87X device dedicates RB3 to
control entry/exit into Programming mode.
When LVP bit is set to ‘1’, the low voltage ICSP pro-
gramming entry is enabled. Since the LVP configura-
tion bit allows low voltage ICSP programming entry in
its erased stat e, an eras ed dev ic e w il l ha ve the LVP bit
enabled at the factory. While LVP is ‘1’, RB3 is dedi-
cated to low voltage ICSP program ming. Bring RB3 to
VDD and then MCLR to VDD to enter programming
mode. All other specifications for high voltage ICSP™
apply.
To disable low voltag e ICSP mode, the LVP bit mus t be
programmed to ‘0’. This must be done while entered
with Hi gh V ol tage En try mode (LVP bit = 1). R B3 is now
a general purpose I/O pin.
2.4.2 SERIAL PROGRAM/VERIFY
OPERATION
The RB6 pin is used as a clock input pin, and the RB7
pin is used for entering command bits and data
input/output during serial operation. To input a com-
mand, the clock pin (RB6) is cycled six times. Each
comma nd bit i s latche d on the falli ng edge of the clock ,
with the Least Significant bit (LSb) of the command
being input first. The data on pin RB7 is required to
have a minimum setup and hold time (see AC/DC
specifications), with respect to the falling edge of the
clock . Command s tha t have dat a as socia ted wit h them
(read and load) are specif ied to ha ve a mi nimum delay
of 1 µs between the command and the data. After this
delay, the clock pin is cycled 16 times with the first cycle
being a STAR T bit and the la st cycl e being a STOP bi t.
Data is also input and output LSb first.
Therefore, during a read operation, the LSb will be
transmi tted on to p in R B7 o n t he rising edge of t he sec -
ond cycle, and during a load operation, the LSb will be
latched on the falling edge of the second cycle. A min-
imum 1 µs del ay is also spec ified b etwe en con secu tive
commands.
All command s are transmitted LSb first . Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
clock . To allow for decoding of command s and reversa l
of data pin configuration, a time separation of at least
1µs is required between a command and a data word
(or another command).
The commands that are available are:
2.4.2.1 Load Configuration
After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits in a “data
word,” as described above, to be programmed into the
configuration memory. A description of the memory
mapping schemes of the program memory for normal
operation and Configuration mode operation is shown
in Figure 2-1. After the configuration memory is
entered, the only way to get back to the user program
memory is to exit the Program/Verify Test mode by
taking MCLR low (VIL).
2.4.2.2 Load Data for Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously . A timing diagram for the load data
comma nd is sh own in Figu re 6-1.
Note: The OSC must not have 72 osc clocks
while the devic e MCLR i s bet we en VIL and
VIHH.
PIC16F87X
DS39025F-page 6 2002 Microchip Technology Inc.
2.4.2.3 Load Data for Data Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied. How-
ever, the data memory is only 8-bits wide, and thus,
only the first 8-bits of data after the START bit will be
prog rammed i nt o t he da ta m em ory. It is st il l nece ss ar y
to cycl e the clo ck the fu ll 16 cy cles in order to al low the
internal circuitry to reset properly. The data memory
contains up to 256 bytes. If the device is code pro-
tected, the data is read as all zeros.
2.4.2.4 Read Data from Program Memory
After receiving this command, the chip will transmit
data bi ts out o f the pr ogr am memor y (use r or co nfigu -
ration) currently access ed , s tarting with the s ec ond ri s-
ing edge of the clock input. The RB7 pin will go into
Output mode on the second rising clock edge, and it
will revert back to Input mode (hi-impedance) after the
16th rising edge. A timing diagram of this command is
shown in Figure 6-2.
2.4.2.5 Read Data from Data Memory
After receiving this command, the chip will transmit
data bi ts out of the d ata me mor y star ting wi th th e sec -
ond rising edge of the clock input. The RB7 pin will go
into Outp ut mod e on the sec ond risin g edg e, and it will
revert ba ck to Input m ode (hi-imped ance) after the 16th
rising edge. As previously stated, the data memory is
8-bits wide, and therefore, only the first 8-bits that are
output are actual data.
2.4.2.6 Increment Address
The PC is incremented when this command is
rece ived. A ti ming diag ram of thi s command is shown
in Figure 6-3.
2.4.2.7 Begin Erase/Pr ogram Cycle
A load comm and must b e given b efore every begin
programming command. Programming of the appro-
priate memory (test program memory, user program
memory or dat a me mory) will begin a fter th is comm and
is rece ived and decoded. An internal timing mechanism
executes an erase before write. The user must allow f or
both erase and programming cycle times for program-
ming to complete. No “end programming” command is
required.
2.4.2.8 Begin Programming
A load comm and must b e given b efore every begin
programming command. Programming of the appro-
priate memory (test program memory, user program
memory or dat a me mory) will begin a fter th is comm and
is rece ived and decoded. An internal timing mechanism
executes a write. The user must allow for program
cycle time for programming to co mplete. No “end pro-
gramming” command is required.
This command is similar to the ERASE/PROGRAM
CYCLE command, except that a word erase is not
done. It is recommended that a bulk erase be per-
formed before starting a series of programming only
cycles.
Note: The Begin Program operation must take
place at 4.5 to 5.5 VDD range.
TABLE 2-2: COMMAND MAPPING FOR PIC16F87X
Command Mapping (MSB … LSB) Data Voltage
Range
Load Configuration XX00000, data (14), 0 2.2V - 5.5V
Load Data for Program Memory XX00100, data (14), 0 2.2V - 5.5V
Read Data from Program Memory XX01000, data (14), 0 2.2V - 5.5V
Increment Address XX0110 2.2V - 5.5V
Begin Erase Programming Cycle 001000 2.2V - 5.5V
Begin Programming Only Cycle 011000 4.5V - 5.5V
Load Data for Data Memory XX00110, data (14), 0 2.2 V - 5.5V
Read Data from Data Memory XX01010, da ta (14), 0 2.2V - 5.5 V
Bulk Erase Setup1 000001 4.5V - 5.5V
Bulk Erase Setup2 000111 4.5V - 5.5V
2002 Microchip Technology Inc. DS39025F-page 7
PIC16F87X
2.5 Erasing Program and Data
Memory
Depen ding on the stat e of the co de protect ion bit s, pro-
gram and data memory will be erased using different
procedures. The first set of procedures is used when
both program and data memories are not code pro-
tected. The second set of procedures must be used
when either memory is code protected. A device pro-
grammer should determine the state of the code pro-
tection bits and then apply the proper procedure to
erase the desired memory.
2.5.1 ERASING NON-CODE PROTECTED
PROGRAM AND DATA MEMORY
When both program and data memories are not code
protected, they must be individually erased using the
following procedures. The only way that bo th memories
are erased using a single procedure is if code protec-
tion is enabled for one of the memories. These proce-
dures do not erase the configuration word or ID
locations.
Procedure to bulk erase program memory:
1. Execute a Load Data for Program Memory com-
mand (000010) with a ’1’ in all locations
(0x3FFF)
2. Execute a Bulk Erase Setup1 command
(000001)
3. Execute a Bulk Erase Setup2 command
(000111)
4. Ex ecute a Begin Erase/ Programm ing comm and
(001000)
5. Wait 8 ms
6. Execute a Bulk Erase Setup1 command
(000001)
7. Execute a Bulk Erase Setup2 command
(000111)
Procedure to bulk erase data memory:
1. Execute a Load Data for Data Memory com-
mand (000011) with a ’1’ in all locations
(0x3FFF)
2. Execute a Bulk Erase Setup1 command
(000001)
3. Execute a Bulk Erase Setup2 command
(000111)
4. Ex ecute a Begin Erase/ Programm ing comm and
(001000)
5. Wait 8 ms
6. Execute a Bulk Erase Setup1 command
(000001)
7. Execute a Bulk Erase Setup2 command
(000111)
2.5.2 ERASING CODE PROTECTED
MEMORY
For the PIC16F87X devices, once code protection is
enabled, all protected program and data memory loca-
tions read all ’0’s and further programming is disabled.
The ID locations and configuration word read out
unscram bl ed and can be rep rogra mm ed norma ll y. The
only procedure to erase a PIC16F87X device that is
code protected is shown in the following procedure.
This method erases program memory, data memory,
configuration bits and ID locations. Since all data
within the program and dat a memory will be erase d
when this procedure is executed, the security of
the data or code is not compromised.
1. Execute a Load Configuration command
(000000) with a ’1’ in all locations (0x3FFF)
2. Execute Increment Address command
(000110) to set address to configuration word
location (0x2007)
3. Execute a Bulk Erase Setup1 command
(000001)
4. Execute a Bulk Erase Setup2 command
(000111)
5. Ex ecute a Begin Eras e/Progra mmin g comm and
(001000)
6. Wait 8 ms
7. Execute a Bulk Erase Setup1 command
(000001)
8. Execute a Bulk Erase Setup2 command
(000111)
PIC16F87X
DS39025F-page 8 2002 Microchip Technology Inc.
FIGURE 2-1: FLOW CHART - PIC16F87X PROGRAM MEMORY (2.2V ≤ VDD < 5.5V)
START
Set VDD = VDDP
Load Data
Wait
All Locations
Done?
Verify al l
Locations
Data Correct?
DONE
Increment
Address
Command
Report Verify
Error
No
No
Command
Begin
Erase/Programming
Command
tera + tprog
2002 Microchip Technology Inc. DS39025F-page 9
PIC16F87X
FIGURE 2-2: FLOW CHART – PIC16F87X PROGRAM MEMORY (4.5V ≤ VDD ≤ 5.5V)
START
Set VDD = VDDP
Load Data
Wait tprog
All Locations
Done?
DONE
Increment
Address
Command
No
Command
Begin
Programming Only
Command
Bulk Erase
Sequence
Verify all
Data Correct?
Locations
Increment
Address
Command
No
Report Verify
Error
PIC16F87X
DS39025F-page 10 2002 Microchip Technology Inc.
FIGUR E 2 - 3 : FLOW CHART – PIC16F87X CONFIGURATION MEMOR Y (2.2V ≤VDD <5.5V)
Program ID
START
Load
Configuration
Data
Location? Program Cycle Read Data
Command
Data Correct?
Report
Programming
Failure
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Program
Cycle
(Config. Word)
Read Data
Command
Data Correct?
Report Program
Configuration
Word Error
DONE
Yes
No
YesNo
No
Yes
Yes
No
Load Data
Command
Begin
Erase/Program
Command
Wait
Address =
0x2004?
PROGRAM CYCLE
tera + tprog
2002 Microchip Technology Inc. DS39025F-page 11
PIC16F87X
FIGURE 2-4: FLOW CHART - PIC16F87X CONFIGURATION MEMORY
Program ID
START
Load
Configuration
Data
Location? Program Cycle Read Data
Command
Data Correct?
Report
Programming
Failure
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Program
Cycle
(Config. Word)
Read Data
Command
Data Correct?
Report Program
Configuration
Word Error
DONE
Yes
No
YesNo
No
Yes
Yes
No
Load Data
Command
Begin
Program Only
Command*
Wa it tprog
Address =
0x2004?
PROGRAM CYCLE
* Assumes that a bulk erase was issued before programming configuration word. If not, use the program flow from Figure 2-4.
PIC16F87X
DS39025F-page 12 2002 Microchip Technology Inc.
3.0 CONFIGURATION WORD
The PIC16F87X has several configuration bits. These
bits can be set (reads ‘0’), or left unchanged (reads ‘1’),
to select various device configurations.
3.1 Device ID W ord
The device ID word for the PIC16F87X is located at
2006h.
TABLE 3-1: DEVICE ID VALUE
Device Device ID Value
Dev Rev
PIC16F870 00 1101 000 x xxxx
PIC16F871 00 1101 001 x xxxx
PIC16F872 00 1000 111 x xxxx
PIC16F873 00 1001 011 x xxxx
PIC16F874 00 1001 001 x xxxx
PIC16F876 00 1001 111 x xxxx
PIC16F877 00 1001 101 x xxxx
2002 Microchip Technology Inc. DS39025F-page 13
PIC16F87X
REGISTER 3-1: CONFIG: CONFIGURATION WORD FOR PIC16F873/874/876/877
(ADDRESS 2007h)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP1 CP0 RESV —WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0
bit 13 bit 0
bit 13-12
bit 5-4 CP1:CP0: FLASH Program Memory Code Protection bits(2)
4 K Devices:
11 = Code protection off
10 = 0F00h to 0FFFh code protected
01 = 0800h to 0FFFh code protected
00 = 0000h to 0FFFh code protected
8 K Devices:
11 = Code protection off
10 = 1F00h to 1FFFh code protected
01 = 1000h to 1FFFh code protected
00 = 0000h to 1FFFh code protected
bit 11 Reserved: Set to ‘1’ for normal operation
bit 10 Unimplemented: Read as ‘1’
bit 9 WRT: FLASH Program Memory Write Enable bit
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8 CPD: Data EE Memory Code Protection bit
1 = C ode protect ion off
0 = D ata EE memory code protect ed
bit 7 LVP: Low Voltage ICSP Programming Enable bit
1 = R B 3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6 BODEN: Brown-out Reset Enable bit(2)
1 = BOR enabled
0 = BO R disabled
bit 3 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = W DT enabled
0 = W DT disabled
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Rese t automatically enables Power-up Timer (PWRT), regardless of the value of
bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
PIC16F87X
DS39025F-page 14 2002 Microchip Technology Inc.
REGISTER 3-2: CONFIG: CONFIGURATION WORD FOR PIC16F870/871/872 (ADDRESS 2007h)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP1 CP0 RESV —WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0
bit 13 bit 0
bit 13-12
bit 5-4 CP1:CP0: FLASH Program Memory Code Protection bits(2)
11 = Code protection off
10 = Not supported
01 = Not supported
00 = 0000h to 07FFh code protected
bit 11 Reserved: Set to ‘1’ for normal operation
bit 10 Unimplemented: Read as ‘1’
bit 9 WRT: FLASH Program Memory Write Enable bit
1 = U nprotect ed program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8 CPD: Data EE Memory Code Protection bit
1 = C ode protect ion off
0 = D ata EE memory code protect ed
bit 7 LVP: Low Voltage ICSP Programming Enable bit
1 = R B 3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6 BODEN: Brown-out Reset Enable bit(2)
1 = BOR enabled
0 = BO R disabled
bit 3 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = W DT enabled
0 = W DT disabled
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: En abling Brown-out Rese t automatically enables Power-up Timer (PWRT), regardless of the value of
bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
2002 Microchip Technology Inc. DS39025F-page 15
PIC16F87X
4.0 EMBEDDING THE CONFIGURATION WO RD AND ID INFORMATION IN THE
HEX FILE
To allow port ability of code , the programm er is required to read the configur ation word and ID loc ations from the H EX
file whe n loading the H EX file. If conf iguration word i nformation was not present in the HEX fil e, then a simple warning
message may be issued. Similarly, while saving a HEX file, configuration word and ID information must be included.
An option to not include this information may be provided.
Specifically for the PIC16F87X, the EEPROM data memory should also be embedded in the HEX file (see
Section 2.2).
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
PIC16F87X
DS39025F-page 16 2002 Microchip Technology Inc.
5.0 CHECKSUM COMPUTATION
Checksum is calculated by reading the contents of the
PIC16F87X memory locations and adding up the
opcodes, up to the maximum user addressable loca-
tion, e.g., 0x1FF for the PIC16F87X. Any carry bits
exceed ing 16 -bit s are neg lecte d. Fina lly, the configu ra-
tion word (appropriately masked) is added to the
checksum. Chec ksum computation f or each member of
the PIC16F87X devi ces is shown in Table 5-1.
The checksum is calculated by summing the following:
•The contents of all program memory locations
•The configuration word, appropriately masked
•Masked ID locations (when applicable)
The Least Significant 16 bits of this sum are the
checksum.
The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
culation differs depending on the code protect setting.
Since the program memory locations read out differ-
ently depending on the code protect setting, the table
describ es how t o m ani pu late the ac tua l program mem-
ory values to simulate the values that would be read
from a p rotecte d dev ice. W hen c alculati ng a check sum
by reading a device, the entire program memory can
simply be read and summed. The configuration word
and ID locations can always be read.
Note that some older devices have an additional value
added in the checksum. This is to maintain compatibil-
ity with older device programmer checksums.
2002 Microchip Technology Inc. DS39025F-page 17
PIC16F87X
TABLE 5-1: CHECKSUM COMPUTATION
Device Code
Protect Checksum* Blank
Value
0x25E6 at 0
and max
address
PIC16F870 OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD
ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C
PIC16F871 OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD
ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C
PIC16F872 OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD
ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C
PIC16F873 OFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF 0x2BFF 0xF7CD
0x 0F00 : 0xFFF SUM[0x0000:0x0EFF ] + CFGW & 0x3BFF +S UM_ID 0x48E E 0xFAA3
0x0800 : 0xFFF SUM[0x0000:0x07FF] + CFGW & 0x3BFF + SUM_ID 0x3FDE 0xF193
ALL CFGW & 0x3BFF + SUM_ID 0x37CE 0x0 39C
PIC16F874 OFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF 0x2BFF 0xF7CD
0x 0F00 : 0xFFF SUM[0x0000:0x0EFF ] + CFGW & 0x3BFF +S UM_ID 0x48E E 0xFAA3
0x0800 : 0xFFF SUM[0x0000:0x07FF] + CFGW & 0x3BFF + SUM_ID 0x3FDE 0xF193
ALL CFGW & 0x3BFF + SUM_ID 0x37CE 0x0 39C
PIC16F876 OFF SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD
0x1F00 : 0x1FFF SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID 0x28EE 0xDAA3
0x1000 : 0x1FFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993
ALL CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C
PIC16F877 OFF SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD
0x1F00 : 0x1FFF SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID 0x28EE 0xDAA3
0x1000 : 0x1FFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993
ALL CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as th e most significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
PIC16F87X
DS39025F-page 18 2002 Microchip Technology Inc.
6.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating Temperature: 0°C ≤ TA ≤ +70°C
Operating Voltage: 2.2V ≤ VDD ≤ 5.5V
Characteristics Sym Min Typ Max Units Conditions/Comments
General
VDD level for Algorithm 1 VDD 2.2 5.5 VLimited command set
(See Table 2-2)
VDD level for Algorithm 2 VDD 4.5 5.5 VAll commands available
High voltage on MCLR for
high voltage programming entry VIHH VDD + 3.5 13.5 V
Voltage on MCLR for
low voltage IC S P programming entr y VIH 2.2 5.5 V
MCLR rise time (VSS to VHH) for Test
mode entry tVHHR 1.0 µs
(RB6, RB7) input high level VIH1 0.8 VDD V Schmitt Trigger input
(RB6, RB7) input low level VIL1 0.2 VDD V Schmitt Trigger input
RB<7:6> setup time before MCLR ↑ tset0 100 ns
RB<7:6> hold time after MCLR ↑ thld0 5 µs
RB3 setup time before MCLR ↑tset2 100 ns
Serial Program/Verify
Data in setup time before clock ↓tset1100 ns
Data in hold time after clock ↓thld1100 ns
Data input not driven to next clock input
(delay required between command/data or
command/command)
tdly11.0 µs
Delay between clock ↓ to clock ↑ of next
command or data tdly2 1.0 µs
Clock ↑ to data out valid (during read data) tdly3 80 ns
Erase cycle time tera 2 4 ms
Programming cycle time tprog 2 4 ms
2002 Microchip Technology Inc. DS39025F-page 19
PIC16F87X
FIGURE 6-1: LOAD DATA COMMAND MCLR = VIHH (PROGRAM/VERIFY)
FIGURE 6-2: READ DATA COMMAND MCLR = VIHH (PROGRAM/VERIFY)
FIGURE 6-3: INCREMENT ADDRESS COMMAND MCLR = VIHH (PROGRAM/VERIFY)
MCLR VIHH
tset0
RB6
(Clock)
RB7
(Data)
RESET
tset1
thld1
tdly1
1µs min.
Program/Verify Te st Mode
tset1
thld1
100 ns min.
1µs min .
tdly2
12 3 4 56
0100XX
12 3 4 5 15
16
strt_bit stp_bit
100 ns min.
}
thld0
}
}
}
MCLR VIHH
tset0
RB6
(Clock)
RB7
(Data)
RESET
tdly1
1µs min.
Program/Verify Test Mode
tset1
thld1
1µs min.
tdly2
12 3 4 56
0010XX
12 3 4 5 15
16
100 ns min.
}
}
tdly3
RB7 = input RB7 = output RB7
thld0
strt_bit stp_bit
input
MCLR VIHH
RB6
(Clock)
RB7
(Data)
RESET
tdly1
1µs min.
Program/Ver ify Test Mode
tset1
thld1
1µs min.
tdly2
12 3 4 56
011 XX
12
100 ns min.
}
}
X0
0
Next Command
PIC16F87X
DS39025F-page 20 2002 Microchip Technology Inc.
FIGURE 6-4: LOAD DATA COMMAND MCLR = VDD (PROGRAM/VERIFY)
FIGURE 6-5: READ DATA COMMAND MCLR = VDD (PROGRAM/VERIFY)
FIGURE 6-6: INCREMENT ADDRESS COMMAND MCLR = VDD (PROGRAM/VERIFY)
MCLR VIH
tset0
RB6
(Clock)
RB7
(Data)
RESET
tset1
thld1
tdly1
1µs min.
Program/Verify Te st Mode
tset1
thld1
100 ns min.
1µs min .
tdly2
12 3 4 56
0100XX
12 3 4 5 15
16
strt_bit stp_bit
100 ns min.
}
thld0
}
}
}
RB3
tset2
MCLR VIH
tset0
RB6
(Clock)
RB7
(Data)
RESET
tdly1
1µs min.
Program/Verify Test Mode
tset1
thld1
1µs min.
tdly2
12 3 4 56
0010XX
12 3 4 5 15
16
100 ns min.
}
}
tdly3
RB7 = input RB7 = output RB7
input
thld0
strt_bit stp_bit
RB3
tset2
MCLR VIH
RB6
(Clock)
RB7
(Data)
RESET
tdly1
1µs min.
Program/Ver ify Test Mode
tset1 thld1
1µs min.
tdly2
12 3 4 56
011 XX
12
100 ns min.
}
}
X0
0
Next Command
RB3
tset2
2002 Microchip Technology Inc. DS39025F - page 21
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Inc orporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or oth er intellectual property rights arising from such
use or otherwise. Use of Microchip’s product s as critical com-
ponents in lif e support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorpora ted in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro® MCUs.
•The PICmicro family meets the specifications contained in the Microchip Data Sheet.
•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside t he operating specifications contained in the data sheet .
The person doing so may be engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
DS39025F-page 22 2002 Microchip Technology Inc.
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