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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow rDS(on) ...7 Ω Typ
DAvalanche Energy . . . 30 mJ
DEight Power DMOS Transistor Outputs of
100-mA Continuous Current
D250-mA Current Limit Capability
DESD Protection . . . 2500 V
DOutput Clamp Voltage ...33 V
DEnhanced Cascading for Multiple Stages
DAll Registers Cleared With Single Input
DLow Power Consumption
description
The TPIC6C596 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include re l a y s, s o l e noids, and other low-current or
medium-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock
(RCK), respectively. The storage register trans-
fers data to the output buffer when shift register
clear (CLR) is high. When CLR i s l ow, all registers
in the device are cleared. When output enable (G)
is held high, all data in the output buffers is held
low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This will provide improved performance for applications where
clock signals may be skewed, devices are not located near one another, or the system must tolerate
electromagnetic interference.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
logic symbol†
2
SRG8
†This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
8
10
7
15
2
EN3
C2
R
C1
1D
G
RCK
CLR
SRCK
SER IN 3
5
4
11
6
13
12
9
14
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
G
GND
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
SER OUT
D, N, OR PW PACKAGE
(TOP VIEW)
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
Copyright 2000–2005, Texas Instruments Incorporated
SLIS093C − MARCH 2000 − REVISED APRIL 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous
sink-current capability. Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit
decreases as the junction temperature increases for additional device protection. The device also provides up
to 2500 V of ESD protection when tested using the human-body model and the 200-V machine model.
The TPIC6C596 is characterized for operation over the operating case temperature range of −40°C to 125°C.
logic diagram (positive logic)
G
RCK
CLR
SRCK
SER IN CLR
DC1 DC2
CLR
DC1
SER OUT
CLR
DC1
CLR
DC1
CLR
DC1
CLR
DC1
CLR
DC1
CLR
DC1
DC2
DC2
DC2
DC2
DC2
DC2
DC2
3DRAIN0
4DRAIN1
16 GND
5DRAIN2
6DRAIN3
11 DRAIN4
12 DRAIN5
13 DRAIN6
14 DRAIN7
8
7
2
10
15
9
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
DC1
SLIS093C − MARCH 2000 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
VCC
Input
GND GND
DRAIN
33 V
20 V
25 V
12 V
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)†
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, VI −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 33 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode anode current 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-to-drain diode anode current (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) 250 mA. . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, ID, TC = 25°C 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, IDM,TC = 25°C (see Note 3) 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, EAS (see Figure 4) 30 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, IAS (see Note 4) 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE TC ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TC = 25°CTC = 125°C
POWER RATING
D1087 mW 8.7 mW/°C217 mW
N1470 mW 11.7 mW/°C 294 mW
PW 1372 mW 10.976 mW/°C274 mW
SLIS093C − MARCH 2000 − REVISED APRIL 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, VCC 4.5 5.5 V
High-level input voltage, VIH 0.85 VCC V
Low-level input voltage, VIL 0.15 VCC V
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on (see Notes 3 and 5 and Figure 11) 250 mA
Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 15 ns
Hold time, SER IN high after SRCK↑, th (see Figure 2) 15 ns
Pulse duration, tw (see Figure 2) 40 ns
Operating case temperature, TC−40 125 °C
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ − TC to 10°C maximum.
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA 33 37 V
VSD Source-to-drain diode forward voltage IF = 100 mA 0.85 1.2 V
VOH
High-level output voltage, SER OUT
IOH = −20 µA, VCC = 4.5 V 4.4 4.49
V
VOH High-level output voltage, SER OUT IOH = −4 mA, VCC = 4.5 V 4 4.2 V
VOL
Low-level output voltage, SER OUT
IOL = 20 µA, VCC = 4.5 V 0.005 0.1
V
VOL Low-level output voltage, SER OUT IOL = 4 mA, VCC = 4.5 V 0.3 0.5 V
IIH High-level input current VCC = 5.5 V, VI = VCC 1µA
IIL Low-level input current VCC = 5.5 V, VI = 0 −1 µA
ICC
Logic supply current
VCC = 5.5 V
All outputs off 20 200
A
ICC Logic supply current VCC = 5.5 V All outputs on 150 500 µA
ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz,
All outputs off, CL = 30 pF,
See Figures 2 and 6 1.2 5 mA
INNominal current VDS(on) = 0.5 V,
TC = 85°C, IN = ID,
See Notes 5, 6 and 7 90 mA
VDS = 30 V, VCC = 5.5 V 0.1 0.2
IDSX Off-state drain current VDS = 30 V,
TC = 125°CVCC = 5.5 V, 0.15 0.3 µA
ID = 50 mA,
VCC = 4.5 V 6.5 9
rDS(on) Static drain-source on-state resistance ID = 50 mA,
TC = 125°C,
VCC = 4.5 V
See Notes 5 and 6
and Figures 7 and 8 9.9 12 Ω
ID = 100 mA,
VCC = 4.5 V 6.8 10
NOTES: 5. Technique should limit TJ − TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
SLIS093C − MARCH 2000 − REVISED APRIL 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output from G 80 ns
tPHL Propagation delay time, high-to-low-level output from G
CL = 30 pF, ID = 75 mA,
50 ns
trRise time, drain output
CL = 30 pF, ID = 75 mA,
See Figures 1, 2, and 9 100 ns
tfFall time, drain output
See Figures 1, 2, and 9
80 ns
tpd Propagation delay time, SRCK↓ to SEROUT CL = 30 pF, ID = 75 mA,
See Figure 2 15 ns
f(SRCK) Serial clock frequency CL = 30 pF, ID = 75 mA,
See Note 8 10 MHz
taReverse-recovery-current rise time
IF = 100 mA, di/dt = 10 A/µs,
100
ns
trr Reverse-recovery time
IF = 100 mA, di/dt = 10 A/µs,
See Notes 5 and 6 and Figure 3 120 ns
NOTES: 5. Technique should limit TJ − TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
D package 115
Rθ
JA
Thermal resistance, junction-to-ambient N package All 8 outputs with equal power 85 °C/W
RθJA
Thermal resistance, junction-to-ambient
PW package
All 8 outputs with equal power
108
C/W
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V
VCC
DRAIN
GND
CLR
SER IN
RL = 200 Ω
CL = 30 pF
(see Note B)
VOLTAGE WAVEFORMS
G
Output
SRCK
RCK
Word
Generator
(see Note A)
76543210 5 V
SRCK
5 V
G
5 V
SER IN
RCK
CLR
5 V
5 V
DUT
15 V
DRAIN1
15 V
0 V
0 V
0 V
0.5
V
0 V
16
7
15
2
10
8
0 V
3−6,
11−14
ID
1
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
SLIS093C − MARCH 2000 − REVISED APRIL 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3−6,
11−14
TEST CIRCUIT
5 V 15 V
VCC
DRAIN
CLR
SER IN
RL = 200 Ω
CL = 30 pF
(see Note B)
G
Output
SRCK
RCK
DUT
GND
Word
Generator
(see Note A)
16
7
15
2
10
8
ID
1
SWITCHING TIMES
G
5 V
50%
24 V
0.5 V
90%
10%
tPLH
tr
50%
90% 10%
tPHL
tf
SRCK
5 V
50%
SER IN 5 V
50% 50%
tsu th
tw
INPUT SETUP AND HOLD WAVEFORMS
Output
0 V
0 V
0 V
50% 50%
50%50%
tpd tpd
SRCK
SER OUT
SER OUT PROPAGATION DELAY WAVEFORM
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.1 A
IF
0
IRM
25% of IRM
ta
trr
di/dt = 10 A/µs
+
−
2500 µF
250 V
L = 0.85 mH
IF
(see Note A)
RG
VGG
(see Note B)
Driver
TP A
50 Ω
Circuit
Under
Test
DRAIN
15 V
t1t3
t2
TP K
TEST CIRCUIT CURRENT WAVEFORM
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 10 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
15 V
30 Ω
1.5 H
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
twtav
IAS = 200 mA
V(BR)DSX = 33 V
VOLTAGE AND CURRENT WAVEFORMS
Input
ID
VDS
See Note B
VCC
DRAIN
CLR
SER IN
G
SRCK
RCK
Word
Generator
(see Note A)
DUT
GND
5 V
VDS
ID
1
7
15
2
10
8
16
3−6,
11−14
5 V
0 V
MIN
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 200 mA.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
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8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
tav − Time Duration of Avalanche − ms
0.1 1 10
IAS − Peak Avalanche Current − A
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
0.01
0.1
1TC = 25°C
Figure 6
0
1
2
3
4
5
6
f − Frequency − MHz
VCC = 5 V
TC = −40C° to 125°C
ICC − Supply Current − mA
SUPPLY CURRENT
vs
FREQUENCY
0.1 1 10 100
Figure 7
ID − Drain Current − mA
0
5
10
15
20
25
30
50 70 90 110 130 150 170 190 210
VCC = 5 V
See Note A
r
DS(on)
− Drain-to-Source On-State Resistance −
Ω
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
250
TC = 25°C
TC = −40°C
TC = 125°C
Figure 8
VCC − Logic Supply Voltage − V
0
2
4
6
8
10
12
4.0 4.5 5.0 5.5 6.0 6.5 7.0
ID = 50 mA
See Note A
rDS(on) − Static Drain-to-Source On-State Resistance − Ω
STATIC
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
TC = 125°C
TC = 25°C
TC = − 40°C
NOTE A: Technique should limit TJ − TC to 10°C maximum.
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9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
TC − Case Temperature − °C
0
20
40
60
80
100
120
140
−50 −25 0 25 50 75 100 125
ID = 75 mA
See Note A
Switching Time − ns
SWITCHING TIME
vs
CASE TEMPERATURE
Figure 9
tPHL
tPLH
tf
tr
NOTE A: Technique should limit TJ − TC to 10°C maximum.
SLIS093C − MARCH 2000 − REVISED APRIL 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
Figure 10
N − Number of Outputs Conducting Simultaneously
0.00
0.05
0.10
0.15
0.20
0.25
12345678
I
D
− Maximum Continuous Drain Current of Each Output − A
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
VCC = 5 V
TC = 25°C
TC = 125°C
TC = 100°C
N − Number of Outputs Conducting Simultaneously
0.00
0.05
0.10
0.15
0.20
0.25
0.30
12345678
ID − Maximum Peak Drain Current of Each Output − A
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
VCC = 5 V
TC = 25°C
d = tw/tperiod
= 1 ms/tperiod
Figure 11
d = 10%
d = 20%
d = 50%
d = 80%
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11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
RθJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W
D PACKAGE†
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
DC Conditions
d = 0.5
d = 0.2
d = 0.1
d = 0.02
d = 0.05
d = 0.01
tw − Pulse Duration − s
tw
tc
ID
0
Single Pulse
†Device mounted on FR4 printed-circuit board with no heat sink
NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = t
w
/t
c
0.0001
0.0001
0.001
0.01
0.1
1
10
0.001 0.01 0.1 1 10
Figure 12
PACKAGE OPTION ADDENDUM
www.ti.com 26-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPIC6C596D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596DRQ1 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TPIC6C596PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6C596PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 26-May-2012
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPIC6C596DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPIC6C596DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPIC6C596DRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPIC6C596PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPIC6C596DR SOIC D 16 2500 367.0 367.0 38.0
TPIC6C596DR SOIC D 16 2500 367.0 367.0 38.0
TPIC6C596DRQ1 SOIC D 16 2500 367.0 367.0 38.0
TPIC6C596PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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