Document:1G5-0126 Rev.1 Page 1
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Description
The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated with an
advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only power
supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application.
A new refresh feature called “ self-refresh “ is supported and very slow CBR cycles are being performed. It is
packaged in JEDEC standard 26/24 - pin plastic SOJ or TSOP (II).
Features
• Single 5V (%) or 3.3V (%) only power supply
• High speed tRAC access time : 50/60 ns
• Low power dissipation
- Active mode : 5V version 605/550 mW (Max.)
3.3V version 396/360 mW (Max.)
- Standby mode : 5V version 1.375 mW (Max.)
3.3V version 0.54 mW (Max.)
• Fast Page Mode access
• I/O level : TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 2048 refresh cycles in 32 ms (Std) or 128ms (S - version)
• 4 refresh mode :
- RAS only refresh
- CAS-before-RAS refresh
- Hidden refresh
- Self - refresh (S - version)
10±
10±
Document:1G5-0126 Rev.1 Page 2
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Pin Description
Pin Name Function
A0 - A10 Address inputs
- Row address A0 - A10
- Column address A0 - A10
- Refresh address A0 - A10
DQ1 ~ DQ4 Data - in/data - out
RAS Row address strobe
CAS Column address strobe
WE Write enable
OE Output enable
Vcc Power (+ 5V or + 3.3V)
Vss Ground
VG26(v) (S)17400DJ
DQ1
WE
VSS
DQ4
A2
A3
V
CC
A0
A1
A10
VCC
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
CAS
OE
A9
26
25
24
23
22
21
8
9
10
11
12
13
19
18
17
16
15
14
RAS
DQ3
NC
DQ2
VG26(v) (S)17400DJ
DQ1
WE
VSS
DQ4
A2
A3
V
CC
A0
A1
A10
VCC
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
CAS
OE
A9
26
25
24
23
22
21
8
9
10
11
12
13
19
18
17
16
15
14
RAS
DQ3
NC
DQ2
Pin configuration
26/24 - PIN 300mil Plastic TSOP (II)
Pin configuration
26/24 - PIN 300mil Plastic SOP
Document:1G5-0126 Rev.1 Page 3
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
WE
GENERATOR
COLUMN-
ADDRESS
BUFFERS (11)
REFRESH
CONTROLLER
REFRESH
COUNTER
BUFFERS (11)
ADDRESS
ROW
NO. 1 CLOCK
GENERATOR
A0
RAS
A1
A2
A3
A4
A5
A6
A7
A8
CONTROL
LOGIC DATA - IN BUFFER
DATA - OUT
BUFFER OE
DQ1
DQ4
COLUMN
DECODER
2048
SENSE AMPLIFIERS
I/O GATING
2048 x 4
2048 x 2048 x 4
MEMORY
ARRAY
2048
ROW
DECODER
Vcc
Vss
Block Diagram
CAS
A9
A10
NO. 2 CLOCK
Document:1G5-0126 Rev.1 Page 4
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Truth Table
Notes : 1. EARLY WRITE only.
FUNCTION RAS CAS WE OE
ADDRESSES
DQSNotes
ROW COL
STANDBY HX X X X High - Z
READ L L HLROW COL Data - Out
WRITE : (EARLY
WRITE) L L L XROW COL Data - In
READ WRITE L L ROW COL Data - Out, Data - In
PAGE -
MODE READ 1st Cycle LHLROW COL Data - Out
2st
Cycle LHLn/a COL Data - Out
PAGE -
MODE WRITE 1st Cycle L L XROW COL Data - In
2st
Cycle L L Xn/a COL Data - In
PAGE - MODE
READ - WRITE 1st Cycle LROW COL Data - Out, Data - In
2st
Cycle Ln/a COL Data - Out, Data - In
HIDDEN
REFRESH READ LHLROW COL Data - Out
WRITE L L XROW COL Data - In 1
RAS - ONLY REFRESH LHX X ROW n/a High - Z
CBR REFRESH LHXXXHigh - Z
HX
→
HL
→
LH→
HL→
HL→
HL→
HL→
HL
→
HL
→
LH
→
HL
→
HL
→
LH
→
LHL→→
LHL→→
HL
→
Document:1G5-0126 Rev.1 Page 5
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Absolute Maximum Rating
Recommended DC Operating Conditions
Capacitance
Ta = 25°C, VCC = % or %, f = 1MHz
Note : 1. Capacitance measured with effective capacitance measuring method.
2. CAS = VIH to disable Dout.
Parameter Symbol Value Unit
Voltage on any pin relative to Vss 5V
3.3V VT-1.0 to + 7.0
-0.5 to + 4.6 V
Supply voltage relative to Vss 5V
3.3V Vcc -1.0 to + 7.0
-0.5 to + 4.6 V
Short circuit output current IOUT 50 mA
Power dissipation PD1.0 W
Operating temperature TOPT 0 to + 70 °C
Storage temperature TSTG -55 to + 125 °C
Parameter/Condition Symbol 5 Volt Version 3.3 Volt Version Unit
Min Typ Max Min Typ Max
Supply Voltage Vcc 4.5 5.0 5.5 3.0 3.3 3.6 V
Input High Voltage, all inputs VIH 2.4 -VCC + 1.02.0 -VCC + 0.3 V
Input Low Voltage, all inputs VIL -1.0 -0.8 -0.3 -0.8 V
Parameter Symbol Typ Max Unit Note
Input capacitance (Address) Cl1 -5pF 1
Input capacitance
(RAS, CAS, OE, WE)Cl2 -7pF 1
Output capacitance
(Data - in, Data - out) CI/O -7pF 1,2
5V10
±
3.3V10
±
Document:1G5-0126 Rev.1 Page 6
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics; 5 - Volt verion
(Ta= 0 to 70°C, VCC = + 5V10%, Vss = 0V)
Parameter Symbol Test Conditions
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
Operating
current ICC1
RAS cycling
CAS cycling
tRC = min. -110 -100 mA 1, 2
Standby
Current
Low
power
S - version
ICC2
TTL interface
RAS, CAS = VIH
Dout = high - Z
-2-2mA
CMOS interface - 0.2V
Dout = high - Z
-0.25 -0.25 mA
Standard
power
version
TTL interface
RAS, CAS = VIH
Dout = high - Z
-2-2mA
CMOS interface - 0.2V
Dout = high - Z
-1-1mA
RAS - only
refresh current ICC3 RAS cycling, CAS = VIH
tRC = min. -110 -100 mA 1, 2
Fast page mode
current ICC4 tPC = min. -80 -70 mA 1,3
CAS - before - RAS
refresh current ICC5 tRC = min.
RAS, CAS cycling -110 -100 mA 1, 2
Self - refresh currant
(S - Version) ICC8 -350 -350
CAS - before - RAS
long refresh
current (S - Version)
ICC9 Standby : VCC -
CAS before RAS refresh :
2048 cycles/128ms
RAS, RAS :
VCC - (Max)
Dout = high - Z,
-500 -500
±
RASCAS,V
CC
≥
RASCAS,V
CC
≥
t
RASS
100
µ
S
≥
µA
0.2V
RAS
≤
0VV
IL
0.2V
≤≤
0.2VV
IH
V
IH
≤≤
t
RAS
300ns
≤
µA
Document:1G5-0126 Rev.1 Page 7
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 5 - Volt Version (cont.)
(Ta = 0 to 70°C, VCC = + 5V10%, Vss = 0V)
Notes :
1. lCC is specified as an average current. It depends on output loading condition and cycle rate when
the device is selected. lCC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For lCC4, address can be changed once or less within one Fast page mode cycle time.
Parameter Symbol Test Conditions VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
lnput leakage
current ILI + 0.5V -5 5-5 5
Output leakage
current ILO + 0.5V
Dout = Disable -5 5-5 5
Output high
voltage VOH lOH = -5mA 2.4 -2.4 -V
Output low
voltage VOL lOL = + 4.2mA -0.4 -0.4 V
±
0VVinV
CC
≤≤
µA
0VVoutV
CC
≤≤
µA
Document:1G5-0126 Rev.1 Page 8
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Verion
(Ta = 0 to 70°C, VCC = + 3.3V10%, Vss = 0V)
Parameter Symbol Test Conditions VG26 (V) (S) 17400D Unit Notes
-5 -6
Min Max Min Max
Operating
current ICC1
RAS cycling
CAS cycling
tRC = min. -110 -100 mA 1, 2
Standby
Current
Low
power
S - version
ICC2
LVTTL interface
RAS, CAS = VIH
Dout = high - Z
-0.5 -0.5 mA
CMOS interface - 0.2V
Dout = high - Z
-0.25 -0.25 mA
Standard
power
version
LVTTL interface
RAS, CAS = VIH
Dout = high - Z
-2-2mA
CMOS interface - 0.2V
Dout = high - Z
-0.5 -0.5 mA
RAS - only
refresh current ICC3 RAS cycling, CAS = VIH
tRC = min. -110 -100 mA 1, 2
Fast page mode
current ICC4 tPC = min. -80 -70 mA 1,3
CAS - before - RAS
refresh current ICC5 tRC = min.
RAS, CAS cycling -110 -100 mA 1, 2
Self - refresh currant
(S - Version) ICC8 -250 -250
CAS - before - RAS
long refresh
current (S - Version)
ICC9 Standby : VCC -
CAS before RAS refresh :
2048 cycles/128ms
RAS, RAS :
VCC - (Max)
Dout = high - Z,
-300 -300
±
RASCAS,V
CC
≥
RASCAS,V
CC
≥
t
RASS
100
µ
S
≥
µA
0.2V
RAS
≤
0VV
IL
0.2V
≤≤
0.2VV
IH
V
IH
≤≤
t
RAS
300ns
≤
µA
Document:1G5-0126 Rev.1 Page 9
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version (cont.)
(Ta = 0 to 70°C, VCC = + 3.3V10%, VSS= 0V)
Notes :
1. lCC is specified as an average current. It depends on output loading condition and cycle rate when
the device is selected. lCC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For lCC4, address can be changed once or less within one Fast page mode cycle time.
Parameter Symbol Test Conditions VG26 (V) (S) 17400D Unit Notes
-5 -6
Min Max Min Max
Input leakage
current ILI + 0.3V -5 5-5 5
Output leakage
current ILO + 0.3V
Dout = Disable -5 5-5 5
Output high
voltage VOH lOH = -2mA 2.4 -2.4 -V
Output low
voltage VOL lOL = + 2mA -0.4 -0.4 V
±
0VVinV
CC
≤≤
µA
0VVoutV
CC
≤≤
µA
Document:1G5-0126 Rev.1 Page 10
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
AC Characteristics
(Ta = 0 to + 70°C, VCC = 5V10% or 3.3V10%, VSS = 0V) * 1, * 2, * 3, * 4
Test conditions
• Output load : two TTL Loads and 100pF(VCC = 5.0V10%)
one TTL Load and 100pF(VCC = 3.3V10%)
• Input timing reference levels :
VIH = 2.4V, VlL = 0.8V (VCC = 5.0V10%); VIH = 2.0V, VlL = 0.8V (VCC = 3.3V10%)
• Output timing reference levels :
VOH = 2.0V, VOL = 0.8V (VCC = 5V10%, 3.3V10%)
Read, Write, Read - Modify - Write and Refresh Cycles
(Common Parameters)
Parameter Symbol
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
Random read or write cycle time tRC 90 -110 -ns
RAS precharge time tRP 30 -40 -ns
CAS precharge time in normal mode tCPN 10 -10 -ns
RAS pulse width tRAS 50 10000 60 10000 ns 5
CAS pulse width tCAS 12 10000 15 10000 ns 6
Row address setup time tASR 0-0-ns
Row address hold time tRAH 8-10 -ns
Column address setup time tASC 0-0-ns 7
Column address hold time tCAH 8-10 -ns
RAS to CAS delay time tRCD 12 37 14 45 ns 8
RAS to column address delay time tRAD 10 25 12 30 ns 9
Column address to RAS lead time tRAL 25 -30 -ns
RAS hold time tRSH 13 -15 -ns
CAS hold time tCSH 50 -60 -ns
CAS to RAS precharge time tCRP 5-5-ns 10
OE to Din delay time tOED 12 -15 -ns
Transition time (rise and fall) tT1 50 1 50 ns 11
Refresh period tREF -32 -32 ms
Refresh period (S - Version) tREF -128 -128 ms
CAS to output in Low-Z tCLZ 0-0-ns
CAS delay time from Din tDZC 0-0-ns
OE delay time from Din tDZO 0-0-ns
±
±
±
±
±
±
±
±
Document:1G5-0126 Rev.1 Page 11
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Read Cycle
Write Cycle
Read - Modigy - Write Cycle
Parameter Symbol
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
Access time from RAS tRAC -50 -60 ns 12
Access time from CAS tCAC -13 -15 ns 13,14
Access time from column address tAA -25 -30 ns 14,15
Access time from OE tOEA -13 -15 ns
Read command setup time tRCS 0-0-ns 7
Read command hold time to CAS tRCH 0-0-ns 10,16
Read command hold time to RAS tRRH 0-0-ns 16
Output buffer turn-off time tOFF 0 13 0 15 ns 17
Output buffer turn-off time from OE tOEZ 0 13 0 15 ns 17
Parameter Symbol
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
Write command setup time tWCS 0-0-ns 7,18
Write command hold time tWCH 8-10 -ns
Write command pulse width tWP 8-10 -ns
Write command to RAS lead time tRWL 13 -15 -ns
Write command to CAS lead time tCWL 8-10 -ns
Data-in setup time tDS 0-0-ns 19
Data-in hold time tDH 8-10 -ns 19
Parameter Symbol
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
Read - modify - write cycle time tRWC 125 -150 -ns
RAS to WE delay time tRWD 65 -80 -ns 18
CAS to WE delay time tCWD 30 -35 -ns 18
Column address to WE delay time tAWD 40 -50 -ns 18
OE hold time from WE tOEH 8-10 -ns
Document:1G5-0126 Rev.1 Page 12
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Refresh Cycle
Fast Page Mode Cycle
Fast Page Mode Read Modify Write Cycle
Parameter Symbol
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
CAS setup time (CBR refresh) tCSR 10 -10 -ns
CAS hold time (CBR refresh) tCHR 10 -10 -ns 10
RAS precharge to CAS hold time tRPC 5-5-ns 7
RAS pulse width (self refresh) tRASS 100 -100 -
RAS precharge time (self refresh) tRPS 90 -110 -ns
CAS hold time (CBR self refresh) tCHS -50 --50 -ns
WE setup time tWSR 0-0-ns
WE hold time tWHR 10 -10 -ns
Parameter Symbol
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
Fast page mode cycle time tPC 35 -40 -ns
Fast page mode CAS Precharge time tCP 10 -10 -ns
Fast page mode RAS pulse width tRASP 50 10560 105ns 20
Access time from CAS precharge tCPA -30 -35 ns 10,14
RAS hold time from CAS precharge tCPRH 30 -35 -ns
Parameter Symbol
VG26 (V) (S) 17400D
Unit Notes
-5 -6
Min Max Min Max
Fast page mode read - modify - write cycle CAS
precharge to WE delay time tCPW 45 -55 - ns 11
Fast page mode read - modify - write cycle time tPRWC 70 -80 -ns
µs
Document:1G5-0126 Rev.1 Page 13
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Notes :
1. AC measurements assume tT = 5ns.
2. An initial pause of 100 is required after power up, and it followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is
used, a minimum of eight CAS-before-RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the VCC and VSS pins shall be supplied with the same voltage.
5. tRAS(min) = tRWD(min) + tRWL(min) + tT in read - modify-write cycle.
6. tCAS(min) = tCWD(min) + tCWL(min) + tT in read - modify-write cycle.
7. tASC(min), tRCS(min), tWCS(min) and tRPC are determined by the falling edge of CAS.
8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.
Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.
9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.
Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.
10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS.
11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between VIH and VIL.
12. Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
13. Assumes that tRCD tRCD(max) and tRAD tRAD(max).
14. Access time is determined by the maximum among tAA, tCAC, tCPA.
15. Assumes that tRCD tRCD(max) and tRAD tRAD(max).
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (
high impedance).
18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS tWCS(min), the cycle is an early write cycle and the
data output will remain open circuit (high impedance) throughout the entire cycle. If tRWD tRWD(min),
tCWD tCWD(min), tAWD tAWD(min), and tCPW tCPW(min), the cycle is a read-modify-write and the
data output will contain data read from the selected cell. If neither of the above sets of conditions is
satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS in an early write cycle and to WE edge in a delayed write or a
read-modify-write cycle.
20. tRASP defines RAS pulse width in Fast page mode cycles.
µs
≤
≤
≥
≤
≤
≥
≥
≥
≥
≥
≥
Document:1G5-0126 Rev.1 Page 14
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Timing Waveforms
• Read Cycle
tRC
tRAS tRP
tCRP
tCPN
tRRH
tRCH
tOEZ
tOFF
tOEA
tCAC
tAA
tRAC
tCLZ D
OUT
tRCS
tASR tRAH tASC tCAH
tRAD tRAL
tCAS
tRSH
tRCD
tT
tCSH
RAS
ADDRESS
DQ1 ~ DQ4
Note : = don’t care
Row Column
CAS
WE
OE
= Invalid Dout
Document:1G5-0126 Rev.1 Page 15
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
•Early Write Cycle
tRC
tRAS tRP
tWCH
tDS tDH
tWCS
tRAL
tCAS
tRSH
tRCD
tT
tCSH
RAS
CAS
WE
DQ1 ~ DQ4
tCRP
tASR tRAH tASC tCAH
ADDRESS Column
Row
tCPN
DIN
tRAD tRAL
Document:1G5-0126 Rev.1 Page 16
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Delayed Write Cycle
tRC
tRAS tRP
tRWL
tRCS
tCAS
tRSH
tRCD
tT
tCSH
RAS
CAS
tASR tRAH tCAH
ADDRESS Column
Row
tASC
DIN
DQ1 ~ DQ4
WE
tCRP
tCPN
tDH
tDS
tOEH
tOED
OE
tDS
OPEN
tWP
tCWL
Document:1G5-0126 Rev.1 Page 17
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Read - Modify - Write Cycle
tRWC
tRAS tRP
tRWD tWP
tRAD
tRWL
tCAS
tCWL
tRCD
tT
tCPN
RAS
CAS
WE
tCRP
tASR tRAH tASC tCAH
ADDRESS Column
Row
DQ1 ~ DQ4
tDH
tDS
OE
tRCS tAWD
tCWD
DIN
tOED tOEH
tOEZ
tOEA
tCAC
tRAC tAA
DQ1 ~ DQ4 DOUT
OPEN
tDZO
tDZC
Document:1G5-0126 Rev.1 Page 18
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Fast Page Mode Read Cycle
tRASP tCPRH
tRCS
tCAS
tRSH
tRCD
tOEA
tCSH
RAS
CAS
tASR tRAH tCAH
ADDRESS
tCAS
WE
tCRP tCP
OE
DQ1 ~ DQ4 OPEN
DOUT 1
tPC
tCP tCAS tCPN
tCRP
tRAD
tCAH
tASC tASC tCAH tASC
tRAL
Row Column 1
tRRH
tRCH
tRAC
tAA tAA tAA
tCPA tCPA tOEZ
tOFF
tCAC
tOEZ
tCAC
tCAC
tCLZ
DOUT N
WE
OE
Column 2 Column N Row
tRP
tOEA tOEA
tCLZ
tOEZ
tCLZ
DOUT 2
tOFF
tOFF
Document:1G5-0126 Rev.1 Page 19
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Fast Page Mode Early Write Cycle
tRASP tRP
tWCS
tCAS
tRSH
tRCD
RAS
CAS
tASR tRAH tCAH
ADDRESS
tCAS
WE
tCP
DQ1 ~ DQ4
tPC
tCP tCAS tCPN
tCRP
tCAH
tASC tASC tCAH tASC
Row Column 1
tDS
WE
Column 2 Column N
tWCH tWCS tWCH tWCS tWCH
tDH tDS tDH tDS tDH
DIN 1 DIN 2 DIN N
tTtCSH
Document:1G5-0126 Rev.1 Page 20
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Fast Page Mode Delayed Write Cycle
tRASP
tCPRH
tRCS
tCAS
tWP
RAS
CAS
tASR
tRAH tCAH
ADDRESS
tCAS
WE
tRCD tRSH
tCAS
tCRP
tRAD
tCAH
tASC tASC
tCAH
tASC
Row Column 1
tRWL
tRCS
tOED
WE
OE
tRP
tT
Column NColumn 2Column 1
tCWL
tRCS
tCWL tCWL
tOED tOED
tOEH tOEH tOEH
tDS
tDH
tWP
tDS
tDH
tWP
tDS
tDH
OPEN OPEN OPEN
DIN 1 DIN N
DIN 2
DQ1 ~ DQ4
tCP
tCP
tCSH tPC
tDZC
tDZO
tDZC
tDZO
tDZC
tDZO
Document:1G5-0126 Rev.1 Page 21
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Fast Page Mode Read - Modify - Write Cycle
tRASP
tCPRH
tRCS
tCAS
tWP
RAS
CAS
tASR
tRAH tCAH
ADDRESS
tCAS
WE
tRCD CP
DQ1 ~ DQ4
tPRWC
tCP tCAS
tCRP
tRAD
tCAH
tASC tASC
tCAH
tASC
Row Column 1
tRWL
tRCS
tOED tCPA
tCAC
WE
OE
tRP
DOUT 2 DOUT N
DOUT 1
tT
t
Column NColumn 2Column 1
tRWD
tAWD
tCWD
tCWL
tRCS
tCWD
tAWD
tCPW tCWL tCPW
tAWD
tCWD
tCWL
tOED tOED
tOEH tOEH tOEH
tCAC
tCAC
tAA
tRAC
tOEZ
tOEA
tAA
tCLZ tOEZ
tAA
tCLZ tOEZ
tDS
tDH
tWP
tDS
tDH
tWP
tDS
tDH
OPEN OPEN
DIN 1 DIN N
DIN 2
DQ1 ~ DQ4
tDZC tDZC
tOEA tOEA tCPA
tOEA
tCLZ
tDZC
tDZO tDZO
tDZO
Document:1G5-0126 Rev.1 Page 22
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
RAS - Only Refresh Cycle
RAS
ADDRESS
tRC
tCRP
tASR tRAH
tT
tRPC
Row
tOFF
CAS
tRAS tRP
OPEN
tCRP
DQ1 ~ DQ4
RAS
tCSR
tWSR
tRP
tTtRPC
tOFF
CAS
tRAS tRP
OPEN
tCRP
DQ1 ~ DQ4
tRPC
tCHR
tRAS tRP
tRC tRC
tCHR
tCSR
tWHR tWSR tWHR
WE
CAS - Before - RAS Refresh Cycle
Document:1G5-0126 Rev.1 Page 23
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
CBR Self - Refesh Cycle
RAS
WE
tRPC
tOFF
tCSR tCHS
tWSR
CAS
tRASS tRPS
OPEN
DQ1 - DQ4
tWHR
High lmpedance
Document:1G5-0126 Rev.1 Page 24
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Hidden Refresh Cycle
tRP
tRAS
RAS
tRCD
tCRP
ADDRESS
WE
tCHR
tCAS
tRSH
tRAH
tASR tASC tCAH
tRAL
Row
tRCH
tOEZ
CAS
DQ1 ~ DQ4
tT
t RCS
D
tRAS
tRAS tRP
tRP
tRC tRC tRC
tRAD
tRRH
tOFF
tOEA
tCAC
tAA
tRAC
Column
OUT
OE
(READ) (REFRESH) (REFRESH)
Document:1G5-0126 Rev.1 Page 25
VIS VG26(V)(S)17400D
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Ordering information
Part Number Access Time Package
VG26 (V) (S) 17400DJ - 5
VG26 (V) (S) 17400DJ - 6
50 ns
60 ns
300mil 26/24 - Pin
Plastic SOJ
• VG
• 26
• V
• S
• 17400
• D
• J
•5
• VIS Memory Product
• Technology
• 3.3V version
• Self refresh
• Device Type and Configuration
• Revision
• Package Type (J : SOJ , T : TSOJ II)
• Speed (5 : 50 ns, 6 : 60 ns)
VG26 (V) (S) 17400DJ - 5
Packaging informationPackaging information
• 300 mil, 26/24-Pin Plastic SOJ
SEATING PLANE
4-e
e
b
b2
0.007"M
C
L
0.025" MIN.
0.004"
SECTION B-B
E2
A
RAD R1
A1 B
B
D
26 21
E
E1
19 14
BASE METAL
WITH PLATING
c1 c
b1
b
0.267 BASIC
0.335 BASIC
0.050 BASIC
R1
e
E1
E2 6.78 BASIC
1.27 BASIC
0.76 ---
7.49 7.62
1.02 0.030
7.75 0.295
17.02
b
D
E
c1
b2
c
b1
A1
A
DIM
0.510.41 0.016
8.51 BASIC
0.18
17.15
---
0.66
0.18
0.41 ---
---
0.46
17.27
0.28
0.670
0.007
0.81
0.30
0.48
0.007
0.026
0.016
MILLIMETERS
MIN. NOM.
2.08
3.25 ---
---
3.51
MAX. MIN.
---
3.76 0.082
0.128
0.305
0.040---
0.300
0.020
0.032
0.019
0.012
0.680
0.011
0.675
---
0.018
---
---
MAX.
0.148
---
NOM.
---
0.138
---
INCHES
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE.
1. CONTROLLING DIMENSION : INCHES
NOTE:
3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR
TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN.
DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH
SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm)
INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE
1 6 8 13
A2
A2 2.54 REF. 0.100 REF.
