LTC2637IMS-LZ12#TRPBF - Linear Technology Corporation

LTC2637

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Octal 12-/10-/8-Bit I2C VOUT

DACs with 10ppm/°C Reference

FEATURES

APPLICATIONS

DESCRIPTION

The LTC

2637 is a family of octal 12-, 10-, and 8-bit

voltage-output DACs with an integrated, high-accuracy,

low-drift 10ppm/°C reference in 14-lead DFN and 16-lead

MSOP packages. It has a rail-to-rail output buffer and is

guaranteed monotonic. The LTC2637-L has a full-scale

output of 2.5V, and operates from a single 2.7V to 5.5V

supply. The LTC2637-H has a full-scale output of 4.096V,

and operates from a 4.5V to 5.5V supply. Each DAC can

also operate with an external reference, which sets the DAC

full-scale output to the external reference voltage.

These DACs communicate via a 2-wire I2C-compatible

serial interface. The LTC2637 operates in both the standard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz). The LTC2637 incorporates a power-on reset

circuit. Options are available for reset to zero-scale or

reset to mid-scale in internal reference mode, or reset to

mid-scale in external reference mode after power-up.

n Integrated Precision Reference:

2.5V Full-Scale 10ppm/°C (LTC2637-L)

4.096V Full-Scale 10ppm/°C (LTC2637-H)

n Maximum INL Error: 2.5LSB (LTC2637-12)

n Low Noise: 0.75mVP-P 0.1Hz to 200KHz

n Guaranteed Monotonic Over –40°C to 125°C

Temperature Range

n Selectable Internal or External Reference

n 2.7V to 5.5V Supply Range (LTC2637-L)

n Ultralow Crosstalk Between DACs (<3nV•s)

n Low Power: 100µA per DAC at 3V (LTC2637-L)

n Power-On-Reset to Zero-Scale/Mid-Scale

n Double-Buffered Data Latches

n Tiny 14-Lead 4mm × 3mm DFN and 16-Lead MSOP

Packages

n Mobile Communications

n Process Control and Industrial Automation

n Automatic Test Equipment

n Portable Equipment

n Automotive

n Optical Networking

BLOCK DIAGRAM

Integral Nonlinearity (LTC2637-LZ12)

2637 BD

GND

VOUTA

VOUTB

VOUTC

VOUTD

CAO

(CA1)

(CA2)

REF

VCC

VOUTH

VOUTG

VOUTF

VOUTE

SCL

INTERNAL REFERENCE SWITCH

DAC A

DECODE

POWER-ON RESET

VREF

DAC B

DAC C

DAC D

DAC H

DAC G

DAC F

DAC E

I2C

ADDRESS

DECODE

( ) MSOP PACKAGE ONLY

REGISTERREGISTERREGISTER

REGISTERREGISTERREGISTERREGISTER

SDA

I2C INTERFACE

CODE

INL (LSB)

–1

–2 1024 3072

2637 TA01

40952048

VCC = 3V

INTERNAL REF.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433,

6937178, 7414561.

LTC2637

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ABSOLUTE MAXIMUM RATINGS

GND

VOUTH

VOUTG

VOUTF

VOUTE

REF

SDA

VCC

VOUTA

VOUTB

VOUTC

VOUTD

CA0

SCL

TOP VIEW

DE PACKAGE

14-LEAD (4mm s 3mm) PLASTIC DFN

TJMAX = 150°C, θJA = 37°C/W

EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB

VCC

VOUTA

VOUTB

VOUTC

VOUTD

CA2

CA0

SCL

GND

VOUTH

VOUTG

VOUTF

VOUTE

REF

CA1

SDA

TOP VIEW

MS PACKAGE

16-LEAD (4mm s 5mm) PLASTIC MSOP

TJMAX = 150°C, θJA = 110°C/W

PIN CONFIGURATION

Supply Voltage (VCC) ................................... –0.3V to 6V

SCL, SDA ..................................................... –0.3V to 6V

VOUTA - VOUTH,

CA0, CA1, CA2 ...................–0.3V to Min(VCC + 0.3V, 6V)

REF ...................................–0.3V to Min(VCC + 0.3V, 6V)

Operating Temperature Range

LTC2637C ................................................ 0°C to 70°C

(Notes 1, 2)

LTC2637I .............................................–40°C to 85°C

LTC2637H (Note 3) ............................ –40°C to 125°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MS Package ......................................................300°C

LTC2637

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ORDER INFORMATION

LTC2637 C DE –L Z 12 #TR PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = 2500-Piece Tape and Reel

RESOLUTION

12 = 12-Bit

10 = 10-Bit

8 = 8-Bit

POWER-ON RESET

MI = Reset to Mid-Scale in Internal Reference Mode

MX = Reset to Mid-Scale in External Reference Mode

Z = Reset to Zero-Scale in Internal Reference Mode

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

DE = 14-Lead DFN

MS = 16-Lead MSOP

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC2637

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PART NUMBER

PART MARKING*VFS WITH INTERNAL

REFERENCE

POWER-ON

RESET TO CODE

POWER-ON

REFERENCE

MODE RESOLUTION VCC

MAXIMUM

INL

DFN MSOP

LTC2637-LMI12

LTC2637-LMI10

LTC2637-LMI8

7LMI2

7LMI1

7LMI8

7LMI12

7LMI10

37LMI8

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

Internal

12-Bit

10-Bit

8-Bit

2.7V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2637-LMX12

LTC2637-LMX10

LTC2637-LMX8

7LMX2

7LMX1

7LMX8

7LMX12

7LMX10

37LMX8

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

External

12-Bit

10-Bit

8-Bit

2.7V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2637-LZ12

LTC2637-LZ10

LTC2637-LZ8

7LZ12

7LZ10

37LZ8

37LZ12

37LZ10

637LZ8

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Zero-Scale

Internal

12-Bit

10-Bit

8-Bit

2.7V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2637-HMI12

LTC2637-HMI10

LTC2637-HMI8

7HMI2

7HMI1

7HMI8

7HMI12

7HMI10

37HMI8

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

Internal

12-Bit

10-Bit

8-Bit

4.5V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2637-HMX12

LTC2637-HMX10

LTC2637-HMX8

7HMX2

7HMX1

7HMX8

7HMX12

7HMX10

37HMX8

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

External

12-Bit

10-Bit

8-Bit

4.5V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2637-HZ12

LTC2637-HZ10

LTC2637-HZ8

7HZ12

7HZ10

37HZ8

37HZ12

37HZ10

637HZ8

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Zero-Scale

Internal

12-Bit

10-Bit

8-Bit

4.5V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

*Above options are available in a 14-lead DFN package (LTC2637xDE) or 16-lead MSOP package (LTC2637xMS).

PRODUCT SELECTION GUIDE

LTC2637

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ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span External Reference

Internal Reference

0 to VREF

0 to 2.5

PSR Power Supply Rejection VCC = 3V±10% or 5V±10% –80 dB

ISC Short Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero-Scale; VOUT shorted to VCC

Full-Scale; VOUT shorted to GND

–28

–48

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l2.7 5.5 V

ICC Supply Current (Note 7) VCC = 3V, VREF =2.5V, External Reference

VCC = 3V, Internal Reference

VCC = 5V, VREF =2.5V, External Reference

VCC = 5V, Internal Reference

0.8

0.9

1.1

1.3

1.5

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V, C-Grade, I-Grade

VCC = 5V, H-Grade

µA

LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/

LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS

LTC2637-8 LTC2637-10 LTC2637-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Resolution l8 10 12 Bits

Monotonicity VCC = 3V, Internal Reference (Note 4) l8 10 12 Bits

DNL Differential Nonlinearity VCC = 3V, Internal Reference (Note 4) l±0.5 ±0.5 ±1 LSB

INL Integral Nonlinearity VCC = 3V, Internal Reference (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB

ZSE Zero-Scale Error VCC = 3V, Internal Reference, Code = 0 l0.5 5 0.5 5 0.5 5 mV

VOS Offset Error VCC = 3V, Internal Reference (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefﬁ cient

VCC=3V, Internal Reference ±10 ±10 ±10 µV/°C

GE Gain Error VCC = 3V, Internal Reference l±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR

GETC Gain Temperature

Coefﬁ cient

VCC = 3V, Internal Reference (Note 10)

C-Grade

I-Grade

H-Grade

ppm/°C

Load Regulation Internal Reference, Mid-Scale,

VCC = 3V±10%,

–5mA ≤ IOUT ≤ 5mA

VCC = 5V±10%, (Note 15)

–10mA ≤ IOUT ≤ 10mA

0.009

0.016

0.035

0.064

0.14

0.256

LSB/mA

ROUT DC Output Impedance Internal Reference, Mid-Scale,

VCC = 3V±10%,

–5mA ≤ IOUT ≤ 5mA

VCC = 5V±10%, (Note 15)

–10mA ≤ IOUT ≤ 10mA

0.09

0.156

0.09

0.156

0.09

0.156



LTC2637

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ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/

LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Input

Input Voltage Range l1V

CC V

Resistance l120 160 200 k

Capacitance 12 pF

IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 1.5 µA

Reference Output

Output Voltage l1.24 1.25 1.26 V

Reference Temperature Coefﬁ cient ±10 ppm/°C

Output Impedance 0.5 k

Capacitive Load Driving 10 µF

Short Circuit Current VCC = 5.5V; REF Shorted to GND 2.5 mA

Digital I/O

VIL Low Level Input Voltage (SDA and SCL) (Note 14) l–0.5 0.3VCC V

VIH High Level Input Voltage (SDA and SCL) (Note 11) l0.7VCC V

VIL(CAn)Low Level Input Voltage on CAn

(n = 0, 1, 2)

See Test Circuit 1 l0.15VCC V

VIH(CAn)High Level Input Voltage on CAn

(n = 0, 1, 2)

See Test Circuit 1 l0.85VCC V

RINH Resistance from CAn (n=0, 1,2)

to VCC to Set CAn = VCC

See Test Circuit 2 l10 k

RINL Resistance from CAn (n=0, 1,2)

to GND to Set CAn = GND

See Test Circuit 2 l10 k

RINF Resistance from CAn (n=0, 1,2)

to VCC or GND to Set CAn = Float

See Test Circuit 2 l2M

VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 12)

20 + 0.1CB

250 ns

tSP Pulse Width of Spikes Suppressed

by Input Filter

l050ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l±1 µA

CIN I/O Pin Capacitance (Note 8) l10 pF

CBCapacitive Load for Each Bus Line l400 pF

CCAnExternal Capacitive Load on Address

Pin CAn (n=0, 1,2)

l10 pF

LTC2637

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LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/

LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Performance

tSSettling Time VCC = 3V (Note 9)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

3.5

4.1

4.5

µs

Voltage Output Slew Rate 1.0 V/µs

Capacitive Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 2.1 nV•s

DAC-to-DAC Crosstalk 1 DAC held at FS, 1 DAC Switched 0 to FS 2.6 nV•s

Multiplying Bandwidth External Reference 320 kHz

enOutput Voltage Noise Density At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

200

180

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

680

730

µVP-P

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/

LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSCL SCL Clock Frequency l0 400 kHz

tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs

tLOW Low Period of the SCL Clock Pin l1.3 µs

tHIGH High Period of the SCL Clock Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated Start Condition l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time of Both SDA and SCL Signals (Note 12) l

20 + 0.1CB

300 ns

tfFall Time of Both SDA and SCL Signals (Note 12) l

20 + 0.1CB

300 ns

tSU(STO) Set-Up Time for Stop Condition l0.6 µs

tBUF Bus Free Time Between a Stop and Start Condition l1.3 µs

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13)

LTC2637

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ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/

LTC2637-HZ10/ LTC2637-HZ8 (VFS =4.096V)

SYMBOL PARAMETER CONDITIONS

LTC2637-8 LTC2637-10 LTC2637-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Resolution l8 10 12 Bits

Monotonicity VCC = 5V, Internal Reference (Note 4) l8 10 12 Bits

DNL Differential

Nonlinearity

VCC = 5V, Internal Reference (Note 4) l±0.5 ±0.5 ±1 LSB

INL Integral Nonlinearity VCC = 5V, Internal Reference (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB

ZSE Zero-Scale Error VCC = 5V, Internal Reference, Code = 0 l0.5 5 0.5 5 0.5 5 mV

VOS Offset Error VCC = 5V, Internal Reference (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefﬁ cient

VCC = 5V, Internal Reference ±10 ±10 ±10 µV/°C

GE Gain Error VCC = 5V, Internal Reference l±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR

GETC Gain Temperature

Coefﬁ cient

VCC = 5V, Internal Reference (Note 10)

C-Grade

I-Grade

H-Grade

ppm/°C

Load

Regulation

VCC = 5V±10%, (Note 15)

Internal Reference, Mid-Scale,

–10mA ≤ IOUT ≤ 10mA

l0.006 0.01 0.022 0.04 0.09 0.16 LSB/mA

ROUT DC Output

Impedance

VCC = 5V±10%, (Note 15)

Internal Reference, Mid-Scale,

–10mA ≤ IOUT ≤ 10mA

l0.09 0.156 0.09 0.156 0.09 0.156 

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span External Reference

Internal Reference

0 to VREF

0 to 4.096

PSR Power Supply Rejection VCC = 5V±10% –80 dB

ISC Short Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero-Scale; VOUT Shorted to VCC

Full-Scale; VOUT Shorted to GND

–28

–48

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l4.5 5.5 V

ICC Supply Current (Note 7) VCC = 5V, VREF = 4.096V, External Reference

VCC = 5V, Internal Reference

1.0

1.1

1.3

1.5

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V, C-Grade, I-Grade

VCC = 5V, H-Grade

µA

Reference Input

Input Voltage Range l1V

CC V

Resistance l120 160 200 k

Capacitance 12 pF

IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 1.5 µA

Reference Output

Output Voltage l2.032 2.048 2.064 V

Reference Temperature Coefﬁ cient ±10 ppm/°C

LTC2637

2637fb

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/

LTC2637-HZ8 (VFS =4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Impedance 0.5 k

Capacitive Load Driving 10 µF

Short Circuit Current VCC = 5.5V; REF Shorted to GND 4 mA

Digital I/O

VIL Low Level Input Voltage (SDA and SCL) (Note 14) l–0.5 0.3VCC V

VIH High Level Input Voltage (SDA and SCL) (Note 11) l0.7VCC V

VIL(CAn)Low Level Input Voltage on CAn

(n = 0, 1, 2)

See Test Circuit 1 l0.15VCC V

VIH(CAn)High Level Input Voltage on CAn

(n = 0, 1, 2)

See Test Circuit 1 l0.85VCC V

RINH Resistance from CAn (n=0, 1,2)

to VCC to Set CAn = VCC

See Test Circuit 2 l10 k

RINL Resistance from CAn (n=0, 1,2)

to GND to Set CAn = GND

See Test Circuit 2 l10 k

RINF Resistance from CAn (n=0, 1,2)

to VCC or GND to Set CAn = Float

See Test Circuit 2 l2M

VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 12)

20 + 0.1CB

250 ns

tSP Pulse Width of Spikes Suppressed

by Input Filter

l050ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l±1 µA

CIN I/O Pin Capacitance (Note 8) l10 pF

CBCapacitive Load for Each Bus Line l400 pF

CCAnExternal Capacitive Load on Address

Pin CAn (n=0, 1,2)

l10 pF

AC Performance

tSSettling Time VCC = 3V (Note 9)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

3.9

4.3

µs

Voltage Output Slew Rate 1 V/µs

Capacitive Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 3 nV•s

DAC-to-DAC Crosstalk 1 DAC held at FS, 1 DAC Switched 0 to FS 3 nV•s

Multiplying Bandwidth External Reference 320 kHz

enOutput Voltage Noise Density At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

250

230

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

680

750

µVP-P

LTC2637

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages are with respect to GND.

Note 3: High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C. Operating at temperatures

above 110°C and with VCC > 4V requires VCC slew rates to be no greater

than 110mV/ms.

Note 4: Linearity and monotonicity are deﬁ ned from code kL to code 2N–1,

where N is the resolution and kL is given by kL = 0.016•(2N/ VFS), rounded

to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity

is deﬁ ned from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL =

16 and linearity is deﬁ ned from code 16 to code 4,095.

Note 5: Inferred from measurement at code 16 (LTC2637-12), code 4

(LTC2637-10) or code 1 (LTC2637-8), and at full-scale.

Note 6: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the speciﬁ ed maximum operating junction temperature may impair

device reliability.

Note 7: Digital inputs at 0V or VCC.

Note 8: Guaranteed by design and not production tested.

Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND.

Note 10: Temperature coefﬁ cient is calculated by dividing the maximum

change in output voltage by the speciﬁ ed temperature range.

Note 11: Maximum VIH = VCC(MAX) + 0.5V.

Note 12: CB = Capacitance of one bus line in pF.

Note 13: All values refer to VIH = VIN(MIN) and VIL = VIL(MAX) levels.

Note 14: Minimum VIL exceeds Absolute Maximum rating. This condition

won’t damage the IC, but could degrade performance.

Note 15: Thermal resistance of MSOP package limits IOUT to

–5mA ≤ IOUT ≤ 5mA for H-grade MSOP parts and VCC = 5V ±10%.

LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/

LTC2637-HZ8 (VFS =4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSCL SCL Clock Frequency l0 400 kHz

tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs

tLOW Low Period of the SCL Clock Pin l1.3 µs

tHIGH High Period of the SCL Clock Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated Start Condition l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns

tfFall Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns

tSU(STO) Set-Up Time for Stop Condition l0.6 µs

tBUF Bus Free Time Between a Stop and Start Condition l1.3 µs

TIMING CHARACTERISTICS

The l denotes speciﬁ cations that apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. VCC =4.5V to 5.5V. (See Figure 1) (Note 13).

LTC2637

2637fb

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

INL vs Temperature DNL vs Temperature

Reference Output Voltage

vs Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

TA = 25°C, unless otherwise noted. LTC2637-L12 (Internal Reference, VFS = 2.5V)

CODE

INL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2637 G01

40952048

VCC = 3V

CODE

DNL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2637 G02

40952048

VCC = 3V

TEMPERATURE (°C)

–50

INL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2637 G03

1500

VCC = 3V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50

DNL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2637 G04

1500

VCC = 3V

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

–50

VREF (V)

1.260

1.255

1.250

1.245

1.240 –25 125100755025

2637 G05

1500

VCC = 3V

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV 2637 G06

9TH CLOCK OF

3RD DATA BYTE

1/4 SCALE TO

3/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

3.6µs

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV 2637 G07

9TH CLOCK OF

3RD DATA BYTE

3/4 SCALE TO

1/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

4.5µs

LTC2637

2637fb

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

INL vs Temperature DNL vs Temperature

Reference Output Voltage

vs Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

TA = 25°C, unless otherwise noted. LTC2637-H12 (Internal Reference, VFS = 4.096V)

CODE

INL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2637 G08

40952048

VCC = 5V

CODE

DNL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2637 G09

40952048

VCC = 5V

TEMPERATURE (°C)

–50

INL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2637 G10

1500

VCC = 5V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50

DNL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2637 G11

1500

VCC = 5V

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

–50

VREF (V)

2.068

2.058

2.048

2.038

2.028 –25 125100755025

2637 G12

1500

VCC = 5V

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV 2637 G13

9TH CLOCK OF

3RD DATA BYTE

1/4 SCALE TO

3/4 SCALE STEP

VCC = 5V, VFS = 4.095V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

4.1µs

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV 2637 G14

9TH CLOCK OF

3RD DATA BYTE

3/4 SCALE TO

1/4 SCALE STEP

VCC = 5V, VFS = 4.095V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

5µs

LTC2637

2637fb

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

Load Regulation Current Limiting Offset Error vs Temperature

LTC2637-10

LTC2637-8

LTC2637

TA = 25°C, unless otherwise noted.

CODE

INL (LSB)

1.0

0.5

–0.5

–1.0 256 768

2637 G15

1023512

VCC = 3V

VFS = 2.5V

INTERNAL REF.

CODE

DNL (LSB)

1.0

0.5

–0.5

–1.0 256 768

2637 G16

1023512

VCC = 3V

VFS = 2.5V

INTERNAL REF.

CODE

INL (LSB)

0.50

0.25

–0.25

–0.50 64 192

2637 G17

255128

VCC = 3V

VFS = 2.5V

INTERNAL REF.

CODE

DNL (LSB)

0.50

0.25

–0.25

–0.50 64 192

2637 G18

255128

VCC = 3V

VFS = 2.5V

INTERNAL REF.

IOUT (mA)

–30

$VOUT (mV)

–6

–4

–2

–8

–10 –20 20100

2637 G19

30–10

VCC = 5V (LTC2637-H)

VCC = 5V (LTC2637-L)

VCC = 3V (LTC2637-L)

INTERNAL REF.

CODE = MID-SCALE

IOUT (mA)

–30

$VOUT (V)

0.20

0.15

0.10

0.05

–0.15

–0.01

–0.05

–0.20 –20 20100

2637 G20

30–10

VCC = 5V (LTC2637-H)

VCC = 5V (LTC2637-L)

VCC = 3V (LTC2637-L)

INTERNAL REF.

CODE = MID-SCALE

TEMPERATURE (°C)

–50

OFFSET ERROR (mV)

–1

–2

–3 –25 125100755025

2637 G21

1500

LTC2637

2637fb

TYPICAL PERFORMANCE CHARACTERISTICS

Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch

Headroom at Rails

vs Output Current Exiting Power-Down to Mid-Scale Power-On Reset to Mid-Scale

Supply Current vs Logic Voltage DAC to DAC Crosstalk (Dynamic) Multiplying Bandwidth

LTC2637

TA = 25°C, unless otherwise noted.

2µs/DIV

VOUT

0.5V/DIV

2637 G22

VFS = VCC = 5V

1/4 SCALE to 3/4 SCALE

SCL

5V/DIV

VOUT

5mV/DIV

2µs/DIV 2637 G23

9TH CLOCK OF

3RD DATA BYTE

LTC2637-H12

VCC = 5V, 3nV•s TYP

LTC2637-L12

VCC = 3V, 2.1nV•s TYP

200µs/DIV

VOUT

5mV/DIV

VCC

2V/DIV

2637 G24

LTC2637-L

ZERO-SCALE

IOUT (mA)

VOUT (V)

5.0

4.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.5

017896543

2637 G25

102

5V SOURCING

3V (LTC2637-L) SOURCING

5V SINKING

3V (LTC2637-L) SINKING

SCL

5V/DIV

VOUT

0.5V/DIV

5µs/DIV 2637 G26

9TH CLOCK OF

3RD DATA BYTE

DACs A TO G IN

POWER-DOWN

MODE

LTC2637H

VCC = 5V

INTERNAL REF

LOGIC VOLTAGE (V)

ICC (mA)

1.8

1.6

1.2

1.4

1.0

0.8

0.6 4321

2637 G28

SWEEP SDA, SCL,

BETWEEN 0V AND VCC

VCC = 5V

VCC = 3V

(LTC2637-L)

SCL

5V/DIV

VOUT

2mV/DIV

1 DAC

SWITCH 0 TO FS

2V/DIV

2µs/DIV 2637 G29

9TH CLOCK OF

3RD DATA BYTE

LTC2637-H12

VCC = 5V, 3nV•s TYP

CREF = 0.1µF

200µs/DIV

VCC

2V/DIV

VOUT

0.5V/DIV

2637 G27

LTC2637-H

LTC2637-L

FREQUENCY (Hz)

2637 G30

–16

–14

–12

–10

–8

–6

–4

–2

–181k 100k 1M10k

VCC = 5V

VREF(DC) = 2V

VREF(AC) = 0.2VP-P

CODE = FULL-SCALE

LTC2637

2637fb

TYPICAL PERFORMANCE CHARACTERISTICS

Gain Error vs Reference Input 0.1Hz to 10Hz Voltage Noise

TA = 25°C, unless otherwise noted.

REFERENCE VOLTAGE (V)

GAIN ERROR (%FSR)

1.0

0.8

0.6

0.4

–0.6

–0.8

–0.4

–0.2

0.2

–1.0 1.5 54.54

2637 G34

5.52 2.5 3 3.5

VCC = 5.5V

GAIN ERROR OF 8 CHANNELS

1s/DIV

10µV/DIV

2637 G35

VCC = 5V, VFS = 2.5V

CODE = MID-SCALE

INTERNAL REF.

Gain Error vs. Temperature Noise Voltage vs. Frequency

LTC2637

TEMPERATURE (°C)

–50

GAIN ERROR (%FSR)

1.0

0.5

–0.5

–1.0 –25 125100755025

2637 G31

1500

FREQUENCY (Hz)

100

NOISE VOLTAGE (nV/√Hz)

500

400

300

200

100

01k 100k

2637 G32

1M10k

VCC = 5V

CODE = MID-SCALE

INTERNAL REF.

LTC2637-H

LTC2637-L

LTC2637

2637fb

PIN FUNCTIONS

VCC (Pin 1/Pin 1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V

(LTC2637-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2637-H). Bypass

to GND with a 0.1µF capacitor.

VOUTA to VOUTH (Pins 2–5, 10–13/Pins 2–5, 12–15): DAC

Analog Voltage Outputs.

CAO (Pin 6/Pin 7): Chip Address Bit 0. Tie this pin to VCC,

GND or leave it ﬂ oating to select an I2C slave address for

the part (See Tables 1 and 2).

SCL (Pin 7/Pin 8): Serial Clock Input Pin. Data is shifted

into the SDA pin at the rising edges of the clock. This

high impedance pin requires a pull-up resistor or current

source to VCC.

SDA (Pin 8/Pin 9): Serial Data Bidirectional Pin. Data is

shifted into the SDA pin and acknowledged by the SDA

pin. This pin is high impedance while data is shifted in.

Open drain N-channel output during acknowledgment. SDA

requires a pull-up resistor or current source to VCC.

REF (Pin 9/Pin 11): Reference Voltage Input or Output.

When External Reference mode is selected, REF is an input

(1V ≤ VREF ≤ VCC) where the voltage supplied sets the

full-scale DAC output voltage. When Internal Reference

is selected, the 10ppm/°C 1.25V (LTC2637-L) or 2.048V

(LTC2637-H) internal reference (half full-scale) is available

at the pin. This output may be bypassed to GND with up

to 10µF, and must be buffered when driving external DC

load current.

GND (Pin 14/Pin 16): Ground.

CA2 (Pin 6, MSOP only): Chip Address Bit 2. Tie this pin

to VCC, GND or leave it ﬂ oating to select an I2C slave ad-

dress for the part (See Table 1).

CA1 (Pin 10, MSOP only): Chip Address Bit 1. Tie this

pin to VCC, GND or leave it ﬂ oating to select an I2C slave

address for the part (See Table 1).

Exposed Pad (Pin 15, DFN Only): Ground. Must be

soldered to PCB Ground.

(DFN/MSOP)

LTC2637

2637fb

BLOCK DIAGRAM

TEST CIRCUITS

2637 BD

GND

VOUTA

VOUTB

VOUTC

VOUTD

CAO

(CA1)

(CA2)

REF

VCC

VOUTH

VOUTG

VOUTF

VOUTE

SCL

INTERNAL REFERENCE SWITCH

DAC A

DECODE

POWER-ON RESET

VREF

DAC B

DAC C

DAC D

DAC H

DAC G

DAC F

DAC E

I2C

ADDRESS

DECODE

( ) MSOP PACKAGE ONLY

REGISTERREGISTERREGISTER

REGISTERREGISTERREGISTERREGISTER

SDA

I2C INTERFACE

2637 TC01

100 CAn

VIH(CAn)/VIL(CAn)

Test Circuit 1

2637 TC01b

CAn

RINH/RINL/RINF

VDD

GND

Test Circuit 2

LTC2637

2637fb

TIMING DIAGRAM

Figure 2. Typical LTC2637 Write Transaction

ACK ACK

123456789123456789123456789123456789

2637 F02

ACK

START

A6 A5 A4 A3

SLAVE ADDRESS

A2 A1 A0 W

SCL

C2C3 C1 C0 A3 A2 A1 A0 XXXX

ACK

1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE

Figure 1. I2C Timing

SDA

SCL

SSrSP

tftrtBUF

tLOW

tHD(STA) tSU(STA) tSU(STO)

tHD(DAT)

ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS

tHIGH

tSU(DAT) tHD(STA) tSP

2637 F01

LTC2637

2637fb

OPERATION

The LTC2637 is a family of octal voltage output DACs in

14-lead DFN and 16-lead MSOP packages. Each DAC can

operate rail-to-rail using an external reference, or with its

full-scale voltage set by an integrated reference. Eighteen

combinations of accuracy (12-, 10-, and 8-bit), power-on

reset value (zero-scale, mid-scale in internal reference

mode, or mid-scale in external reference mode), and full-

scale voltage (2.5V or 4.096V) are available. The LTC2637

is controlled using a 2-wire I2C interface.

Power-On Reset

The LTC2637-HZ/ LTC2637-LZ clear the output to zero-scale

when power is ﬁ rst applied, making system initialization

consistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2637

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The LTC2637-HMI/LTC2637-HMX/LTC2637-LMI/

LTC2637-LMX provide an alternative reset, setting the

output to mid-scale when power is ﬁ rst applied. The

LTC2637-LMI and LTC2637-HMI power up in internal

reference mode, with the output set to a mid-scale volt-

age of 1.25V and 2.048V, respectively. The LTC2637-LMX

and LTC2637-HMX power-up in external reference mode,

with the output set to mid-scale of the external reference.

Default reference mode selection is described in the Refer-

ence Modes section.

Power Supply Sequencing

The voltage at REF (Pin 9, DFN; Pin 11, MSOP) must be

kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see

Absolute Maximum Ratings). Particular care should be

taken to observe these limits during power supply turn-

on and turn-off sequences, when the voltage at VCC is in

transition.

Transfer Function

The digital-to-analog transfer function is:

VOUT(IDEAL) =k

⎛

⎝

⎜⎞

⎠

⎟VREF

where k is the decimal equivalent of the binary DAC

input code, N is the resolution, and VREF is either 2.5V

(LTC2637-LMI/LTC2637-LMX/LTC2637-LZ) or 4.096V

(LTC2637-HMI/LTC2637-HMX/LTC2637-HZ) when in

Internal Reference mode, and the voltage at REF when in

External Reference mode.

I2C Serial Interface

The LTC2637 communicates with a host using the stan-

dard 2-wire I2C interface. The timing diagrams (Figures

1 and 2) show the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines. The value of

these pull-up resistors is dependent on the power supply

and can be obtained from the I2C speciﬁ cations. For an I2C

bus operating in the fast mode, an active pull-up will be

necessary if the bus capacitance is greater than 200pF.

The LTC2637 is a receive-only (slave) device. The master

can write to the LTC2637. The LTC2637 will not acknowl-

edge (NAK) a read request from the master.

START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition. A

START condition is generated by transitioning SDA from

high to low while SCL is high.

When the master has ﬁ nished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

another I2C device.

LTC2637

2637fb

OPERATION

Acknowledge

The Acknowledge (ACK) signal is used for handshaking

between the master and the slave. An ACK (active LOW)

generated by the slave lets the master know that the lat-

est byte of information was properly received. The ACK

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the ACK clock pulse.

The slave-receiver must pull down the SDA bus line dur-

ing the ACK clock pulse so that it remains a stable LOW

during the HIGH period of this clock pulse. The LTC2637

responds to a write by a master in this manner but does

not acknowledge a read operation; in that case, SDA is

retained HIGH during the period of the ACK clock pulse.

Chip Address

The state of pins CA0, CA1 and CA2 (CA1 and CA2 are

only available on the MSOP package) determines the slave

address of the part. These pins can each be set to any

one of three states: VCC, GND or ﬂ oat. This results in 27

(MSOP Package) or 3 (DFN Package) selectable addresses

for the part. The slave address assignments are shown

in Tables 1 and 2.

In addition to the address selected by the address pins,

the part also responds to a global address. This address

allows a common write to all LTC2637 parts to be ac-

complished using one 3-byte write transaction on the

I2C bus. The global address, listed at the end of Tables 1

and 2, is a 7-bit hardwired address not selectable by CA0,

CA1 or CA2. If another global address is required, please

consult the factory.

The maximum capacitive load allowed on the address pins

(CA0, CA1 and CA2) is 10pF, as these pins are driven during

address detection to determine if they are ﬂ oating.

Table 1. Slave Address Map (MSOP Package)

CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0

GNDGNDGND0010000

GNDGNDFLOAT0010001

GND GND VCC 0010010

GNDFLOATGND0010011

GNDFLOATFLOAT0100000

GND FLOAT VCC 0100001

GND VCC GND0100010

GND VCC FLOAT0100011

GND VCC VCC 0110000

FLOATGNDGND0110001

FLOATGNDFLOAT0110010

FLOAT GND VCC 0110011

FLOATFLOATGND1000000

FLOATFLOATFLOAT1000001

FLOAT FLOAT VCC 1000010

FLOAT VCC GND1000011

FLOAT VCC FLOAT1010000

FLOAT VCC VCC 1010001

VCC GNDGND1010010

VCC GNDFLOAT1010011

VCC GND VCC 1100000

VCC FLOATGND1100001

VCC FLOATFLOAT1100010

VCC FLOAT VCC 1100011

VCC VCC GND1110000

VCC VCC FLOAT1110001

VCC VCC VCC 1110010

GLOBAL ADDRESS 1110011

Table 2. Slave Address Map (DFN Package)

CA0 A6A5A4A3A2A1A0

GND 0010000

FLOAT 0010001

VCC 0010010

GLOBAL ADDRESS 1 1 1 0 0 1 1

LTC2637

2637fb

OPERATION

Write Word Protocol

The master initiates communication with the LTC2637

with a START condition and a 7-bit slave address followed

by the Write bit (W) = 0. The LTC2637 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0, CA1

or CA2) or the global address. The master then transmits

three bytes of data. The LTC2637 acknowledges each byte

of data by pulling the SDA line low at the 9th clock of each

data byte transmission. After receiving three complete bytes

of data, the LTC2637 executes the command speciﬁ ed in

the 24-bit input word.

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2637 does not acknowledge the

extra bytes of data (SDA is high during the 9th clock).

The format of the three data bytes is shown in Figure

3. The ﬁ rst byte of the input word consists of the 4-bit

command, followed by the 4-bit DAC address. The next

two bytes contain the 16-bit data word, which consists

of the 12-, 10- or 8-bit input code, MSB to LSB, followed

by 4, 6 or 8 don’t-care bits (LTC2637-12, LTC2637-10

and LTC2637-8, respectively). A typical LTC2637 write

transaction is shown in Figure 4.

The command bit assignments (C3-C0) and address (A3-

A0) assignments are shown in Tables 3 and 4. The ﬁ rst

four commands in the table consist of write and update

operations. A write operation loads a 16-bit data word

from the 32-bit shift register into the input register. In an

update operation, the data word is copied from the input

8-bit input code, and is converted to an analog voltage at

the DAC output. Write to and Update combines the ﬁ rst

two commands. The Update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

Table 3. Command Codes

COMMAND*

C3 C2 C1 C0

0000Write to Input Register n

0001Update (Power Up) DAC Register n

0010Write to Input Register n, Update (Power Up) All

0011Write to and Update (Power Up) DAC Register n

0100Power Down n

0101Power Down Chip (All DAC’s and Reference)

0110Select Internal Reference (Power Up Reference)

0111Select External Reference (Power Down Internal

Reference)

1111No Operation

*Command codes not shown are reserved and should not be used.

Table 4. Address Codes

ADDRESS (n)*

A3 A2 A1 A0

0000DAC A

0001DAC B

0010DAC C

0011DAC D

0100DAC E

0101DAC F

0110DAC G

0111DAC H

1111All DACs

*Address codes not shown are reserved and should not be used.

Reference Modes

For applications where an accurate external reference is

either not available, or not desirable due to limited space,

the LTC2637 has a user-selectable, integrated reference.

The integrated reference voltage is internally ampliﬁ ed

by 2x to provide the full-scale DAC output voltage range.

LTC2637

2637fb

OPERATION

Figure 3. Command and Data Input Format

1ST DATA BYTE

Input Word (LTC2637-12)

Write Word Protocol for LTC2637

C2 C1 C0 A3 A2 A1 A1 D9D10D11

SWACK

SLAVE ADDRESS 1ST DATA BYTE

D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

ACK 2ND DATA BYTE ACK 3RD DATA BYTE ACK P

2637 F03

2ND DATA BYTE

INPUT WORD

3RD DATA BYTE

1ST DATA BYTE

Input Word (LTC2637-10)

C2 C1 C0 A3 A2 A1 A0 D7D8D9 D6 D5 D4 D3 D2 D1 D0 XXXXX

2ND DATA BYTE 3RD DATA BYTE

1ST DATA BYTE

Input Word (LTC2637-8)

C2 C1 C0 A3 A2 A1 A0 D5D6D7 D4 D3 D2 D1 D0 XXXXXXX

2ND DATA BYTE 3RD DATA BYTE

The LTC2637-LMI/ LTC2637-LMX/ LTC2637-LZ provides

a full-scale output of 2.5V. The LTC2637-HMI/ LTC2637-

HMX/ LTC2637-HZ provides a full-scale output of 4.096V.

The internal reference can be useful in applications where

the supply voltage is poorly regulated. Internal Reference

mode can be selected by using command 0110b, and is

the power-on default for LTC2637-HZ/ LTC2637-LZ, as

well as for LTC2637-HMI/ LTC2637-LMI.

The 10ppm/°C, 1.25V (LTC2637-LMI/ LTC2637-LMX/

LTC2637-LZ) or 2.048V (LTC2637-HMI/ LTC2637-HMX/

LTC2637-HZ) internal reference is available at the REF pin.

Adding bypass capacitance to the REF pin will improve

noise performance; and up to 10µF can be driven without

oscillation. The REF output must be buffered when driving

an external DC load current.

Alternatively, the DAC can operate in External Reference

mode using command 0111b. In this mode, an input voltage

supplied externally to the REF pin provides the reference

(1V ≤ VREF ≤ VCC) and the supply current is reduced. The

external reference voltage supplied sets the full-scale DAC

output voltage. External Reference mode is the power-on

default for LTC2637-HMX/ LTC2637-LMX.

The reference mode of LTC2637-HZ/ LTC2637-LZ/ LTC2637-

HMI/ LTC2637-LMI (internal reference power-on default),

can be changed by software command after power up. The

same is true for LTC2637-HMX/ LTC2637-LMX (external

reference power-on default).

Power-Down Mode

For power-constrained applications, power-down mode can

be used to reduce the supply current whenever less than

eight DAC outputs are needed. When in power-down, the

buffer ampliﬁ ers, bias circuits, and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC outputs are put into a high-impedance state, and

the output pins are passively pulled to ground through in-

dividual 200k resistors. Input and DAC register contents

are not disturbed during power down.

Any DAC channel or combination of channels can be put

into power-down mode by using command 0100b in

combination with the appropriate DAC address, (n). The

supply current is reduced approximately 10% for each DAC

powered down. The integrated reference is automatically

powered down when external reference is selected using

LTC2637

2637fb

OPERATION

command 0111b. In addition, all the DAC channels and

the integrated reference together can be put into power-

down mode using Power Down Chip command 0101b.

When the integrated reference and all DAC channels are

in power-down mode, the REF pin becomes high imped-

ance (typically > 1G). For all power-down commands

the 16-bit data word is ignored.

Normal operation resumes after executing any command

that includes a DAC update, (as shown in Table 1). The

selected DAC is powered up as its voltage output is up-

dated. When a DAC which is in a powered-down state is

powered up and updated, normal settling is delayed. If

less than eight DACs are in a powered-down state prior

to the update command, the power-up delay time is 10µs.

However, if all eight DACs and the integrated reference

are powered down, then the main bias generation circuit

block has been automatically shut down in addition to

the DAC ampliﬁ ers and reference buffers. In this case,

the power up delay time is 12µs. The power-up of the

integrated reference depends on the command that pow-

ered it down. If the reference is powered down using the

Select External Reference Command (0111b), then it can

only be powered back up using Select Internal Reference

Command (0110b). However, if the reference was powered

down using Power Down Chip Command (0101b), then in

addition to Select Internal Reference Command (0110b),

any command that powers up the DACs will also power

up the integrated reference.

Voltage Output

The LTC2637’s DAC output integrated rail-to-rail ampliﬁ ers

have guaranteed load regulation when sourcing or sinking

up to 10mA at 5V, and 5mA at 3V.

Load regulation is a measure of the ampliﬁ er’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to ohms. The ampliﬁ er’s DC output

impedance is 0.1 when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50 typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage is

50 • 1mA, or 50mV). See the graph “Headroom at Rails

vs. Output Current” in the Typical Performance Charac-

teristics section.

The ampliﬁ er is stable driving capacitive loads of up to

500pF.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is lim-

ited to voltages within the supply range.

Since the analog output of the DAC cannot go below ground,

it may limit for the lowest codes as shown in Figure 5b.

Similarly, limiting can occur near full scale when the REF

pin is tied to VCC. If VREF = VCC and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits

at VCC, as shown in Figure 5c. No full-scale limiting can

occur if VREF is less than VCC–FSE.

Offset and linearity are deﬁ ned and tested over the region

of the DAC transfer function where no output limiting can

occur.

Board Layout

The PC board should have separate areas for the analog and

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

LTC2637

2637fb

analog section of the ground plane. The resistance from

the LTC2637 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1). Note that the LTC2637 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2637 is sinking large currents, this current ﬂ ows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to conﬁ ne digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

OPERATION

A6 A5 A4 A3 A2 A1 A0 WC3

C3ACK

SLAVE ADDRESS

ACK ACK ACK

C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXXX

START STOP

FULL-SCALE

VOLTAGE

ZERO-SCALE

VOLTAGE

SDA

SCL

X = DON’T CARE

VOUT

A5 A4 A3 A2 A1 A0 C2 C1 C0 A3 A2 A1 A0

891234567

1234567

891234567 89123456789

COMMAND/ADDRESS MS DATA LS DATA

2637 F04

Figure 4. Typical LTC2637 Input Waveform—Programming DAC Output for Full-Scale

Figure 5. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits).

(a) Overall Transfer Function

(b) Effect of Negative Offset for Codes Near Zero

2637 F04

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V 2,0480 4,095

INPUT CODE

OUTPUT

VOLTAGE

(a)

VREF = VCC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

LTC2637

2637fb

TYPICAL APPLICATION

2637 TA02

LTC2637MS-LMI12

DAC A

DAC B

DAC C

DAC D

DAC H

DAC G

DAC F

DAC E

REF

SDA

SCL

CA0

CA1

CA2

VCC

0.1µF 0.1µF

LT1991

VCC

VEE

REF

OUT 6VOUT = ±5V

0.1µF

–15V

15V

GND 16

–

0.1µF

15V

–15V

1/2 LT1469

DAC A

30k

LT1634-1.25

–15V

I2C

BUS

OUTA

6061

–

OUTB

RFBA

RVOSA

GND

IOUT1A

IOUT2A 3

30k

–15V

DAC B

VDD

ROFSA

RIN1

RCOM1

REFA

DAC D

–

OUTD

DAC C

–

OUTC

–

1/2 LT1469

0.1µF

15V

–15V

0.1µF

30k

–15V

30k

–15V

LTC2755 LTC6240

–

LT1634-1.25

LTC2637 DACs Adjust LTC2755-16 Offsets, Ampliﬁ ed with LT1991 PGA to ±5V

LTC2637

2637fb

PACKAGE DESCRIPTION

3.00 p0.10

(2 SIDES)

4.00 p0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEW—EXPOSED PAD

1.70 p 0.10

0.75 p0.05

R = 0.115

TYP

R = 0.05

TYP

3.00 REF

1.70 p 0.05

148

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DE14) DFN 0806 REV B

PIN 1 NOTCH

R = 0.20 OR

0.35 s 45o

CHAMFER

3.00 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

2.20 p0.05

0.70 p0.05

3.60 p0.05

PACKAGE

OUTLINE

0.25 p 0.05 0.25 p 0.05

0.50 BSC

3.30 p0.05 3.30 p0.10

0.50 BSC

DE Package

14-Lead (4mm × 3mm) Plastic DFN

(Reference LTC DWG # 05-08-1708 Rev B)

MS Package

16-Lead (4mm × 5mm) Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev Ø)

MSOP (MS16) 1107 REV Ø

0.53 p 0.152

(.021 p .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

16151413121110

12345678

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0o – 6o TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 p 0.127

(.035 p .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 p 0.038

(.0120 p .0015)

TYP

0.50

(.0197)

BSC

4.039 p 0.102

(.159 p .004)

(NOTE 3)

0.1016 p 0.0508

(.004 p .002)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

0.280 p 0.076

(.011 p .003)

REF

4.90 p 0.152

(.193 p .006)

LTC2637

2637fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 10/09 Update LTC2637-12 Maximum Limits 5, 6, 8

B 06/10 Added details to Note 3

Revised Typical Application circuit

Added Typical Application drawing and revised Related Parts

LTC2637

2637fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0610 REV B • PRINTED IN USA

PART NUMBER DESCRIPTION COMMENTS

LTC2636 Octal 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference 125A per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

External REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm

DFN and 16-Lead MSOP Packages

LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output

LTC2605/LTC2615/

LTC2625

Octal 16-/14-/12-Bit VOUT DACs with I2C Interface 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,

I2C Interface

LTC2600/LTC2610/

LTC2620

Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

LTC2656/LTC2657 Octal 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max

Reference

±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail

Output, 20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages

LTC2654/LTC2655 Quad 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max

Reference

±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail

Output, 20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP

Packages

LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/°C

Reference

±2.5 LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

External REF Mode, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP

Packages

LTC2630/LTC2632 Single 12-/10-/8-Bit, SPI/ I2C VOUT DACs with 10ppm/°C

Reference

180A per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

Rail-to-Rail Output, in SC70 (LTC2630)/ ThinSOT™(LTC2631)

LTC2640 Single 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference 180A per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

External REF Mode, Rail-to-Rail Output, in ThinSOT

Ampliﬁ ers

LT1991 Precision, 100µA Gain Selectable Ampliﬁ er Gain Accuracy of 0.04%, Gains from –13 to 14, 100A Precision

Op-Amp

LT1469 Dual 90MHz, 22V/µs 16-Bit Accurate Operational Ampliﬁ er 90MHz Gain Bandwidth, 125µV offset, 900ns , 22V/µs Slew Rate

Precision Op-Amp

RELATED PARTS

TYPICAL APPLICATION

LTC2637 DACs Adjust LTC2755-16 Offsets, Ampliﬁ ed with LT1991 PGA to ±5V

2637 TA03

LTC2637MS-LMI12

DAC A

DAC B

DAC C

DAC D

DAC H

DAC G

DAC F

DAC E

REF

SDA

SCL

CA0

CA1

CA2

VCC

0.1µF 0.1µF

LT1991

VCC

VEE

REF

OUT 6VOUT = ±5V

0.1µF

–15V

15V

GND 16

–

0.1µF

15V

–15V

1/2 LT1469

DAC A

30k

LT1634-1.25

–15V

I2C

BUS

OUTA

6061

–

OUTB

RFBA

RVOSA

GND

IOUT1A

IOUT2A 3

30k

–15V

DAC B

VDD

ROFSA

RIN1

RCOM1

REFA

DAC D

–

OUTD

DAC C

–

OUTC

–

1/2 LT1469

0.1µF

15V

–15V

0.1µF

30k

–15V

30k

–15V

LTC2755 LTC6240

–

LT1634-1.25