Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF5329DS Rev. 5, 11/2008 MAPBGA-256 17mm x 17mm MCF532x ColdFire(R) Microprocessor Data Sheet Features * Version 3 ColdFire variable-length RISC processor core * System debug support * JTAG support for system level board testing * On-chip memories - 16-Kbyte unified write-back cache - 32-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC, LCD controller, and USB host and OTG) * Power management * Liquid Crystal Display Controller (LCDC) * Embedded Voice-over-IP (VoIP) system solution * SDR/DDR SDRAM Controller * Universal Serial Bus (USB) Host Controller * Universal Serial Bus (USB) On-the-Go (OTG) controller * Synchronous Serial Interface (SSI) * Fast Ethernet Controller (FEC) * Cryptography Hardware Accelerators * FlexCAN Module * Three Universal Asynchronous Receiver Transmitters (UARTs) * I2C Module * Queued Serial Peripheral Interface (QSPI) * Pulse Width Modulation (PWM) module * Real Time Clock * Four 32-bit DMA Timers * Software Watchdog Timer * Four Periodic Interrupt Timers (PITs) * Phase Locked Loop (PLL) * Interrupt Controllers (x2) * DMA Controller * FlexBus (External Interface) * Chip Configuration Module (CCM) * Reset Controller * General Purpose I/O interface (c) Freescale Semiconductor, Inc., 2008. All rights reserved. MAPBGA-196 15mm x 15mm Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 MCF5329 1 2 3 4 5 MCF532x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 Supply Voltage Sequencing and Separation Cautions . .5 3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5 3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6 4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.2 Pinout--256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3 Pinout--196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17 5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .18 5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .19 5.6 External Interface Timing Characteristics . . . . . . . . . . .20 5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .23 5.7.2 DDR SDRAM AC Timing Characteristics . . . . . General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . Reset and Configuration Override Timing . . . . . . . . . . LCD Controller Timing Specifications . . . . . . . . . . . . . USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ULPI Timing Specification . . . . . . . . . . . . . . . . . . . . . . SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . I2C Input/Output Timing Specifications . . . . . . . . . . . . Fast Ethernet AC Timing Specifications . . . . . . . . . . . 5.15.1 MII Receive Signal Timing . . . . . . . . . . . . . . . . 5.15.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . 5.15.3 MII Async Inputs Signal Timing . . . . . . . . . . . . 5.15.4 MII Serial Management Channel Timing . . . . . 5.16 32-Bit Timer Module Timing Specifications . . . . . . . . . 5.17 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 5.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 5.19 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Package Dimensions--256 MAPBGA . . . . . . . . . . . . . 7.2 Package Dimensions--196 MAPBGA . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 6 7 8 25 28 29 30 33 33 33 35 37 37 37 38 38 39 39 40 42 42 45 45 46 47 MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table of Contents MCF532x Family Comparison USB Host M5 S4 M6 FlexBus Chip Selects SDRAMC S1 LCDC M2 M1 S7 USB OTG USB Host LCDC SDRAMC QSPI External Interface XBS M4 (To/From PADI) (To/From SRAM backdoor) M0 S6 Cryptography Modules I 2C UART INTC0 RNGA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 USB OTG INTC1 FEC MDHA QSPI UARTs PWMs, EPORT, Watchdog, PITs PLL RTC XTAL EXTAL32K LCDC EXTAL CLKOUT SSI Reset TRST TCLK TMS TDI TDO 16 KByte Cache (1024x32)x4 SDRAMC FEC CANRX CANTX SSI CS[5:0] TA TS BE/BWE[3:0] PORTS USB Host XTAL32K XCVR XCVR V3 ColdFire CPU USB OTG RESET RCON RSTOUT EMAC BDM DIV PWM DMA Timer DREQn DACKn D[31:0] A[23:0] R/W DMA ULPI Interface (To/From PADI) I2C FlexCAN DMA Timers (To/From PADI) PADI -- Pin Muxing SDRAMC SKHA (To/From PADI) 32 KByte SRAM (4096x32)x2 JTAG TAP JTAG_EN (To/From XBS backdoor) Figure 1. MCF5329 Block Diagram 1 MCF532x Family Comparison The following table compares the various device derivatives available within the MCF532x family. Table 1. MCF532x Family Configurations Module ColdFire Version 3 Core with EMAC (Enhanced Multiply-Accumulate Unit) MCF5327 MCF5328 MCF53281 MCF5329 * * * * Core (System) Clock up to 240 MHz Peripheral and External Bus Clock (Core clock / 3) up to 80 MHz Performance (Dhrystone/2.1 MIPS) up to 211 Unified Cache 16 Kbytes Static RAM (SRAM) 32 Kbytes MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 3 Ordering Information Module MCF5327 MCF5328 MCF53281 MCF5329 LCD Controller * * * * SDR/DDR SDRAM Controller * * * * USB 2.0 Host * * * * USB 2.0 On-the-Go * * * * -- * * * * * * * Fast Ethernet Controller (FEC) -- * * * Cryptography Hardware Accelerators -- -- -- * Embedded Voice-over-IP System Solution -- -- * -- FlexCAN 2.0B communication module -- -- * * UARTs 3 3 3 3 I2C * * * * QSPI * * * * PWM Module * * * * Real Time Clock * * * * 32-bit DMA Timers 4 4 4 4 Watchdog Timer (WDT) * * * * Periodic Interrupt Timers (PIT) 4 4 4 4 Edge Port Module (EPORT) * * * * Interrupt Controllers (INTC) 2 2 2 2 16-channel Direct Memory Access (DMA) * * * * FlexBus External Interface * * * * General Purpose I/O Module (GPIO) * * * * JTAG - IEEE(R) 1149.1 Test Access Port * * * * 196 MAPBGA 256 MAPBGA 256 MAPBGA 256 MAPBGA UTMI+ Low Pin Interface (ULPI) Synchronous Serial Interface (SSI) Package 2 Ordering Information Table 2. Orderable Part Numbers Freescale Part Number Description Package Speed Temperature MCF5327CVM240 MCF5327 RISC Microprocessor 196 MAPBGA 240 MHz -40 to +85 C MCF5328CVM240 MCF5328 RISC Microprocessor 256 MAPBGA 240 MHz -40 to +85 C MCF53281CVM240 MCF53281 RISC Microprocessor 256 MAPBGA 240 MHz -40 to +85 C MCF5329CVM240 MCF5329 RISC Microprocessor 256 MAPBGA 240 MHz -40 to +85 C MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 1. MCF532x Family Configurations (continued) 3 Hardware Design Considerations 3.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible. 10 Board IVDD PLL VDD Pin 10 F 0.1 F GND Figure 2. System PLL VDD Power Filter 3.2 USB Power Filtering To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible. 0 Board EVDD USB VDD Pin 10 F 0.1 F GND Figure 3. USB VDD Power Filter NOTE In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown. 3.3 Supply Voltage Sequencing and Separation Cautions The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 3.3.1 Power Up Sequence If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Hardware Design Considerations Pin Assignments and Reset States high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on the internal ESD protection clamp diodes. Power Down Sequence If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. 2. Drop IVDD/PLLVDD to 0 V. Drop EVDD/SDVDD supplies. 4 Pin Assignments and Reset States 4.1 Signal Multiplexing The following table lists all the MCF532x pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to Section 7, "Package Information," for package diagrams. For a more detailed discussion of the MCF532x signals, consult the MCF5329 Reference Manual (MCF5329RM). NOTE In this table and throughout this document, a single signal within a group is designated without square brackets (i.e., A23), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO default to their GPIO functionality. Table 3. MCF5327/8/9 Signal Information and Muxing Voltage Domain MCF53281 MCF5329 256 MAPBGA Dir.1 MCF5328 256 MAPBGA MCF5327 196 MAPBGA RESET2 -- -- -- I EVDD J11 N15 N15 RSTOUT -- -- -- O EVDD P14 P14 P14 Signal Name GPIO Alternate 1 Alternate 2 Reset Clock EXTAL -- -- -- I EVDD L14 P16 P16 2 XTAL -- -- -- O EVDD K14 N16 N16 EXTAL32K -- -- -- I EVDD M11 P13 P13 XTAL32K -- -- -- O EVDD N11 R13 R13 FB_CLK -- -- -- O SDVDD L1 T2 T2 MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 3.3.2 Pin Assignments and Reset States MCF53281 MCF5329 256 MAPBGA RCON -- -- -- I EVDD M7 M8 M8 DRAMSEL -- -- -- I EVDD G11 H12 H12 Signal Name GPIO Alternate 1 Alternate 2 Dir.1 Voltage Domain MCF5328 256 MAPBGA MCF5327 196 MAPBGA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Mode Selection 2 FlexBus A[23:22] -- FB_CS[5:4] -- O SDVDD B11,C11 C13, D13 C13, D13 A[21:16] -- -- -- O SDVDD B12, A12, D11, C12, B13, A13 E13, A14, B14, C14, A15, B15 E13, A14, B14, C14, A15, B15 A[15:14] -- SD_BA[1:0]3 -- O SDVDD A14, B14 D14, B16 D14, B16 A[13:11] -- SD_A[13:11]3 -- O SDVDD C13, C14, D12 C15, C16, D15 C15, C16, D15 A10 -- -- -- O SDVDD D13 D16 D16 A[9:0] -- SD_A[9:0]3 -- O SDVDD D14, E11-14, F11-F14, G14 E14-E16, F13-F16, G16- G14 E14-E16, F13-F16, G16- G14 D[31:16] -- SD_D[31:16]4 -- I/O SDVDD H3-H1, J4-J1, K1, L4, M2, M3, N1, N2, P1, P2, N3 M1-M4, N1-N4, T3, P4, R4, T4, N5, P5, R5, T5 M1-M4, N1-N4, T3, P4, R4, T4, N5, P5, R5, T5 D[15:1] -- FB_D[31:17]4 -- I/O SDVDD F4-F1, G5-G2, L5, N4, P4, M5, N5, P5, L6 J3-J1, K4-K1, L2, R6, N7, P7, R7, T7, P8, R8 J3-J1, K4-K1, L2, R6, N7, P7, R7, T7, P8, R8 D02 -- FB_D[16]4 -- I/O SDVDD M6 T8 T8 PBE[3:0] SD_DQM[3:0]3 -- O M4 L4, P6, L3, N6 L4, P6, L3, N6 BE/BWE[3:0] SDVDD H4, P3, G1, OE PBUSCTL3 -- -- O SDVDD P6 R9 R9 TA2 PBUSCTL2 -- -- I SDVDD G13 G13 G13 R/W PBUSCTL1 -- -- O SDVDD N6 N8 N8 TS PBUSCTL0 DACK0 -- O SDVDD D2 H4 H4 O SDVDD -- B13, A13 B13, A13 O SDVDD A11, D10, C10 A12, B12, C12 A12, B12, C12 O SDVDD B10 D12 D12 Chip Selects FB_CS[5:4] PCS[5:4] FB_CS[3:1] PCS[3:1] FB_CS0 -- -- -- -- -- MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 7 Pin Assignments and Reset States MCF53281 MCF5329 256 MAPBGA SD_A10 -- -- -- O SDVDD L2 P2 P2 SD_CKE -- -- -- O SDVDD E1 H2 H2 SD_CLK -- -- -- O SDVDD K3 R1 R1 SD_CLK -- -- -- O SDVDD K2 R2 R2 SD_CS1 -- -- -- O SDVDD -- J4 J4 SD_CS0 -- -- -- O SDVDD E2 H1 H1 SD_DQS3 -- -- -- O SDVDD H5 L1 L1 SD_DQS2 -- -- -- O SDVDD K6 T6 T6 SD_SCAS -- -- -- O SDVDD L3 P3 P3 SD_SRAS -- -- -- O SDVDD M1 R3 R3 SD_SDR_DQS -- -- -- O SDVDD K4 P1 P1 SD_WE -- -- -- O SDVDD D1 H3 H3 Signal Name GPIO Alternate 1 Alternate 2 Dir.1 Voltage Domain MCF5328 256 MAPBGA MCF5327 196 MAPBGA SDRAM Controller External Interrupts Port5 IRQ72 PIRQ72 -- -- I EVDD J13 J13 J13 IRQ62 PIRQ62 USBHOST_ VBUS_EN -- I EVDD -- J14 J14 IRQ52 PIRQ52 USBHOST_ VBUS_OC -- I EVDD -- J15 J15 IRQ42 PIRQ42 SSI_MCLK -- I EVDD L13 J16 J16 IRQ32 PIRQ32 -- -- I EVDD M14 K14 K14 IRQ22 PIRQ22 USB_CLKIN -- I EVDD M13 K15 K15 IRQ12 PIRQ12 DREQ12 SSI_CLKIN I EVDD N13 K16 K16 FEC FEC_MDC PFECI2C3 I2C_SCL2 -- O EVDD -- C1 C1 FEC_MDIO PFECI2C2 I2C_SDA2 -- I/O EVDD -- C2 C2 FEC_TXCLK PFECH7 -- -- I EVDD -- A2 A2 FEC_TXEN PFECH6 -- -- O EVDD -- B2 B2 FEC_TXD0 PFECH5 ULPI_DATA0 -- O EVDD -- E4 E4 FEC_COL PFECH4 ULPI_CLK -- I EVDD -- A8 A8 FEC_RXCLK PFECH3 ULPI_NXT -- I EVDD -- C8 C8 FEC_RXDV PFECH2 ULPI_STP -- I EVDD -- D8 D8 FEC_RXD0 PFECH1 ULPI_DATA4 -- I EVDD -- C6 C6 MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Pin Assignments and Reset States Signal Name GPIO Alternate 1 Alternate 2 Voltage Domain MCF53281 MCF5329 256 MAPBGA Dir.1 MCF5328 256 MAPBGA MCF5327 196 MAPBGA FEC_CRS PFECH0 ULPI_DIR -- I EVDD -- B8 B8 FEC_TXD[3:1] PFECL[7:5] ULPI_DATA[3:1] -- O EVDD -- D3-D1 D3-D1 FEC_TXER PFECL4 -- -- O EVDD -- B1 B1 FEC_RXD[3:1] PFECL[3:1] ULPI_DATA[7:5] -- I EVDD -- E7, A6, B6 E7, A6, B6 FEC_RXER PFECL0 -- -- I EVDD -- D4 D4 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 3. MCF5327/8/9 Signal Information and Muxing (continued) LCD Controller LCD_D17 PLCDDH1 CANTX -- O EVDD -- -- C9 LCD_D16 PLCDDH0 CANRX -- O EVDD -- -- D9 LCD_D17 PLCDDH1 -- -- O EVDD A6 C9 -- LCD_D16 PLCDDH0 -- -- O EVDD B6 D9 -- LCD_D15 PLCDDM7 -- -- O EVDD C6 A7 A7 LCD_D14 PLCDDM6 -- -- O EVDD D6 B7 B7 LCD_D13 PLCDDM5 -- -- O EVDD A5 C7 C7 LCD_D12 PLCDDM4 -- -- O EVDD B5 D7 D7 LCD_D[11:8] PLCDDM[3:0] -- -- O EVDD C5, D5, A4, B4 D6, E6, A5, B5 D6, E6, A5, B5 LCD_D7 PLCDDL7 -- -- O EVDD C4 C5 C5 LCD_D6 PLCDDL6 -- -- O EVDD B3 D5 D5 LCD_D5 PLCDDL5 -- -- O EVDD A3 A4 A4 LCD_D4 PLCDDL4 -- -- O EVDD A2 A3 A3 LCD_D[3:0] PLCDDL[3:0] -- -- O EVDD D4, C3, D3, B2 B4, C4, B3, C3 B4, C4, B3, C3 LCD_ACD/ LCD_OE PLCDCTLH0 -- -- O EVDD D7 B9 B9 LCD_CLS PLCDCTLL7 -- -- O EVDD C7 A9 A9 LCD_CONTRAST PLCDCTLL6 -- -- O EVDD B7 D10 D10 LCD_FLM/ LCD_VSYNC PLCDCTLL5 -- -- O EVDD A7 C10 C10 LCD_LP/ LCD_HSYNC PLCDCTLL4 -- -- O EVDD A8 B10 B10 LCD_LSCLK PLCDCTLL3 -- -- O EVDD B8 A10 A10 LCD_PS PLCDCTLL2 -- -- O EVDD C8 A11 A11 LCD_REV PLCDCTLL1 -- -- O EVDD D8 B11 B11 LCD_SPL_SPR PLCDCTLL0 -- -- O EVDD B9 C11 C11 MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 9 Pin Assignments and Reset States Alternate 1 Alternate 2 MCF5327 196 MAPBGA MCF5328 256 MAPBGA MCF53281 MCF5329 256 MAPBGA USB Host & USB On-the-Go USBOTG_M -- -- -- I/O USB VDD G12 L15 L15 USBOTG_P -- -- -- I/O USB VDD H13 L16 L16 USBHOST_M -- -- -- I/O USB VDD K13 M15 M15 USBHOST_P -- -- -- I/O USB VDD J12 M16 M16 FlexCAN (MCF53281 & MCF5329 only) CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing: I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX. PWM PWM7 PPWM7 -- -- I/O EVDD -- H13 H13 PWM5 PPWM5 -- -- I/O EVDD -- H14 H14 PWM3 PPWM3 DT3OUT DT3IN I/O EVDD H14 H15 H15 PWM1 PPWM1 DT2OUT DT2IN I/O EVDD J14 H16 H16 SSI SSI_MCLK PSSI4 -- -- I/O EVDD -- G4 G4 SSI_BCLK PSSI3 U2CTS PWM7 I/O EVDD -- F4 F4 SSI_FS PSSI2 U2RTS PWM5 I/O EVDD -- G3 G3 SSI_RXD2 PSSI1 U2RXD CANRX I EVDD -- -- G2 SSI_TXD2 PSSI0 U2TXD CANTX O EVDD -- -- G1 2 SSI_RXD PSSI1 U2RXD -- I EVDD -- G2 -- SSI_TXD2 PSSI0 U2TXD -- O EVDD -- G1 -- I2C I2C_SCL2 PFECI2C1 CANTX U2TXD I/O EVDD -- -- F3 2 PFECI2C0 CANRX U2RXD I/O EVDD -- -- F2 I2C_SCL2 PFECI2C1 -- U2TXD I/O EVDD E3 F3 -- I2C_SDA2 PFECI2C0 -- U2RXD I/O EVDD E4 F2 -- I2C_SDA DMA DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing: TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 GPIO Voltage Domain Signal Name Dir.1 Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Pin Assignments and Reset States Voltage Domain MCF53281 MCF5329 256 MAPBGA Dir.1 MCF5328 256 MAPBGA MCF5327 196 MAPBGA QSPI_CS2 PQSPI5 U2RTS -- O EVDD P10 T12 T12 QSPI_CS1 PQSPI4 PWM7 USBOTG_ PU_EN O EVDD L11 T13 T13 QSPI_CS0 PQSPI3 PWM5 -- O EVDD -- P11 P11 -- O EVDD N10 R12 R12 Signal Name GPIO Alternate 1 Alternate 2 QSPI 2 QSPI_CLK PQSPI2 I2C_SCL QSPI_DIN PQSPI1 U2CTS -- I EVDD L10 N12 N12 QSPI_DOUT PQSPI0 I2C_SDA -- O EVDD M10 P12 P12 UARTs U1CTS PUARTL7 SSI_BCLK -- I EVDD C9 D11 D11 U1RTS PUARTL6 SSI_FS -- O EVDD D9 E10 E10 U1TXD PUARTL5 SSI_TXD2 -- O EVDD A9 E11 E11 U1RXD PUARTL4 SSI_RXD2 -- I EVDD A10 E12 E12 U0CTS PUARTL3 -- -- I EVDD P13 R15 R15 U0RTS PUARTL2 -- -- O EVDD N12 T15 T15 U0TXD PUARTL1 -- -- O EVDD P12 T14 T14 U0RXD PUARTL0 -- -- I EVDD P11 R14 R14 Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins. DMA Timers DT3IN PTIMER3 DT3OUT U2RXD I EVDD C1 F1 F1 DT2IN PTIMER2 DT2OUT U2TXD I EVDD B1 E1 E1 DT1IN PTIMER1 DT1OUT DACK1 I EVDD A1 E2 E2 DT0OUT DREQ02 I EVDD C2 E3 E3 -- I EVDD L12 M13 M13 -- 2 TRST -- I EVDD N14 P15 P15 PSTCLK -- TCLK2 -- O EVDD L7 T9 T9 BKPT -- TMS2 -- I EVDD M12 R16 R16 DSI -- TDI2 -- I EVDD K12 N14 N14 DSO -- TDO -- O EVDD N9 N11 N11 DDATA[3:0] -- -- -- O EVDD DT0IN PTIMER0 BDM/JTAG6 JTAG_EN7 DSCLK -- -- N7, P7, L8, N9, P9, N10, N9, P9, N10, M8 P10 P10 MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Pin Assignments and Reset States Signal Name GPIO Alternate 1 Alternate 2 Voltage Domain MCF53281 MCF5329 256 MAPBGA Dir.1 MCF5328 256 MAPBGA MCF5327 196 MAPBGA PST[3:0] -- -- -- O EVDD N8, P8, L9, M9 R10, T10, R11, T11 R10, T10, R11, T11 Test TEST7 -- -- -- I EVDD E10 A16 A16 PLL_TEST8 -- -- -- I EVDD -- N13 N13 E6, E7, F5-F7, H9, J8, J9, K8, K9, K11 Power Supplies 1 2 3 4 5 6 7 8 EVDD -- -- -- -- -- E8, F5-F8, E8, F5-F8, G5, G6, H5, G5, G6, H5, H6, J11, H6, J11, K11, K12, K11, K12, L9-L11, M9, L9-L11, M9, M10 M10 IVDD -- -- -- -- -- PLL_VDD -- -- -- -- -- H10 SD_VDD -- -- -- -- -- E8, E9, F8-F10, J5-J7, K7 USB_VDD -- -- -- -- -- G10 L14 L14 VSS -- -- -- -- -- G6-G9, H6-H8, P9 G7-G10, H7-H10, J7-10, K7-K10, L12, L13 G7-G10, H7-H10, J7-10, K7-K10, L12, L13 PLL_VSS -- -- -- -- -- H11 K13 K13 USB_VSS -- -- -- -- -- H12 M14 M14 E5, K5, K10, E5, G12, M5, E5, G12, M5, J10 M11, M12 M11, M12 J12 J12 E9, F9-F11, E9, F9-F11, G11, H11, G11, H11, J5, J6, K5, J5, J6, K5, K6, L5-L8, K6, L5-L8, M6, M7 M6, M7 Refers to pin's primary function. Pull-up enabled internally on this signal for this mode. The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor when accessing SDRAM memory space and are included here for completeness. Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins. GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions. If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. Pull-down enabled internally on this signal for this mode. Must be left floating for proper operation of the PLL. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 3. MCF5327/8/9 Signal Information and Muxing (continued) MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Pin Assignments and Reset States 13 Pin Assignments and Reset States NOTE Pinout--256 MAPBGA Figure 4 shows a pinout of the MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 devices. NOTE The pin at location N13 (PLL_TEST) must be left floating or improper operation of the PLL module occurs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FB_CS3 FB_CS4 A20 A17 TEST A FB_CS2 FB_CS5 A19 A16 A14 B FB_CS1 A23 A18 A13 A12 C U1CTS FB_CS0 A22 A15 A11 A10 D FEC_ LCD_ LCD_ LCD_ FEC_ LCD_ FEC_ LCD_ LCD_ LCD_ TXCLK D4 D5 D9 RXD2 D15 COL CLS LSCLK PS FEC_ FEC_ LCD_ LCD_ LCD_ FEC_ LCD_ FEC_ LCD_ LCD_LP/ LCD_ TXER TXEN D1 D3 D8 RXD1 D14 CRS ACD/OE HSYNC REV FEC_ FEC_ LCD_ LCD_ LCD_ FEC_ LCD_ FEC_ LCD_ LCD_FLM/ LCD_ MDC MDIO D0 D2 D7 RXD0 D13 RXCLK D17 VSYNC SPL_SPR FEC_ FEC_ FEC_ FEC_ LCD_ LCD_ LCD_ FEC_ LCD_ LCD_CON TXD1 TXD2 TXD3 RXER D6 D11 D12 RXDV D16 TRAST E DT2IN DT1IN DT0IN EVDD SD_VDD U1RTS U1TXD U1RXD A21 A9 A8 A7 E F DT3IN I2C_ I2C_ SSI_ SDA SCL BCLK G SSI_ TXD H SD_ CS0 SD_CKE SD_WE J D13 D14 D15 K D9 D10 D11 D12 D8 BE/ BWE1 BE/ BWE3 A B C D L NC SD_ DQS3 SSI_ RXD SSI_FS FEC_ TXD0 SSI_ MCLK TS LCD_ FEC_ D10 RXD3 EVDD EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD NC A6 A5 A4 A3 F EVDD EVDD VSS VSS VSS VSS SD_VDD IVDD TA A0 A1 A2 G EVDD EVDD VSS VSS VSS VSS SD_VDD PWM7 PWM5 PWM3 PWM1 H VSS VSS VSS VSS EVDD IRQ7 IRQ6 IRQ5 IRQ4 J VSS VSS VSS VSS EVDD EVDD PLL_ VSS IRQ3 IRQ2 IRQ1 K EVDD EVDD EVDD VSS USB_ USBOTG USB USB VSS _VDD OTG_M OTG_P RCON EVDD EVDD IVDD IVDD JTAG_ USBHOST USB USB EN _VSS TDO/ QSPI_ PLL_ DSO DIN TEST QSPI_ QSPI_ EXTAL CS0 DOUT 32K QSPI_ XTAL CLK 32K QSPI_ QSPI_ CS2 CS1 12 13 IVDD SD_CS1 SD_VDD SD_VDD SD_VDD SD_VDD SD_VDD SD_VDD SD_VDD SD_VDD M D31 D30 D29 D28 IVDD N D27 D26 D25 D24 D19 BE/ BWE0 D6 R/W DDATA3 DDATA1 SD_A10 SD_CAS D22 D18 BE/ BWE2 D5 D2 DDATA2 DDATA0 R SD_CLK SD_CLK SD_RAS D21 D17 D7 D4 D1 OE PST3 PST1 D3 D0 PST2 PST0 7 8 10 11 P T SD_DR _DQS NC FB_CLK D23 D20 D16 1 2 3 4 5 SD_VDD SD_VDD SD_ DQS2 6 TCLK/ PSTCLK 9 DRAM SEL PLL_ VDD HOST_M HOST_P M TDI/DSI RESET XTAL N RSTOUT TRST/ DSCLK EXTAL P U0RXD U0CTS TMS/ BKPT R U0TXD U0RTS NC T 14 15 16 Figure 4. MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 Pinout Top View (256 MAPBGA) MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 14 L Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 4.2 Electrical Characteristics 4.3 Pinout--196 MAPBGA A B C D E F G H J K L M N P 1 2 3 4 5 6 DT1IN LCD_ D4 LCD_ D5 LCD_ D9 LCD_ D13 LCD_ D17 LCD_FLM/ LCD_LP/ VSYNC HSYNC D2TIN LCD_ D0 LCD_ D6 LCD_ D8 LCD_ D12 LCD_ D16 LCD_CON TRAST DT3IN DT0IN LCD_ D2 LCD_ D7 LCD_ D11 LCD_ D15 SD_WE TS LCD_ D1 LCD_ D3 LCD_ D10 SD_CKE SD_CS0 I2C_SCL I2C_SDA 7 8 9 10 11 12 13 14 U1TXD U1RXD FB_CS3 A20 A16 A15 LCD_ LSCLK LCD_ SPL_SPR FB_CS0 A23 A21 A17 A14 LCD_ CLS LCD_ PS U1CTS FB_CS1 A22 A18 A13 A12 LCD_ D14 LCD_ ACD/OE LCD_ REV U1RTS FB_CS2 A19 A11 A10 A9 IVDD EVDD EVDD SD_VDD SD_VDD TEST A8 A7 A6 A5 SD_VDD SD_VDD SD_VDD A4 A3 A2 A1 D12 D13 D14 D15 EVDD EVDD EVDD BE/ BWE1 D8 D9 D10 D11 VSS VSS VSS VSS USB OTG_VDD DRAM SEL USB OTG_M TA A0 D29 D30 D31 BE/ BWE3 SD_ DQS3 VSS VSS VSS EVDD PLL_ VDD PLL_ VSS USBHOST _VSS USB OTG_P PWM3 D25 D26 D27 D28 SD_VDD EVDD EVDD IVDD RESET USB HOST_P IRQ7 PWM1 D24 SD_CLK SD_CLK SD_DR_ DQS IVDD SD_ DQS2 SD_VDD EVDD EVDD IVDD EVDD TDI/DSI USB HOST_M XTAL FB_CLK SD_A10 SD_CAS D23 D7 D1 TCLK/ PSTCLK DDATA1 PST1 QSPI_ DIN QSPI_ CS1 JTAG_ EN IRQ4 EXTAL SD_VDD SD_VDD A B C D E F G H J K L M SD_RAS D22 D21 BE/ BWE0 D4 D0 RCON DDATA0 PST0 QSPI_ DOUT EXTAL 32K TMS/ BKPT IRQ2 IRQ3 D20 D19 D16 D6 D3 R/W DDATA3 PST3 TDO/ DSO QSPI_ CLK XTAL 32K U0RTS IRQ1 TRST/ DSCLK D18 D17 BE/ BWE2 D5 D2 OE DDATA2 PST2 VSS QSPI_ CS2 U0RXD U0TXD U0CTS RSTOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 N P Figure 5. MCF5327CVM240 Pinout Top View (196 MAPBGA) 5 Electrical Characteristics This document contains electrical specification tables and reference timing diagrams for the MCF5329 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5329. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 The pinout for the MCF5327CVM240 package is shown below. Electrical Characteristics NOTE 5.1 Maximum Ratings Table 4. Absolute Maximum Ratings1, 2 Rating Symbol Value Unit Core Supply Voltage IVDD - 0.5 to +2.0 V CMOS Pad Supply Voltage EVDD - 0.3 to +4.0 V DDR/Memory Pad Supply Voltage SDVDD - 0.3 to +4.0 V PLL Supply Voltage PLLVDD - 0.3 to +2.0 V VIN - 0.3 to +3.6 V ID 25 mA TA (TL - TH) - 40 to +85 C Tstg - 55 to +150 C Digital Input Voltage 3 Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range 1 2 3 4 5 Functional operating conditions are given in Section 5.4, "DC Electrical Specifications." Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or EVDD). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, and then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and EVDD. Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Ensure external EVDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 The parameters specified in this MCU document supersede any values found in the module specifications. Electrical Characteristics 5.2 Thermal Characteristics Characteristic Symbol 256MBGA 196MBGA Unit Junction to ambient, natural convection Four layer board (2s2p) JMA 371,2 421,2 C/W Junction to ambient (@200 ft/min) Four layer board (2s2p) JMA 341,2 381,2 C/W Junction to board -- JB 273 323 C/W Junction to case -- JC 164 194 C/W Junction to top of package -- jt 41,5 51,5 C/W Maximum operating junction temperature -- Tj 105 105 1 2 3 4 5 o C JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D x JMA ) Eqn. 1 Where: TA QJMA PD PINT PI/O = = = = = Ambient Temperature, C Package Thermal Resistance, Junction-to-Ambient, C/W PINT + PI/O IDD x IVDD, Watts - Chip Internal Power Power Dissipation on Input and Output Pins -- User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: K P D = --------------------------------( T J + 273C ) Eqn. 2 Solving equations 1 and 2 for K gives: 2 K = P D x ( T A x 273C ) + Q JMA x P D Eqn. 3 MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 5. Thermal Characteristics Electrical Characteristics 5.3 ESD Protection Table 6. ESD Protection Characteristics1, 2 Characteristics Symbol Value Units ESD Target for Human Body Model HBM 2000 V 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 5.4 DC Electrical Specifications Table 7. DC Electrical Specifications Characteristic Symbol Min Max Unit Core Supply Voltage IVDD 1.4 1.6 V PLL Supply Voltage PLLVDD 1.4 1.6 V EVDD 3.0 3.6 V 1.70 2.25 3.0 1.95 2.75 3.6 USBVDD 3.0 3.6 V CMOS Input High Voltage EVIH 2 EVDD + 0.3 V CMOS Input Low Voltage EVIL VSS - 0.3 0.8 V CMOS Output High Voltage IOH = -5.0 mA EVOH EVDD - 0.4 -- V CMOS Output Low Voltage IOL = 5.0 mA EVOL -- 0.4 V SDRAM and FlexBus Input High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDVIH 1.35 1.7 2 SDVDD + 0.3 SDVDD + 0.3 SDVDD + 0.3 SDRAM and FlexBus Input Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDVIL VSS - 0.3 VSS - 0.3 VSS - 0.3 0.45 0.8 0.8 CMOS Pad Supply Voltage SDRAM and FlexBus Supply Voltage Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) USB Supply Voltage V SDVDD V V MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. Electrical Characteristics Table 7. DC Electrical Specifications (continued) Symbol Min Max SDVDD - 0.35 2.1 2.4 -- -- -- -- -- -- 0.3 0.3 0.5 Iin -1.0 1.0 A Weak Internal Pull-Up Device Current, tested at VIL Max.1 IAPU -10 -130 A Input Capacitance 2 All input-only pins All input/output (three-state) pins Cin -- -- 7 7 SDRAM and FlexBus Output High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOH = -5.0 mA for all modes SDVOH SDRAM and FlexBus Output Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOL = 5.0 mA for all modes SDVOL Input Leakage Current Vin = VDD or VSS, Input-only pins 1 Unit V Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Characteristic V pF Refer to the signals section for pins having weak internal pull-up devices. This parameter is characterized before qualification rather than 100% tested. 2 5.5 Oscillator and PLL Electrical Characteristics Table 8. PLL Electrical Characteristics Num Characteristic Symbol Min. Value Max. Value Unit fref_crystal fref_ext 12 12 251 401 MHz MHz fsys fsys/3 488 x 10-6 163 x 10-6 240 80 MHz MHz tcst -- 10 ms 1 PLL Reference Frequency Range Crystal reference External reference 2 Core frequency CLKOUT Frequency2 3 Crystal Start-up Time3, 4 4 EXTAL Input High Voltage Crystal Mode5 All other modes (External, Limp) VIHEXT VIHEXT VXTAL + 0.4 EVDD/2 + 0.4 -- -- V V 5 EXTAL Input Low Voltage Crystal Mode5 All other modes (External, Limp) VILEXT VILEXT -- -- VXTAL - 0.4 EVDD/2 - 0.4 V V 7 PLL Lock Time 3, 6 tlpll -- 50000 CLKIN tdc 40 60 % IXTAL 1 3 mA 3 8 Duty Cycle of reference 9 XTAL Current 10 Total on-chip stray capacitance on XTAL CS_XTAL 1.5 pF 11 Total on-chip stray capacitance on EXTAL CS_EXTAL 1.5 pF MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 19 Electrical Characteristics Table 8. PLL Electrical Characteristics (continued) 12 Characteristic Symbol Min. Value Max. Value Unit CL See crystal spec Discrete load capacitance for XTAL CL_XTAL 2*CL - CS_XTAL - CPCB_XTAL7 pF Discrete load capacitance for EXTAL CL_EXTAL 2*CL-CS_EXTAL - CPCB_EXTAL7 pF -- -- 10 TBD % fsys/3 % fsys/3 Crystal capacitive load 13 14 Cjitter 17 CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter 18 Frequency Modulation Range Limit 3, 10, 11 (fsysMax must not be exceeded) Cmod 0.8 2.2 %fsys/3 19 VCO Frequency. fvco = (fref * PFD)/4 fvco 350 540 MHz 1 The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency. 2 All internal registers retain data at 0 Hz. 3 This parameter is guaranteed by characterization before qualification rather than 100% tested. 4 Proper PC board layout procedures must be followed to achieve specifications. 5 This parameter is guaranteed by design rather than 100% tested. 6 This specification is the PLL lock time only and does not include oscillator start-up time. 7 C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. 10 Modulation percentage applies over an interval of 10 s, or equivalently the modulation rate is 100 KHz. 11 Modulation range determined by hardware design. 5.6 External Interface Timing Characteristics Table 9 lists processor bus input timings. NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the FB_CLK output. All other timing relationships can be derived from these values. Timings listed in Table 9 are shown in Figure 7 and Figure 8. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Num Electrical Characteristics * The timings are also valid for inputs sampled on the negative clock edge. 1.5V FB_CLK (80MHz) THOLD Input Setup And Hold Invalid 1.5V Valid 1.5V Invalid trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time FB_CLK Vh = VIH Vl = VIL B4 B5 Inputs Figure 6. General Input Timing Requirements 5.6.1 FlexBus A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories. 5.6.1.1 FlexBus AC Timing Characteristics The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock. Table 9. FlexBus AC Timing Specifications Num Characteristic Symbol Min Max Unit -- Frequency of Operation fsys/3 -- 80 Mhz FB1 Clock Period (FB_CLK) tFBCK (tcyc) 12.5 -- ns FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1 tFBCHDCV -- 7.0 ns FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2 tFBCHDCI 1 -- ns MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 TSETUP Electrical Characteristics Num Characteristic Symbol Min Max Unit FB4 Data Input Setup tDVFBCH 3.5 -- ns FB5 Data Input Hold tDIFBCH 0 -- ns FB6 Transfer Acknowledge (TA) Input Setup tCVFBCH 4 -- ns FB7 Transfer Acknowledge (TA) Input Hold tCIFBCH 0 -- ns 1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, "DDR SDRAM AC Timing Characteristics" for SD_CS[3:0] timing. 2 The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual for more information. NOTE The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read and write bus cycles the address signals are indeterminate. S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[23:0] FB_A[23:0] FB_D[31:X] FB2 FB5 ADDR[31:X] DATA FB4 FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB6 FB7 FB_TA Figure 7. FlexBus Read Timing MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 9. FlexBus AC Timing Specifications (continued) Electrical Characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 FB2 FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB6 FB7 FB_TA Figure 8. FlexBus Write Timing 5.7 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. 5.7.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device's SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS signal and its usage. Table 10. SDR Timing Specifications Symbol * Characteristic Frequency of Operation1 2 Symbol Min Max Unit * 60 80 MHz tSDCK 12.5 16.67 ns SD3 Pulse Width High3 tSDCKH 0.45 0.55 SD_CLK SD4 Pulse Width Low4 tSDCKH 0.45 0.55 SD_CLK SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid tSDCHACV -- 0.5 x SD_CLK + 1.0 ns SD6 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold tSDCHACI 2.0 -- ns SD7 SD_SDR_DQS Output Valid5 tDQSOV -- Self timed ns tDQVSDCH 0.25 x SD_CLK 0.40 x SD_CLK ns SD1 Clock Period 6 SD8 SD_DQS[3:0] input setup relative to SD_CLK MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 ADDR[23:0] FB_A[23:0] Electrical Characteristics Table 10. SDR Timing Specifications (continued) Characteristic Symbol Min Max Unit SD9 SD_DQS[3:2] input hold relative to SD_CLK7 tDQISDCH Does not apply. 0.5xSD_CLK fixed width. SD10 Data (D[31:0]) Input Setup relative to SD_CLK (reference only)8 tDVSDCH 0.25 x SD_CLK -- ns SD11 Data Input Hold relative to SD_CLK (reference only) tDISDCH 1.0 -- ns tSDCHDMV -- 0.75 x SD_CLK + 0.5 ns tSDCHDMI 1.5 -- ns SD12 SD13 1 2 3 4 5 6 7 8 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5329 Reference Manual for more information on setting the SDRAM clock rate. SD_CLK is one SDRAM clock in (ns). Pulse width high plus pulse width low cannot exceed min and max clock period. Pulse width high plus pulse width low cannot exceed min and max clock period. SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat. SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat. The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec is provided as guidance. SD2 SD1 SD_CLK SD3 SD5 SD_CSn SD_RAS SD_CAS SD_WE A[23:0] SD_BA[1:0] CMD SD4 ROW COL SD11 SDDM SD12 D[31:0] WD1 WD2 WD3 WD4 Figure 9. SDR Write Timing MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 24 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Symbol Electrical Characteristics SD2 SD1 SD_CLK SD5 SD3 CMD 3/4 MCLK Reference SD4 A[23:0], SD_BA[1:0] ROW COL tDQS SDDM SD6 SD_SDR_DQS (Measured at Output Pin) Board Delay SD_DQS[3:2] SD8 (Measured at Input Pin) SD7 Board Delay Delayed SD_CLK SD9 D[31:0] from Memories WD1 NOTE: Data driven from memories relative to delayed memory clock. WD2 WD3 WD4 SD10 Figure 10. SDR Read Timing 5.7.2 DDR SDRAM AC Timing Characteristics When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. Table 11. DDR Timing Specifications Num * Characteristic Frequency of Operation 1 Symbol Min Max Unit tDDCK 60 80 Mhz tDDSK 12.5 16.67 ns DD2 Pulse Width High 2 tDDCKH 0.45 0.55 SD_CLK DD3 Pulse Width Low3 tDDCKL 0.45 0.55 SD_CLK DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Valid3 tSDCHACV -- 0.5 x SD_CLK + 1.0 ns DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold tSDCHACI 2.0 -- ns DD6 Write Command to first DQS Latching Transition tCMDVDQ -- 1.25 SD_CLK DD7 Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode)4, 5 tDQDMV 1.5 -- ns DD1 Clock Period MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 SD_CSn, SD_RAS, SD_CAS, SD_WE Electrical Characteristics Num Characteristic Symbol Min Max Unit DD8 Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode)6 tDQDMI 1.0 -- ns DD9 Input Data Skew Relative to DQS (Input Setup)7 tDVDQ -- 1 ns tDIDQ 0.25 x SD_CLK + 0.5ns -- ns DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH 0.5 -- ns DD12 DQS input read preamble width tDQRPRE 0.9 1.1 SD_CLK DD13 DQS input read postamble width tDQRPST 0.4 0.6 SD_CLK DD14 DQS output write preamble width tDQWPRE 0.25 DD15 DQS output write postamble width tDQWPST 0.4 8 DD10 1 2 3 4 5 6 7 8 Input Data Hold Relative to DQS SD_CLK 0.6 SD_CLK SD_CLK is one SDRAM clock in (ns). Pulse width high plus pulse width low cannot exceed min and max clock period. Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and voltage variations. This specification relates to the required input setup time of today's DDR memories. The processor's output setup should be larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. This specification relates to the required hold time of today's DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 26 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 11. DDR Timing Specifications (continued) DD1 DD3 SD_CLK SD_CSn,SD_WE, SD_RAS, SD_CAS DD5 A[13:0] D[31:24]/D[23:16] Freescale Semiconductor CMD DD4 DD6 ROW COL DD7 DM3/DM2 DD8 SD_DQS3/SD_DQS2 DD7 WD1 WD2 WD3 WD4 DD8 Figure 11. DDR Write Timing MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Electrical Characteristics DD2 SD_CLK 27 Electrical Characteristics DD1 DD2 DD3 SD_CLK CL=2 DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS CMD CL=2.5 DD4 A[13:0] ROW COL DD9 DQS Read Preamble CL = 2 SD_DQS3/SD_DQS2 DQS Read Postamble DD10 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble CL = 2.5 SD_DQS3/SD_DQS2 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 Figure 12. DDR Read Timing 5.8 General Purpose I/O Timing Table 12. GPIO Timing1 1 Num Characteristic Symbol Min Max Unit G1 FB_CLK High to GPIO Output Valid tCHPOV -- 10 ns G2 FB_CLK High to GPIO Output Invalid tCHPOI 1.5 -- ns G3 GPIO Input Valid to FB_CLK High tPVCH 9 -- ns G4 FB_CLK High to GPIO Input Invalid tCHPI 1.5 -- ns GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 28 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 SD_CLK Electrical Characteristics G2 G1 GPIO Outputs G3 G4 GPIO Inputs Figure 13. GPIO Timing 5.9 Reset and Configuration Override Timing Table 13. Reset and Configuration Override Timing Num 1 Characteristic Symbol Min Max Unit R1 RESET Input valid to FB_CLK High tRVCH 9 -- ns R2 FB_CLK High to RESET Input invalid tCHRI 1.5 -- ns tRIVT 5 -- tCYC 1 R3 RESET Input valid Time R4 FB_CLK High to RSTOUT Valid tCHROV -- 10 ns R5 RSTOUT valid to Config. Overrides valid tROVCV 0 -- ns R6 Configuration Override Setup Time to RSTOUT invalid tCOS 20 -- tCYC R7 Configuration Override Hold Time after RSTOUT invalid tCOH 0 -- ns R8 RSTOUT invalid to Configuration Override High Impedance tROICZ -- 1 tCYC During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. FB_CLK R1 R2 R3 RESET R4 R4 RSTOUT R8 R5 R6 R7 Configuration Overrides*: (RCON, Override pins]) Figure 14. RESET and Configuration Override Timing NOTE Refer to the CCM chapter of the MCF5329 Reference Manual for more information. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 29 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 FB_CLK Electrical Characteristics 5.10 LCD Controller Timing Specifications This sections lists the timing specifications for the LCD Controller. Num Parameter Minimum Maximum Unit T1 LCD_LSCLK Period 25 2000 ns T2 Pixel data setup time 11 -- ns T3 Pixel data up time 11 -- ns Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with bus width is set and LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and LCD_LD signals can also be programmed. T1 LCD_LSCLK LCD_LD[17:0] T2 T3 Figure 15. LCD_LSCLK to LCD_LD[17:0] timing diagram Non-display region T3 T1 LCD_VSYNC Display region T4 T2 LCD_HSYNC LCD_OE LCD_LD[17:0] Line Y Line 1 T5 T6 XMAX Line Y T7 LCD_HSYNC LCD_LSCLK LCD_OE LCD_LD[15:0] (1,1) (1,2) (1,X) Figure 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 30 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 14. LCD_LSCLK Timing Electrical Characteristics Number Description Minimum Value Unit T5+T6+T7-1 (VWAIT1*T2)+T5+T6+T7-1 Ts T1 End of LCD_OE to beginning of LCD_VSYNC T2 LCD_HSYNC period -- XMAX+T5+T6+T7 Ts T3 LCD_VSYNC pulse width T2 VWIDTH*T2 Ts T4 End of LCD_VSYNC to beginning of LCD_OE 1 (VWAIT2*T2)+1 Ts T5 LCD_HSYNC pulse width 1 HWIDTH+1 Ts T6 End of LCD_HSYNC to beginning to LCD_OE 3 HWAIT2+3 Ts T7 End of LCD_OE to beginning of LCD_HSYNC 1 HWAIT1+1 Ts Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 15. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC and LCD_OE can be programmed as active high or active low. In Figure 16, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 16, LCD_LSCLK is always active. Note: XMAX is defined in number of pixels in one line. XMAX LCD_LSCLK LCD_LD D1 D320 LCD_SPL_SPR D2 D320 T1 T2 LCD_HSYNC T3 T2 T4 LCD_CLS T4 T5 T6 LCD_PS T7 T7 LCD_REV Figure 17. Sharp TFT Panel Timing MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 31 Electrical Characteristics Num Description Minimum Value Unit T1 LCD_SPL/LCD_SPR pulse width -- 1 Ts T2 End of LCD_LD of line to beginning of LCD_HSYNC 1 HWAIT1+1 Ts T3 End of LCD_HSYNC to beginning of LCD_LD of line 4 HWAIT2 + 4 Ts T4 LCD_CLS rise delay from end of LCD_LD of line 3 CLS_RISE_DELAY+1 Ts T5 LCD_CLS pulse width 1 CLS_HI_WIDTH+1 Ts T6 LCD_PS rise delay from LCD_CLS negation 0 PS_RISE_DELAY Ts T7 LCD_REV toggle delay from last LCD_LD of line 1 REV_TOGGLE_DELAY+1 Ts Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line. Note: Falling of LCD_PS aligns with rising edge of LCD_CLS. Note: LCD_REV toggles in every LCD_HSYN period. T1 T1 LCD_VSYNC T3 T2 T4 XMAX T2 LCD_HSYNC LCD_LSCLK Ts LCD_LD[15:0] Figure 18. Non-TFT Mode Panel Timing Table 17. Non-TFT Mode Panel Timing Num Description Minimum Value Unit T1 LCD_HSYNC to LCD_VSYNC delay 2 HWAIT2 + 2 Tpix T2 LCD_HSYNC pulse width 1 HWIDTH + 1 Tpix T3 LCD_VSYNC to LCD_LSCLK -- 0 T3 Ts -- T4 LCD_LSCLK to LCD_HSYNC 1 HWAIT1 + 1 Tpix Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK can be programmed as active high or active low. In Figure 18, all three signals are active high. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width = 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 32 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 16. Sharp TFT Panel Timing Electrical Characteristics 5.11 USB On-The-Go 5.12 ULPI Timing Specification Control and data timing requirements for the ULPI pins are given in Table 18. These timings apply in synchronous mode only. All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a 50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge. The ULPI interface on the MCF5329 processor is compliant with the industry standard definition. THD TSD THC TDD TSC TDC ULPI_CLK ULPI_STP (Input) ULPI_DATA (Input-8bit) ULPI_DIR/ULPI_NXT (Output) ULPI_DATA (Output-8bit) Figure 19. ULPI Timing Diagram Table 18. ULPI Interface Timing 5.13 Parameter Symbol Min Max Units Setup time (control in, 8-bit data in) TSC, TSD -- 3.0 ns Hold time (control in, 8-bit data in) THC, THD -1.5 -- ns Output delay (control out, 8-bit data out) TDC, TDD -- 6.0 ns SSI Timing Specifications This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync (SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below. Table 19. SSI Timing - Master Modes1 Num Description 2 S1 SSI_MCLK cycle time S2 SSI_MCLK pulse width high / low 3 S3 SSI_BCLK cycle time S4 SSI_BCLK pulse width S5 SSI_BCLK to SSI_FS output valid Symbol Min Max Units tMCLK 8 x tSYS -- ns 45% 55% tMCLK 8 x tSYS -- ns 45% 55% tBCLK -- 15 ns tBCLK MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 33 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 The MCF5329 device is compliant with industry standard USB 2.0 specification. Electrical Characteristics Num Description Symbol Min Max Units S6 SSI_BCLK to SSI_FS output invalid -2 -- ns S7 SSI_BCLK to SSI_TXD valid -- 15 ns S8 SSI_BCLK to SSI_TXD invalid / high impedence -4 -- ns S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 15 -- ns S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 -- ns 1 All timings specified with a capactive load of 25pF. SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK). 3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not exceed 4 x fSYS. 2 Table 20. SSI Timing - Slave Modes1 Num 1 Description Symbol Min Max Units tBCLK 8 x tSYS -- ns 45% 55% tBCLK S11 SSI_BCLK cycle time S12 SSI_BCLK pulse width high/low S13 SSI_FS input setup before SSI_BCLK 10 -- ns S14 SSI_FS input hold after SSI_BCLK 3 -- ns S15 SSI_BCLK to SSI_TXD/SSI_FS output valid -- 15 ns S16 SSI_BCLK to SSI_TXD/SSI_FS output invalid/high impedence -2 -- ns S17 SSI_RXD setup before SSI_BCLK 10 -- ns S18 SSI_RXD hold after SSI_BCLK 3 -- ns All timings specified with a capactive load of 25pF. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 34 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 19. SSI Timing - Master Modes1 (continued) Electrical Characteristics S1 S2 S2 SSI_MCLK (Output) SSI_BCLK (Output) S4 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 S3 S4 S5 S6 SSI_FS (Output) S9 S10 SSI_FS (Input) S7 S7 S8 S8 SSI_TXD S9 S10 SSI_RXD Figure 20. SSI Timing - Master Modes S11 SSI_BCLK (Input) S12 S12 S15 S16 SSI_FS (Output) S13 S14 SSI_FS (Input) S15 S16 S16 S15 SSI_TXD S17 S18 SSI_RXD Figure 21. SSI Timing - Slave Modes 5.14 I2C Input/Output Timing Specifications Table 21 lists specifications for the I2C input timing parameters shown in Figure 22. Table 21. I2C Input Timing Specifications between SCL and SDA Num Characteristic Min Max Units I1 Start condition hold time 2 -- tcyc I2 Clock low period 8 -- tcyc I3 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) -- 1 ms I4 Data hold time 0 -- ns MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 35 Electrical Characteristics Num Characteristic Min Max Units I5 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) -- 1 ms I6 Clock high time 4 -- tcyc I7 Data setup time 0 -- ns I8 Start condition setup time (for repeated start condition only) 2 -- tcyc I9 Stop condition setup time 2 -- tcyc Table 22 lists specifications for the I2C output timing parameters shown in Figure 22. Table 22. I2C Output Timing Specifications between SCL and SDA Num Characteristic Min Max Units I11 Start condition hold time 6 -- tcyc I2 1 Clock low period 10 -- tcyc I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) -- -- s I4 1 Data hold time 7 -- tcyc I5 3 I3 2 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) -- 3 ns I6 1 Clock high time 10 -- tcyc I7 1 Data setup time 2 -- tcyc I8 1 Start condition setup time (for repeated start condition only) 20 -- tcyc Stop condition setup time 10 -- tcyc I9 1 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 22. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 22 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 22 shows timing for the values in Table 22 and Table 21. I5 I6 I2 I2C_SCL I1 I4 I7 I8 I3 I9 I2C_SDA Figure 22. I2C Input/Output Timings MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 36 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 21. I2C Input Timing Specifications between SCL and SDA (continued) Electrical Characteristics 5.15 Fast Ethernet AC Timing Specifications 5.15.1 MII Receive Signal Timing The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FEC_RXCLK frequency. Table 23 lists MII receive channel timings. Table 23. MII Receive Signal Timing Num Characteristic Min Max Unit M1 FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup 5 -- ns M2 FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold 5 -- ns M3 FEC_RXCLK pulse width high 35% 65% FEC_RXCLK period M4 FEC_RXCLK pulse width low 35% 65% FEC_RXCLK period Figure 23 shows MII receive signal timings listed in Table 23. M3 FEC_RXCLK (input) M4 FEC_RXD[3:0] (inputs) FEC_RXDV FEC_RXER M1 M2 Figure 23. MII Receive Signal Timing Diagram 5.15.2 MII Transmit Signal Timing Table 24 lists MII transmit channel timings. The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FEC_TXCLK frequency. Table 24. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid 5 -- ns M6 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid -- 25 ns M7 FEC_TXCLK pulse width high 35% 65% FEC_TXCLK period M8 FEC_TXCLK pulse width low 35% 65% FEC_TXCLK period Figure 24 shows MII transmit signal timings listed in Table 24. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 37 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V. Electrical Characteristics M7 M5 M8 FEC_TXD[3:0] (outputs) FEC_TXEN FEC_TXER M6 Figure 24. MII Transmit Signal Timing Diagram 5.15.3 MII Async Inputs Signal Timing Table 25 lists MII asynchronous inputs signal timing. Table 25. MII Async Inputs Signal Timing Num M9 Characteristic FEC_CRS, FEC_COL minimum pulse width Min Max Unit 1.5 -- FEC_TXCLK period FEC_CRS FEC_COL M9 Figure 25. MII Async Inputs Timing Diagram 5.15.4 MII Serial Management Channel Timing Table 26 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 26. MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) 0 -- ns M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay) -- 25 ns M12 FEC_MDIO (input) to FEC_MDC rising edge setup 10 -- ns M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 -- ns M14 FEC_MDC pulse width high 40% 60% FEC_MDC period M15 FEC_MDC pulse width low 40% 60% FEC_MDC period MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 38 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 FEC_TXCLK (input) Electrical Characteristics M14 M15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 FEC_MDC (output) M10 FEC_MDIO (output) M11 FEC_MDIO (input) M12 M13 Figure 26. MII Serial Management Channel Timing Diagram 5.16 32-Bit Timer Module Timing Specifications Table 27 lists timer module AC timings. Table 27. Timer Module AC Timing Specifications Name 5.17 Characteristic Min Max Unit T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 -- tCYC T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 -- tCYC QSPI Electrical Specifications Table 28 lists QSPI timings. Table 28. QSPI Modules AC Timing Specifications Name Characteristic Min Max Unit QS1 QSPI_CS[3:0] to QSPI_CLK 1 510 tCYC QS2 QSPI_CLK high to QSPI_DOUT valid. -- 10 ns QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold) 2 -- ns QS4 QSPI_DIN to QSPI_CLK (Input setup) 9 -- ns QS5 QSPI_DIN to QSPI_CLK (Input hold) 9 -- ns MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 39 Electrical Characteristics QS1 QSPI_CLK QS2 QSPI_DOUT QS3 QS4 QS5 QSPI_DIN Figure 27. QSPI Timing 5.18 JTAG and Boundary Scan Timing Table 29. JTAG and Boundary Scan Timing Characteristics1 Num 1 Symbol Min Max Unit J1 TCLK Frequency of Operation fJCYC DC 1/4 fsys/3 J2 TCLK Cycle Period tJCYC 4 -- tCYC J3 TCLK Clock Pulse Width tJCW 26 -- ns J4 TCLK Rise and Fall Times tJCRF 0 3 ns J5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 4 -- ns J6 Boundary Scan Input Data Hold Time after TCLK Rise tBSDHT 26 -- ns J7 TCLK Low to Boundary Scan Output Data Valid tBSDV 0 33 ns J8 TCLK Low to Boundary Scan Output High Z tBSDZ 0 33 ns J9 TMS, TDI Input Data Setup Time to TCLK Rise tTAPBST 4 -- ns J10 TMS, TDI Input Data Hold Time after TCLK Rise tTAPBHT 10 -- ns J11 TCLK Low to TDO Data Valid tTDODV 0 26 ns J12 TCLK Low to TDO High Z tTDODZ 0 8 ns J13 TRST Assert Time tTRSTAT 100 -- ns J14 TRST Setup Time (Negation) to TCLK High tTRSTST 10 -- ns JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 40 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 QSPI_CS[3:0] Electrical Characteristics J2 J3 J3 TCLK (input) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 VIH VIL J4 J4 Figure 28. Test Clock Input Timing TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 29. Boundary Scan (JTAG) Timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 30. Test Access Port Timing TCLK J14 TRST J13 Figure 31. TRST Timing MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 41 Current Consumption 5.19 Debug AC Timing Specifications Table 30 lists specifications for the debug AC timing parameters shown in Figure 32. Num 1 Characteristic Min Max Units D0 PSTCLK cycle time 2 2 tSYS = 1/fSYS D1 PSTCLK rising to PSTDDATA valid -- 3.0 ns D2 PSTCLK rising to PSTDDATA invalid 1.5 -- ns D3 DSI-to-DSCLK setup 1 -- PSTCLK D41 DSCLK-to-DSO hold 4 -- PSTCLK D5 DSCLK cycle time 5 -- PSTCLK D6 BKPT assertion time 1 -- PSTCLK DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK. D0 PSTCLK D2 D1 PSTDDATA[7:0] Figure 32. Real-Time Trace AC Timing D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 33. BDM Serial Port AC Timing 6 Current Consumption All current consumption data is lab data measured on a single device using an evaluation board. Table 31 shows the typical power consumption in low-power modes. These current measurements are taken after executing a STOP instruction. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 42 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 30. Debug AC Timing Specification Current Consumption Table 31. Current Consumption in Low-Power Modes1,2 Stop Mode 3 (Stop 11)5 Stop Mode 2 (Stop 10)4 Stop Mode 1(Stop 01)4 Voltage 58 MHz (Typ)3 64 MHz (Typ)3 72 MHz (Typ)3 80 MHz (Typ)3 80 MHz (Peak)4 3.3 V 3.9 3.92 4.0 4.0 4.0 1.5 V 1.04 1.04 1.04 1.04 1.08 3.3 V 4.69 4.72 4.8 4.8 4.8 1.5 V 2.69 2.69 2.70 2.70 2.75 3.3 V 4.72 4.73 4.81 4.81 4.81 1.5 V 15.28 16.44 17.85 19.91 20.42 3.3 V 21.65 21.68 24.33 26.13 26.16 1.5 V 15.47 16.63 18.06 20.12 20.67 3.3 V 22.49 22.52 25.21 27.03 39.8 1.5 V 26.79 28.85 30.81 34.47 97.4 3.3 V 33.61 33.61 42.3 50.5 62.6 1.5 V 56.3 60.7 65.4 73.4 132.3 Units Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Mode mA Stop Mode 0 (Stop 00)4 Wait/Doze Run 1 2 3 4 5 All values are measured with a 3.30V EVDD, 3.30V SDVDD and 1.5V IVDD power supplies. Tests performed at room temperature with pins configured for high drive strength. Refer to the Power Management chapter in the MCF532x Reference Manual for more information on low-power modes. All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port off before entering low power mode. All code executed from flash. All peripheral clocks on before entering low power mode. All code is executed from flash. See the description of the low-power control register (LCPR) in the MCF532x Reference Manual for more information on stop modes 0-3. Power Consumption (mW) 450 400 350 Stop 0 - Flash 300 Stop 1 - Flash 250 Stop 2 - Flash 200 Stop 3 - Flash 150 Wait/Doze - Flash 100 Run - Flash 50 0 58 64 72 80 80(peak) fsys/3 (MHz) Figure 34. Current Consumption in Low-Power Modes MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 43 Current Consumption Table 32. Typical Active Current Consumption Specifications1 Voltage Typical2 Active (Flash) Peak3 3.3V 7.73 7.74 1.5V 2.87 3.56 3.3V 8.57 8.60 1.5V 4.37 5.52 3.3V 40.10 49.3 1.5V 65.90 91.70 3.3V 44.40 54.0 1.5V 69.50 97.0 3.3V 53.6 63.7 1.5V 74.6 104.7 3.3V 63.0 73.7 1.5V 79.6 112.9 Unit 1.333 MHz 2.666 MHz 58 MHz mA 64 MHz 72 MHz 80 MHz 1 All values are measured with a 3.30 V EVDD, 3.30 V SDVDD and 1.5 V IVDD power supplies. Tests performed at room temperature with pins configured for high drive strength. 2 CPU polling a status register. All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port disabled. 3 Peak current measured while running a while(1) loop with all modules active. Figure 35 shows the estimated maximum power consumption. Estimated Power Consumption vs. Core Frequency Power Consumption (mW) 300 250 200 150 100 50 0 0 40 80 120 160 Core Frequency (MHz) 200 240 Figure 35. Estimated Maximum Power Consumption MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 44 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 fsys/3 Frequency Package Information 7 Package Information This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF532x devices. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 NOTE The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire. 7.1 Package Dimensions--256 MAPBGA Figure 36 shows MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 package dimensions. X D M Laser mark for pin A1 identification in this area Y 5 K A 0.30 Z A2 A1 256X Z E 4 0.15 Z Detail K Rotated 90 Clockwise Top View 0.20 15X e S 15 13 11 16 14 12 10 15X e 3. Metalized mark for pin A1 identification in this area 7654321 4. A B C D E F G H J K L M N P R T S Notes: 1. 2. M 5. 256X b 3 0.25 M Z X Y 0.10 M Z Bottom View View M-M Dimensions are in millimeters. Interpret dimensions and tolerances per ASME Y14.5M, 1994. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. Parallelism measurement shall exclude any effect of mark on top surface of package. Dim A A1 A2 b D E e S Millimeters Min Max 1.25 1.60 0.27 0.47 1.16 REF 0.40 0.60 17.00 BSC 17.00 BSC 1.00 BSC 0.50 BSC Figure 36. 256 MAPBGA Package Outline MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 45 Package Information 7.2 Package Dimensions--196 MAPBGA NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension B is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. D X Laser mark for pin 1 identification in this area Y M K Millimeters DIM Min Max E A A1 A2 b D E e S 1.32 1.75 0.27 0.47 1.18 REF 0.35 0.65 15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC M Top View 0.20 13X e S 14 13 12 11 10 9 6 5 4 3 2 Metalized mark for pin 1 identification in this area 1 A B C S 13X e D 5 E 0.30 Z F A A2 G H J K L M A1 Z 0.15 Z 4 Detail K Rotated 90 Clockwise N P 3 196X b 0.30 Z X Y Bottom View View M-M 0.10 Z Figure 37. 196 MAPBGA Package Dimensions (Case No. 1128A-01) MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 46 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Figure 37 shows the MCF5327CVM240 package dimensions. Revision History 8 Revision History Table 33. MCF5329DS Document Revision History 0 Substantive Changes Date of Release * Initial release. 11/2005 0.1 * Added not to Section 7, "Package Information." * Added top view and bottom view where appropriate in mechanical drawings and pinout figures. * Figure 6: Corrected "FB_CLK (75MHz)" label to "FB_CLK (80MHz)" 3/2006 1 * Corrected MCF5327 196MAPBGA ball map locations in Table 5 for the following signals: RCON, D1, D0, OE, R/W, SD_DQS2, PSTCLK, DDATA[3:0], PST[3:0], EVDD, IVDD, and SD_VDD. Figure 5 was correct. * Updated thermal characteristic values in Table 5. * Updated DC electricals values in Table 7. * Updated Section 3.3, "Supply Voltage Sequencing and Separation Cautions" and subsections. * Updated and added Oscillator/PLL characteristics in Table 8. * Table 9: Swapped min/max for FB1; Removed FB8 & FB9. * Updated SDRAM write timing diagram, Figure 9. * Table 11: Added values for frequency of operation and DD1. * Reworded first paragraph in Section 5.12, "ULPI Timing Specification." * Updated Figure 19. * Replaced figure & table Section 5.13, "SSI Timing Specifications," with slave & master mode versions. * Removed second sentence from Section 5.15.2, "MII Transmit Signal Timing," regarding no minimum frequency requirement for TXCLK. * Removed third and fourth paragraphs from Section 5.15.2, "MII Transmit Signal Timing," as this feature is not supported on this device. * Updated figure & table Section 5.19, "Debug AC Timing Specifications." * Renamed & moved previous version's Section 5.5 "Power Consumption" to Section 6, "Current Consumption." Added additional real-world data to this section as well. 7/2007 2 * Added MCF53281 device information throughout: features list, family configuration table, ordering information table, signals description table, and relevant package diagram titles * Remove Footnote 1 from Table 11. * Changed document type from Advance Information to Technical Data. 8/2007 3 * Corrected MCF53281 in features list table. This device contains CAN, but does not feature the cryptography accelerators. * In pin-multiplexing table, moved MCF53281 label from the MCF5328 column to the MCF5329 column, because this device contains CAN output signals. 10/2007 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Rev. No. MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor 47 Revision History Rev. No. Substantive Changes Date of Release 4 * Corrected pinouts in Signal Information and Pin-Muxing table for 196 MAPBGA device: Changed D[15:1] entry from "F4-F1, G4-G2..." to "F4-F1, G5-G2..." Changed DSO/TDO entry from "P9" to "N9" * Corrected D0 spec in Table 30 from 1.5 x tsys to 2 x tsys for min and max balues. * Updated FlexBus read and write timing diagrams in Figure 7 and Figure 8. * Removed footnote 2 from the IRQ[7:1] alternate functions USBHOST VBUS_EN, USBHOST VBUS_OC, SSI_MCLK, USB_CLKIN, and SSI_CLKIN signals in Signal Information and Pin-Muxing table. * Updated pinouts for 196 MAPBGA device, MCF5327CVM240 in both Figure 5 and Table 2. The following locations are affected: G10-12, H12-14, J11-14, K12-13, L12-13, M12-14, N13. The following signals are affected: USBOTG_VDD, USBHOST_VSS, USBOTG_M, USBOTG_P, USBHOST_M, USBHOST_P, DRAMSEL, PWM3, PWM1, IRQ[7,4,3,2,1], RESET, TDI/DSI, JTAG_EN, TMS/BKPT. 4/2008 5 Changed the following specs in Table 10 and Table 11: * Minimum frequency of operation from TBD to 60MHz * Maximum clock period from TBD to 16.67 ns 11/2008 MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 48 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Table 33. MCF5329DS Document Revision History (continued) MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 5 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240 Revision History 49 Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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