MCF53281CVM240 - Freescale Semiconductor, Inc.

Freescale Semiconductor

Data Sheet: Technical Data Document Number: MCF5329DS

Rev. 5, 11/2008

MCF5329

MAPBGA–256

17mm x 17mm MAPBGA–196

15mm x 15mm

Features

• Versio n 3 Col d Fire variable-length RISC processor core

• System debug support

• JTAG support for system level bo a rd testing

• On-chip memories

– 16-Kbyte unified write-back cache

– 32-Kbyte dual-ported SRAM on CPU internal bus,

accessible by core and non-core bus masters (e.g., DMA,

FEC, LCD controller, and USB host and OTG)

• Power management

• Liquid Crystal Display C ontrol ler (LCDC)

• Embedded Voice-over-IP (VoIP) system solution

• SDR/DDR SDRAM Controller

• Universal Serial Bus (USB) Host Controller

• Universal Serial Bus (US B) On-the-Go (OTG) controller

• Synchronous Serial Interface (SSI)

• Fast Ethernet Controller (FEC)

• Cryptography Hardware Accelerators

• FlexCAN Module

• Three Universal Asynchronous Receiver Tr ansmitters

(UARTs)

•I

2C Module

• Queued Serial Peripheral Interface (QSPI)

• Pulse Width Modulation (PWM) module

• Real Time Clock

• Four 32-bit DMA Timers

• Software Watchdog Timer

• Four Periodic In terr upt Timers (PITs)

• Phase Locked Loop (PLL)

• Interrupt Controllers (x2)

• DMA Controller

• FlexBus (External Interface)

• Chip Configuration Module (CCM)

• Reset Controller

• General Purpose I/O interface

MCF532x ColdFire®

Microprocessor Data Sheet

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor2

Table of Contents

1MCF532x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5

3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.3 Supply Voltage Sequencing and Separation Cautions . .5

3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5

3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6

4 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6

4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .14

4.3 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15

5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17

5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .18

5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .19

5.6 External Interface Timing Characteristics. . . . . . . . . . .20

5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .23

5.7.2 DDR SDRAM AC Timing Characteristics. . . . . 25

5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 28

5.9 Reset and Configuration Override Timing . . . . . . . . . . 29

5.10 LCD Controller Timing Specifications . . . . . . . . . . . . . 30

5.11 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.12 ULPI Timing Specification . . . . . . . . . . . . . . . . . . . . . . 33

5.13 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 33

5.14 I2C Input/Output Timing Specifications . . . . . . . . . . . . 35

5.15 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 37

5.15.1 MII Receive Signal Timing . . . . . . . . . . . . . . . . 37

5.15.2 MII Transmit Signal Timing. . . . . . . . . . . . . . . . 37

5.15.3 MII Async Inputs Signal Timing . . . . . . . . . . . . 38

5.15.4 MII Serial Management Channel Timing . . . . . 38

5.16 32-Bit Timer Module Timing Specifications. . . . . . . . . 39

5.17 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . 39

5.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40

5.19 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . 42

6 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.1 Package Dimensions—256 MAPBGA. . . . . . . . . . . . . 45

7.2 Package Dimensions—196 MAPBGA. . . . . . . . . . . . . 46

8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Family Comparison

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 3

Figure 1. MCF5329 Block Diagram

1 MCF532x Family Comparison

The following table compares the various device derivatives avail a ble wit hin the MCF532x family.

Table 1. MCF532x Fa mily Configurations

Module MCF5327 MCF5328 MCF53281 MCF5329

ColdFire Version 3 Core with EMAC

(Enhanced Multiply-Accumulate Unit) ••••

Core (System) Clock up to 240 MHz

Peripheral and External Bus Clock

(Core clock ÷ 3) up to 80 MHz

Performance (Dhrystone/2.1 MIPS) up to 211

Unified Cache 16 Kbytes

Static RAM (SRAM) 32 Kbytes

FlexBus

D[31:0]

A[23:0]

R/W

CS[5:0]

XBS

M1 M0

PWMs, EPORT,

JTAG

TAP

TRST

TCLK

TMS

TDI

TDO

Cache

(1024x32)x4

DMA

UARTs

FlexCAN I2CQSPI

DMA Timers

Watchdog, PITs

PADI — Pin Muxing

EXTAL

XTAL

CLKOUT

16 KByte

Chip

External

Selects

(To/From PADI)

CANTX

CANRX

FEC

DMA Timer

SDRAMC

UART

I2C

SDRAMC

QSPI

JTAG_EN

RTC

USB Host

LCDC

Reset

PORTS

SDRAMC

SSI

LCDC

USB OTG

RESET

SRAM

(4096x32)x2

32 KByte

PLL

SDRAMC

USB Host

USB OTG

ULPI Interface

INTC0

INTC1

RCON

LCDC

SSI

V3 ColdFire CPU

DIV EMAC

BDM

(To/Fr om PA D I)

RNGA

SKHA

MDHA

Cryptography

Modules

Interface

RSTOUT

EXTAL32K

XTAL32K

(To/From SRAM backdoor)

(To/From XBS backdoor)

DREQn

DACKn

(To/From PADI)

USB Host

USB OTG

BE/BWE[3:0]

PWM

XCVR XCVR

(To/Fr om PA D I)

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Ordering Information

Freescale Semiconductor4

2 Ordering Information

LCD Controller • • • •

SDR/DDR SDRAM Controller • • • •

USB 2.0 Host • • • •

USB 2.0 On-the-Go • • • •

UTMI+ Low Pin Interface (ULPI) — • • •

Synchronous Serial Interf ace (SSI) • • • •

Fast Ethernet Controller (FEC) — • • •

Cryptogr aphy Hardware Accelerators — — — •

Embedded Voice-over-IP System Solution — — • —

FlexCAN 2.0B communication module — — • •

UARTs 3333

I2C ••••

QSPI • • • •

PWM Module • • • •

Real Time Clock • • • •

32-bit DMA Timers 4444

Watchdog Timer (WDT) • • • •

Periodic Interrupt Timers (PIT) 4444

Edge Port Module (EPORT) • • • •

Interrupt Controllers (INTC) 2222

16-channel Direct Memory Access (DMA) • • • •

FlexBus External Interface • • • •

General Purpose I/O Module (GPIO) • • • •

JTAG - IEEE® 1149.1 Test Access Port • • • •

Package 196

MAPBGA 256

MAPBGA

Table 2. Orderable Part Numbers

Freescale Part

Number Description Package Speed Temperature

MCF5327CVM240 MCF5327 RISC Microprocessor 196 MAPBGA 240 MHz –40° to +85° C

MCF5328CVM240 MCF5328 RISC Microprocessor 256 MAPBGA 240 MHz –40° to +85° C

MCF53281CVM240 MCF53281 RISC Microprocessor 256 MAPBGA 240 MHz –40° to +85° C

MCF5329CVM240 MCF5329 RISC Microprocessor 256 MAPBGA 240 MHz –40° to +85° C

Table 1. MCF532x Family Configurations (continued)

Module MCF5327 MCF5328 MCF53281 MCF5329

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Hardware Design Considerations

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 5

3 Hardware Design Considerations

3.1 PLL Power Filtering

To further enhance no ise is olati on, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in

Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as

close to the dedicated PLLVDD pin as possible.

Figure 2. System PLL VDD Power Filter

3.2 USB Power Filtering

To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be

connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as

close to the dedicated USBVDD pin as possible.

Figure 3. USB VDD Power Filter

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel

with those shown.

3.3 Supply Voltage Sequencing and Separation Cautions

The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V o r

3.3V) and EVDD are specified relative to IVDD.

3.3.1 Power Up Sequence

If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to

the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD

must pow ered up . I VDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is

Board IVDD 10 Ω

0.1 µF

PLL VDD Pin

10 µF

GND

Board EVDD 0 Ω

0.1 µF

USB VDD Pin

10 µF

GND

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Pin Assignments and Reset States

Freescale Semiconductor6

high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid

turning on the internal ESD protection clamp diodes.

3.3.2 Power Down Sequence

If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.

There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should

not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is undesired high current in the

ESD protection diodes. There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IVDD/PLLVDD to 0 V.

2. Drop EVDD/SDVDD supplies.

4 Pin Assignments and Reset States

4.1 Signal Multiplexing

The following table lists all the MCF532x pins grouped by function. The Dir column is the direction for the primary func tio n

of the pin only. Refer to Section 7, “Package Information,” for package diagrams. For a more detailed discussion of the

MCF532x signals, consult the MCF5329 Reference Manual (MCF5329RM).

NOTE

In this table and throughout th is document, a single signal within a group is designat ed

without square brackets (i.e., A23), while designations for multiple signals within a group

use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed

numbers when these numbers are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality. Pins that are

muxed with GPIO default to their GPIO functionali ty.

Table 3. MCF5327/8/9 Signal Information and Muxing

Signal Name GPIO Alternate 1 Alternate 2

Dir.1

Voltage

Domain

MCF5327

196

MAPBGA

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

Reset

RESET2— — — I EVDD J11 N15 N15

RSTOUT — — — O EVDD P14 P14 P14

Clock

EXTAL — — — I EVDD L14 P16 P16

XTAL2— — — O EVDD K14 N16 N16

EXTAL32K — — — I EVDD M11 P13 P13

XTAL32K — — — O EVDD N11 R13 R13

FB_CLK — — — O SDVDD L1 T2 T2

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Pin Assignments and Res et States

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 7

Mode Selection

RCON2— — — I EVDD M7 M8 M8

DRAMSEL — — — I EVDD G11 H12 H12

FlexBus

A[23:22] — FB_CS[5:4] — O SDVDD B11,C11 C13, D13 C13, D13

A[21:16] — — — O SDVDD B12, A12,

D11, C12,

B13, A13

E13, A14,

B14, C14,

A15, B15

E13, A14,

B14, C14,

A15, B15

A[15:14] — SD_BA[1:0]3—O

SDVDD A14, B14 D14, B16 D14, B16

A[13:11] — SD_A[13:11]3—O

SDVDD C13, C14,

D12 C15, C16,

D15 C15, C16,

D15

A10 — — — O SDVDD D13 D16 D16

A[9:0] — SD_A[9:0]3—O

SDVDD D14,

E11–14,

F11–F14,

G14

E14–E16,

F13–F16,

G16– G14

E14–E16,

F13–F16,

G16– G14

D[31:16] —SD_D[31:16]4—I/O SDVDD H3–H1,

J4–J1, K1,

L4, M2, M3,

N1, N2, P1,

P2, N3

M1–M4,

N1–N4, T3,

P4, R4, T4,

N5, P5, R5,

M1–M4,

N1–N4, T3,

P4, R4, T4,

N5, P5, R5,

D[15:1] —FB_D[31:17]4—I/O SDVDD F4–F1,

G5–G2, L5,

N4, P4, M5,

N5, P5, L6

J3–J1,

K4–K1, L2,

R6, N7, P7,

R7, T7, P8,

J3–J1,

K4–K1, L2,

R6, N7, P7,

R7, T7, P8,

D02—FB_D[16]4—I/O SDVDD M6 T8 T8

BE/BWE[3:0] PBE[3:0] SD_DQM[3:0]3— O SDVDD H4, P3, G1,

M4 L4, P6, L3,

N6 L4, P6, L3,

OE PBUSCTL3 — — O SDVDD P6 R9 R9

TA2PBUSCTL2 — — I SDVDD G13 G13 G13

R/W PBUSCTL1 — — O SDVDD N6 N8 N8

TS PBUSCTL0 DACK0 —O

SDVDD D2 H4 H4

Chip Selects

FB_CS[5:4] PCS[5:4] — — O SDVDD — B13, A13 B13, A13

FB_CS[3:1] PCS[3:1] O SDVDD A11, D10,

C10 A12, B12,

C12 A12, B12,

C12

FB_CS0 ———O

SDVDD B10 D12 D12

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Dir.1

Voltage

Domain

MCF5327

196

MAPBGA

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Pin Assignments and Reset States

Freescale Semiconductor8

SDRAM Controller

SD_A10 — — — O SDVDD L2 P2 P2

SD_CKE — — — O SDVDD E1 H2 H2

SD_CLK — — — O SDVDD K3 R1 R1

SD_CLK ———O

SDVDD K2 R2 R2

SD_CS1 ———O

SDVDD —J4 J4

SD_CS0 ———O

SDVDD E2 H1 H1

SD_DQS3 — — — O SDVDD H5 L1 L1

SD_DQS2 — — — O SDVDD K6 T6 T6

SD_SCAS ———O

SDVDD L3 P3 P3

SD_SRAS ———O

SDVDD M1 R3 R3

SD_SDR_DQS — — — O SDVDD K4 P1 P1

SD_WE ———O

SDVDD D1 H3 H3

External Interrupts Port5

IRQ72PIRQ72— — I EVDD J13 J13 J13

IRQ62PIRQ62USBHOST_

VBUS_EN — I EVDD —J14 J14

IRQ52PIRQ52USBHOST_

VBUS_OC — I EVDD —J15 J15

IRQ42PIRQ42SSI_MCLK — I EVDD L13 J16 J16

IRQ32PIRQ32— — I EVDD M14 K14 K14

IRQ22PIRQ22USB_CLKIN — I EVDD M13 K15 K15

IRQ12PIRQ12DREQ12SSI_CLKIN IEVDD N13 K16 K16

FEC

FEC_MDC PFECI2C3 I2C_SCL2— O EVDD —C1 C1

FEC_MDIO PFECI2C2 I2C_SDA2—I/O EVDD —C2 C2

FEC_TXCLK PFECH7 — — I EVDD —A2 A2

FEC_TXEN PFECH6 — — O EVDD —B2 B2

FEC_TXD0 PFECH5 ULPI_DATA0 — O EVDD —E4 E4

FEC_COL PFECH4 ULPI_CLK — I EVDD —A8 A8

FEC_RXCLK PFECH3 ULPI_NXT — I EVDD —C8 C8

FEC_RXDV PFECH2 ULPI_STP — I EVDD —D8 D8

FEC_RXD0 PFECH1 ULPI_DATA4 — I EVDD —C6 C6

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Dir.1

Voltage

Domain

MCF5327

196

MAPBGA

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Pin Assignments and Res et States

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 9

FEC_CRS PFECH0 ULPI_DIR — I EVDD —B8 B8

FEC_TXD[3:1] PFECL[7:5] ULPI_DATA[3:1] — O EVDD —D3–D1 D3–D1

FEC_TXER PFECL4 — — O EVDD —B1 B1

FEC_RXD[3:1] PFECL[3:1] ULPI_DATA[7:5] — I EVDD —E7, A6, B6 E7, A6, B6

FEC_RXER PFECL0 — — I EVDD —D4 D4

LCD Controller

LCD_D17 PLCDDH1 CANTX — O EVDD — — C9

LCD_D16 PLCDDH0 CANRX — O EVDD — — D9

LCD_D17 PLCDDH1 — — O EVDD A6 C9 —

LCD_D16 PLCDDH0 — — O EVDD B6 D9 —

LCD_D15 PLCDDM7 — — O EVDD C6 A7 A7

LCD_D14 PLCDDM6 — — O EVDD D6 B7 B7

LCD_D13 PLCDDM5 — — O EVDD A5 C7 C7

LCD_D12 PLCDDM4 — — O EVDD B5 D7 D7

LCD_D[11:8] PLCDDM[3:0] — — O EVDD C5, D5, A4,

B4 D6, E6, A5,

B5 D6, E6, A5,

LCD_D7 PLCDDL7 — — O EVDD C4 C5 C5

LCD_D6 PLCDDL6 — — O EVDD B3 D5 D5

LCD_D5 PLCDDL5 — — O EVDD A3 A4 A4

LCD_D4 PLCDDL4 — — O EVDD A2 A3 A3

LCD_D[3:0] PLCDDL[3:0] — — O EVDD D4, C3, D3,

B2 B4, C4, B3,

C3 B4, C4, B3,

LCD_ACD/

LCD_OE PLCDCTLH0 — — O EVDD D7 B9 B9

LCD_CLS PLCDCTLL7 — — O EVDD C7 A9 A9

LCD_CONTRAST PLCDCTLL6 — — O EVDD B7 D10 D10

LCD_FLM/

LCD_VSYNC PLCDCTLL5 — — O EVDD A7 C10 C10

LCD_LP/

LCD_HSYNC PLCDCTLL4 — — O EVDD A8 B10 B10

LCD_LSCLK PLCDCTLL3 — — O EVDD B8 A10 A10

LCD_PS PLCDCTLL2 — — O EVDD C8 A11 A11

LCD_REV PLCDCTLL1 — — O EVDD D8 B11 B11

LCD_SPL_SPR PLCDCTLL0 — — O EVDD B9 C11 C11

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Dir.1

Voltage

Domain

MCF5327

196

MAPBGA

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Pin Assignments and Reset States

Freescale Semiconductor10

USB Host & USB On-the-Go

USBOTG_M — — — I/O USB

VDD G12 L15 L15

USBOTG_P — — — I/O USB

VDD H13 L16 L16

USBHOST_M — — — I/O USB

VDD K13 M15 M15

USBHOST_P — — — I/O USB

VDD J12 M16 M16

FlexCAN (MCF53281 & MCF5329 only)

CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:

I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX.

PWM

PWM7 PPWM7 — — I/O EVDD —H13 H13

PWM5 PPWM5 — — I/O EVDD —H14 H14

PWM3 PPWM3 DT3OUT DT3IN I/O EVDD H14 H15 H15

PWM1 PPWM1 DT2OUT DT2IN I/O EVDD J14 H16 H16

SSI

SSI_MCLK PSSI4 — — I/O EVDD —G4 G4

SSI_BCLK PSSI3 U2CTS PWM7 I/O EVDD —F4 F4

SSI_FS PSSI2 U2RTS PWM5 I/O EVDD —G3 G3

SSI_RXD2PSSI1 U2RXD CANRX IEVDD — — G2

SSI_TXD2PSSI0 U2TXD CANTX OEVDD — — G1

SSI_RXD2PSSI1 U2RXD — I EVDD —G2 —

SSI_TXD2PSSI0 U2TXD — O EVDD —G1 —

I2C

I2C_SCL2PFECI2C1 CANTX U2TXD I/O EVDD — — F3

I2C_SDA2PFECI2C0 CANRX U2RXD I/O EVDD — — F2

I2C_SCL2PFECI2C1 —U2TXD I/O EVDD E3 F3 —

I2C_SDA2PFECI2C0 —U2RXD I/O EVDD E4 F2 —

DMA

DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:

TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Dir.1

Voltage

Domain

MCF5327

196

MAPBGA

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Pin Assignments and Res et States

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 11

QSPI

QSPI_CS2 PQSPI5 U2RTS — O EVDD P10 T12 T12

QSPI_CS1 PQSPI4 PWM7 USBOTG_

PU_EN OEVDD L11 T13 T13

QSPI_CS0 PQSPI3 PWM5 — O EVDD —P11 P11

QSPI_CLK PQSPI2 I2C_SCL2— O EVDD N10 R12 R12

QSPI_DIN PQSPI1 U2CTS — I EVDD L10 N12 N12

QSPI_DOUT PQSPI0 I2C_SDA — O EVDD M10 P12 P12

UARTs

U1CTS PUARTL7 SSI_BCLK — I EVDD C9 D11 D11

U1RTS PUARTL6 SSI_FS — O EVDD D9 E10 E10

U1TXD PUARTL5 SSI_TXD2— O EVDD A9 E11 E11

U1RXD PUARTL4 SSI_RXD2— I EVDD A10 E12 E12

U0CTS PUARTL3 — — I EVDD P13 R15 R15

U0RTS PUARTL2 — — O EVDD N12 T15 T15

U0TXD PUARTL1 — — O EVDD P12 T14 T14

U0RXD PUARTL0 — — I EVDD P11 R14 R14

Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins.

DMA Timers

DT3IN PTIMER3 DT3OUT U2RXD IEVDD C1 F1 F1

DT2IN PTIMER2 DT2OUT U2TXD IEVDD B1 E1 E1

DT1IN PTIMER1 DT1OUT DACK1 IEVDD A1 E2 E2

DT0IN PTIMER0 DT0OUT DREQ02IEVDD C2 E3 E3

BDM/JTAG6

JTAG_EN7— — — I EVDD L12 M13 M13

DSCLK —TRST2— I EVDD N14 P15 P15

PSTCLK —TCLK2— O EVDD L7 T9 T9

BKPT —TMS2— I EVDD M12 R16 R16

DSI —TDI2— I EVDD K12 N14 N14

DSO —TDO — O EVDD N9 N11 N11

DDATA[3:0] — — — O EVDD N7, P7, L8,

M8 N9, P9, N10,

P10 N9, P9, N10,

P10

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Dir.1

Voltage

Domain

MCF5327

196

MAPBGA

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Pin Assignments and Reset States

Freescale Semiconductor12

PST[3:0] — — — O EVDD N8, P8, L9,

M9 R10, T10,

R11, T11 R10, T10,

R11, T11

Test

TEST7— — — I EVDD E10 A16 A16

PLL_TEST8— — — I EVDD —N13 N13

Power Supplies

EVDD — — — — — E6, E7,

F5–F7, H9,

J8, J9, K8,

K9, K11

E8, F5–F8,

G5, G6, H5,

H6, J11,

K11, K12,

L9–L11, M9,

M10

E8, F5–F8,

G5, G6, H5,

H6, J11,

K11, K12,

L9–L11, M9,

M10

IVDD — — — — — E5, K5, K10,

J10 E5, G12, M5,

M11, M12 E5, G12, M5,

M11, M12

PLL_VDD — — — — — H10 J12 J12

SD_VDD — — — — — E8, E9,

F8–F10,

J5–J7, K7

E9, F9–F11,

G11, H11,

J5, J6, K5,

K6, L5–L8,

M6, M7

E9, F9–F11,

G11, H11,

J5, J6, K5,

K6, L5–L8,

M6, M7

USB_VDD — — — — — G10 L14 L14

VSS — — — — — G6–G9,

H6–H8, P9 G7–G10,

H7–H10,

J7–10,

K7–K10,

L12, L13

G7–G10,

H7–H10,

J7–10,

K7–K10,

L12, L13

PLL_VSS — — — — — H11 K13 K13

USB_VSS — — — — — H12 M14 M14

1Refers to pin’s primary functio n.

2Pull-up enabled internally on this signal for this mode.

3The SDRAM functions of these signals are not programmab le by the user . The y are dynamically switched by the processor

when accessing SDRAM memory space and ar e included here for completeness.

4Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating

the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

5GPIO functionality is determined by the edge port module. The GPIO module is only responsible f or assigning the alternate

functions.

6If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for

assigning these pins.

7Pull-down enabled internally on this signal for this mode.

8Must be left floating for proper operation of the PLL.

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Dir.1

Voltage

Domain

MCF5327

196

MAPBGA

MCF5328

256

MAPBGA

MCF53281

MCF5329

256

MAPBGA

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Pin Assignments and Res et States

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 13

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Pin Assignments and Reset States

Freescale Semiconductor14

NOTE

4.2 Pinout—256 MAPBGA

Figure 4 shows a pinout of the MCF5328CVM240, MCF5328 1CVM240, and MCF5329CVM240 devices.

NOTE

The pin at location N13 (PLL_TEST) mu st be left floating or improper operation of the

PLL module occurs.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ANC FEC_

TXCLK LCD_

D4 LCD_

D5 LCD_

D9 FEC_

RXD2 LCD_

D15 FEC_

COL LCD_

CLS LCD_

LSCLK LCD_

PS FB_CS3 FB_CS4 A20 A17 TEST A

BFEC_

TXER FEC_

TXEN LCD_

D1 LCD_

D3 LCD_

D8 FEC_

RXD1 LCD_

D14 FEC_

CRS LCD_

ACD/OE LCD_LP/

HSYNC LCD_

REV FB_CS2 FB_CS5 A19 A16 A14 B

CFEC_

MDC FEC_

MDIO LCD_

D0 LCD_

D2 LCD_

D7 FEC_

RXD0 LCD_

D13 FEC_

RXCLK LCD_

D17 LCD_FLM/

VSYNC LCD_

SPL_SPR FB_CS1 A23 A18 A13 A12 C

DFEC_

TXD1 FEC_

TXD2 FEC_

TXD3 FEC_

RXER LCD_

D6 LCD_

D11 LCD_

D12 FEC_

RXDV LCD_

D16 LCD_CON

TRAST U1CTS FB_CS0 A22 A15 A11 A10 D

EDT2IN DT1IN DT0IN FEC_

TXD0 IVDD LCD_

D10 FEC_

RXD3 EVDD SD_VDD U1RTS U1TXD U1RXD A21 A9 A8 A7 E

FDT3IN I2C_

SDA I2C_

SCL SSI_

BCLK EVDD EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD NC A6 A5 A4 A3 F

GSSI_

TXD SSI_

RXD SSI_FS SSI_

MCLK EVDD EVDD VSS VSS VSS VSS SD_VDD IVDD TA A0 A1 A2 G

HSD_

CS0 SD_CKE SD_WE TS EVDD EVDD VSS VSS VSS VSS SD_VDD DRAM

SEL PWM7 PWM5 PWM3 PWM1 H

JD13 D14 D15 SD_CS1 SD_VDD SD_VDD VSS VSS VSS VSS EVDD PLL_

VDD IRQ7 IRQ6 IRQ5 IRQ4 J

KD9 D10 D11 D12 SD_VDD SD_VDD VSS VSS VSS VSS EVDD EVDD PLL_

VSS IRQ3 IRQ2 IRQ1 K

LSD_

DQS3 D8 BE/

BWE1 BE/

BWE3 SD_VDD SD_VDD SD_VDD SD_VDD EVDD EVDD EVDD VSS USB_

VSS USBOTG

_VDD USB

OTG_M USB

OTG_P L

MD31 D30 D29 D28 IVDD SD_VDD SD_VDD RCON EVDD EVDD IVDD IVDD JTAG_

EN USBHOST

_VSS USB

HOST_M USB

HOST_P M

ND27 D26 D25 D24 D19 BE/

BWE0 D6 R/W DDATA3 DDATA1 TDO/

DSO QSPI_

DIN PLL_

TEST TDI/DSI RESET XTAL N

PSD_DR

_DQS SD_A10 SD_CAS D22 D18 BE/

BWE2 D5 D2 DDATA2 DDATA0 QSPI_

CS0 QSPI_

DOUT EXTAL

32K RSTOUT TRST/

DSCLK EXTAL P

R SD_CLK SD_CLK SD_RAS D21 D17 D7 D4 D1 OE PST3 PST1 QSPI_

CLK XTAL

32K U0RXD U0CTS TMS/

BKPT R

TNC FB_CLK D23 D20 D16 SD_

DQS2 D3 D0 TCLK/

PSTCLK PST2 PST0 QSPI_

CS2 QSPI_

CS1 U0TXD U0RTS NC T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 4. MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 Pinout Top View (256 MAPBGA)

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 15

4.3 Pinout—196 MAPBGA

The pinout for the MCF5327CVM240 package is shown below.

5 Electrical Characteristics

This document contains electrical specification tables and reference timing diagrams for the MCF5329 microcontroller unit.

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications of MCF5329.

The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not

be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications

will be met. Finalized specifications will be published after complete characterization and device qualifications have been

completed.

12 3 456 7 89 1011121314

ADT1IN LCD_

D4 LCD_

D5 LCD_

D9 LCD_

D13 LCD_

D17 LCD_FLM/

VSYNC LCD_LP/

HSYNC U1TXD U1RXD FB_CS3 A20 A16 A15 A

BD2TIN LCD_

D0 LCD_

D6 LCD_

D8 LCD_

D12 LCD_

D16 LCD_CON

TRAST LCD_

LSCLK LCD_

SPL_SPR FB_CS0 A23 A21 A17 A14 B

CDT3IN DT0IN LCD_

D2 LCD_

D7 LCD_

D11 LCD_

D15 LCD_

CLS LCD_

PS U1CTS FB_CS1 A22 A18 A13 A12 C

DSD_WE TS LCD_

D1 LCD_

D3 LCD_

D10 LCD_

D14 LCD_

ACD/OE LCD_

REV U1RTS FB_CS2 A19 A11 A10 A9 D

ESD_CKE SD_CS0 I2C_SCL I2C_SDA IVDD EVDD EVDD SD_VDD SD_VDD TEST A8 A7 A6 A5 E

FD12 D13 D14 D15 EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD A4 A3 A2 A1 F

GBE/

BWE1 D8 D9 D10 D11 VSS VSS VSS VSS USB

OTG_VDD DRAM

SEL USB

OTG_M TA A0 G

HD29 D30 D31 BE/

BWE3 SD_

DQS3 VSS VSS VSS EVDD PLL_

VDD PLL_

VSS USBHOST

_VSS USB

OTG_P PWM3 H

JD25 D26 D27 D28 SD_VDD SD_VDD SD_VDD EVDD EVDD IVDD RESET USB

HOST_P IRQ7 PWM1 J

KD24 SD_CLK SD_CLK SD_DR_

DQS IVDD SD_

DQS2 SD_VDD EVDD EVDD IVDD EVDD TDI/DSI USB

HOST_M XTAL K

LFB_CLK SD_A10 SD_CAS D23 D7 D1 TCLK/

PSTCLK DDATA1 PST1 QSPI_

DIN QSPI_

CS1 JTAG_

EN IRQ4 EXTAL L

MSD_RAS D22 D21 BE/

BWE0 D4 D0 RCON DDATA0 PST0 QSPI_

DOUT EXTAL

32K TMS/

BKPT IRQ2 IRQ3 M

ND20 D19 D16 D6 D3 R/W DDATA3 PST3 TDO/

DSO QSPI_

CLK XTAL

32K U0RTS IRQ1 TRST/

DSCLK N

PD18 D17 BE/

BWE2 D5 D2 OE DDATA2 PST2 VSS QSPI_

CS2 U0RXD U0TXD U0CTS RSTOUT P

12 3 456 7 89 1011121314

Figure 5. MCF5327CVM240 Pinout Top View (196 MAPBGA)

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor16

NOTE

The parameters specified in this MCU document supersede any values found in the module

specifications.

5.1 Maximum Ratings

Table 4. Absolute Maximum Ratings1, 2

1Functional operating condition s are given in Section 5.4, “DC Electr ical Specifications.”

Absolute maximum ratings are stress ratings only, and functiona l operation at the maxima is

not guaranteed. Continued operation at these levels may affect device reliability or cause

per manent damage to the device.

2This device contains circuitry protecting against damage due to high static voltage or electrical

fields; however, it is advised that normal precautions be taken to avoid application of any

voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or

EVDD).

Rating Symbol Value Unit

Core Supply Voltage IVDD – 0.5 to +2.0 V

CMOS Pad Supply Voltage EVDD – 0.3 to +4.0 V

DDR/Memory Pad Supply Voltage SDVDD – 0.3 to +4.0 V

PLL Supply Voltage PLLVDD – 0.3 to +2.0 V

Digital Input Voltage 3

3Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages,

and then use the larger of the two values.

VIN – 0.3 to +3.6 V

Instantaneous Maximum Current

Single pin limit (applies to all pins) 3, 4, 5

4All functional non-supply pins are internally clamp ed to VSS and EVDD.

5P ow er supply must maintain regulation within operating EVDD range during instantaneous and

operating maximum current conditions. If positiv e injection current (Vin > EVDD) is greater than

IDD, the injection current ma y flo w out of EVDD and could result in e xternal power supply going

out of regulation. Ensure external EVDD load shunts current greater than maximum injection

current. This is the greatest risk when the MCU is not consuming power (e x; no cloc k). Power

supply must maintain regulation with in operating EVDD range during instantaneous and

operating maximum current conditions.

ID25 mA

Operating Temperature Range (Packaged) TA

(TL - TH)– 40 to +85 °C

Storage Temperature Range Tstg – 55 to +150 °C

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 17

5.2 Thermal Characteristics

The average chip-junction temperature (TJ) in °C can be obtained from:

Eqn. 1

Where:

TA= Ambient Temperature, °C

QJMA = Package Thermal Resistance, Junction-to-Ambient, °C/W

PD=P

INT + PI/O

PINT =I

DD × IVDD, Watts - Chip Internal Power

PI/O = Power Dissipation on Input and Output Pins — User Determined

For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:

Eqn. 2

Solving equations 1 and 2 for K giv e s:

Eqn. 3

Table 5. Thermal Characteristics

Characteristic Symbol 256MBGA 196MBGA Unit

Junction to ambient, natural convection Four layer board

(2s2p) θJMA 371,2

1θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 f or natural conv ection.

F reescale recommends the use of θJmA and pow er dissipation specifications in the system design to pre v ent

device junction temperatures from e xceeding the rated specification. System designers should be aware that

device junction temperatures can be significantly influenced by board lay out and surrounding devices.

Conformance to the device junction temperature specification can be verified by ph ysical measurement in the

customer’s system using the Ψjt parameter, the device power dissipation, and the method described in

EIA/JESD Standard 51-2.

2Per JEDEC JESD5 1-6 with the board horizontal.

421,2 °C / W

Junction to ambient (@200 ft/min) F our lay er board

(2s2p) θJMA 341,2 381,2 °C / W

Junction to board — θJB 273

3Ther mal resistance between the die and the prin ted circuit board in conformance with JEDEC JESD51-8.

Board temperature is measured on the top surface of the board near the package.

323°C / W

Junction to case — θJC 164

4Ther mal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

194°C / W

Junction to top of package — Ψjt 41,5

5Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written in conformance with Psi-JT.

51,5 °C / W

Maximum operating junction temperature — Tj105 105 oC

TJTAPDΘJMA

×()+=

PDK

TJ273°C+()

---------------------------------

DTA273°C×()QJMA PD

×+×=

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor18

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)

for a known T A. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively

for any value of TA.

5.3 ESD Protection

5.4 DC Electrical Specifications

Table 6. ESD Protection Characteristics1, 2

1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for A utomotive

Grade Integrated Circuits.

2A device is defined as a failure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

perf ormed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

Characteristics Symbol Value Units

ESD Target for Human Body Model HBM 2000 V

Table 7. DC Electrical Specifications

Characteristic Symbol Min Max Unit

Core Supply Voltage IVDD 1.4 1.6 V

PLL Supply Voltage PLLVDD 1.4 1.6 V

CMOS Pad Supply Voltage EVDD 3.0 3.6 V

SDRAM and FlexBus Supply Voltage

Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)

DDR/Bus Pad Supply Voltage (nominal 2.5V)

SDR/Bus Pad Supply Voltage (nominal 3.3V)

SDVDD 1.70

2.25

3.0

1.95

2.75

3.6

USB Supply Voltage USBVDD 3.0 3.6 V

CMOS Input High Voltage EVIH 2EV

DD +0.3 V

CMOS Input Low Voltage EVIL VSS – 0.3 0.8 V

CMOS Output High Voltage

IOH = –5.0 mA EVOH EVDD – 0.4 — V

CMOS Output Low Voltage

IOL = 5.0 mA EVOL —0.4V

SDRAM and FlexBus Input High Voltage

Mobile DDR/Bus Input High Voltage (nominal 1.8V)

DDR/Bus Pad Supply Voltage (nominal 2.5V)

SDR/Bus Pad Supply Voltage (nominal 3.3V)

SDVIH 1.35

1.7

SDVDD +0.3

SDRAM and FlexBus Input Low Voltage

Mobile DDR/Bus Input High Voltage (nominal 1.8V)

DDR/Bus Pad Supply Voltage (nominal 2.5V)

SDR/Bus Pad Supply Voltage (nominal 3.3V)

SDVIL VSS – 0.3

VSS – 0.3

0.45

0.8

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 19

5.5 Oscillator and PLL Electrical Characteristics

SDRAM and FlexBus Output High Voltage

Mobile DDR/Bus Input High Voltage (nominal 1.8V)

DDR/Bus Pad Supply Voltage (nominal 2.5V)

SDR/Bus Pad Supply Voltage (nominal 3.3V)

IOH = –5.0 mA for all modes

SDVOH SDVDD –0.35

2.1

2.4

—

SDRAM and FlexBus Output Low Voltage

Mobile DDR/Bus Input High Voltage (nominal 1.8V)

DDR/Bus Pad Supply Voltage (nominal 2.5V)

SDR/Bus Pad Supply Voltage (nominal 3.3V)

IOL = 5.0 mA for all modes

SDVOL —

—

0.3

0.5

Input Leakage Current

Vin = VDD or VSS, Input-only pins Iin −1.0 1.0 μA

Weak Internal Pull-Up Device Current, tested at VIL Max.1IAPU −10 −130 μA

Input Capacitance 2

All input-only pins

All input/outpu t (three-state) pins

Cin —

—7

1Refer to the signals section for pins having weak internal pull-up devices.

2This parameter is characterized before qualific ation rather than 100% tested.

Table 8. PLL Electrical Characteristics

Num Characteristic Symbol Min.

Value Max.

Value Unit

1PLL Reference Frequency Range

Crystal reference

External reference fref_crystal

fref_ext

12 251

401MHz

MHz

2Core frequency

CLKOUT Frequency2fsys

fsys/3

488 x 10−6

163 x 10−6240

80 MHz

MHz

3 Crystal Start-up Time3, 4 tcst —10ms

4EXTAL Input High Voltage

Crystal Mode5

All other modes (External, Limp) VIHEXT

VIHEXT

VXTAL + 0.4

EVDD/2 + 0.4 —

—V

5EXTAL Input Low Voltage

Crystal Mode5

All other modes (External, Limp) VILEXT

VILEXT

—

—VXTAL – 0.4

EVDD/2 – 0.4 V

7 PLL Lock Time 3, 6 tlpll — 50000 CLKIN

8 Duty Cycle of reference 3 tdc 40 60 %

9 XTAL Current IXTAL 13mA

10 Total on-chip stray capacitance on XTAL CS_XTAL 1.5 pF

11 Total on-chip stray capacitance on EXTAL CS_EXTAL 1.5 pF

Table 7. DC Electrical Specifications (continued)

Characteristic Symbol Min Max Unit

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor20

5.6 External Interface Timing Characteristics

Table 9 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and output delay with

respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.

All other timing relationships can be derived from these values. Timings listed in Table 9

are shown in Figure 7 and Figure 8.

12 Crystal capacitive load CLSee crystal

spec

13 Discrete load capacitance for XTAL CL_XTAL 2*CL –

CS_XTAL –

CPCB_XTAL7

14 Discrete load capacitance for EXTAL CL_EXTAL 2*CL–-

CS_EXTAL –

CPCB_EXTAL7

17 CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max

Peak-to-peak Jitter (Clock edge to clock edge)

Long Term Jitter

Cjitter —

—10

TBD % fsys/3

% fsys/3

18 Frequency Modulation Range Limit 3, 10, 11

(fsysMax must not be exceeded) Cmod 0.8 2.2 %fsys/3

19 VCO Frequency. fvco = (fref * PFD)/4 fvco 350 540 MHz

1The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock

frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.

2All internal registers retain data at 0 Hz.

3This parameter is guaranteed by characterization before qualification rather than 100% te sted.

4Proper PC board layout procedures must be followed to achieve specifications.

5This parameter is guaranteed by design rather than 100% tested.

6This specification is the PLL lock time only and does not include oscillator start-up time.

7CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

8Jitter is the average deviation from the programmed frequency measured over the specified inter val at maximum fsys.

Measurements are made with the device powered by filtered supplies and clocked by a stab le external clock signal.

Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and vari ation in crystal oscillator frequency increase

the Cjitter percentage for a given interval.

9Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.

10 Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.

11 Modulation range determined by hardware design.

Table 8. PLL Electrical Characteristics (continued)

Num Characteristic Symbol Min.

Value Max.

Value Unit

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 21

Figure 6. General Input Timing Requirements

5.6.1 FlexBus

A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up

to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external

boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For

asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose

chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.

Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or

longword (32 bits) wide. Control signal timing is compatible with comm on ROM/flash memories.

5.6.1.1 FlexBus AC Timing Characteristics

The following timing numbers indicate wh en data is latched or driven onto the external bus, relative to the system clock.

Table 9. FlexBus AC Timing Specifications

Num Characteristic Symbol Min Max Unit

— Frequency of Operation fsys/3 —80Mhz

FB1 Clock Period (FB_CLK) tFBCK (tcyc) 12.5 — ns

FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1tFBCHDCV —7.0ns

FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2 tFBCHDCI 1—ns

Invalid Invalid

FB_CLK (80MHz) TSETUP THOLD

Input Setup And Hold

1.5V

trise

Vh = VIH

Vl = VIL

1.5V1.5V Valid

tfall

Vh = VIH

Vl = VIL

Input Rise Time

Input Fall Time

* The timings are also valid for inputs sampled on the negative clock edge.

Inputs

FB_CLK B4 B5

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MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor22

NOTE

The processor drives the data lines during the first clock cycle of the transfer

with the full 32-bit address. This may be ignored by standard connected

devices using non-multiplexed address and data buses. However, some

applications may find this feature beneficial.

The address and data busses are muxed between the FlexBus and SDRAM

controller . At the end of the read and write bus cycles the address signals are

indeterminate.

Figure 7. FlexBus Read Timing

FB4 Data Input Setup tDVFBCH 3.5 — ns

FB5 Data Input Hold tDIFBCH 0—ns

FB6 Transfer Acknowledge (TA) Input Setup tCVFBCH 4—ns

FB7 Transfer Acknowledge (TA) Input Hold tCIFBCH 0—ns

1Timing f or chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC

Timing Characteristics” for SD_CS[3:0] timing.

2The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual

f or more information.

Table 9. FlexBus AC Timing Specifications (continued)

Num Characteristic Symbol Min Max Unit

FB_CLK

FB_R/W

S0 S1 S2 S3

FB_TS

FB_A[23:0]

FB_D[31:X]

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

DATA

ADDR[31:X]

ADDR[23:0]

FB3

FB1

FB2 FB5

FB4

FB7

FB6

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Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 23

Figure 8. FlexBus Write Timing

5.7 SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master . It supports standard SDRAM or

double data rate (DDR) SDRAM, but it do es not support both at the same time.

5.7.1 SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,

when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a

DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device

for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read

cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the

SD_SDR_DQS signal and its usage.

Table 10. SDR Timing Specifications

Symbol Characteristic Symbol Min Max Unit

•Frequency of Operation1•60 80 MHz

SD1 Clock Period2tSDCK 12.5 16.67 ns

SD3 Pulse Width High3tSDCKH 0.45 0.55 SD_CLK

SD4 Pulse Width Low4tSDCKH 0.45 0.55 SD_CLK

SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,

SD_CS[1:0] - Output Valid tSDCHACV —0.5 ×SD_CLK

+1.0 ns

SD6 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,

SD_CS[1:0] - Output Hold tSDCHACI 2.0 — ns

SD7 SD_SDR_DQS Output Valid5tDQSOV — Self timed ns

SD8 SD_DQS[3:0] inp ut setup relative to SD_CLK6tDQVSDCH 0.25 ×

SD_CLK 0.40 ×SD_CLK ns

FB_CLK

FB_R/W

FB_TS

FB_OE

S0 S2 S3

DATA

ADDR[31:X]

FB_A[23:0]

FB_D[31:X]

ADDR[23:0]

FB_CSn, FB_BE/BWEn

FB_TA

FB3

FB1

FB2

FB7

FB6

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor24

Figure 9. SDR Write Timing

SD9 SD_DQS[3:2] input hold rela tive to SD_CLK7tDQISDCH Does not apply. 0.5×SD_CLK fixed width.

SD10 Data (D[31:0]) Input Setup relative to SD_CLK (reference

only)8tDVSDCH 0.25 ×

SD_CLK —ns

SD11 Data Input Hold relative to SD_CLK (reference only) tDISDCH 1.0 — ns

SD12 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid tSDCHDMV —0.75 ×SD_CLK

+ 0.5 ns

SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold tSDCHDMI 1.5 — ns

1The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5329

Reference Manual for more information on setting the SDRAM clock rate.

2SD_CLK is one SDRAM clock in (ns).

3Pulse width high plus pulse width low cannot exceed min and max clock peri od.

4Pulse width high plus pulse width low cannot exceed min and max clock peri od.

5SD_DQS is designed to pulse 0.25 clock bef ore the rising edge of the memory clock. This is a guideline only. Subtle v ariation

from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.

6SDR_DQS is designed to pulse 0.25 clock before the rising edge of the me mory clock. This spec is a guideline only. Subtle

va riation from this guideline is e xpected. SDR_DQS only pulses during a read cycle and one pulse occurs f or each data beat.

7The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge

does not affect the memory controller .

8Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be

centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup

spec is provided as guidance.

Table 10. SDR Timing Specifications (continued)

Symbol Characteristic Symbol Min Max Unit

SD_CLK

SDDM

D[31:0]

A[23:0]

SD_BA[1:0]

CMD

ROW

SD1

SD4

COL

SD5

WD1 WD2 WD3 WD4

SD12

SD11

SD_CSn

SD_RAS

SD_WE

SD_CAS

SD2

SD3

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Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 25

Figure 10. SDR Read Timing

5.7.2 DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timi ng num bers must be followed to properly latch or drive

data onto the memory bus. All timing num bers are relative to the four DQS byte lanes.

Table 11. DDR Timing Specifications

Num Characteristic Symbol Min Max Unit

•Frequency of Operation tDDCK 60 80 Mhz

DD1 Clock Period1tDDSK 12.5 16.67 ns

DD2 Pulse Width High2tDDCKH 0.45 0.55 SD_CLK

DD3 Pulse Width Low3tDDCKL 0.45 0.55 SD_CLK

DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Valid3tSDCHACV —0.5 ×SD_CLK

+1.0 ns

DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Hold tSDCHACI 2.0 — ns

DD6 Write Command to first DQS Latching Transition tCMDVDQ — 1.25 SD_CLK

DD7 Data and Data Mask Output Setup (DQ-->DQS) Relative

to DQS (DDR Wr ite Mode)4, 5tDQDMV 1.5 — ns

SD_CLK

SD_CSn,

SDDM

D[31:0]

A[23:0],

SD_RAS,

SD_BA[1:0]

CMD

ROW

SD1

SD4

COL

WD1 WD2 WD3 WD4

SD9

3/4 MCLK

SD_SDR_DQS

SD_DQS[3:2]

Delayed

SD10

SD7

Board Delay

SD8

Board Delay

SD6

tDQS

Reference

SD_CLK

from

Memories

(Measured at Output Pi n)

(Measured at Input Pin)

SD5

NOTE: Data driven from memories relative

to dela yed memory clock.

SD_WE

SD_CAS,

SD2

SD3

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MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor26

DD8 Data and Data Mask Output Hold (DQS-->DQ) Relative to

DQS (DDR Write Mode)6tDQDMI 1.0 — ns

DD9 Input Data Skew Relative to DQS (Input Setup)7tDVDQ —1ns

DD10 Input Data Hold Relative to DQS8tDIDQ 0.25 ×SD_CLK

+0.5ns —ns

DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH 0.5 — ns

DD12 DQS input read preamble width tDQRPRE 0.9 1.1 SD_CLK

DD13 DQS input read postamble width tDQRPST 0.4 0.6 SD_CLK

DD14 DQS output write preamble width tDQWPRE 0.25 SD_CLK

DD15 DQS output write postamble width tDQWPST 0.4 0.6 SD_CLK

1SD_CLK is one SDRAM clock in (ns).

2Pulse width high plus pulse width low cannot exceed min and max clock period.

3Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,

and voltage variations.

4This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be

larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.

MEM_D ATA[31:24] is relative to MEM_DQS[3], MEM_D ATA[23:16] is relative to MEM_DQS[2], MEM_D ATA[15:8] is relativ e to

MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

5The first data beat is valid bef ore the first rising edge of DQS and after the DQS write preamb le. The re maining data beats are

valid for each subsequent DQS edge.

6This specification relates to the required hold time of toda y’s DDR memories. MEM_D ATA[31:24] is relative to MEM_DQS[3],

MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative

MEM_DQS[0].

7Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data li ne

becomes valid. This input sk e w m ust include DDR memory output skew and system le v el board sk ew (due to routing or other

factors).

8Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line

becomes invalid.

Table 11. DDR Timing Specifications (continued)

Num Characteristic Symbol Min Max Unit

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 27

Figure 11. DDR Write Timing

SD_CLK

SD_CSn,SD_WE,

DM3/DM2

D[31:24]/D[23:16]

A[13:0]

SD_RAS, SD_CAS CMD

ROW

DD1

DD5

DD4

COL

WD1 WD2 WD3 WD4

DD7

SD_DQS3/SD_DQS2

DD8

DD7

SD_CLK

DD3

DD2

DD6

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MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor28

Figure 12. DDR Read Timing

5.8 General Purpose I/O Timing

Table 12. GPIO Timing1

1GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins.

Num Characteristic Symbol Min Max Unit

G1 FB_CLK High to GPIO Output Valid tCHPOV —10ns

G2 FB_CLK High to GPIO Output Invalid tCHPOI 1.5 — ns

G3 GPIO Input Valid to FB_CLK High tPVCH 9—ns

G4 FB_CLK High to GPIO Input Invalid tCHPI 1.5 — ns

SD_CLK

SD_CSn,SD_WE,

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

A[13:0]

SD_RAS, SD_CAS CMD

ROW

DD1

DD5

DD4

WD1 WD2 WD3 WD4

SD_DQS3/SD_DQS2

DD9

SD_CLK

DD3

DD2

D[31:24]/D[23:16] WD1 WD2 WD3 WD4

DD10

CL=2

CL=2.5

COL

DQS Read

Preamble DQS Read

Postamble

DQS Read

Preamble DQS Read

Postamble

CL = 2.5 CL = 2

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Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 29

Figure 13. GPIO Timing

5.9 Reset and Configuration Override Timing

Figure 14. RESET and Configuration Override Timing

NOTE

Refer to the CCM chapter of the MCF5329 Reference Manual for m ore information.

Table 13. Reset and Configuration Override Timing

Num Characteristic Symbol Min Max Unit

R1 RESET Input valid to FB_CLK High tRVCH 9—ns

R2 FB_CLK High to RESET Input invalid tCHRI 1.5 — ns

R3 RESET Input valid Time 1

1During low pow er STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to

the system. Thus, RESET must be held a minimum of 100 ns.

tRIVT 5—t

CYC

R4 FB_CLK High to RSTO UT Valid tCHROV —10ns

R5 RSTOUT valid to Config. Overrides valid tROVCV 0—ns

R6 Configuration Override Setup Time to RSTOUT invalid tCOS 20 — tCYC

R7 Configuration Override Hold Time after RSTOUT invalid tCOH 0—ns

R8 RSTOUT invalid to Configuration Override High Impedance tROICZ —1t

CYC

FB_CLK

GPIO Outputs

G3 G4

GPIO Inputs

R1 R2

FB_CLK

RESET

RSTOUT

R7R6R5

Configu r at i o n Overrides* :

(RCON, Override pins])

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MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor30

5.10 LCD Controller Timing Specifications

This sections lists the timing specifications for the LCD Controller.

Figure 15. LCD_LSC LK to LC D_LD[17:0] timing diagram

Figure 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Table 14. LCD_LSCLK Timing

Num Parameter Minimum Maximum Unit

T1 LCD_LSCLK Per i od 25 2000 ns

T2 Pixel data setup time 11 — ns

T3 Pixel data up time 11 — ns

Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with

bus width is set and LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus

width settings, LCD_LSCLK is equal to the pixel cloc k divided by bus width. The polarity of LCD_LSCLK

and LCD_LD signals can also be programmed.

T2 T3

LCD_LSCLK

LCD_LD[17:0]

Line 1 Line Y

T1 T4

(1,1) (1,2) (1,X)

T5 T7

T6 XMAX

LCD_VSYNC

LCD_HSYNC

LCD_OE

LCD_LD[17:0]

LCD_LSCLK

LCD_HSYNC

LCD_OE

LCD_LD[15:0]

Display regionNon-display region

Line Y

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Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 31

Figure 17. Sharp TFT Panel Timing

Table 15. 4/8/1 2/16/18 Bit/Pixel TFT Color Mode P anel Timing

Number Description Minimum Value Unit

T1 End of LCD_OE to beginning of LCD_VSYNC T5+T6+T7-1 (VWAIT1·T2)+T5+T6+T7-1 Ts

T2 LCD_HSYNC period — XMAX+T5+T6+T7 Ts

T3 LCD_VSYNC pulse width T2 VWIDTH·T2 Ts

T4 End of LCD_VSYNC to beginning of LCD_OE 1 (VWAIT2·T2)+1 Ts

T5 LCD_HSYNC pulse width 1 HWIDTH+1 Ts

T6 End of LCD_HSYNC to beginning to LCD_OE 3 HWAIT2+3 Ts

T7 End of LCD_OE to beginning of LC D_HSYNC 1 HWAIT1+1 Ts

Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC and LCD_OE can be programmed as active high or active

low. In Figure 16, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the

LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 16, LCD_LSCLK is always active.

Note: XMAX is defined in number of pixels in one line.

D1 D2 D320

LCD_LSCLK

LCD_LD

LCD_SPL_SPR

LCD_HSYNC

LCD_CLS

LCD_PS

LCD_REV

XMAX

D320

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MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor32

Figure 18. Non-TFT Mode Panel Timing

Table 16. Sharp TFT Panel Timing

Num Description Minimum Value Unit

T1 LCD_SPL/LCD_SPR pulse width — 1 Ts

T2 End of LCD_LD of line to beginning of LCD_HSYNC 1 HWAIT1+1 Ts

T3 End of LCD_HSYNC to beginning of LCD_LD of line 4 HWAIT2 + 4 Ts

T4 LCD_CLS rise delay from end of LCD_LD of line 3 CLS_RISE_DELAY+1 Ts

T5 LCD_CLS pulse width 1 CLS_HI_WIDTH+1 Ts

T6 LCD_PS rise delay from LCD_CLS negation 0 PS_RISE_DELAY Ts

T7 LCD_REV toggle delay from last LCD_LD of line 1 REV_TOGGLE_DELAY+1 Ts

Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line.

Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.

Note: LCD_REV toggles in every LCD_HSYN period.

Table 17. Non-TFT Mode Panel Timing

Num Description Minimum Value Unit

T1 LCD_HSYNC to LCD_VSYNC delay 2 HWAIT2 + 2 Tpix

T2 LCD_HSYNC pulse width 1 HWIDTH + 1 Tpix

T3 LCD_VSYNC to LCD_LSCLK — 0 ≤ T3 ≤ Ts —

T4 LCD_LSCL K to LCD_HSYNC 1 HWAIT1 + 1 Tpix

Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK

can be programmed as active high or activ e low . In Figure 18, all three signals are active high. When it is in CSTN

mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width

= 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.

T2 T4

T3 XMAX

LCD_VSYNC

LCD_LSCLK

LCD_HSYNC

LCD_LD[15:0]

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Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 33

5.11 USB On-The-Go

The MCF5329 device is compliant with industry standard USB 2.0 specification .

5.12 ULPI Timing Specification

Control and data timing requirements for the ULPI pins are given in Table 18. These timings apply in synchronous mode only.

All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a

50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge.

The ULPI interface on the MCF5329 processor is compliant with the industry standard definition.

Figure 19. ULPI Timing Diagram

5.13 SSI Timing Specifications

This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given

for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync

(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings

remain valid by inverting the clock sign al (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.

Table 18. ULPI Interface Timing

Parameter Symbol Min Max Units

Setup time (control in, 8-bit data in) TSC, TSD — 3.0 ns

Hold time (control in, 8-bit data in) THC, THD −1.5 — ns

Output delay (control out, 8-bit data out) TDC, TDD — 6.0 ns

Table 19. SSI Timing – Master Modes1

Num Description Symbol Min Max Units

S1 SSI_MCLK cycle time2tMCLK 8 × tSYS —ns

S2 SSI_MCLK pulse width high / low 45% 55% tMCLK

S3 SSI_BCLK cycle time3tBCLK 8 × tSYS —ns

S4 SSI_BCLK pulse width 45% 55% tBCLK

S5 SSI_BCLK to SSI_FS output valid — 15 ns

TSC

THC

TSD

TDC

TDD

ULPI_CLK

ULPI_STP

ULPI_DATA

ULPI_DIR/ULPI_NXT

ULPI_DATA

THD

(Output)

(Input)

(Input-8bit)

(Output-8bit)

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor34

S6 SSI_BCLK to SSI_FS output invalid -2 — ns

S7 SSI_BCLK to SSI_TXD valid — 15 ns

S8 SSI_BCLK to SSI_TXD invalid / high impedence -4 — ns

S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 15 — ns

S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns

1All timings specified with a capactive load of 25pF.

2SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock

(SYSCLK).

3SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the

minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure

that SSI_BCLK does not exceed 4 x fSYS.

Table 20. SSI Timing – Slave Modes1

1All timings specified with a capactive load of 25pF.

Num Description Symbol Min Max Units

S11 SSI_BCLK cycle time tBCLK 8 × tSYS —ns

S12 SSI_BCLK pulse width high/low 45% 55% tBCLK

S13 SSI_FS input setup before SSI_BCLK 10 — ns

S14 SSI_FS input hold after SSI_BCLK 3 — ns

S15 SSI_BCLK to SSI_TXD/SSI_FS output valid — 15 ns

S16 SSI_BCLK to SSI_TXD/SSI_FS output invalid/high

impedence -2 — ns

S17 SSI_RXD setup before SSI_BCLK 10 — ns

S18 SSI_RXD hold after SSI_BCLK 3 — ns

Table 19. SSI Timing – Master Modes1 (continued)

Num Description Symbol Min Max Units

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 35

Figure 20. SSI Timing – Master Modes

Figure 21. SSI Timing – Slave Modes

5.14 I2C Input/Output Timing Specifications

Table 21 lists specifications for the I2C input timi ng paramet e rs shown in Figure 22.

Table 21. I2C Input Timing Specifications between SCL and SDA

Num Characteristic Min Max Units

I1 Start condition hold time 2 — tcyc

I2 Clock low period 8 — tcyc

I3 I2C_SCL/I2C_S DA rise time (VIL = 0.5 V to VIH =2.4 V) — 1 ms

I4 Data hold time 0 — ns

SSI_MCLK

(Output)

SSI_BCLK

(Output)

SSI_FS

(Output)

SSI_TXD

SSI_RXD

S1 S2 S2

S4 S4

S5 S6

S7 S8 S8

S9 S10

SSI_FS

(Input)

S9 S10

SSI_BCLK

(Input)

SSI_FS

(Input)

SSI_TXD

SSI_RXD

S11

S12 S12

S14

S15 S16 S16

S17 S18

S15

S13

SSI_FS

(Output)

S15 S16

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor36

Table 22 lists specifications for the I2C output timing parameters shown in Figure 22.

Figure 22 shows timin g for the values in Table 22 and Table 21.

Figure 22. I2C Input/Output Timings

I5 I2C_SCL/I2C_SD A fall time (VIH = 2.4 V to VIL =0.5 V) — 1 ms

I6 Clock high time 4 — tcyc

I7 Data setup time 0 — ns

I8 Sta rt condition setup time (for repeated start condition only) 2 — tcyc

I9 Stop condition setup time 2 — tcyc

Table 22. I2C Output Timing Specifications between SCL and SDA

Num Characteristic Min Max Units

I11

1Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = 0x20) results in minimum output timings as shown in Table 22. The I2C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed into the IFDR; however, the numbers

given in Table 22 are minimum values.

Start condition hold time 6 — tcyc

I2 1 Clock low period 10 — tcyc

I3 2

2Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only activ ely drive

low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and

pull-up resistor values.

I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V) — — µs

I4 1Data hold time 7 — tcyc

I5 3

3Specified at a nominal 50-pF load.

I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 3 ns

I6 1Clock high time 10 — tcyc

I7 1Data setup time 2 — tcyc

I8 1Start condition setup time (for repeated start condition only) 2 0 — tcyc

I9 1Stop condi tion setup time 10 — tcyc

Table 21. I2C Input Timing Specifications between SCL and SDA (continued)

Num Characteristic Min Max Units

I2 I6

I1 I4

I8 I9

I2C_SCL

I2C_SDA

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 37

5.15 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.

5.15.1 MII Receive Signal Timing

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency

must exceed twice the FEC_RXCLK frequency.

Table 23 lists MII receive channel timings.

Figure 23 shows MII receive signal timings listed in Table 23.

Figure 23. MII Receive Signal Timing Diagram

5.15.2 MII Transmit Signal Timing

Table 24 lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency

must exceed twice the FEC_TXCLK frequency.

Figure 24 shows MII transmit signal timings listed in Table 24.

Table 23. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup 5 — ns

M2 FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold 5 — ns

M3 FEC_RXCLK pulse width high 35% 65% FEC_RXCLK period

M4 FEC_RXCLK pulse width low 35% 65% FEC_RXCLK period

Table 24. MII Transmit Signal Timing

Num Characteristic Min Max Unit

M5 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid 5 — ns

M6 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid — 25 ns

M7 FEC_TXCLK pulse width high 35% 65% FEC_TXCLK period

M8 FEC_TXCLK pu l s e widt h low 35% 65% FEC_TXCLK period

M1 M2

FEC_RXCLK (input)

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor38

Figure 24. MII Transmit Signal Timing Diagram

5.15.3 MII Async Inputs Signal Timing

Table 25 lists MII asynchronous inputs signal timing.

Figure 25. MII Async Inputs Timing Diagram

5.15.4 MII Serial Management Channel Timing

Table 26 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5

MHz.

Table 25. MII Async Inputs Signal Timin g

Num Characteristic Min Max Unit

M9 FEC_CRS, FEC_COL minimum pulse width 1.5 — FEC_TXCLK period

Table 26. MII Serial Management Channel Timing

Num Characteristic Min Max Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum

propagation delay) 0— ns

M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay) — 25 ns

M12 FEC_MDIO (input) to FEC_MDC rising edge setup 10 — ns

M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns

M14 FEC_MDC pulse width high 40% 60% FEC_MDC period

M15 FEC_MDC pulse width low 40% 60% FEC_MDC period

FEC_TXCLK (input)

FEC_TXD[3:0] (outputs)

FEC_TXEN

FEC_TXER

FEC_CRS

FEC_COL

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 39

Figure 26. MII Serial Management Channel Timing Dia gram

5.16 32-Bit Timer Module Timing Specifications

Table 27 lists timer module AC timings.

5.17 QSPI Electrical Specifications

Table 28 lists QSPI timings.

Table 27. Timer Module AC Timing Specifications

Name Characteristic Min Max Unit

T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — tCYC

T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — tCYC

Table 28. QSPI Modules AC Timing Specifications

Name Characteristic Min Max Unit

QS1 QSPI_CS[3:0] to QSPI_CLK 1 510 tCYC

QS2 QSPI_CLK high to QSPI_DOUT valid. — 10 ns

QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold) 2 — ns

QS4 QSPI_DIN to QSPI_CLK (Input setup) 9 — ns

QS5 QSPI_DIN to QSPI_CLK (Input hold) 9 — ns

M11

FEC_MDC (output)

FEC_MDIO (output)

M12 M13

FEC_MDIO (input)

M10

M14 M15

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor40

Figure 27. QSPI Timing

5.18 JTAG and Boundary Scan Timing

Table 29. JTAG and Boundary Scan Timing

Num Characteristics1

1JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Symbol Min Max Unit

J1 TCLK Frequency of Operation fJCYC DC 1/4 fsys/3

J2 TCLK Cycle Period tJCYC 4— t

CYC

J3 TCLK Clock Pulse Width tJCW 26 — ns

J4 TCLK Rise and Fall Times tJCRF 03 ns

J5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 4— ns

J6 Boundary Scan Input Data Hold Time af te r TC LK R ise tBSDHT 26 — ns

J7 TCLK Low to Boundary Scan Output Data Valid tBSDV 033 ns

J8 TCLK Low to Boundary Scan Output High Z tBSDZ 033 ns

J9 TMS, TDI Input Data Setup Time to TCLK Rise tTAPBST 4— ns

J10 TMS, TDI Input Data Hold Time after TCLK Rise tTAPBHT 10 — ns

J11 TCLK Low to TDO Data Valid tTDODV 026 ns

J12 T CLK Low to TDO High Z tTDODZ 08 ns

J13 TRST Assert Time tTRSTAT 100 — ns

J14 TRST Setup Time (Negation) to TCLK High tTRSTST 10 — ns

QSPI_CS[3:0]

QSPI_CLK

QSPI_DOUT

QS5

QS1

QSPI_DIN

QS3 QS4

QS2

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Electrical Characteristics

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 41

Figure 28. Test Clock Input Timing

Figure 29. Boundary Scan (JTAG) Timing

Figure 30. Test Access Port Timing

Figure 31. TRST Timing

TCLK VIL

VIH

J4 J4

(input)

J3 J3

Input Data Valid

Output Data Valid

TCLK

Data Inputs

Data Output s

VIL VIH

J6J5

Input Data Valid

Output Data Valid

TCLK

TDI

TDO

TMS

VIL VIH

J9 J10

J11

J12

J11

TCLK

TRST

J13

J14

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Current Consumption

Freescale Semiconductor42

5.19 Debug AC Timing Specifications

Table 30 lists specifications for the debug AC timing parameters shown in Figure 32.

Figure 32. Real-Time Trace AC Timing

Figure 33. BDM Serial Port AC Timing

6 Current Consumption

All current consumption data is lab data measured on a single device using an evaluation board. Table 31 shows the typical

power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.

Table 30. Debug AC Timing Specification

Num Characteristic Min Max Units

D0 PSTCLK cycle time 2 2 tSYS = 1/fSYS

D1 PSTCLK rising to PSTDDATA valid — 3.0 ns

D2 PSTCLK rising to PSTDDATA invalid 1.5 — ns

D3 DSI-to-DSCLK setup 1 — PSTCLK

D41

1DSCLK and DSI are synchronized inter nally. D4 is measured from the synchronized

DSCLK input relative to the rising edge of PSTCLK.

DSCLK-to-DSO hold 4 — PSTCLK

D5 DSCLK cycle time 5 — PSTCLK

D6 BKPT assertion time 1 — PSTCLK

PSTCLK

PSTDDATA[7:0]

D1 D2

Past

Current

DSCLK

DSI

DSO

Current

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Current Consumption

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 43

Figure 34. Current Consumption in Low-Power Modes

Table 31. Current Consumption in Low-Power Modes1,2

1All values are measured with a 3.30V EVDD, 3.30V SDVDD and 1.5V IVDD power supplies. Tests performed at room

temperature with pins configured for high drive strength.

2Refer to the Power Management chapter in the MCF532x Reference Manual for more information on low-power

modes.

Mode Voltage 58 MHz

(Typ)3

3All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port off before entering low

power mode. All code e xecuted from flash.

64 MHz

(Typ)372 MHz

(Typ)380 MHz

(Peak)4

4All periphe ral clocks on before entering low power mode. All code is execute d from flash.

Units

Stop Mode 3 (Stop 11)5

5See the description of the low-power control register (LCPR) in the MCF532x Reference Manual for more

information on stop modes 0–3.

3.3 V 3.9 3.92 4.0 4.0 4.0

1.5 V 1.04 1.04 1.04 1.04 1.08

Stop Mode 2 (Stop 10)43.3 V 4.69 4.72 4.8 4.8 4.8

1.5 V 2.69 2.69 2.70 2.70 2.75

Stop Mode 1(Stop 01)43.3 V 4.72 4.73 4.81 4.81 4.81

1.5 V 15.28 16.44 17.85 19.91 20.42

Stop Mode 0 (Stop 00)43.3 V 21.65 21.68 24.33 26.13 26.16

1.5 V 15.47 16.63 18.06 20.12 20.67

Wait/Doze 3.3 V 22.49 22.52 25.21 27.03 39.8

1.5 V 26.79 28.85 30.81 34.47 97.4

Run 3.3 V 33.61 33.61 42.3 50.5 62.6

1.5 V 56.3 60.7 65.4 73.4 132.3

100

150

200

250

300

350

400

450

58 64 72 80 80(peak)

fsys/3 (MHz)

Power Consum ption (mW)

Stop 0 - Flash

Stop 1 - Flash

Stop 2 - Flash

Stop 3 - Flash

Wait/Doze - Flash

Run - Flash

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Current Consumption

Freescale Semiconductor44

Figure 35 shows the estimated maximum power consumption.

Figure 35. Estimated Maximum Power Consumption

Table 32. Typical Active Current Consumption Specifications1

1All values are measured with a 3.30 V EVDD, 3.30 V SD VDD and 1.5 V IVDD power

supplies. Tests perf ormed at room temperature with pins configured for high drive

strength.

fsys/3 Frequency Voltage Typical2 Active

(Flash)

2CPU polling a status register. All peripheral clocks except UAR T0, FlexBus,

INTC0, reset controller, PLL, and edge port disabled.

Peak3

3Peak current measured while running a while (1) loop with all modules active.

Unit

1.333 MHz 3.3V 7.73 7.74

1.5V 2.87 3.56

2.666 MHz 3.3V 8.57 8.60

1.5V 4.37 5.52

58 MHz 3.3V 40.10 49.3

1.5V 65.90 91.70

64 MHz 3.3V 44.40 54.0

1.5V 69.50 97.0

72 MHz 3.3V 53.6 63.7

1.5V 74.6 104.7

80 MHz 3.3V 63.0 73.7

1.5V 79.6 112.9

Estimated Power Consumption vs. Cor e Fr equency

100

150

200

250

300

0 40 80 120 160 200 240

Core Frequency (MHz)

Power Consumption (mW

)

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Pa ckage Information

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 45

7 Pac kage Inf ormation

This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF532 x devices.

NOTE

The mechanical drawings are the latest revisions at the time of publication of this

document. The most up-to-date mechanical drawings can be found at the product summary

page located at http://www.freescale.com/coldfire.

7.1 Package Dimensions—256 MAPBGA

Figure 36 shows MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 package dimensions.

Figure 36. 256 MAPBGA Package Outline

Laser mark for pin A1

identification in

this area

0.20

Metalized mark for

pin A1 identification

in this area

123456710

e15X

e15X b256X

0.25 YZ

0.10 X

Detail K

View M-M

Rotated 90° Clockwise

40.15

Z0.30

256X

Notes:

1. Dimensions are in millimeters.

2. Interpret dimen sions and tolerances

per ASME Y14.5M, 1994.

3. Dimension b is measured at the

maximum solder ball diameter, paral lel

to datum plane Z.

4. Datum Z (seating plane) is defined by

the spherical crowns of the solder

balls.

5. Parallelism measurement shall exclude

any effect of mark on top surface of

package.

Dim Min Max

Millimeters

A1.25 1.60

0.27 0.47

A2 1.16 REF

b0.40 0.60

D17.00 BSC

E17.00 BSC

e1.00 BSC

S0.50 BSC

Top View

Bottom View

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available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Package Information

Freescale Semiconductor46

7.2 Package Dimensions—196 MAPBGA

Figure 37 shows the MCF5327CVM240 package dimensions.

Figure 37. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

0.20

Laser mark for pin 1

identification in

this area

13X

0.15 Z

0.30 Z

Rotated 90 Clockwise

Detail K

View M-M

e13X

X0.30 YZ

0.10 Z

196X

Metalized mark for

pin 1 identification

in this area

14 13 12 11 5 4 3 2

NOTES:

1. Dimensions are in millimeters.

2. Interpret dimensions and tolerances

per ASME Y14.5M, 1994.

3. Dimension B is measured at the

maximum solder ball diameter,

parallel to datum plane Z.

4. Datum Z (seating plane) is defined

by the spherical crowns of the solder

balls.

5. Parallelism measurement shall

exclude any effect of mark on top

surface of package.

DIM Min Max

Millimeters

A1.32 1.75

A1 0.27 0.47

A2 1.18 REF

b0.35 0.65

D15.00 BSC

E15.00 BSC

e1.00 BSC

S0.50 BSC

1610 9

Top View

Bottom View

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Revision History

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 47

8 Re vision History

Table 33. MCF5329DS Document Revision History

Rev. No. Substantive Changes Date of Release

0 • Initial release. 11/2005

0.1 • Added not to Section 7, “Package Information.”

• Added top view and bottom view where appropriate in mechanical

drawings and pinout figures.

• Figure 6: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”

3/2006

1 • Corrected MCF5327 196MAPBGA ball map locations in Table 5 for

the f ollowing signals: RCON, D1, D0, OE, R/W, SD_DQS2, PSTCLK,

DDATA[3:0], PST[3:0], EVDD, IVDD, and SD_VDD. Figure 5 was

correct.

• Updated thermal character istic values in Table 5.

• Updated DC electricals values in Table 7.

• Updated Section 3.3, “Supply Voltage Sequencing and Separation

Cautions” and subsections.

• Updated and added Oscillator/PLL character istics in Table 8.

• Table 9: Swapped min/max for FB1; Removed FB8 & FB9.

• Updated SDRAM write timing diagram, Figure 9.

• Table 11: Added values for frequency of operation and DD1.

• Reworded first paragraph in Section 5.12, “ULPI Timing

Specification.”

• Updated Figure 19.

• Replaced figure & table Section 5.13, “SSI Timing Specifications,”

with slave & master mode versions.

• Remo ved second sentence from Section 5.15.2, “MII Transmit Signal

Timing,” regarding no minimum frequency requirement for TXCLK.

• Removed third and fourth paragraphs from Section 5.15.2, “MII

Transmit Signal Timing,” as this feature is not supported on this

device.

• Updated figure & table Section 5.19, “Debug AC Timing

Specifications.”

• Renamed & moved previous version’s Section 5.5 “Power

Consumption” to Section 6, “Current Consumption.” Added additional

real-world data to this section as well.

7/2007

2 • Added MCF53281 device information throughout: features list, f amily

configuration table, ordering information table, signals description

table, and relevant package diagram titles

• Remove Footnote 1 from Table 11.

• Changed document type from Advance Inf ormation to Technical Data.

8/2007

3 • Corrected MCF53281 in features list table. This device contains CAN,

but does not feature the cryptography accelerators.

• In pin-multiplexing table, moved MCF53281 label from the MCF5328

column to the MCF5329 column, because this device contains CAN

output signals.

10/2007

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Revision History

Freescale Semiconductor48

4 • Corrected pinouts in Signal Information and Pin-Muxing table for

196 MAPBGA device:

Changed D[15:1] entry from “F4–F1, G4–G2...” to “F4–F1, G5–G2...”

Changed DSO/TDO entry from “P9” to “N9”

• Corrected D0 spec in Table 30 from 1.5 x tsys to 2 x tsys for min and

max balues.

• Updated FlexBus read and write timing diagrams in Figure 7 and

Figure 8.

• Rem ov ed f ootnote 2 from the IRQ[ 7:1] alternate funct ions USBHOST

VBUS_EN, USBHOST VBUS_OC, SSI_MCLK, USB_CLKIN, and

SSI_CLKIN signals in Signal Information and Pin-Muxing table.

• Updated pinouts f or 196 MAPBGA device, MCF5327CVM240 in both

Figure 5 and Table 2.

The follo wing locations are aff ected: G10–12, H12–14, J11–14,

K12–13, L12–13 , M12–14, N13.

The f ollowing signals are affected: USBOTG_VDD , USBHOST_VSS,

USBO TG_M, USBOTG_P, USBHOST_M, USBHOST_P, DRAMSEL,

PWM3, PWM1, IRQ[7,4,3,2,1], RESET, TDI/DSI, JTAG_EN,

TMS/BKPT.

4/2008

5 Changed the following specs in Table 10 and Table 11:

• Minimum frequency of operation from TBD to 60MHz

• Maximum clock period from TBD to 16.67 ns

11/2008

Table 33. MCF5329DS Document Revision History (cont inued)

Rev. No. Substantive Changes Date of Release

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Revision History

MCF532x Cold Fire® Microprocessor Data Sheet, Rev. 5

Freescale Semiconductor 49

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MCF5327CVM240, MCF53281CVM240, MCF5328CVM240, MCF5329CVM240

Document Number : MCF5329DS

Rev. 5

11/2008

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