IS43LR16320B, IS46LR16320B
1 1
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8M x 16Bits x 4Banks Mobile DDR SDRAM
Description
The IS43/46LR16320B is a 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x
16 bits. This product uses a double-data-rate architecture to achieve high-speed opera tion. The Data Input/ Output signals are transmitted
on a 16bit bus. The double data rate architecture is essentially a 2
N
prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
The data paths are internally pipelined and 2 n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are
compatible with LVCMOS.
Features
• JEDEC standard 1.8V power supply.
• VDD = 1.8V, VDDQ = 1.8V
• Four internal banks for concurre nt operation
• MRS cycle with address key programs
- CAS latency 2, 3 (clock)
- B ur st leng t h (2, 4, 8, 16)
- Burst type (sequential & interleave)
• Fully differential c lock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• 64ms refresh period (8K cycle)
• Auto & self refresh
• Concurrent Auto Precharge
• Maximum clock frequency up to 166MHZ
• Maximum data rate up to 333Mbps/pin
• Power Saving support
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength
o r 1/2, 1/4, 1/8 o f Full Stren gth
• LVCMOS compatible inputs/outputs
• 60-Ball FBGA package
Copyright © 2010 Integrated Sili con Solution, Inc . All rights reserved. IS S I reserves the right t o make changes to this specification and its
products at any time without noti ce. ISSI ass umes no liability arisi ng out of the appl i cation or use of any inf ormation, products or services
described herein. Custom ers are advised to obtain the latest version of this device specif ic ation before relying on any publi shed inf orm ati on
and before pl acing orders for produc ts.
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Figure1: 60Ba ll FBGA Ba ll As s ignmen t
A
B
C
D
E
F
G
H
J
K
1 2 3 4 5 6 7 8 9
VSS DQ15 VSSQ
VDDQ DQ13 DQ14
VSSQ DQ11 DQ12
VDDQ DQ9 DQ10
VSS UDM NC
CKE CK /CK
A9 A11 A12
A6 A7 A8
VSS A4 A5
VDDQ DQ0 VDD
DQ1 DQ2 VSSQ
DQ3 DQ4 VDDQ
DQ5 DQ6 VSSQ
NC LDM VDD
/WE /CAS /RAS
/CS BA0 BA1
A10 A0 A1
A2 A3 VDD
VSSQ UDQS DQ8 DQ7 LDQS VDDQ
[Top View]
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Table2 : Pin Desc r iptions
Symbol Type Function Descriptions
CK, /CK Input System Clock
The system clock input. CK and /CK are differential c lock
inputs. All address and control input signals are registered on
the crossing of the rising edge of CK and falling edge of /CK.
Input and output data is referenced to the crossing of CK and
/CK.
CKE Input Clock Enable
CKE is clock enable controls input. CKE HIGH activates, and
CKE LOW deactivates internal clock sig nals, and device input
buffers and output drivers. CKE is synchronous for all functions
except for SELF REFRESH EXIT, which is achieved
asynchronously.
/CS Input Chip Select
/CS enables (registered Low) and disables (registered High)
the command decoder. All commands are masked when /CS
IS REGISTERED high. /CS provides for external bank selection
on systems with multiple ba nks. /CS is considered part of the
command code.
BA0, BA1 Input Bank Address
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA0 and BA1 also
determine which mode register (standa rd mode register or
extended mode register ) is loaded during a LOAD MODE
REGISTER co mman d.
A0~A12 Input Address Row Address : RA0~RA12
Column Address : CA0~CA9
Auto Precharge : A10
/RAS, /C AS, /WE Input Row Address Strobe,
Column Address Strobe,
Write Enable
/RAS, /CAS and /WE define the operation.
Refer function truth table for details.
LDM, UDM Input Data Input Mask
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM balls are input-only.
DQ0~DQ15 In/Output Data Input/Output Data input/output pin.
LDQS, UDQS In/Output Data Input/Output
Strobe
Output with read data, input with write data . DQS is edge-
aligned with read data, centered in write data. Data strobe is
used to capture data.
VDD Supply Power Supply Power supply
VSS Supply Ground Ground
VDDQ Supply DQ Power Supply Power supply for DQ
VSSQ Supply DQ Ground Ground for DQ
NC NC No Connection No connection.
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Figure2 : Functional Block Diagram
Extended
Mode
Register Self refresh
Logic & timer
Internal Row
Counter
Row
Pre
Decoder
Column
Pre
Decoder
Column Add
Counter
Address
Register
Mode Register Data Out Control
Burst
Counter
Address Buffers State Machine
Row Decoders
Row Decoders
Row Decoders
Row Decoders
8Mx16 BAN K 1
8Mx16 BAN K 0
Memory
Cell
Array
Column Decoders
8Mx16 BAN K 2
8Mx16 BAN K 3
Write Data Register
2-bit Prefetch Unit
Sense AMP&I/O Gate
Output Buffer & Logic
DQ0
.
.
.
.
.
.
.
DQ15
Data Strobe
Transmitter
Data Strobe
Receiver
Input Buffer & Logic
|
|
16
|
|
|
|
32
|
|
DS
UDQS,LDQS
DS
X16
X32
PASR
Row Active
Refresh
Column Active
Bank Select
Burst
Length
CAS
Latency
---------
A0
A1
A12
BA0
BA1
LDM/UDM
/WE
/CAS
/RAS
/CS
CKE
CK
/CK
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Figure3 : Simplified State Dia gra m
Power
On
Precharge
All Banks
MRS
EMRS
Active
Power
Down
Deep Power
Down
Idle
All Banks
Precharged
Self
Refresh
Auto
Refresh
Row
Active
Precharge
PREALL
WRITE
WRIT E A
READ
READ A
Burst
Stop
Precharge
Power
Down
DPDS
Power
Applied
DPDSX
MRS REFA
REFS
REFSX
ACT
CKEH
CKEL
PRE
CKEL
CKEH
WRITE READ BST
PRE
PRE PRE
WRITE A
WRITE READ
READ A
READ
WRITE A READ A
Automatic
sequence
ACT = Active
BST = Burst
CKEL = Enter Power- Down
CKEH = Exi t Power-Down
DPDS = E nter Deep Power-Down
DPDSX = Exit Deep Power- Down
EMRS = Ext. Mode Reg. Set
MRS = Mode Register Set
PRE = Precharge
PREALL= Precharge A ll Banks
REFA = Auto Refresh
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
READ = Read w/o Auto Precharge
READ A = Read with Auto Prechar ge
WRITE = Write w/o Auto Precharge
WRITE A = Write with Auto Prechar ge
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Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
M3 Burst Type
0 Sequential
1 Interleave
M6 M5 M4 CAS Late ncy
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
M2 M1 M0 Burst Length
M3 = 0 M3 = 1
0 0 0 Reserved Reserved
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 16 16
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
Address Bus
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Figure4 : Mode Register S et ( MRS ) Definition
A12
BA0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 CAS Latency BT Burst Length
Note: M14(BA1) and M13(BA0) must be set to “0” to select Mode Register (vs. the Extended M od e Register)
Mode Register (Mx)
BA1
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Table3 : Burst Definition
Burst Length S tarti ng Co l umn Add res s Order of Access within a Burst
A3 A2 A1 A0 Sequential Mode I nterleave Mode
2 x x x 0 0-1 0-1
x x x 1 1-0 1-0
4
x x 0 0 0-1-2-3 0-1-2-3
x x 0 1 1-2-3-0 1-0-3-2
x x 1 0 2-3-0-1 2-3-0-1
x x 1 1 3-0-1-2 3-2-1-0
8
x 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
x 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
x 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
x 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
x 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
x 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
x 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
x 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
16
0 0 0 0 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0 0 0 1 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14
0 0 1 0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13
0 0 1 1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12
0 1 0 0 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11
0 1 0 1 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10
0 1 1 0 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9
0 1 1 1 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8
1 0 0 0 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7
1 0 0 1 9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8 9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6
1 0 1 0 10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9 10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5
1 0 1 1 11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10 11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4
1 1 0 0 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11 12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3
1 1 0 1 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12 13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2
1 1 1 0 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1
1 1 1 1 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0
Note :
1. For a burst length of two, A1-A9 select the block of two burst; A0 selects the starting column within the block.
2. For a burst length of four, A2-A9 select the block of four burst; A0-A1 select the starting column within the block.
3. For a burst length of eight, A3-A9 select the block of eight burst; A0-A2 select the starting column within the block.
4. For a burst length of sixteen, A4-A9 select the block of eight burst; A0-A3 select the starting column within the block.
5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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Figure5 : Extended Mode Set (EMRS) Register
Address Bus
Extended Mode Register (Ex)
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
E2 E1 E0 Self Refresh Coverage
0 0 0 Four Banks
0 0 1 Two Bank (BA1=0)
0 1 0 One Bank (BA1=BA0=0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
E6 E5 Driver Strength
0 0 Full Strength
0 1 1/2 Strength
1 0 1/4 Strength
1 1 1/8 St rengt h
A12
BA0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 DS 0 0 PASR
Note: E14(BA1) must be set to “1” and E13(BA0) must be set to “0” to select Extended Mode Register (vs. the base Mode
Register)
BA1
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The 512Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912-bits. It is internally
configured as a quad-bank DRAM. The 512Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock
cycle at the I/O balls, single read or write access for the 512Mb Mobile DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
Read and Write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
It should be noted that the DLL signal that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has
been omitted to save power.
Prior to normal operation, the Mobile DDR SDRAM must be powered up and initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions and device operation.
Power up and Initialization
Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ (simultaneously).
After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile DDR. Then, 2 or more
Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a Mode Register Set(MRS) command will be issued to
program the specific mode of operation (Cas Latency, Burst length, etc.) And a Extended Mode Register Set(EMRS) command will be issued
to Partial Array Self Refresh(PASR). The following these cycles, the Mobile DDR SDRAM is ready for normal operation. To ensure device
functionality, there is a predefined sequence that must occur at device power up or if there is any interruption of device power.
To properly initialize the Mobile DDR SDRAM, this sequence must be followed:
1. To prevent device latch-up, it is recommended the core power (VDD) and I/O power (VDDQ) be from the same power source and brought
up simultaneously. If separate power sources are used, VDD must lead VDDQ.
2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock.
3. Once the clock is stable, a 200μs (minimum) delay is required by the Mobile DDR SDRAM prior to applying an executable command.
During this time, NOP or DESELECT commands must be issued on the command bus.
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Issue a second AUTO REFRESH
command followed by NOP or DESELECT commands for at least tRFC time. As part of the individualization sequence, two AUTO REFRESH
commands must be issued. Typically, both of these commands are issued at this stage as described above.
7. Using the LOAD MODE REGISTER command, load the standard mode register as desired.
8. Issue NOP or DESELECT commands for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating modes. Note that the order in
which the standard and extended mode registers are programmed is not critical.
10. Issue NOP or DESELECT commands for at least tMRD time.
11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command.
Functional Description
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Notes:
1. PCG = PRECHARGE command, MRS = LOAD MOD E REGIST ER com man d, AREF = AUTOREFRESH command,
ACT = ACTIVE command, RA = Row address, BA = Bank addres s.
2. NOP or DESELECT commands are required for at least 200μs.
3. Other valid commands are possib le.
4. NOPs or DESELECTs are required during this time.
5. Two clocks at minimum.
Figure6 : Power up sequence
ACT
BA
BA 0 = L ,
BA 1 = H
BA 0 = L ,
BA 1 = L
All
Banks
MRS MRS AR EF AR EF PCG NOP NOP
2 NOP 3
C L K
/ C L K
CKE
T 0
C ommand
1
T 1 Ta 0
tCL
DM
A 0 ~ A 9 ,
A11,
A12
Tb 0 Tc 0 Td 0 Te 0 Tf 0
tCK
LVCMOS
HIGH LEVEL
A 10
BA 0 , BA 1
DQS , DQ High - Z
T = 200 µ s
tIS
RA CODE CODE
tIS tIH
RA CODE CODE
tIS tIH
tIS tIH
tRP
4 tRFC
4 tRFC
4 tMRD
4,5 tMRD
tIH
VDDQ
VDD
tIS tIH
Load Standard Mode
Register Load Extended Mode
Register
Power - up : VDD and C L K stable Don
’ t care
4,5
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Mode Register
The mode register is used to define the specific mode of operation of the Mobile DDR SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency. The mode register is programmed via the LOAD MODE REGISTER command and will retain the
stored information until programmed again, the device goes into deep power-down mode, or the device loses power.
Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency,
and A7-A12 should be set to zero. BA0 and BA1 must be zero to access the mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure
(Mode Register Set Definition). The burst length determines the maximum number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4,8 or 16 are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A9 when the burst
length is set to two; by A2-A9 when the burst length is set to four; by A3-A9 when the burst length is set to eight; and by A4-A9 when the
burst length is set to sixteen. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block.
The programmed burst length applies to both READ and WRITE bursts.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 2, 3 clocks, as shown in Figure (Standard Mode Register Definition).
For CL = 3, if the READ command is registered at clock edge n, then the data will be available at (n + 2 clocks + tAC). For CL = 2, if the
READ command is registered at clock edge n, then the data will be available at (n + 1 clock + tAC).
Figure7 : CAS Latency (BL=4)
/ C K
C K
C ommand
T 0 T 1 T 2 T 3 T 1 n T 2 n T 3 n
READ NOP NOP NOP
DQS
DQ
tAC
CL = 3
D
OUT
n + 1
tRPRE
2 tCK
T 4 T 4 n
NOP
tRPST
D OUT
n D OUT
n + 2 D
OUT
n + 3
Don ’ t care
DQS
DQ
tAC
CL = 2
D OUT
n + 1
tRPRE
1 tCK
tRPST
D OUT
n D OUT
n + 2 D OUT
n + 3
L
L
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Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special
features of the Mobile DDR SDRAM. They include Partial Array Self Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command (BA0=0, BA1=1) and retains the stored information until
programmed again, the device goes into deep power-down mode, or the device loses power.
The Extended Mode Register must be programmed with A7 through A12 set to “0”. The Extended Mode Register must be loaded when all
banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation.
Violating either of these requirements results in unspecified operation.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options are as follows:
• Full array: banks 0, 1, 2, and 3
• Half array: banks 0 and 1
• Quarter array: bank 0
WRITE and READ commands can still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH.
Data in banks that are disabled will be lost.
Output Driver Strength
Because the Mobile DDR SDRAM is designed for use in smaller systems that are mostly point to point, an option to control the drive
strength of the output buffers is available. Drive strength should be selected based on the expected loading of the memory bus. Bits A5 and
A6 of the extended mode register can be used to select the driver strength of the DQ outputs. There are four allowable settings for the
output drivers.
Temperature Compensated Self Refresh
In the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device.
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to the
case temperature of the Mobile SDRAM device. This allows great power savings during SELF REFRESH during most operating temperature
ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature.
At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often.
Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures.
This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures. It is not supported for
any temperature grade with TA above +85°C.
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Commands
The following COMMANDS Truth Table and DM Operation Tr uth Ta ble provide quick reference of available commands. This is followed by a
written description of each command.
Deselect
The DESELECT function (/CS HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. The Mobile DDR SDRAM is
effectively deselected. Operations already in progress are not affected.
NO Operation (NOP)
The NO OPER ATI ON (NOP ) command is us ed to instruct the s elec ted DDR SDRAM to perform a NOP (/CS = LOW, /RAS = /CAS = /WE =
HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
Active
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent acc ess . The value on the BA0, BA1 inputs
selects the bank, and the a ddress provided on inputs A0–A12 selects the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be iss ued before opening a different row in the same bank.
Read
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0–A9 selects the starting column loc ation. T he value on input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged a t the end of the READ burst; if auto precharge is not
selected, the row will remain open for subsequent ac ces ses.
Write
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the b ank, and the
address provided on inputs A0-A9
selects the starting column location. The value on input A10 determines whether or not auto prechar ge is
used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not
selected, the row will remain open for subse quent accesses. Input data appearing on the DQs is written to the memory array subject to the
DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to
memory; if the DM signal is reg istered HIGH, the corresponding data inputs will be ig nor e d, and a WRITE will not be executed to that
byte/column location.
Precharge
The PRECHAR GE command is used to deac tivate the open row in a particular bank or the open row in all banks. The bank(s) will be ava ilable
for a subsequent row access a specified time (tR P) after the precharge command is iss ued. Ex cept in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameter s. Input A10 determines whether one or all b anks are to be prec harged, and in the case where
only one bank is to be precharged, inputs BA0, BA1select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE
command will be treated as a N OP if there is no open row in that bank (idle state), or if the previously open row is already in the process of
precharging.
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Auto P recha rge
Auto precharge is a feature which perform s the same individual-bank precharge function described a bove, but without requiring an explicit
command. This is accomp lished by using A1 0 to enable auto precharge in conjunction w ith a sp ecific R E AD or WRITE command. A
precharge of the bank/row that is addressed with the READ or WRITE command is automatically perfor m e d upon completion of the READ or
WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. This
device supports concurrent auto precharge if the command to the other bank does not interrupt the data tr ansfer to the current b ank. Auto
precharge ensur e s that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an
explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN). The user must not iss ue a nother
command to the same bank until the precharge time (tRP ) is completed.
Burst Terminate
The BURST TERMINATE command is used to truncate READ bursts (with auto prechar ge disabled ). The most rec e ntly registered READ
command prior to the BURST TER MINATE command will be truncated. The ope n page which the READ burst was terminated from remains
open.
Auto R efresh
AUTO REFRESH is used during normal operation of the Mobile DDR SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in
FPM/ EDO DR AMs . This command is nonpers istent, so it must be issued each time a refresh is required . The addressing is genera ted by the
internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. The 512Mb Mobile DD R SDRAM
requires AUTO REFRESH cycles at an average interval of T REFI (maximum). To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refres h interval is provided.
Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the auto refresh period.
The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later.
Self Refresh
The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the r e st of the system is power e d down. When
in the self refresh mode, the Mobile DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled (LOW). All command and address input signals except CKE are “Don’t Care” during SELF
REFRESH.
During SELF REF RESH, the device is refreshed as identified in the external mode re gister (see PASR setting). For a the full array refresh, all
four banks are refreshed simultaneous ly with the refres h frequenc y set by an internal s elf refres h oscillator. This oscillator changes due to
the temperature s e nsors input. As the case temperature of the Mobile DDR SDRAM increases, the oscillatio n frequency will cha nge to
accommodate the change of temperature. This happens because the DRAM capacitors lose c harge faster at higher temperatures. T o ensure
efficient power dissipation during self refresh, the oscillator will change to refresh at the slowest rate possible to maintain the devices data.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, Clock must be stable prior to CKE going back HIGH. Once
CKE is HIGH, the Mobile DDR SDRAM must have NOP commands issued for tX SR is required for the completion of any internal refresh in
progress. The SELF REFRESH command is not applicable for operation with TA > 85oC.
Deep Po wer-down
Deep Power Down is an operating mode to achieve ma ximum power reduction by eliminating the pow er of the whole memory array of the
devices. Data in the array and in t he mode and extended mode registers will not be retained once the device enters Deep Power Down M ode.
This mode is entered by having all banks idle then / CS and /WE held low with /R AS and /CAS held high at the rising edge of the clock, w hile
CKE is low. This mode is exited by asserting CKE high. After applying NOP commands for 20 0 μs, the Power Up and Initialization sequence
must be followed.
IS43LR16320B, IS46LR16320B
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Note:
1. All states and sequences not shown are illeg al or rese rved.
2. DESLECT and NOP are functionally interchangeable.
3. Autoprecharge is non-persis tent. A 10 High enables Autoprecharge, w hile A1 0 Low disables Autoprechar ge
4. Burst Terminate applies to only Read bursts with autoprecharge d isabled .
This command is undefined and should not be used for Read with Autoprecharge enabled, and for Write bursts.
5. This command is BURST T ERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.
6. If A10 is low, bank ad dress determines whic h bank is to be precharged. If A10 is high, all banks are precharged and BA0-BA1 are don‘t
care.
7. This command is AUTO REFRESH if CKE is High, and SELF REFRE SH if CKE is low.
8. All address inputs and I/O are ''don't care'' except for CKE. Internal refresh counters control Bank and R ow addressing.
9. All banks must b e precharged before issuing an AUTO-REFRESH or SELF REFRESH comma nd.
10. BA0 and BA1 value select between M RS and EMR S.
11. Used to mask write data, provided coinc ident with the corresponding data.
12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
Function /CS /RAS /CAS /WE BA A10/AP ADDR Note
DESEL ECT (NOP) H X X X X X X 2
NO OPERATION (NOP) L H H H X X X 2
ACTIVE (Select Bank and activate Row) L L H H V Row Row
READ (Select bank and column and start r e ad burst) L H L H V L Col
READ w ith AP (Read Burst with Auto recharge) L H L H V H Col 3
WRITE (Select bank and column and s ta rt write burst) L H L L V L Col
WRITE with AP (Write Burst w ith Auto recharg e) L H L L V H Col 3
BURST T ERMINA TE or ente r DEEP PO W ER D O W N L H H L X X X 4,5
PRECHA RG E (Deac tivate Row in selected b ank) L L H L V L X 6
PRECHARGE ALL (Deactivate rows in all banks) L L H L X H X 6
AUTO REFRESH or enter SELF REFRESH L L L H X X X 7,8,9
MODE REGI STER SET L L L L V Op_Code 10
Function DM DQ Note
Write Enable L Valid 11
Write Inhibit H X 11
Table5 : DM Truth Table
Table4: Command Truth Table
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Note:
1. CKEn is the logic s tate of CKE at clock edge
n
; CKE
n
-1 was the state of CKE at the previous clock edge.
2. Current state is the sta te of Mobile DDR immediately pr ior to clock edge
n
.
3. COMMANDn is the command registered at clock edge n, and ACTION
n
is the result of COMMAN D
n
.
4. All states and sequences not shown are illeg al or rese rved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP ) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REF RE SH exit time (tX SR) should elapse b efore a command other than NOP or DESELECT is issued.
8. The Deep Power-Down exit procedure must be followed as disc ussed in the Deep Power-Down se ction of the Func tional Des cr iption.
9. The clock must toggle at least one time during the tXP period.
10. The clock must toggle at least once during the tXSR time.
See the other Truth Tables H H
Enter Deep Power
Down
BURST T ERMINA TE All Banks Idle L H
Self Refresh Entry AUTO REFRESH All Banks Idle L H
5 Active Power Down
Entry
NOP or DESELECT Bank(s) Ac tive L H
5 Precharge Power
Down entry
NOP or DESELECT All Banks Idle L H
5,8 Exit Deep Power Down NOP or DESELECT Deep Power Down H L
5,7,10 Exit Self Refresh NOP or DESELECT Self Refresh H L
5,6,9 Exit Power Down NOP or DESELECT Power Down H L
Maintain Deep Power Down X Deep Power Down L L
Maintain Self Refresh X Self Refresh L L
Maintain Power Down X Power Down L L
Note ACTION
n
COMMAND
n Cur rent Sta te
CKEn CKEn-1
Table6 : CKE T ruth Table
IS43LR16320B, IS46LR16320B
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Note:
1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or
Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illeg al or rese rved.
4. This command may or may not be bank specific. If all banks are being precharg ed, they must be in a valid state for precharging.
5. A command other than NOP should not be issued to the same bank while a READ or WRITE Burst with auto precharge is enabled.
6. The new Read or Write command could be auto precharge enabled or auto precharge disabled.
7. Current State Definitions:
I dle: The bank has been precharged, and tRP has been met.
R ow Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
R ead: A READ burst has been initiated, with AU TO PRECHARG E disabled, and has not yet terminated or been terminated.
Write: a WR ITE burst has been initiated, with AU TO PRECHAR GE disabled, and has not yet terminated or been terminated.
8. The following s tates mus t not be interrupted by a command iss ued to the same bank.
DE SE LECT or NOP commands or allowable c ommands to the other bank should be issued on any cloc k edge occurring during these
s tates. Allow able c ommands to the other bank are determined by its current state and Truth Table3, and according to Truth Table 4.
• Precharging: Starts w ith the registration of a PRE CHAR G E command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
• Row Activating: Starts w ith registr ation of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the ''row active'' state.
• Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends when tRP has
been met. Once tRP has been met, the bank will be in the idle state.
• Write with AP Enabled: Starts with registration of a WRITE command with AUT O PRE CHAR GE enabled and ends w hen tRP has been
met. Once tRP is met, the bank will be in the idle state.
Table7 : Current S tate BANK
n
Truth Table(COMMAND TO BANK
n
)
Current State Command Action Note
/CS /RAS /CAS /WE Description
Any H X X X DESELECT(NOP) Continue previous Oper ation
L H H H NOP Continue previous Opera tion
Idle
L L H H ACTIVE Select and activate row
L L L H AUTO REFRESH Auto refresh 10
L L L L MODE REGISTER
SET Mode register set 10
L L H H PRECHARGE No action if bank is idle
Row Active
L H L H READ Select Column & start read burst
L H L L WRITE Select Column & start write burst
L L H L PRECHARGE Deactivate Row in bank (or banks) 4
Read
(without Auto
recharge)
L H L H READ Truncate Read & start new Read burst 5,6
L H L L WRITE Truncate Read & start new Write burst 5,6,13
L L H L PRECHARGE Truncate Read, start Precharge
L H H L BURST TERMI NA TE Burst terminate 11
Write
(without Auto
precharge)
L H L H READ Truncate Write & start new Read burst 5,6,12
L H L L WRITE Truncate Write & start new Write burst 5,6
L L H L PRECHARGE Truncate Write, start Precharge 12
IS43LR16320B, IS46LR16320B
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9. The following s tates mus t not be interrupted by any executable command; DESE LE CT or NOP commands must be applied to each
positive c lock edge during these states.
• Refreshing: Starts with registration of an AUTO REFRE SH command and ends when tRFC is met.
Once tRFC is met, the Mobile DDR will be in an ''all banks idle'' s tate.
• Accessing M ode Register: Starts with re gistration of a MODE REG ISTE R SET command and ends when tMRD has been met.
Once tMRD is met, the Mobile DDR will be in an ''all b anks idle'' state.
• Precharging All: Starts with the registra tion of a PRECHAR G E ALL command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
10. Not bank-spec ific; requires that all banks are idle and no bursts are in progress .
11. Not bank-specific. BURST TERMINATE affects the most re cent READ burst, regardless of bank.
12. Requires appropriate DM masking.
13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end the
READ prior to asserting a WRITE command.
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Table8 : Current State BANK
n
Truth Table (COMMAND TO BANK
m
)
Current State Command Action Note
/CS /RAS /CAS /WE Description
Any H X X X DESELECT(NOP) Continue previous Operation
L H H H NOP Continue previous Operation
Idle X X X X ANY Any command allowed to bank m
Row Activating, Active,
or Precharging
L L H H ACTIVE Activate Row
L H L H READ St art READ burst 8
L H L L WRITE Start WRITE burst 8
L L H L PRECHARGE Precharge
Read with Auto Precha
rge disabled
L L H H ACTIVE Activate Row
L H L H READ State READ burst 8
L H L L WRITE Start WRITE burst 8,10
L L H L PRECHARGE Precharge
Write with Auto
precharge disabled
L L H H ACTIVE Activate Row
L H L H READ St art READ burst 8,9
L H L L WRITE Start WRITE burst 8
L L H L PRECHARGE Precharge
Read with Auto
Precharge
L L H H ACTIVE Activate Row
L H L H READ St art READ burst 5,8
L H L L WRITE Start WRITE burst 5,8,10
L L H L PRECHARGE Precharge
Write with Auto
precharge
L L H H ACTIVE Activate Row
L H L H READ St art READ burst 5,8
L H L L WRITE Start WRITE burst 5,8
L L H L PRECHARGE Precharge
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Note:
1. The table applies when both CKE
n
-1 and CKE
n
are HIGH , and after tXSR or tXP has been met if the previous state was Self Refresh or
Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illeg al or rese rved.
4. Current State Definitions:
I dle: The bank has been precharged, and tRP has been met.
R ow Active: A row in the bank has been activated, and tRCD has been met. No data bursts/acc ess es and no register acces ses ar e in
progress.
R ead: A READ burst has been initiated, with AU TO PRECHARG E disabled, and has not yet terminated or been terminated.
Write: a WR ITE burst has been initiated, with AU TO PRECHAR GE disabled, and has not yet terminated or been terminated.
5. Read with AP enabled and Write with AP enabled: The read with Autoprecharge enabled or Write with Autoprecharge enabled states
can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge period is defined as if the
same burs t was executed with Auto Precharge disab led and then followed with the earlie st poss ible PR E CHAR GE command that still
ac ces ses all the data in the burst.
For Write with Auto precharge, the pre charge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled.
The access period starts with registration of the command and ends where the precharge pe riod (or tRP ) begins.
During the prechar ge period, of the Read with Autoprecharge enab led or Write with Autoprecharg e enabled s tates, ACT IVE ,
PRECHARGE, READ , and WRITE commands to the other bank may be applied; during the access p eriod, only ACTIV E and PRECHARGE
c ommands to the other banks may be applied. In either cas e, all other related limitations apply
(e.g. contention between READ data and WRITE data must be avoided).
6. AUTO REFRE SH, SELF REFR ESH , and MODE REGISTER SET commands may only be issued when all bank are idle.
7. A BURST TERMINATE command cannot be issued to another bank;
It applies to the bank represented by the current state only.
8. READs or WRITEs listed in the Command column include RE ADs and WRITEs with AUTO PRECHA RG E enabled and READs and WRIT Es
with AUTO PRECHARGE disabled.
9. Requires appropriate DM masking.
10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be issued to
end the READ prior to asserting a WRITE command.
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Table9 : Absolute Maximum Rating
Parameter Symbol Rating Unit
Ambient Temperature (Automotive, A1)
TA
-40 ~ 85
°C
Ambient Temperature (Automotive, A2) -40 ~ 105
Ambient Temperature (Industrial) -40 ~ 85
Ambient Temperature (Commercial) 0 ~ 70
Storage Temperature TSTG -55 ~ 150 °C
Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 2.7 V
Voltage on VDD relative to VSS VDD, VDDQ -0.5 ~ 2.7 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD 0.7 W
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table10 : DC Operating Condition
(Voltage referenced to VSS=0V; TA= 0 ~ 70 °C for Commercial grade; TA= -40 ~ 85 °C for Industrial and Automotive, A1;
TA= -40 ~ 105 °C f or A utomoti ve, A2)
Note :
1. All Voltages are referenced to VSS = 0V
2. VDD and VDDQ must track each other, and VDDQ must not exceed the level of VDD
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 1.7 1.8 1.95 V 1
Power Supply Voltage VDDQ 1.7 1.8 1.95 V 1,2
Input High Voltage VIH (DC) 0.7 x VDDQ VDDQ + 0.3 V
Input Low Voltage VIL (DC) -0.3 0.3 x VDDQ V
Output High Voltage VOH (DC) 0.9 x VDDQ - V IOH=-0.1mA
Output Low Voltage VOL (DC) - 0.1 x VDDQ V IOL=0.1mA
Input Leakage Current ILI -2 2 uA
Output Leakage Current ILO -5 5 uA
Table11 : AC Operating Condition
Note :
1. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same.
Parameter Symbol Min Max Unit Note
Input High Voltage, all inputs VIH (AC) 0.8 x VDDQ VDDQ + 0.3 V
Input Low Voltage, a ll inputs VIL (AC) -0.3 0.2 x VDDQ V
Input Crossing Point Voltage, CK and /CK inputs VIX 0.4 x VDDQ 0.6 x VDDQ V 1
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Table13 : AC Operating Tes t Condition
(Vo lt age r ef eren ced to V SS=0V; TA= 0 ~ 70 °C for Commercial grade; TA= -40 ~ 85 °C for Industrial and Automotive, A1;
TA= -40 ~ 105 °C for Automotive, A2)
Parameter Symbol Value Unit
AC Input High/Low Level Voltage VIH / VIL 0.8 x VDDQ / 0.2 x VDDQ V
Input Timing Measurement Referenc e Level Voltage VTRIP 0.5 x VDDQ V
Input Rise / Fall Time tR / t F 1 / 1 ns
Output Timing Measur ement Refer ence Level Voltage VOUTREF 0.5 x VDDQ V
Output Load Capacitance for Access Time Measurement CL 20 pF
Figure8 : Output load circuit
Table12 : Capacitance (TA=25 °C, f=1MHz, VDD=1.8V)
Parameter Pin Symbol Min Max Unit
Input Capacitance
CK, /CK CI1 1.5 3.0 pF
A0~A12, BA0~BA1, CK E, /C S , /RA S ,
/CAS, /WE CI2 1.5 3.0 pF
LDM, UDM CI3 3.0 5.0 pF
Data & DQS Input/Output Capacitance DQ0~DQ15, LDQS, UDQS CIO 3.0 5.0 pF
Table14 : AC Oversh oot/Unders hoot Specifi ca tion
Parameter Specification
Maximum Peak Amplitude allowed for Overshoot Area 0.9V
Maximum Peak Amplitude allowed for Unders hoot Area 0.9V
Maximum Overshoot Are a above VDD/VDDQ 3V-ns
Maximum Undershoot Area be low VSS/VSSQ 3V-ns
Figure9 : AC Overshoot/Undershoot Definition
Maximum Amplitude
VDD/VDDQ
VSS/VSSQ
Voltage [V]
Maximum Amplitude
Time [ns]
Overshoot Area
Undershoot Ar ea
Output
14.4KΩ
14.4KΩ
1.8V
20pF
Output
20pF
50Ω
VTT=0.5 x VDDQ
Z0=50Ω
DC Output Load Circuit AC Output Load Circuit
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Table15 : DC Characteristic (DC operating conditions unless otherwise noted) (3, 4)
Note : 1. Measured with outputs open.
2. Refresh per iod is 64 ms, applicable for TA ≤ 85°C.
3. All values applicable for operation with TA ≤ 85°C.
4. For A2 temperature grade with TA > 85°C: IDD2P, IDD2PS, IDD3PS are derated to 2x these values; IDD2N,
IDD2NS, IDD3N, IDD3NS, IDD5 are derated to 25% above the values; IDD8 is not tested.
5. Typical value at room temperature.
Parameter Symbol Test Co nditio n Speed Unit Note
-6 -75
Operating one bank active-
precharge current IDD0 tRC = tRC(min),
tCK = tCK(min),
CKE is HIGH, /CS
is HIGH between valid c ommands , address inputs
are SWITCHING, data bus inputs are STABLE 70 65 mA 1
Precharge power-down standby
current IDD2P All banks idle, CKE is LOW, /CS is HIGH, tCK =
tCK(min), address and control inputs are
SWITCHING, data bus inputs are STABLE 0.4 mA
Precharge power-down standby
current with clock stop IDD2PS All banks idle, CKE is LOW, /CS is HIGH, CK = LOW,
/CK = HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE 0.4 mA
Precharge non power-down
standby current IDD2N All banks idle , CKE is HIGH, /CS is HIGH, tCK =
tCK(min)
,
address and control inputs are
SWITCHING, data bus inputs are STABLE 5 mA
Precharge non power-down
standby current with clock s top IDD2NS All banks idle, CKE is HIGH, /CS is HIGH, CK = LOW,
/CK = HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE 2 mA
Active power-down standby
current IDD3P One bank active, CKE is LOW, /CS is HIGH, tCK =
tCK(min), ad dress and control inputs are
SWITCHING, data bus inputs are STABLE 0.5 mA
Active power-down standby
current with clock stop IDD3PS One bank active, CKE is LOW, /CS is HIGH, CK =
LOW, /CK = HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE 0.5 mA
Active non power-down
standby current IDD3N One bank active, CKE is HIGH, /CS is HIGH, tCK =
tCK(min), ad dress and control inputs are
SWITCHING, data bus inputs are STABLE 15 mA
Active non power-down
standby current with clock
stop IDD3NS One bank active, CKE is HIGH, /CS is HIGH, CK =
LOW, /CK = HIGH, addre ss and control inputs are
SWITCHING, data bus inputs are STABLE 10 mA
Operating burst read current IDD4R
One bank active, BL=4, CL=3, tCK = tCK(min),
continuous read bursts, IOUT=0mA,
address inputs are SWITCHING, 50% data change
each burst transfer
110 100 mA 1
Operating burst write current
IDD4W One bank active, BL=4, tCK=tCK(min), continuous
write bursts, address inputs are SWITCHING, 50%
data change each burst transfer 100 90 mA 1
Auto Refresh Current IDD5 tRC=tRFC(min), tCK=tCK(min), burst refresh,
CKE is HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE 90 mA 2
Self
Refresh
Current
PASR TCSR
IDD6
CKE is LOW
CK=LOW, /CK=HIGH
tCK=tCK(min)
Extended Mode Register set to all 0's, address and
control inputs are STABLE , data bus inputs are
STABLE
uA
4 banks 85°C 800
40°C 560
2 Banks 85°C 550
40°C 380
1 Bank 85°C 450
40°C 310
Standby Current in
Deep Power Down Mode IDD8 Address and control inputs are ST ABLE , data bus
inputs are STA BLE 10 uA 5
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Parameter Symbol -6 -75 Unit Note
Min Max Min Max
System Clock Cycle time CL=3 tCK 6 100 7.5 100 ns 1
CL=2 12 12 ns 1
DQ Output access time from CK, /CK CL=3 tAC 2.0 5.5 2.0 6.0 ns
CL=2 2.0 8.0 2.0 8.0
Clock High pulse width tCH 0.45 0.55 0.45 0.55 tCK
Clock Low pulse width tCL 0.45 0.55 0.45 0.55 tCK
DQ and DM Inp ut Se tup time tDS 0.6 0.9 ns 2, 3, 4, 9
DQ and DM Inp ut Hold time tDH 0.6 0.9 ns 2, 3, 4, 9
DQ and DM Inp ut Pulse width tDIPW 1.8 2.0 ns 5
Addre ss and Control Inp ut Setup time tIS 1.1 1.3 ns 4, 6, 7
Address and Control Input Hold time tIH 1.1 1.3 ns 4, 6, 7
DQS - DQ Skew tDQSQ 0.5 0.6 ns
Half Clock Pe rio d tHP min (tCH, tC L ) m in (tC H, tC L) ns
Data Ho ld Sk e w Fac to r tQHS 0.65 0.75 ns
DQ / DQS Output Hold time fro m DQ S tQH tHP-0.65 tHP-0.75 ns
Write C o mm and to first DQS Latching T ransition tDQSS 0.75 1.25 0.75 1.25 tCK
DQS Input High pulse Width tDQSH 0.4 0.6 0.4 0.6 tCK
DQS Input Low pulse Width tDQSL 0.4 0.6 0.4 0.6 tCK
Access Window of DQS from CK, /CK CL=3 tDQSCK 2.0 5.5 2.0 6.0 ns
CL=2 2.0 8.0 2.0 8.0 ns
ACTIVE to PRECHARGE Command Period tRAS 42 100K 45 100K ns
ACTIVE to ACTIVE Command Period tRC 60 67.5 ns
Mode Register Set command cycle time tMRD 2 2 tCK
Refresh Period tREF 64 64 ms 15
Average periodic refresh interval tREFI 7.8 7.8 us 10, 15
Auto Refresh Period tRFC 110 110 ns
Active to Read or Write delay tRCD 18 22.5 ns
Precharge command period tRP 18 22.5 ns
Active Bank
A
to Ac tive Bank
B
Delay tRRD 12 15 ns
Write Recovery time tWR 12 15 ns
Auto Precharge Write Recovery + Precharge time tDAL (tWR/tCK) + (tRP/tCK) 13
Inter nal W rit e to R e ad C o m m and De l ay tWTR 2 1 tCK
DQS Read preamble CL=3 tRPRE 0.9 1.1 0.9 1.1 tCK 11
CL=2 0.5 1.1 0.5 1.1 tCK 11
DQS Read postamble tRPST 0.4 0.6 0.4 0.6 tCK
DQS Write preamble setup time tWPRES 0 0 ns 12
DQS Write pr e amble hold time tWPREH 0.25 0.25 tCK
DQS Write pos tamble tWPST 0.4 0.6 0.4 0.6 tCK
Exit Po w e r Down to ne x t valid co mm and De lay tXP 25 25 ns 14
Self Refresh Exit to next valid Command Delay tXSR 200 200 ns
Table16: AC Character i st i c (AC operation conditions unless otherwise noted)
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Note :
1. The c lock frequency must remain constant (stab le clock is defined as a signal cycling within timing constraints spec ified for the
clock pin) during acc ess or precharge states (R E AD, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
2. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising inp ut signals, and VIH(DC) to
VIL(AC) for falling input signals.
3. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
4. Input slew rate.
5. These parameters guar antee device timing b ut they are not necessar ily tested on each device .
6. The transition time for address and command inp uts is meas ured b etween VI H and VIL.
7. A CK,/CK slew rate must be ≥ 1.0V/ns (2.0V/ns if measured differentially) is assumed for this parameter.
8. tHZ and tLZ transitions occ ur in the same ac ces s time w indows as valid data transitions. These para meters ar e not referred to a specific
voltage level, but specify when the device is no longer driving ( HZ), or begins driving (LZ).
9. Input/Output Delta Rise/Fall Rate Derating
The value 1/slew rate(1) – 1/slew rate (2) (ns/V ) determines the Δrise or Δfall rate and the adder for tDS or tDH.
10. A maximum of eight Refresh c ommands c an be posted to any given Low-Power DDR SDRAM, meaning that the maximum absolute
interval between any Refresh command and the next Refresh command is 8*tREFI.
11. A low level on DQS may be maintained during High -Z states (DQS drivers disabled) by adding a weak pull-down element in the system.
It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled) .
12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
transition is de fined as monotonic and meeting the input slew rate specific ations of the device. When no writes w ere pr eviously in
progress on the bus , DQS will be tra nsitioning from Hi-Z to logic LOW. If a previous write wa s in progr ess , DQS could be HIGH, LOW, or
transitioning from HI GH to LOW at this time, depending on tDQSS.
13. If either add end is not an integer, round up.
14. At least one clock pulse is required during tXP.
15. The specifications in the tab le for TREF and TREFI are applicable for all temperature grades with TA ≤ +85°C. Only A2 temperature grade
supports operation with TA > +85°C, and these values must be further constrained with T REF max of 32ms, and TREFI max of 3.9μs.
Input setup/hold slew rate [V/ns] ∆tIS [ps] ∆tIH [ps] ∆tDS [ps] ∆tDH [ps]
1.0 0 0 0 0
0.8 +50 +50 +75 +75
0.6 +100 +100 +150 +150
CK,/CK setup/hold slew rate [V/ns ] ∆tDS/∆tIS [ps] ∆tDH/∆tIH [ps]
1.0 0 0
I/O ∆ Rise or Fall Rate (ns/V) ∆tDS [ps] ∆tDH [ps]
0 0 0
±0.25 +50 +50
±0.50 +100 +100
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Timing Diagram
Bank/row Activation
The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of the BA0,BA1 inputs
selects the bank, and the address provided on A0-A12(or the highest address bit) selects the row.
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank must be opened. This
is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. The row remains active until a
PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command is issued to the bank.
A PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command must be issued before opening a different
row in the same bank.
Figure11 : tRCD, tRRD, tRC
Once a row is Open(with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the tRCD specification.
tRCD(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command can be entered.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been
closed(precharge). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent
ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
Figure10 : Active command
Notes :
1. RA : Row address
2. BA : Bank address
C L K
/ C L K
CKE
/ CS
/ RAS
/ CAS
/ WE
RA
BA
A 0 ~ A 12
BA 0 , BA 1 Don ’ t care
RD / WT
with AP ACT NOP NOP NOP
Bank a
ROW
ACT NOP
/ CLK
C L K
C ommand
T 0 T 1 T 2 T 3
A 0 - A 12
BA 0 , BA 1
COL
Bank a
T 4 T a 0 T a 1
t RCD
Don
’ t care
ROW
Bank b
t RRD
Bank a
ROW
ACT
t RC
T a 2
tCH tCL
tIS tIH tC K
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Read
The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and address inputs select
the starting column location.
The value of A10 determines whether or not auto-precharge is used. If auto-precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. The valid data-
out elements will be available CAS latency after the READ command is issued.
The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble and the last data-
out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon completion of a burst, assuming no new READ
commands have been initiated, the I/O's will go high-Z.
Figure12 : Read command
Notes :
1. CA : Column address
2. BA : Bank address
3. A10=High : Enable Auto precharge
A10=Low : Disable Auto precharge
Figure13 : Read Data out timing (BL=4)
Notes:
1. BL=4
2. Shown with nominal tAC, tDQSCK and tDQSQ
C L K
/ C L K
CKE
/ CS
/ RAS
/ CAS
/ WE
CA
A 0 ~ A 9
A 10
BA
BA 0 , BA 1 Don
’
t care
Bank a
COL n
/ C L K
C L K
C ommand
T 0 T 1 T 2 T 3 T 1 n T 2 n T 3 n
READ NOP NOP NOP
DQS
DQ
CL = 3
D OUT
n + 1
tRPRE
T 4 T 4 n
NOP
tRPST
D OUT
n D OUT
n + 2 D OUT
n + 3
Don ’ t care
Address
tAC tDQSCK
tQH tLZ tHZ
tDQSQ
DQS
DQ
CL = 2
D
OUT
n + 1
D OUT
n D OUT
n + 2 D OUT
n + 3
tRPRE
tAC tRPST
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Figure14 : Consecutive Read bursts (BL=4)
Figure15 : Non-Co nsecu tiv e R ea d b u rsts ( B L= 4)
Notes:
1. Dout n or m = Data-Out from Column n or m
2. BL=4,8 ,16 (if 4, the bursts are concatenated; If 8 or 16, the second burst interrupts the first)
3. Shown with nominal tAC, tDQSCK and tDQSQ
Notes:
1. Dout n or m = Data-Out from Column n or m
2. BL=4,8 ,16 (if 4, the bursts are concatenated; If 8 or 16, the second burst interrupts the first)
3. Shown with nominal tAC, tDQSCK and tDQSQ
D OUT
m
Bank a
COL m
Bank a
COL n
NOP READ NOP NOP NOP READ
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQ
CL = 3
Command
DQS
Don
’
t care
D OUT
n + 1
D
OUT
n D
OUT
n + 2 D OUT
n + 3 D OUT
m + 1
Bank a
COL m
Bank a
COL n
NOP READ NOP NOP NOP READ
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQ
CL = 3
Command
DQS
Don
’ t care
D
OUT
n + 1
D
OUT
n D
OUT
n + 2 D
OUT
n + 3
CL = 3
NOP
D
OUT
m D
OUT
m + 1
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Figure17 : Read Burs t t ermina t e (B L= 4, 8 or 16)
Truncat ed Reads
Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure16. The BURST TERMINATE
latency is equal to the READ (CAS) latency, i.e., the BURST TERMIN ATE command should be issued x cycles a fter the READ command,
where x equals the number of desired da ta ele m e nt pairs (pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is
necessary, the BURST TERM IN ATE c ommand must be used.
A READ burst may be followed by, or truncated with, a PRECHARG E command to the same bank provided that auto precharge was not
activated. The PRECHARG E command should be issued x cycles after the READ command, where x equals the number of desired data
element pairs (pa irs are required b y the n-prefetch architecture). This is show n in Figure ( RE AD to PRECHA RG E ). Following the
PRECHA RG E command, a subseq uent command to the same bank cannot be issued until tR P is met.
Figure16 : Random Read access
Notes:
1. Dout n or m,p,q = Data-Out from Column n or m,p,q
2. BL=2,4 ,8,1 6 (if 4,8 or 16, the following burs t interrupts the previous)
3. Reads are to an Active row in any bank.
4. Shown with nominal tAC, tDQSCK and tDQSQ
Notes:
1. Dout n = Data-Out from Column n
2. CKE=high
3. Shown with nominal tAC, tDQSCK and tDQSQ
Bank a
COL m Bank a
COL p
D
OUT
p
Bank a
COL q
Bank a
COL n
READ READ READ NOP NOP READ
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQ
CL = 3
Command
DQS
Don
’ t care
D
OUT
n + 1
D
OUT
n D
OUT
m D
OUT
m + 1
NOP
D
OUT
q D
OUT
q + 1
D
OUT
p + 1
Bank a
COL n
NOP READ BST NOP NOP
T 0 T 1 T 2 T 3
A ddress
T 4
/ CLK
CLK
DQ
CL = 3
Command
DQS
Don
’ t care
D OUT
n + 1
D
OUT
n
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Figure19 : Read to Precharge (BL=4)
Figure18 : Read to write terminate (BL=4,8 or 16)
Notes:
1. Dout n = Data-Out from Column n , Din m = Data-In from Column m.
2. CKE=high
3. Shown with nominal tAC, tDQSCK and tDQSQ
Notes:
1. Dout n = Data-Out from Column n.
2. Read to Precharge equals 2 tCK, which allows 2 data pairs of Data-Out.
3. Shown with nominal tAC, tDQSCK and tDQSQ
Bank a
COL m
NOP
Bank a
COL n
NOP READ BST WRITE NOP
T 0 T 1 T 2 T 3
A ddress
T 4
/ CLK
CLK
DQ
CL = 3
Command
DQS
Don
’ t care
D OUT
n + 1
D
OUT
n
tDQSS
( NOM )
D
IN
m D IN
m + 1
T 5
Bank a
( a , or all )
Bank a
COL n
PCG READ NOP ACT NOP NOP
T 0 T 1 T 2 T 3
ADDRESS
T 4 T 5
/ CLK
CLK
DQ
CL = 3
Command
DQS
Bank a
Row
tRP
Don
’ t care
D OUT
n + 1
D OUT
n D OUT
n + 2 D OUT
n + 3
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Figure21 : Write B u rst (B L= 4 )
Write
The WRITE command is used to initiate a Burst Write ac ces s to an active r ow. The value of BA0, BA1 selects the bank and address inp uts
select the starting column loc ation.
The value of A10 determines whether or not auto p recharge is used.If autoprecharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto precharge is not selected, the row will r emain open for subsequent ac ces s. Input data
appearing on the d ata bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given
DM signal is regis tered low , the corresponding da ta will be written to the memory; if the DM signal is register ed high, the c orresponding
data-inputs will be ignored, and a write will not be executed to that byte/column location. The memory controller drives the DQS during
write operations. The initial low s tate of the DQS is known as the write preamb le and the low state following the las t data-in element is w rite
postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z and any additional input
data will be ignored.
Figure20 : Write command
Notes :
1. CA : Column address
2. BA : Bank address
3. A10=High : Enable Auto precharge
A10=Low : Disable Auto precharge
Notes:
1. Din n = Data-In from Column n.
C L K
/ C L K
CKE
/ CS
/ RAS
/ CAS
/ WE
CA
A 0 ~ A 9
A 10
BA
BA 0 , BA 1 Don
’ t care
Bank a
COL m
Bank a
COL n
WRITE NOP WRITE
/ C L K
C L K
T 0 T 1 T 2 T 3 T 1 n T 2 n
DQ
tDQSS tWPST
Don
’ t care
DQS
tWPRES tWPRE tDH tDS
D M
D IN
n D IN
n + 1 D
IN
n + 2 D IN
n + 3
A ddress
Command
tDQSH
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Figure22 : Consecutive Write to write (BL=4)
Figure23 : Non-Co nsecu tiv e W rit e to write ( B L= 4)
Notes:
1. Din n = Data-In from Column n.
2. Each Write comma nd may be to any banks.
Notes:
1. Din n = Data-In from Column n.
2. Each Write comma nd may be to any banks.
WRITE WRITE NOP NOP NOP NOP
Bank a
COL n
D IN
m
Bank a
COL m
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D
IN
n D IN
n + 1 D
IN
n + 2 D IN
n + 3 D
IN
m + 1 D IN
m + 2 D
IN
m + 3
Don ’ t care
NOP WRITE NOP NOP WRITE NOP
Bank a
COL n
D IN
m
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D IN
n D IN
n + 1 D IN
n + 2 D IN
n + 3 D
IN
m + 1 D IN
m + 2 D
IN
m + 3
Don ’ t care
Bank a
COL m
tDQSS
( NOM )
NOP
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Figure24 : Random Write to write
Figure25 : Write to Read (Uninterrupting)
Notes:
1. Din n,p,m,q = Data-In from Column n,p,m,q.
2. Each Write comma nd may be to any banks.
Notes:
1. Din n = Data-In from Column n, Dout m = Data-Out from Column m.
2. tWTR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command ca n be directed to different banks, in which cas e tWTR is not required and the Read command
could be applied ea lie r.
D IN
q + 1
Bank a
COL q
Bank a
COL p
WRITE WRITE WRITE WRITE NOP
Bank a
COL n
D IN
m
Bank a
COL m
T 0 T 1 T 2 T 3
A ddress
T 4
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D IN
n D IN
n + 1 D IN
p D IN
p + 1 D
IN
m + 1 D IN
q
Don ’ t care
T 0 T 1 T 2 T 3 T 4 T 5
NOP WRITE
Bank a
COL m
NOP NOP READ NOP
Bank a
COL n
A ddress
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D IN
n D IN
n + 1 D IN
n + 2 D IN
n + 3
Don ’ t care
CL = 3
NOP NOP
D
OUT
m + 1
D OUT
m
t WTR
D
OUT
m + 2
T 6 T 7
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Figure26 : Write to Read (Interrupting)
Figure27 : Write t o Read (Odd nu mb er of dat a In terru pt in g)
Notes:
1. Din n = Data-In from Column n, Dout m = Data-Out from Column m.
2. tWTR is referenced from the first positive CK edge after the last data-in pair.
Notes:
1. Din n = Data-In from Column n, Dout m = Data-Out from Column m.
2. tWTR is referenced from the first positive CK edge after the last data-in pair.
WRITE NOP
T 6 T 7
NOP NOP READ NOP
Bank a
COL n
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D
IN
n D
IN
n + 1
Don ’ t care
Bank a
COL m
CL = 3
NOP NOP
D
OUT
m + 1
D
OUT
m D OUT
m + 2 D
OUT
m + 3
t WTR
T 6 T 7
T 0 T 1 T 2 T 3 T 4 T 5
DQS
DQ
tDQSS
( NOM )
DM
D
IN
n
Don ’ t care
CL = 3
D
OUT
m + 1
D OUT
m D
OUT
m + 2 D
OUT
m + 3
t WTR
WRITE NOP NOP NOP READ NOP
Bank a
COL n
A ddress
/ CLK
CLK
Command
Bank a
COL m
NOP NOP
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Figure28 : Write to Precharge (Uninterrupting)
Figure29 : Write to Precharge (Interrupting)
Notes:
1. Din n = Data-In from Column n.
2. tWR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command can be directed to different banks, in which case tWR is not required and the Read command
could be applied ea lie r.
Notes:
1. Din n = Data-In from Column n.
2. tWR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command can be directed to different banks, in which case tWR is not required and the Read command
could be applied ea lie r.
PCG NOP WRITE NOP NOP NOP
Bank a
COL n
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D
IN
n D
IN
n + 1 D
IN
n + 2 D IN
n + 3
Don ’ t care
tWR
NOP WRITE NOP NOP PCG NOP
Bank a
COL n
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D IN
n D IN
n + 1
tWR
Don ’ t care
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Figure30 : Write to Precharge (Odd number of data Interrupting)
Notes:
1. Din n = Data-In from Column n.
2. tWR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command can be directed to different banks, in which case tWR is not required and the Read command
could be applied ea lie r.
Don ’ t care
NOP WRITE NOP NOP PCG NOP
Bank a
COL n
T 0 T 1 T 2 T 3
A ddress
T 4 T 5
/ CLK
CLK
DQS
DQ
tDQSS
( NOM )
Command
DM
D IN
n
tWR
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Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The banks will be available
for subsequent row access some specified time (tRP) after the Precharge command issued.
Input A10 determines whether one or all banks are to be precharged. In the case where only one bank is to be precharged (A10=Low),
inputs BA0,BA1 select the banks.
When all banks are to be precharged (A10=High), inputs BA0,BA1 are treated as a “Don’t Care”. Once a bank has been precharged, it is in
the idle state and must be actived prior to any Read or Write commands being issued to that bank.
Figure31 : Precharge comma nd
Notes :
1. BA : Bank address
Mode R egist er
The mode register contains the spec ific mode of operation of the Mobile DDR SDRAM. This register includes the s election of a burst length
( 2, 4, 8, 16), a cas latency(2, 3), a burst type. The mode register set must be done before any activate command after the power up
sequence.
Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command.
tCK 2 CK min
0 1 2 3 4 5 6 7 8
/CLK
CLK
9 10
CMD
tRP
Precharge
All Bank
Mode
Resister
Set
Command
(any)
Figure32 : Mode Resister Set
C L K
/ C L K
CKE
/ CS
/ RAS
/ CAS
/ WE
BA
A 10
BA 0 , BA 1 Don ’ t care
IS43LR16320B, IS46LR16320B
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Figure34 : Self refresh
Self refresh
This state retains data in the Mobile DDR, even if the rest of the system is powered down (even w ithout external clocking) . Note refresh
interval timing while in Self R efresh mod e is scheduled internally in the Mobile DDR and may vary and may not meet tREFI time. "Don't
Care" except CKE, which must remain low . An internal refres h cyc le is scheduled on Self R efresh entry. T he procedure for exit ing Self
Refresh mode requires a series of commands. First clock must be stable before CKE going high. NOP commands should b e issued for the
duration of the refresh exit time (tXSR) , because time is required for the completion of any internal refres h in progres s. Th e use of SELF
REFR E SH mode introduces the poss ibility that an internally timed event can be missed w hen CKE is raised for exit from self re fres h mode.
Figure33 : Auto refresh
Auto refresh
The Auto refresh command is used during normal operation of the Mobile DDR. It is non persistent, so must be issued each time a refresh
is required. The refresh addressing is generated by the internal refresh controller. The Mobile DDR requires AUTO REFRESH commands at an
average periodic interval of tRE FI. To allow for improved efficiency in sched uling and switching b etween tas ks, some flex ibility in the
absolute refr e sh interval is pr ovided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile DDR, and th e
maximum absolute inter val between any AUTO REFRE SH command and the next AUTO REFRE SH command is 8*tR EF I.
AREF NOP NOP NOP AREF PCG NOP
/ C L K
C L K
CKE
T 0
C ommand
T 1 T 3
tCH tCL
DQS , DQ , DM
Tb 0
tIS tIH
A 10
tC K
T 2 T 4 Ta 0
tRP
Don ’ t care
VALID
A 0 ~ A 9 ,
A11, A12 All Banks
One Bank
BA
BA 0 , BA 1
ACT NOP
Tb 0
RA
Ta 2
BA
RA
NOP
VALID
tRFC tRFC
tIS tIH
VALID NOP AREF NOP
/ C L K
C L K
CKE
T 0
C ommand
T 1 T a 0
DQS , DQ , DM
Tb 0
tIS tIH
T a 1
tRP Don ’ t care
Address
tXSR
tIS tIH tIS tIS
VALID
Self - refresh mode entry Self - refresh mode ex it
IS43LR16320B, IS46LR16320B
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Figure35 : Po wer d ow n ( Act iv e or P recharg e)
Figure36 : Deep Power down
Power down
Power down occurs if CKE is set low coincident w ith Device Deselec t or NOP command and when no accesses a re in progres s. If power
down occurs when all banks are idle, it is Prec harge Power Down. If Power down occurs w hen one or more banks are Active, it is referred to
as Active power down. The device cannot stay in this mode for longer than the refresh requirements of the device, without los ing data. The
power down state is exited by setting CKE high while iss uing a Device Des elect or NOP command. A valid command ca n be issued after tX P.
Deep Power d own
The Deep Power-Dow n (DPD) mode enables very low standb y currents. All internal voltage generators inside the M obile DDR are stopped
and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Ne xt Figure, DEEP
POWER-DOWN COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus prior to
entering the DPD mode. While in this state, CKE must be held in a constant low state. To exit the DPD mode, CKE is taken high after the
clock is stable and NOP command must be maintained for at least 200 us.
VALID NOP NOP VALID
/ C L K
C L K
CKE
T 0
C ommand
T 1 Ta 0
tCH tCL
DQS , DQ , DM
tIS tIH
VALID
Address
tC K
VALID
tIS
tIS tIH
tIS tIH
T 2 Ta 1 Tb 0
Must not exceed refres h device limits Don
’
t care
Power - down mode entry Power - down mode exit
t XP
VALID NOP NOP DPD NOP
/ C L K
C L K
CKE
T 0
C ommand
T 1 Ta 0
DQS , DQ , DM
Tb 0
Address
tC KE
VALID
tIS
T 2 Ta 1 Ta 2
Don ’ t care
Deep Power - down mode
entry Deep Power - down mode
exit
T = 200 us
IS43LR16320B, IS46LR16320B
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Clock Stop Mode
Clock stop mode is a feature supp orted by Mobile DDR SDRAM devices. It reduces clock-related power consumption during idle periods of
the device.
Conditions: the Mobile DDR SDRAM supports clock stop in case:
• Th e last access comm and (ACT IVE, REA D, W RITE, PRECHARGE, AUT O REFRES H or MODE REGI STER S ET) has executed to completion,
including any data-out during read bursts; the number of required clock pulses per access command depends on the device's A C timing
parameters and the clock frequency;
• The related timing condition ( tRCD, tWR, tRP, tRFC, tMRD) has been met;
• CKE is held HIGH.
When all conditions have been met, the device is either in ''idle'' or ''row active'' s tate, and clock stop mode may be entered w ith CK held
LOW and /CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command have to be issued for at least one clock
cycle b e fore the next access command ma y be applied. Add itional clock pulse s might be r e quired depending on the system characteristics.
Figure37 illustrates the clock stop mode:
• Initially the device is in c lock stop mode;
• The clock is resta rted with the rising edg e of T0 and a NOP on the command inputs;
• With T1 a valid access c ommand is latched; this comma nd is follow ed by NOP commands in order to allow for clock stop as soon as this
acces s command has c ompleted;
• T
n
is the last clock puls e required b y the access command latc hed with T1 .
• The timing condition of this acces s c ommand is met with the completion of T
n
; therefore Tn is the last clock pulse required by this
command and the clock is then s topped.
Figure 37 : Clock Stop Mode
DQ,DQS (High – Z)
Exit Clock
Stop Mode Enter Clock
Stop Mode
Vail
Command
CKE
T0 T1 T2 T
n
/CLK
CLK
ADD
Timing Condition
CMD
Clock
stopped
Don’t Care
NOP CMD NOP NOP NOP
Valide
High
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Configuration Frequency
(MHz) Speed
(ns) Order Part No. Package
32Mx16 166 6 IS43LR16320B-6BL 60-ball BGA, Lead-free
Ordering Inform ation – VDD = 1.8V
Commercial Ran ge: ( 0 oC to +70oC)
Configuration Frequency
(MHz) Speed
(ns) Order Part No. Package
32Mx16 166 6 IS43LR16320B-6BLI 60-ball BGA, Lead-free
Industrial Range: (-40oC to +85oC)
Configuration Frequency
(MHz) Speed
(ns) Order Part No. Package
32Mx16 166 6 IS46LR16320B-6BLA1 60-ball BGA, Lead-free
Automotive Range, A1: (-40oC to +85oC)
Configuration Frequency
(MHz) Speed
(ns) Order Part No. Package
32Mx16 166 6 IS46LR16320B-6BLA2 60-ball BGA, Lead-free
Automotive Range, A2: (-40oC to +105oC)
Note: The -6 speed option supports -75 timing specifications.
