MB8116800A-70PFTN - Fujitsu

March 1996

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

PRODUCT PROFILE SHEET

Edition 2.1

11mW max. (TTL level) / 5.5mW max. (CMOS level)

•2,097,152 words × 8 bit organization

•Silicon gate, CMOS, Advanced

Capacitor Cell

•All input and output are TTL compatible

•4096 refresh cycles every 65.6ms

•Self refresh function

NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings

are exceeded. Functional operation should be restricted to the conditions as

detailed in the operational sections of this data sheet. Exposure to absolute

maximum rating conditions for extended periods may af fect device reliability.

This device contains circuitry to protect the inputs against

damage due to high static voltages or electric fields. However ,

it is advised that normal precautions be taken to avoid

application of any voltage higher than maximum rated voltages

to this high impedance circuit.

CMOS 2M X 8BIT FAST PAGE MODE DYNAMIC RAM

MB8116800A

-60/-70

Parameter MB8116800A MB8116800A

RAS Access Time

PRODUCT LINE & FEATURES

CMOS 2,097,152 x 8BIT Fast Page Mode Dynamic RAM

The Fujitsu MB8116800A is a fully decoded CMOS Dynamic RAM (DRAM) that contains

16,777,216 memory cells accessible in 8-bit increments. The MB8116800A features a ”fast

page” mode of operation whereby high-speed random access of up to 512-bits of data within

the same row can be selected. The MB8116800A DRAM is ideally suited for mainframe,

buffers, hand-held computers video imaging equipment, and other memory applications where

very low power dissipation and high bandwidth are basic requirements of the design. Since the

standby current of the MB8116800A is very small, the device can be used as a non-volatile

memory in equipment that uses batteries for primary and/or auxiliary power.

The MB8116800A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer

polysilicon and two-layer aluminum process. This process, coupled with advanced stacked

capacitor memory cells, reduces the possibility of soft errors and extends the time interval

between memory refreshes. Clock timing requirements for the MB8116800A are not critical

and all inputs are TTL compatible.

60ns max.

Fast Page Mode Cycle T ime

Plastic SOJ Package

(LCC-28P-M07)

Random Cycle Time

Address Access Time

Plastic TSOP Packages

(FPT-28P-M14)

–60 –70

CAS Access Time

110ns min.

30ns max.

15ns max.

40ns min.

495mW max.

70ns max.

130ns min.

35ns max.

17ns max.

45ns min.

440mW max.

•Early write or OE controlled write capability

•RAS only, CAS-before-RAS, or Hidden

Refresh

•Fast page Mode, Read-Modify-Write

capability

•On chip substrate bias generator for high

performance

Parameter Symbol Value Unit

Voltage at any pin relative to VSS

ABSOLUTE MAXIMUM RATINGS (see NOTE)

VIN, VOUT

Operating Temperature

Voltage of VCC supply relative to VSS

Power Dissipation

Short Circuit Output Current

VCC



TOPE

–0.5 to +7.0

1.0

0 to 70

Storage Temperature TSTG –55 to +125

°C

Package and Ordering Information

28-pin plastic (400mil) SOJ,

order as MB8116800A-××PJ

28-pin plastic (400mil) TSOP-II

with normal bend leads,

order as MB8116800A-××PFTN

Operating current

Standby current

Low Power

Dissipation

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

Fig. 1 – MB8116800A DYNAMIC RAM – BLOCK DIAGRAM

CAPACITANCE (TA = 25°C, f = 1MHz)

Mode

Control

Write

Clock

Gen

A10

A11

RAS

CAS

Clock

Gen #2

Data In

Buffer

DQ1 to

DQ8

VCC

VSS

Data Out

Buffer

Column

Decoder

Clock

Gen #1

Sense Ampl &

I/O Gate

16,777,216 Bit

Storage

Cell

Address

Buffer

Pre-

Decoder

Refresh

Address

Counter

Row

Decoder

Substrate

Bias Gen

Symbol UnitParameter

Input Capacitance, A0 to A11 CIN1 pF

Input Capacitance, RAS, CAS, WE, OE CIN2 pF

Max

Input/Output Capacitance, DQ1 to DQ8 CDQ pF

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

1 Pin Index

PIN ASSIGNMENTS AND DESCRIPTIONS

VCC 1

DQ1

DQ2

DQ3

DQ4

VSS

DQ8

DQ7

DQ6

DQ5

/WE

/RAS

A11

A10

VCC

/CAS

/OE

28-Pin SOJ

(TOP VIEW) Designator Function

A0 to A11 Address inputs

row : A0 to A11

column: A0 to A8

refresh : A0 to A11

RAS Row address strobe

CAS Column address strobe

Write enable

Output enable

DQ1 to DQ8 Data Input/Output

VCC +5.0 volt power supply

VSS Circuit ground

VCC

DQ1

DQ2

DQ3

DQ4

VSS

DQ8

DQ7

DQ6

DQ5

/WE

/RAS

A11

A10

VCC

/CAS

/OE

1 Pin Index

28-Pin TSOP

(TOP VIEW)

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

RECOMMENDED OPERATING CONDITIONS

Symbol UnitMin Typ Max

Parameter

Supply Voltage 4.5

Ambient

5.0 5.5

0°C to +70°C

VCC

Operating Temp.

Notes

VSS

VIH

VIL

00 0

2.4 6.5

–0.3 0.8

Input High Voltage, all inputs

Input High Voltage, all inputs/outputs∗

∗ : Undershoots of up to –2.0 volts with a pulse width not exceeding 20ns are acceptable.

FUNCTIONAL OPERATION

ADDRESS INPUTS

T wenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix. Since only twelve address bits (A0 to

A11) are available, the row and column inputs are separately strobed by RAS and CAS as shown in Figure 1. First, twelve row address bits are input

on pins A0–through–A11 and latched with the row address strobe (RAS) then, nine column address bits are input and latched with the column ad-

dress strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively. The address

latches are of the flow-through type; thus, address information appearing after tRAH (min) + tT is automatically treated as the column address.

WRITE ENABLE

The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is se-

lected. During the read mode, input data is ignored.

DATA INPUT

Input data is written into memory in either of three basic ways–an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The

falling edge of WE or CAS, whichever is later , serves as the input data-latch strobe. In an early write cycle, the input data (DQ1-DQ8) is strobed by

CAS and the setup/hold times are referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes

Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.

DATA OUTPUT

The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers

remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are

obtained under the following conditions:

tRAC : from the falling edge of RAS when tRCD (max) is satisfied.

tCAC : from the falling edge of CAS when tRCD is greater than tRCD (max).

tAA : from column address input when tRAD is greater than tRAD (max).

tOEA : from the falling edge of OE when OE is brought Low after tRAC, tCAC, or t AA.

The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the output buffers remain in a high-im-

pedance state during the entire cycle.

FAST PAGE MODE OF OPERATION

The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the

same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in

which row addresses are common. For each fast page of memory, any of 512 x 8-bits can be accessed and, when multiple MB8116800As are used,

CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read,

write, and/or ready-modify-write cycles are permitted.

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

DC CHARACTERISTICS

Symbol Unit

Parameter

Output high voltage VOH V

Output low voltage VOL

Input leakage current (any input) II(L) µA

Min Typ Max



0.4

Value

(Recommended operating conditions unless otherwise noted) Notes 3

IOH = –5.0mA

IOL = +4.2mA

0V ≤VIN ≤VCC;

4.5V ≤VCC ≤5.5V;

VSS = 0V ; All other pins

under test = 0V

2.4



–10



Conditions

Notes

Output leakage current 0V ≤VOUT ≤VCC;

Data out disabled

IDQ(L)

Operating current

(Average power

supply current)

MB8116800A-60

MB8116800A-70 ICC1 RAS & CAS cycling;

tRC = min

Standby current

(Power supply

current)

TTL level

CMOS level ICC2 RAS = CAS = VIH

RAS = CAS ≥ VCC–0.2V

Refresh current #1

(Average power

supply current)

MB8116800A-60

MB8116800A-70 ICC3 CAS = VIH, RAS cycling;

tRC = min

Fast Page Mode

Current

MB8116800A-60

MB8116800A-70 ICC4 RAS = VIL,, CAS cycling;

tPC = min

Refresh current #2

(Average power

supply current)

MB8116800A-60

MB8116800A-70 ICC5 RAS cycling;

CAS-before-RAS;

tRC = min

10–10 

80

2.0

1.0

80

70

Refresh current #3

(Average power sup-

ply current)

RAS = VIL, CAS = VIL

Self refresh ;

tRASS = min. 1000 µA

MB8116800A-60

MB8116800A-70

ICC9 

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

AC CHARACTERISTICS

Symbol Unit

Parameter

tREF ms

T ime Between Refresh

Min Max

MB8116800A-70

(At recommended operating conditions unless otherwise noted.) Notes 3,4,5

Notes

No. Min Max

65.6

MB8116800A-60



2tRC ns

Random Read/Write Cycle Time 

110

3tRWC ns

Read-Modify-Write Cycle Time 

150

4tRAC ns

Access Time from RAS 60



5tCAC ns

Access Time from CAS 15



6tAA ns

Column Address Access T ime 30



7tOH ns

Output Hold T ime 

8tON ns

Output Buf fer Turn On Delay Time 

9tOFF ns

Output Buf fer Turn Off Delay Time 15



10 tTns

T ransition Time 503

tRP ns

RAS Precharge T ime 

tRAS ns

RAS Pulse Width 10000060

tRSH ns

RAS Hold T ime 

tCRP ns

CAS to RAS Precharge Time 

tRCD ns

RAS to CAS Delay Time 4520

tCAS ns

CAS Pulse Width 

tCSH ns

CAS Hold T ime 

tCPN ns

CAS Precharge T ime (Normal) 

tASR ns

Row Address Set Up T ime 

tRAH ns

Row Address Hold T ime 

tASC ns

Column Address Set Up T ime 

tCAH ns

Column Address Hold T ime 

tAR ns

Column Address Hold T ime from RAS 

tRAD ns

RAS to Column Address Delay T ime 3015

tRAL ns

Column Address to RAS Lead Time 

tCAL ns

Column Address to CAS Lead Time 

tRCS ns

Read Command Set Up T ime 

tRRH ns

Read Command Hold T ime

Referenced to RAS 

29 tRCH ns

Read Command Hold T ime

Referenced to CAS 

tWCS ns

Write Command Set Up Time 

tWCH ns

Write Command Hold Time 

tWCR ns

Write Hold Time from RAS 

tWP ns

WE Pulse Width 

tRWL ns

Write Command to RAS Lead Time 

tCWL ns

Write Command to CAS Lead Time 

65.6



130



174

17

35





503



10000070



5320



3515



6,9

7,9

8,9

11,12

15, 20

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

CAS Set Up T ime for CAS-before-

RAS Refresh

AC CHARACTERISTICS (Continued)

Symbol Unit

Parameter

tDS ns

DIN Set Up T ime

Min Max

MB8116800A-70

(At recommended operating conditions unless otherwise noted.) Notes 3,4,5

Notes

No. Min Max



MB8116800A-60

37 tDH ns

DIN Hold T ime 

38 tDHR ns

Data Hold T ime from RAS 

39 tRWD ns

RAS to WE Delay Time 

40 tCWD ns

CAS to WE Delay Time 

41 tAWD ns

Column Address to WE Delay Time 

tOEA ns

Access Time from OE 15



tOEL ns

OE to RAS Lead T ime for Valid Data 

tOEH ns

OE Hold Time Referenced to WE 

tOED ns

OE to Data In Delay T ime 

tCDD ns

CAS to Data In Delay T ime 15 

tDZC ns

DIN to CAS Delay Time 

tDZO ns

DIN to OE Delay Time 

tRASP ns

Fast Page Mode RAS Pulse width 100000



tCPA ns

Access Time from CAS Precharge 35



tCP ns

Fast Page Mode CAS Precharge Time 

tRHCP ns

Fast Page Mode RAS Hold Time

from CAS Precharge 

66 tCPWD ns

Fast Page Mode CAS Precharge

to WE Delay Time 

9,18

tRPC ns

RAS Precharge T ime to CAS

Active T ime (Refresh cycles) 

tCSR ns



44 CAS Hold Time for CAS-before-

RAS Refresh tCHR ns



46 Output Buf fer Turn Off Delay

from OE tOEZ ns15



tPC ns

Fast Page Mode Read/Write

Cycle Time 

tPRWC ns

Fast Page Mode Read-Modify-Write

Cycle Time 



17 



100000







MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

Notes:

1. Referenced to VSS.

2. ICC depends on the output load conditions and cycle rates;

The

specified values are obtained with the output open. ICC

depends on the number of address change as RAS = VIL,

CAS = VIH and VIL > –0.3V.

ICC1, ICC3, Icc4 and ICC5 are specified at one time of address

cha

nge during RAS = VIL and CAS = VIH. ICC2 is specified

during RAS = VIH and VIL > –0.3V.

3. An initial pause (RAS = CAS = VIH) of 200µs is required after

power-up followed by any eight RAS–only cycles before

proper device operation is achieved. In case of using internal

refresh counter, a minimum of eight CAS-before-RAS initiali-

zation cycles instead of 8 RAS cycles are required.

4. AC characteristics assume tT = 5ns.

5. VIH (min) and VIL (max) are reference levels for measuring tim-

ing of input signals. Also transition times are measured be-

tween VIH (min) and VIL (max).

6. Assumes that tRCD ≤ tRCD (max), tRAD ≤ tRAD (max). If tRCD is

greater than the maximum recommended value shown in this

table, tRAC will be increased by the amount that tRCD exceeds

the value shown. Refer to Fig.2 and 3.

7. If tRCD ≥ tRCD (max), tRAD ≥ tRAD (max), and tASC ≥ tAA

–tCAC–tT, access time is tCAC.

8. If tRAD ≥ tRAD (max) and tASC ≤ tAA –tCAC– tT, access time is

tAA.

9. Measured with a load equivalent to two TTL loads and 100pF.

10. tOFF and tOEZ is specified that output buffer change to high

impedance state.

1 1. Operation within the t RCD (max) limit ensures that tRAC (max)

can be met. tRCD (max) is specified as a reference point only; if

tRC

D is greater than the specified tRCD (max) limit, access time

is controlled exclusively by tCAC or tAA.

12. tRCD (min) = tRAH (min) + 2tT + tASC (min).

13. Operation within the tRAD (max) limit ensures that tRAC (max)

can be met. tRAD (max) is specified as a reference point only; if

tRAD is greater than the specified tRAD (max) limit, access time

is controlled exclusively by tCAC or tAA.

14. Either t RRH or tRCH must be satisfied for a read cycle.

15. tWCS is specified as a reference point only. If tWCS ≥ tWCS

(min)

the data output pin will remain High-Z state through entire

cycle.

16. Assumes that t WCS < tWCS (min).

17. Either t DZC or tDZO must be satisfied.

18. tCPA is access time from the selection of a new column address

(that

is caused by changing CAS from ”L” to ”H”). Therefore, if

tCP is long, tCPA is longer than tCPA (max).

19. Assumes that CAS -before-RAS refresh.

20. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operat-

ing parameters. They are included in the data sheet as an

electrical characteristic only . If tWCS ≥ tWCS (min), the cycle is

an early write cycle and DOUT pin will maintain high impedance

state through-out the entire cycle. If tCWD ≥ tCWD (min), tRWD ≥

tRW

D (min), tAWD ≥ tAWD (min) and tCPWD ≥tCPWD (min) , the

cycle is a read-modify-write cycle and data from the selected

cell will appear at the DOUT pin. If neither of the above

conditions is satisfied, the cycle is a delayed write cycle and

invalid data will appear the DOUT pin, and write operation can

be executed by satisfying tRWL, tCWL, and tRAL specifications.

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

100

120

2006040 10080

70ns version

60ns version

tRAC (ns)

tRCD (ns)

2004030 6050

70ns version

tRAC (ns)

tRAD (ns)

1003020 5040

tCPA (ns)

tCP (ns)

60ns version

70ns version

Fig. 2 – tRAC vs. tRCD Fig. 3 – tRAC vs. tRAD Fig. 4 – tCPA vs. tCP

60ns version

FUNCTIONAL TRUTH TABLE

X; ”H” or ”L”

∗; It is impossible in Fast Page Mode.

Input DataClock Input

Standby

Reflesh Note

Address

Operation Mode

Read Cycle

Write Cycle

(Early Write)

Read-Modify-

Write Cycle

RAS-only

Refresh Cycle

CAS-before-RAS

Refresh Cycle

Hidden Refresh

Cycle

ColumnRow

Previous data

is kept

Input Output

tRCS ≥ tRCS

(min)

tWCS ≥ tWCS

(min)

– – – – H H X X High-Z

Valid – L L H L Valid Valid Yes∗

Valid L L L X High-Z Valid

Valid

Valid L L L Valid Valid

Valid

Valid – L H X X High-Z

–

– L L X X High-Z

–

– tCSR ≥ tCSR

(min)

– H L L Valid

–

H H L

RAS CAS WE OE

H X

Yes∗

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

DESCRIPTION

T o implement a read operation, a valid address is latched in by the RAS and CAS address strobes and with WE set to a High level and OE set

to a low level, the output is valid once the memory access time has elapsed. The access time is determined by RAS(tRAC), CAS(tCAC),

OE(tOEA) or column addresses (tAA) under the following conditions:

If tRCD > tRCD(max), access time = tCAC.

If tRAD > tRAD(max), access time = tAA

If OE is brought Low after tRAC, tCAC, or tAA(whichever occurs later), access time = tOEA.

However, if either CAS or OE goes High, the output returns to a high-impedance state after t OH is satisfied.

RAS

Fig. 5 – READ CYCLE

VIH

VIL

VIH

VIL

CAS

VIH

VIL

A0 to A11

WE VIH

VIL

VIH

VIL

(Output) VOH

VOL

OE VIH

VIL

(Input)

”H” or ”L”

tRC

tRAS

tAR

tRP

tCDD

tRCD

tCRP

tASR tRAH tASC tCAH tOEL

tRCH

tRRH

tRCS

tDZC

tOEA

tOEZ

tDZO tON tOED

tOH

tOFF

tRAD

ROW ADD COLUMN ADD

tRAL

tCAL

tAA

tCAC

tRAC

HIGH-Z

HIGH-Z tOH

tCSH

tRSH

tCAS

tON

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

DESCRIPTION

A write cycle is similar to a read cycle except WE is set to a Low state and OE is an ”H” or ”L” signal. A write cycle can be implemented in either

of three ways – early write, delayed write, or read-modify-write. During all write cycles, timing parameters tRWL, tCWL and tRAL must be satis-

fied. In the early write cycle shown above tWCS satisfied, data on the DQ pin is latched with the falling edge of CAS and written into memory .

RAS

Fig. 6 – EARLY WRITE CYCLE (OE = ”H” or ”L”)

VIH

VIL

VIH

VIL

CAS

VIH

VIL

A0 to A11

WE VIH

VIL

VIH

VIL

(Output) VOH

VOL

(Input)

”H” or ”L”

tRC

tRAS

tRP

tCSH

tRCD

tCRP

tCAS

tASR tRAH tASC tCAH

HIGH-Z

ROW ADD COLUMN ADD

tWCR

tWCS tWCH

tDH

tDS

VALID DATA IN

tRSH

tAR

tDHR

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

RAS

Fig. 7 – DELAYED WRITE CYCLE

VIH

VIL

VIH

VIL

CAS

VIH

VIL

A0 to A11

WE VIH

VIL

VIH

VIL

(Input)

VOH

VOL

OE VIH

VIL

(Output)

”H” or ”L”

DESCRIPTION

In the Delayed write cycle, tWCS is not satisfied; thus, the data on the DQ pins is latched with the falling edge of WE and written into memory .

The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tDS).

tRC

tRAS

tCAS

tRCD

tCRP

tASR tCAH

tRCS

tDZC

Invalid Data

tCSH tRP

tASC

tRAH

tCWL

tWP

tDS

tDH

tOED

tDZO tOEH

tOEZ

ROW

ADD COL

ADD

VALID

DATA IN

tRSH

tWCH tRWL

HIGH-Z

HIGH-Z HIGH-Z

tON

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

RAS

Fig. 8 – READ-MODIFY-WRITE-CYCLE

VIH

VIL

VIH

VIL

CAS

VIH

VIL

A0 to A11

WE VIH

VIL

VIH

VIL

(Input)

VOH

VOL

OE VIH

VIL

(Output)

”H” or ”L”

DESCRIPTION

The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read-modify-write

cycle, OE must be changed from Low to High after the memory access time.

tRWC

tRAS

tRCD

tCRP

tASR tCAH

tRWL

tRCS

tRP

tASC

tRAH

tCWL

tDS

tDH

tOED

tDZO

tOEH

ROW

ADD COL

ADD

tRAD

tCWD

tWP

VALID

tOEZ

tOH

tRWDtAWD

tDZC

HIGH-Z

tCAC

tRAC tAA

tON

HIGH-Z HIGH-Z

VALID

DATA IN

tOEA

MB8116800A-60

MB8116800A-70

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

– PRELIMINARY –

Edition 2.1

RAS

Fig. 9 – FAST PAGE MODE READ CYCLE

VIH

VIL

VIH

VIL

CAS

VIH

VIL

A0 to A11

WE VIH

VIL

VIH

VIL

(Input)

VOH

VOL

OE VIH

VIL

(Output)

”H” or ”L”

DESCRIPTION

The fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address.

This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive

memory cycles in which the row address is latched. The access time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the lastest in

occuring.

tRASP

tCRP

tASR tASC

tRCS

tRHCP

tRP

tRCD

ROW

ADD COL

ADD

tCAS

tRSH

tPC

tCAS

tCP

tRCH tRCS tRCH tRCS

tDZC tCPA

tDZC

tCAH

tAR

tCAH

tRAH tASC

tRRH

tCAH

tASC

tRCH

tCDD

Valid Data

tDZO

tOH

tDZO

tON

tOH

tCAC

tON

tOEA

tAA

tOEZ tOEA

tOED tOED

tOH

tRAD

COL

ADD COL

ADD

tOFF

tCSH

tRAL

tOEL

HIGH-Z

tOFF

HIGH-Z

tDZO tCAC

tOEZ

tAA

HIGH-Z

tRAC

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RAS

Fig. 10 – FAST PAGE MODE EARLY WRITE CYCLE (OE = ”H ”or ”L”)

VIH

VIL

VIH

VIL

CAS

VIH

VIL

A0 to A11

WE VIH

VIL

VIH

VIL

(Input)

VOH

VOL

(Output)

”H” or ”L”

DESCRIPTION

The fast page mode early write cycle is executed in the same manner as the fast page mode read cycle except the states of WE and OE are

reversed. Data appearing on the DQ pins is latched on the falling edge of CAS and written into memory . During the fast page mode early

write cycle, including the delayed (OE) write and read-modify-write cycles, tCWL must be satisfied.

tRASP

tRP

ROW

ADD

tRSH

tPC

tRCD

tCSH

tCAS

tASC

tCAH

COL

ADD COL

ADD

HIGH-Z

tCAS

tCP

COL

ADD

tCAH

tASC

tCAH

VALID

DATA VALID

DATA

tWCS tWCH

tWCS

tWCH tWCS tWCH

tDS tDH

tASC

tRAH

tDS tDH

tAR

tWCR

tDHR

tASR

tCRP

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Fig. 11 – FAST PAGE MODE DELAYED WRITE CYCLE

DESCRIPTION

The fast page mode delayed write cycle is executed in the same manner as the fast page mode early write cycle except for the states of WE

and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the fast page mode delayed write cycle,

OE must be changed from Low to High before WE goes Low (tOED + tT + tDS).

“H” or “L”

Invalid Data

RAS

CAS

(Output)

(Input)

to A

011

VALID VALID

COL

ADD COL

ADD

RASP

RSH

CAS

CRP

ASR

tASC

tCAH

tASC

tCAH

CWL

tOEZ

RCD

RAH

ROW

ADD

tOEH

RCS

tOED

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

VIH

VIL

tON

CSH

tPC

CAS

CWL

RWL

WCH

DZC

tDZO

tOEH tOED

tOEZ

HIGH–Z

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DESCRIPTION

During the fast page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data ap-

pears at the DQ pins during a normal cycle.

CWD

ÉÉ

“H” or “L”

Valid Data

ÉÉ

RAS

CAS

(Output)

(Input)

to A

011

VALID VALID

COL

ADD COL

ADD

RASP

PRWC

CRP

ASR

tASC

tCAH

tASC

CAH

CWL

CAC

tOEZ

tOEA tCPA

HIGH–Z

RCD

RAH

Fig. 12 Fast Page Mode Read Modify Write Cycle

ROW

ADD

tOEH tOEA tOEH

CPWD

RCS

tOED

RAS

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

VIH

VIL

RAD

tON

tAA

AWD

tOEZ

RWD

DZC

RWL

CAC

tDZO

tOED

CWD

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DESCRIPTION

CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low for the

specified setup time (tCSR) before RAS goes Low , the on-chip refresh control clock generators and refresh address counter are enabled. An

internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-be-

fore-RAS refresh operation.

RAS

Fig. 13 – RAS-ONLY REFRESH (WE = OE = ”H”or ”L”)

VIH

VIL

VIH

VIL

A0 to A11

VIH

VIL

(Output) ”H” or ”L”

CAS

RAS

Fig. 14 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = ”H”or ”L”)

VIH

VIL

tRC

(Output)

”H” or ”L”

HIGH–Z

tRAS

CAS VIH

VIL

tRPC

tCPN tCSR tCHR

tRP

tOFF

tOH

DESCRIPTION

Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 4096 row addresses ev-

ery 65.6–milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh.

RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched on the

falling edge of RAS. During RAS-only refresh, D OUT pins are kept in a high-impedance state.

tRC

tRP

tASR tRPC

HIGH–Z

tRAH

tCRP

tOH

tCRP

tRAS

tOFF

ROW ADDRESS

VOH

VOL

VOH

VOL

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RAS

Fig. 15 – HIDDEN REFRESH CYCLE

VIH

VIL

VIH

VIL

CAS

VIH

VIL

A0 to A11

WE VIH

VIL

VIH

VIL

(Input)

VOH

VOL

OE VIH

VIL

(Output)

”H” or ”L”

DESCRIPTION

A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS and cycling

RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that

is required by DRAMs that do not have CAS-before-RAS refresh capability.

tRC

tRP

tCHR

tRC

tRAS tRAS

tRP

tOEL

tRSH

tRAD

tRAH

tASC

tCAH

tRCS tRRH

tCAC

tDZC tCDD

tDZO tOEA tOED

tOEZ

tCRP

tASR

tOH

tOFF

tON

ROW

ADDRESS COLUMN

ADDRESS

VALID DATA OUT

tRCD

tRAL

tAR

tAA

tRAC

HIGH-Z

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DESCRIPTION

A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function of

CAS-before-RAS refresh circuitry . If, a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held Low, read

and write operations are enabled as shown above. Row and column addresses are defined as follows:

Row Address: Bits A0 through A11 are defined by the on-chip refresh counter.

Column Address: Bits A0 through A8 are defined by latching levels on A0–A8 at the second falling edge of CAS.

The CAS-before-RAS Counter Test procedure is as follows;

1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.

2) Use the same column address throughout the test.

3) Write ”0” to all 4096 row addresses at the same column address by using normal write cycles.

4) Read ”0” written in procedure 3) and check; simultaneously write ”1” to the same addresses by using CAS -before-RAS

refresh counter test (read-modify-write cycles). Repeat this procedure 4096 times with addresses generated by the

internal refresh address counter.

5) Read and check data written in procedure 4) by using normal read cycle for all 4096 memory locations.

6) Reverse test data and repeat procedures 3), 4), and 5).

CAS

RAS

Fig. 16 – CAS–BEFORE–RAS REFRESH COUNTER TEST CYCLE

VIH

VIL

VIH

VIL

VIH

VIL

A0 to A11

WE VIH

VIL

VOH

VOL

(Input) VIH

VIL

OE VIH

VIL

(Output)

”H” or ”L”

Symbol Unit

Parameter Min Max

No. Min Max

tFCAC ns

Access Time from CAS

MB8116800A-70

(At recommended operating conditions unless otherwise noted.)

MB8116800A-60



tFCAH ns

Column Address Hold T ime 

tFCWD ns

CAS toWE Delay T ime 

tFCAS ns

CAS Pulse width 

tFRSH ns

RAS Hold T ime 





Note: Assumes that CAS-before-RAS refresh counter test cycle only.

tCRP tRP

tCP

tRCS

tFCAH

tASC

Valid Data

tCWL

tWP

tCHR tFRSH

tRWL

tFCWD

tDH

tDS

tDZC

tOED

tON

tOEA

tDZO tOEZ

tOEH

VALID DATA IN

HIGH–Z

COLUMN ADDRESSES

tFCAC

HIGH–Z HIGH–Z

tFCAS

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CAS Hold T ime tCHS

DESCRIPTION

(At recommended operating conditions unless otherwise noted.)

Note . Assumes self refresh cycle only

Fig. 17 – SELF REFRESH CYCLE (A0–A11 = WE = OE = ”H” or ”L”)

Parameter Unit

Min Max

No. Min Max

100 RAS Pulse Width —100100

MB8116800A-70MB8116800A-60

Symbol

tRASS

101 tRPS 125

——

110

RAS Precharge T ime

102 –50–50

The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is operated

in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator.

If CAS goes to ”L” before RAS goes to ”L” (CBR) and the condition of CAS ”L” and RAS ”L” is kept for term of tRASS (more than 100µs), the

device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using internal refresh

address counter during ”RAS=L” and ”CAS=L”.

Exit from self refresh cycle is performed by toggling RAS and CAS to ”H” with specified tCHS min.. In this time, RAS must be kept ”H” with

specified tRPS min..

Using self refresh mode, data can be retained without external CAS signal during system is in standby.

Restriction for Self Refresh operation ;

For self refresh operation, the notice below must be considered.

1) In the case that distributed CBR refresh are operated between read/write cycles

Self refresh cycles can be executed without special rule if 4,096 cycles of distributed CBR refresh are executed within tREF

max..

2) In the case that burst CBR refresh or distributed/burst /RAS only refresh are operated between read/write cycles

4,096 times of burst CBR refresh or 4,096 times of burst /RAS only refresh must be executed before and after Self refresh

cycles.

—

RAS

(Output)

VIH

VIL

VOH

VOL

VIH

VIL

RASS

tRPS

tRPC

tCSR

CPN

OFF

HIGH–Z

“H” or “L”

tCHS

——

µs

* read/write operation can be performed non refresh time within tNS or tSN

CAS

A0 to A11, WE, OE = ”H” or ”L”

4,096 burst refresh cycle 4,096 burst refresh cycle

RAS VIH

VIL

Read/W rite operation

RASS

Self Refresh operation Read/W rite operation

t< 4ms < 4ms

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PACKAGE DIMENSIONS

(Suffix: -PJ)

Dimensions in

inches (millimeters)

28 15

28-LEAD PLASTIC LEADED CHIP CARRIER

(CASE No.: LCC-28P-M07)

1994 FUJITSU LIMITED C28058S-2C(W)

“A”

.004(0.10)

∗.725±.005

(18.42±0.13)

.050±.005

(1.27±0.13)

.098(2.50)NOM

.650(16.51)REF

INDEX .400(10.16)

NOM

.108(2.75)NOM.

.025(0.64)MIN.

.370±.020

(9.40±0.51)

.432±.005

(10.97±0.13)

∗ Resin protrusion (Each side : .006(0.15)MAX.)

LEAD No.

R.032(0.81)TYP.

.008+.002

–.001

(0.20 )

+0.05

–0.02

.134+.014

–.008 (3.40 )

+0.35

–0.20

Details of “A” part

.032(0.81)

MAX

.017±.004

(0.43±0.10)

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Edition 2.1

PACKAGE DIMENSIONS (Continued)

(Suffix: -PFTN)

Dimensions in

inches (millimeters)

1994 FUJITSU LIMITED F28040S-1C(W)

28-LEAD PLASTIC FLAT PACKAGE

(CASE No.: FPT-28P-M14)

INDEX “A”

Details of “A” part

28 15

.016±.004

(0.40±0.10)

.050(1.27)

TYP .650(16.51)REF

.043+.004

–.002

(1.10 )

+0.10

–0.05

.004(0.10)

.006(0.15)MAX

.006(0.15)

.020(0.50)MAX

.010(0.25)

.400±.004

(10.16±0.10)

.005±.002

(0.125±0.05)

.424±.008

(10.76±0.20)

∗ Resin Protrusion : (Each Side : .006(0.15)MAX)

(MOUNTING

HEIGHT)

.020±.004

(0.50±0.10)

∗.725±.004

(18.41±0.10)

.463±.008

(11.76±0.20)

LEAD No.

0(0)MIN

.008(0.21)

(STAND OFF

HEIGHT)

Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical

semiconductor applications. Complete information sufficient for construction purposes

is not necessarily given.

The information contained in this document has been carefully checked and is believed

to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.

The information contained in this document does not convey any license under the

copyrights, patent rights or trademarks claimed and owned by Fujitsu.

Fujitsu reserves the right to change products or specifications without notice.

No part of this publication may be copied or reproduced in any form or by any means, or

transferred to any third party without prior written consent of Fujitsu.

The products described in this document are not intended for use in equipment requiring

high reliability, such as marine relays and medical life–support systems. For such appli-

cations, contact your Fujitsu sales representative.

If the products and technologies described in this document are controlled by the For-

eign Exchange and Foreign Trade Control Act established in Japan, their export is sub-

ject to prior approval based on the said act.

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Visit our web site for the latest information:

http://www.fujitsumicro.com

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please contact the Fujitsu Microelectronics Customer Response Center (CRC). The CRC

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