ATXMEGA32A4-AUR - Atmel - Datasheet.World

This document contains complete and detailed description of all modules included in

the AVR® XMEGATM A Microcontroller family. The XMEGA A is a family of low power,

high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the

AVR enhanced RISC architecture. The available XMEGA A modules described in this

manual are:

•AVR CPU

•Memories

•DMA - Direct Memory Access Controller

•Event System

•System Clock and Clock options

•Power Management and Sleep Modes

•System Control and Reset

•Battery Backup System

•WDT - Watchdog Timer

•Interrupts and Programmable Multi-level Interrupt Controller

•PORT - I/O Ports

•TC - 16-bit Timer/Counter

•AWeX - Advanced Waveform Extension

•Hi-Res - High Resolution Extension

•RTC - Real Time Counter

•RTC32 - 32-bit Real Time Counter

•TWI - Two Wire Serial Interface

•SPI - Serial Peripheral Interface

•USART - Universal Synchronous and Asynchronous Serial Receiver and Transmitter

•IRCOM - IR Communication Module

•AES and DES Crypto Engine

•EBI - External Bus Interface

•ADC - Analog to Digital Converter

•DAC - Digital to Analog Converter

•AC - Analog Comparator

•IEEE 1149.1 JTAG Interface

•PDI - Program and Debug Interface

•Memory Programming

•Peripheral Address Map

•Register Summary

•Interrupt Vector Summary

•Instruction Set Summary

8077H- AVR-12/09

8-bit

XMEGA A

Microcontroller

XMEGA A

MANUAL

Preliminary

8077H–AVR–12/09

XMEGA A

1. About the Manual

This document contains in-depth documentation of all peripherals and modules available for the

AVR XMEGA A Microcontroller family. All features are documented on a functional level and

described in a general sense. All peripherals and modules described in this manual may not be

present in all XMEGA A devices.

For all device specific information such as characterization data, memory sizes, modules and

peripherals available and their absolute memory addresses refer to the device datasheets.

When several instances of one peripheral such as a PORT exist in one device, each instance of

a module will have a unique name, such as PORTA, PORTB etc. Register, bit names are unique

within one module.

For more details on applied use and code examples for all peripherals and modules, refer to the

XMEGA A specific application notes available from: http://www.atmel.com/avr.

1.1 Reading the Manual

The main sections describe the various modules and peripherals. Each section contains a short

feature list of the most important features and a short overview describing the module. The

remaining section describes the features and functions in more details.

The register description sections list all registers, and describe each bit/flag and its function. This

includes details on how to set up and enable various features in the module. When multiple bits

are needed for a configuration setting, these are grouped together in a bit group. The possible

bit group configurations are listed for all bit groups together with their associated Group Configu-

ration and a short description. The Group Configuration refer to the defined configuration name

used in the XMEGA A and assembler header files and application note source code.

The register summary sections list the internal register map for each module type.

The interrupt vector summary sections list the interrupt vectors and offset address for each mod-

ule type.

1.2 Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

1.3 Recommended Reading

• XMEGA A Device Datasheets

• XMEGA Application Notes

This manual only contains general modules and peripheral descriptions. The XMEGA A device

datasheet contains device specific information. The XMEGA application notes contain example

code and show applied use of the modules and peripherals.

For new users it is recommended to read the AVR1000 - Getting Started Writing C-code for

XMEGA, and AVR1900 - Getting started with ATxmega128A1 application notes.

8077H–AVR–12/09

XMEGA A

2. Overview

The XMEGA A is a family of low power, high performance and peripheral rich CMOS 8/16-bit

microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instruc-

tions in a single clock cycle, the XMEGA A achieves throughputs approaching 1 Million

Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction, executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs many times faster than conven-

tional single-accumulator or CISC based microcontrollers.

The XMEGA A devices provide the following features: In-System Programmable Flash with

Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,

eight-channel Event System and Programmable Multi-level Interrupt Controller, up to 78 general

purpose I/O lines, 16- or 32-bit Real Time Counter (RTC), up to eight flexible 16-bit Timer/Coun-

ters with compare modes and PWM, up to eight USARTs, up to four I2C and SMBUS compatible

Two Wire Serial Interfaces (TWIs), up to four Serial Peripheral Interfaces (SPIs), AES and DES

crypto engine, up to two 8-channel, 12-bit ADCs with optional differential input with programma-

ble gain, up to two 2-channel, 12-bit DACs, up to four analog comparators with window mode,

programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators

with PLL and prescaler and programmable Brown-Out Detection.

The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,

is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this

can also be used for On-chip Debug and programming.

The XMEGA A devices have five software selectable power saving modes. The Idle mode stops

the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all

peripherals to continue functioning. The Power-down mode saves the SRAM and register con-

tents but stops the oscillators, disabling all other functions until the next TWI or pin-change

interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,

allowing the application to maintain a timer base while the rest of the device is sleeping. In

Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is

sleeping. This allows very fast start-up from external crystal combined with low power consump-

tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue

to run. To further reduce power consumption, the peripheral clock to each individual peripheral

can optionally be stopped in Active mode and Idle sleep mode.

The devices are manufactured using Atmel's high-density nonvolatile memory technology. The

program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader

running in the device can use any interface to download the application program to the Flash

memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-

cation Flash section is updated, providing true Read-While-Write operation. By combining an

8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A is a powerful

microcontroller family that provides a highly flexible and cost effective solution for many embed-

ded applications.

The XMEGA A devices are supported with a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators, programmers, and

evaluation kits.

8077H–AVR–12/09

XMEGA A

2.1 Block Diagram

Figure 2-1. XMEGA A Block Diagram

Power

Supervision

POR/BOD &

RESET

PORT A (8)

PORT B (8)

EVENT ROUTING NETWORK

DMA

Controller

BUS

Controller

SRAM

EBI

ADCA

DACA

ACA

DACB

ADCB

ACB

OCD

PORT K (8)

PORT J (8)

PORT H (8)

PDI

CPU

PH[0..7]

PJ[0..7]

PK[0..7]

PA[0..7]

PB[0..7]/

JTAG

Watchdog

Timer

Watchdog

Oscillator

Interrupt

Controller

DATA BUS

Prog/Debug

Controller

VCC

GND

PORT R (2)

XTAL1

XTAL2

PR[0..1]

TOSC1

TOSC2

PQ[0..7]

Oscillator

Circuits/

Clock

Generation

Oscillator

Control

Real Time

Counter

Event System

Controller

JTAG

PDI_D

RESET/

PDI_CLK

PORT B

Sleep

Controller

Flash EEPROM

NVM Controller

DES

AES

IRCOM

PORT C (8)

PC[0..7]

TCC0:1

USARTC0:1

TWIC

SPIC

PORT D (8)

PD[0..7]

TCD0:1

USARTD0:1

TWID

SPID

PORT E (8)

PE[0..7]

TCE0:1

USARTE0:1

TWIE

SPIE

PORT F (8)

PF[0..7]

TCF0:1

USARTF0:1

TWIF

SPIF

PORT G (8) PG[0..7]

PORT L (8) PL[0..7]

PORT Q (8)

PORT N (8)

PORT P (8)

PORT M (8) PL[0..7]

PP[0..7] PN[0..7]

Int. Ref.

AREFA

AREFB

Tempref

VCC/10

8077H–AVR–12/09

XMEGA A

3. AVR CPU

3.1 Features

•8/16-bit high performance AVR RISC CPU

– 138 instructions

– Hardware multiplier

•32x8-bit registers directly connected to the ALU

•Stack in RAM

•Stack Pointer accessible in I/O memory space

•Direct addressing of up to 16M bytes of program memory and 16M bytes of data memory

•True 16/24-bit access to 16/24-bit I/O registers

•Efficient support for both 8-, 16- and 32-bit Arithmetic

•Configuration Change Protection of system critical features

3.2 Overview

XMEGA uses the 8/16-bit AVR CPU. The main function of the CPU is to ensure correct program

execution. The CPU is able to access memories, perform calculations and control peripherals.

Interrupt handling is described in a separate section, refer to ”Interrupts and Programmable

Multi-level Interrupt Controller” on page 123 for more details on this.

3.3 Architectural Overview

In order to maximize performance and parallelism, the AVR uses a Harvard architecture with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the Program Memory. This concept enables instructions to be executed

in every clock cycle. For the summary of all AVR instructions refer to ”Instruction Set Summary”

on page 388. For details of all AVR instructions refer to http://www.atmel.com/avr.

8077H–AVR–12/09

XMEGA A

Figure 3-1. Block Diagram of the AVR Architecture

The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or

between a constant and a register. Single register operations can also be executed in the ALU.

After an arithmetic operation, the Status Register is updated to reflect information about the

result of the operation.

The ALU is directly connected to the fast-access Register File. The 32 x 8-bit general purpose

working registers all have single clock cycle access time allowing single-cycle Arithmetic Logic

Unit (ALU) operation between registers or between a register and an immediate. Six of the 32

registers can be used as three 16-bit address pointers for program and data space addressing -

enabling efficient address calculations.

The memory spaces are all linear and regular memory maps. The Data Memory space and the

Program Memory space are two different memory spaces.

The Data Memory space is divided into I/O registers and SRAM. In addition the EEPROM can

be memory mapped in the Data Memory.

All I/O status and control registers reside in the lowest 4K bytes addresses of the Data Memory.

This is referred to as the I/O Memory space. The lowest 64 addresses can be accessed directly,

or as the data space locations from 0x00 - 0x3F. The rest is the Extended I/O Memory space,

ranging from 0x40 to 0x1FFF. I/O registers here must be access as data space locations using

load (LD/LDS/LDD) and store (ST/STS/STD) instructions.

Flash

Program

Memory

Instruction

Decode

Program

Counter

OCD

32 x 8 General

Purpose

Registers

ALU Multiplier/

DES

Instruction

STATUS/

CONTROL

Peripheral

Module 1

Peripheral

Module n EEPROM PMICSRAM

DATA BUS

8077H–AVR–12/09

XMEGA A

The SRAM holds data, and code cannot be executed from here. It can easily be accessed

through the five different addressing modes supported in the AVR architecture. The first SRAM

address is 0x2000.

Data address 0x1000 to 0x1FFF is reserved for memory mapping of EEPROM.

The Program Memory is divided in two sections, the Application Program section and the Boot

Program section. Both sections have dedicated Lock bits for write and read/write protection. The

SPM instruction that is used for self-programming of the Application Flash memory must reside

in the Boot Program section. A third section exists inside the Application section. This section,

the Application Table section, has separate Lock bits for write and read/write protection. The

Application Table section can be used for storing non-volatile data or application software.

3.4 ALU - Arithmetic Logic Unit

The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or

between a constant and a register. Single register operations can also be executed. The ALU

operates in direct connection with all the 32 general purpose registers. In a typical single cycle

ALU operation, two operands are output from the Register File, the operation is executed, and

the result is stored back in the Register File.

In order to operate on data in the Data Memory, these must first be loaded into the Register File.

After the operation, the data can be stored from the Register File and back to the Data Memory.

The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions.

After an arithmetic or logic operation, the Status Register is updated to reflect information about

the result of the operation.

3.4.1 Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul-

tiplier supports different variations of signed and unsigned integer and fractional numbers:

• Multiplication of unsigned integers.

• Multiplication of signed integers.

• Multiplication of a signed integer with an unsigned integer.

• Multiplication of unsigned fractional numbers.

• Multiplication of signed fractional numbers.

• Multiplication of a signed fractional number and with an unsigned.

A multiplication takes two CPU clock cycles.

3.5 Program Flow

After reset, the program will start to execute from program address 0. Program flow is provided

by conditional and unconditional jump and call instructions, able to directly address the whole

address space. Most instructions have a single 16-bit word format. Every program memory

address contains a 16- or 32-bit instruction. The Program Counter (PC) addresses the location

from where instructions are fetched. During interrupts and subroutine calls, the return address

PC is stored on the Stack.

8077H–AVR–12/09

XMEGA A

When an enabled interrupt occurs, the Program Counter is vectored to the actual interrupt vector

in order to execute the interrupt handling routine. Hardware clears the corresponding interrupt

flag automatically.

A flexible interrupt controller has dedicated control registers with an additional Global Interrupt

Enable bit in the Status Register. All interrupts have a separate interrupt vector, starting from the

Reset Vector at address 0 in the Program Memory. All interrupts have a programmable interrupt

level. Within each level they have priority in accordance with their interrupt vector position where

the lower interrupt vector address has the higher priority.

3.6 Instruction Execution Timing

The AVR CPU is driven by the CPU clock clkCPU. No internal clock division is used. Figure 3-2

on page 8 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 3-2. The Parallel Instruction Fetches and Instruction Executions

Figure 3-3 on page 8 shows the internal timing concept for the Register File. In a single clock

cycle an ALU operation using two register operands is executed, and the result is stored back to

the destination register.

Figure 3-3. Single Cycle ALU Operation

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

8077H–AVR–12/09

XMEGA A

3.7 Status Register

The Status Register (SREG) contains information about the result of the most recently executed

arithmetic or logic instruction. This information can be used for altering program flow in order to

perform conditional operations. Note that the Status Register is updated after all ALU opera-

tions, as specified in the instruction set reference. This will in many cases remove the need for

using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine nor restored

when returning from an interrupt. This must be handled by software.

The Status Register is accessible in the I/O Memory space.

3.8 Stack and Stack Pointer

The Stack is used for storing return addresses after interrupts and subroutine calls. It can also

be used for storing temporary data. The Stack Pointer (SP) register always points to the top of

the Stack. It is implemented as two 8-bit registers that is accessible in the I/O Memory space.

Data is pushed and popped from the Stack using the PUSH and POP instructions. The Stack is

implemented as growing from higher memory locations to lower memory locations. This implies

that a pushing data on the Stack decreases the SP, and popping data off the Stack increases

the SP.The SP is automatically loaded after reset, and the initial value is the highest address of

the internal SRAM. If the SP is changed, it must be set to point above address 0x2000 and it

must be defined before any subroutine calls are executed or before interrupts are enabled.

During interrupts or subroutine calls the return address is automatically pushed on the Stack.

The return address can be two or three bytes, depending of the memory size of the device. For

devices with 128K bytes or less of program memory the return address is two bytes, hence the

Stack Pointer is decremented/incremented by two. For devices with more than 128K bytes of

program memory, the return address is three bytes, hence the SP is decremented/incremented

by three. The return address is popped of the Stack when returning from interrupts using the

RETI instruction, and subroutine calls using the RET instruction.

The SP is decremented by one when data is pushed onto the Stack with the PUSH instruction,

and incremented by one when data is popped off the Stack using the POP instruction.

To prevent corruption when updating the Stack Pointer from software, a write to SPL will auto-

matically disable interrupts for up to 4 instructions or until the next I/O memory write.

3.9 Register File

The Register File consists of 32 x 8-bit general purpose registers. In order to achieve the

required performance and flexibility, the Register File supports the following input/output

schemes:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

8077H–AVR–12/09

XMEGA A

Figure 3-4. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

The Register File is located in a separate address space, so the registers are not accessible as

data memory.

3.9.1 The X-, Y- and Z- Registers

The registers R26..R31 have added functions besides their general-purpose usage.

These registers can form 16-bit address pointers for addressing of the Data Memory. The three

address registers is called the X-, Y-, and Z-register. The Z-register can also be used as an

address pointer to read from and/or write to the Flash Program Memory, Signature Rows, Fuses

and Lock Bits.

Figure 3-5. The X-, Y- and Z-registers

The lowest register address holds the least significant byte (LSB). In the different addressing

modes these address registers have functions as fixed displacement, automatic increment, and

automatic decrement (see the instruction set reference for details).

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Bit (individually) 7R27 07 R26 0

X-register XH XL

Bit (X-register) 15 8 7 0

Bit (individually) 7R29 07 R28 0

Y-register YH YL

Bit (Y-register) 15 8 7 0

Bit (individually) 7R31 07 R30 0

Z-register ZH ZL

Bit (Z-register) 15 8 7 0

8077H–AVR–12/09

XMEGA A

3.10 RAMP and Extended Indirect Registers

In order to access program memory or data memory above 64K bytes, the address or address

pointer must be more than 16-bits. This is done by concatenating one register to one of the X-,

Y- or Z-registers, and this register then holds the most significant byte (MSB) in a 24-bit address

or address pointer.

These registers are only available on devices with external bus interface and/or more than 64K

bytes of program or data memory space. For these devices, only the number of bits required to

address the whole program and data memory space in the device is implemented in the

registers.

3.10.1 RAMPX, RAMPY and RAMPZ Registers

The RAMPX, RAMPY and RAMPZ registers are concatenated with the X-, Y-, and Z-registers

respectively to enable indirect addressing of the whole data memory space above 64K bytes

and up to 16M bytes.

Figure 3-6. The combined RAMPX + X, RAMPY + Y and RAMPZ + Z registers

When reading (ELPM) and writing (SPM) program memory locations above the first 128K bytes

of the program memory, RAMPZ is concatenated with the Z-register to form the 24-bit address.

LPM is not affected by the RAMPZ setting.

3.10.2 RAMPD Register

This register is concatenated with the operand to enable direct addressing of the whole data

memory space above 64K bytes. Together RAMPD and the operand will form a 24-bit address.

Figure 3-7. The combined RAMPD + K register

3.10.3 EIND - Extended Indirect Register

EIND is concatenated with the Z-register to enable indirect jump and call to locations above the

first 128K bytes (64K words) of the program memory.

Figure 3-8. The combined EIND + Z register

Bit (Individually) 7 0 7 0 7 0

RAMPX XH XL

Bit (X-pointer) 23 16 15 8 7 0

Bit (Individually) 7 0 7 0 7 0

RAMPY YH YL

Bit (Y-pointer) 23 16 15 8 7 0

Bit (Individually) 7 0 7 0 7 0

RAMPZ ZH ZL

Bit (Z-pointer) 23 16 15 8 7 0

Bit (Individually) 7 0 15 0

RAMPD K

Bit (D-pointer) 23 16 15 0

Bit (Individually) 7 0 7 0 7 0

EIND ZH ZL

Bit (D-pointer) 23 16 15 8 7 0

8077H–AVR–12/09

XMEGA A

3.11 Accessing 16-bits Registers

The AVR data bus is 8-bit so accessing 16-bit registers requires atomic operations. These regis-

ters must be byte-accessed using two read or write operations. When reading the high byte is

buffered and when writing the low byte will be buffered. A 16-bit register is connected to the 8-bit

bus and a temporary register using a 16-bit bus. This ensures that the low- and high-byte of 16-

bit registers is always accessed simultaneously when reading or writing the register.

For a write operation, the low-byte of the 16-bit register must be written before the high-byte.

The low-byte is then written into the temporary register. When the high-byte of the 16-bit register

is written, the temporary register is copied into the low-byte of the 16-bit register in the same

clock cycle.

For a read operation, the low-byte of the 16-bit register must be read before the high-byte. When

the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the

temporary register in the same clock cycle as the low byte is read. When the high-byte is read, it

is then read from the temporary register.

Interrupts can corrupt the timed sequence if the interrupt is triggered and try to access the same

16-bit register during an atomic 16-bit read/write operations. To prevent this, interrupts can be

disabled when writing or reading 16-bit registers.

The temporary registers can also be read and written directly from user software.

3.11.1 Accessing 24- and 32-bit Registers

For 24- and 32-bit registers the read and write access is done in the same way as described for

16-bit registers, except there are two temporary registers for 24-bit register and three for 32-bit

registers. The least significant byte must be written first when doing a write, and read first when

doing a read.

3.12 Configuration Change Protection

System critical I/O register settings are protected from accidental modification. The SPM instruc-

tion is protected from accidental execution, and the LPM instruction is protected when reading

the fuses and signature row. This is handled globally by the Configuration Change Protection

(CCP) register. Changes to the protected I/O registers or bit, or execution of the protected

instructions are only possible after the CPU writes a signature to the CCP register. The different

signatures is described the register description.

There are 2 mode of operation, one for protected I/O registers and one for protected SPM/LPM.

3.12.1 Sequence for write operation to protected I/O registers

1. The application code writes the signature for change enable of protected I/O registers

to the CCP register.

2. Within 4 instruction cycles, the application code must write the appropriate data to the

protected register. Most protected registers also contain a write enable/change enable

bit. This bit must be written to one in the same operation as the data is written. The pro-

tected change is immediately disabled if the CPU performs write operations to the I/O

8077H–AVR–12/09

XMEGA A

3.12.2 Sequence for execution of protected SPM/LPM

1. The application code writes the signature for execution of protected SPM/LPM to the

CCP register.

2. Within 4 instruction cycles, the application code must execute the appropriate instruc-

tion. The protected change is immediately disabled if the CPU performs write

operations to the data memory, or if SLEEP is executed.

Once the correct signature is written by the CPU, interrupts will be ignored for the configuration

change enable period. Any interrupt request (including Non-Maskable Interrupts) during the

CPP period will set the corresponding interrupt flag as normal and the request is kept pending.

After the CPP period any pending interrupts are executed according to their level and priority.

DMA requests are still handled, but do not influence the protected configuration change enable

period. A signature written by the DMA is ignored.

3.13 Fuse Lock

For some system critical features it is possible to program a fuse to disable all changes in the

associated I/O control registers. If this is done, it will not be possible to change the registers from

the user software, and the fuse can only be reprogrammed using an external programmer.

Details on this are described in the data sheet module where this feature is available.

3.14 Register Description

3.14.1 CCP - Configuration Change Protection Register

• Bit 7:0 - CCP[7:0] - Configuration Change Protection

The CCP register must be written with the correct signature to enable change of the protected

I/O register or execution of the protected instruction for a maximum of 4 CPU instruction cycles.

All interrupts are ignored during these cycles. After these cycles interrupts automatically handled

again by the CPU, and any pending interrupts will be executed according to their level and prior-

ity. When the Protected I/O register signature is written, CCP[0] will read as one as long as the

protected feature is enabled. Similarly when the Protected SPM/LPM signature is written CCP[1]

will read as one as long as the protected feature is enabled. CCP[7:2] will always be read as

zero. Table 3-1 on page 13 shows the signature for the various modes.

3.14.2 RAMPD - Extended Direct Addressing Register

This register is concatenated with the operand for direct addressing (LDS/STS) of the whole

data memory space on devices with more than 64K bytes of data memory. When accessing

Bit 76543210

+0x04 CCP[7:0] CCP

Read/WriteWWWWWWR/WR/W

Initial Value 00000000

Table 3-1. Modes of CPU Change Protection

Signature Group Configuration Description

0x9D SPM Protected SPM/LPM

0xD8 IOREG Protected IO register

8077H–AVR–12/09

XMEGA A

data addresses below 64K bytes, this register is not in use. This register is not available if the

data memory including external memory is less than 64K bytes.

• Bit 7:0 – RAMPD[7:0]: Extended Direct Addressing bits

These bits holds the 8 MSB of the 24-bit address created by RAMPD and the 16-bit operand.

Only the number of bits required to address the available data memory is implemented for each

device. Unused bits will always read as zero.

3.14.3 RAMPX - Extended X-Pointer Register

This register is concatenated with the X-register for indirect addressing (LD/LDD/ST/STD) of the

whole data memory space on devices with more than 64K bytes of data memory. When access-

ing data addresses below 64K bytes, this register is not in use. This register is not available if the

data memory including external memory is less than 64K bytes.

• Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address bits

These bits holds the 8 MSB of the 24-bit address created by RAMPX and the 16-bit X-register.

Only the number of bits required to address the available data memory is implemented for each

device. Unused bits will always read as zero.

3.14.4 RAMPY - Extended Y-Pointer Register

This register is concatenated with the Y-register for indirect addressing (LD/LDD/ST/STD) of the

whole data memory space on devices with more than 64K bytes of data memory. When access-

ing data addresses below 64K bytes, this register is not in use. This register is not available if the

data memory including external memory is less than 64K bytes.

• Bit 7:0 – RAMPY[7:0]: Extended Y-pointer Address bits

These bits hold the 8 MSB of the 24-bit address created by RAMPY and the 16-bit Y-register.

Only the number of bits required to address the available data memory is implemented for each

device. Unused bits will always read as zero.

3.14.5 RAMPZ - Extended Z-Pointer Register

This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the

whole data memory space on devices with more than 64K bytes of data memory. RAMPZ is

concatenated with the Z-register when reading (ELPM) program memory locations above the

Bit 76543210

+0x08 RAMPD[7:0] RAMPD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x09 RAMPX[7:0] RAMPX

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Bit 76543210

+0x0A RAMPY[7:0] RAMPY

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

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XMEGA A

first 64K bytes, and writing (SPM) program memory locations above the first 128K bytes of the

program memory.

When accessing data addressees below 64K bytes, reading program memory locations below

64K bytes and writing program memory locations below 128K bytes, this register is not in use.

This register is not available if the data memory including external memory and program mem-

ory in the device is less than 64K bytes.

• Bit 7:0 – RAMPZ[7:0]: Extended Z-pointer Address bits

These bits holds the 8 MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register.

Only the number of bits required to address the available data and program memory is imple-

mented for each device. Unused bits will always read as zero.

3.14.6 EIND - Extended Indirect Register

This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP)

and call (ECALL) to the whole program memory space devices with more than 128K bytes of

program memory. For jump or call to addressees below 128K bytes, this register is not in use.

This register is not available if the program memory in the device is less than 128K bytes.

• Bit 7:0 - EIND[7:0]: Extended Indirect Address bits

These bits holds the 8 MSB of the 24-bit address created by EIND and the 16-bit Z-register.

Only the number of bits required to access the available program memory is implemented for

each device. Unused bits will always read as zero.

3.14.7 SPL - Stack Pointer Register Low

The SPH and SPL register pair represent the 16-bit value SP. The SP holds the Stack Pointer

that point to the top of the Stack. After reset, the Stack Pointer points to the highest internal

SRAM address.

Only the number of bits required to address the available data memory including external mem-

ory, up to 64K bytes is implemented for each device. Unused bits will always read as zero.

Note: 1. Refer to specific device datasheets for exact initial values.

• Bit 7:0 - SP[7:0]: Stack Pointer Register Low byte

These bits hold the 8 LSB of the 16-bits Stack Pointer (SP).

Bit 76543210

+0x0B RAMPZ[7:0] RAMPZ

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Bit 76543210

+0x0C EIND[7:0] EIND

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Bit 76543210

+0x0D SP[7:0] SPL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value(1) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

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3.14.8 SPH - Stack Pointer Register High

Note: 1. Refer to specific device datasheets for exact initial values.

• Bits 7:0 - SP[15:8]: Stack Pointer Register High byte

These bits hold the 8 MSB of the 16-bits Stack Pointer (SP).

3.14.9 SREG - Status Register

The Status Register (SREG) contains information about the result of the most recently executed

arithmetic or logic instruction.

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for interrupts to be enabled. If the Global Interrupt

Enable Register is cleared, none of the interrupts are enabled independent of the individual

interrupt enable settings. The I-bit is not cleared by hardware after an interrupt has occurred.

The I-bit can be set and cleared by the application with the SEI and CLI instructions, as

described in the “Instruction Set Description”.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions Bit Load (BLD) and Bit Store (BST) use the T-bit as source or destina-

tion for the operated bit. A bit from a register in the Register File can be copied into T by the BST

instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD

instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag (H) indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The Sign bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag (V) supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag (N) indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

Bit 76543210

+0x0E SP[15:8] SPH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value(1) 0/10/10/10/10/10/10/10/1

Bit 76543210

+0x0F I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

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XMEGA A

• Bit 1 – Z: Zero Flag

The Zero Flag (Z) indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag (C) indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

3.15 Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 Reserved - - - - - - - -

+0x01 Reserved - - - - - - - -

+0x02 Reserved - - - - - - - -

+0x03 Reserved - - - - - - - -

+0x04 CCP CCP[7:0] 13

+0x05 Reserved - - - - - - - -

+0x06 Reserved - - - - - - - -

+0x07 Reserved - - - - - - - -

+0x08 RAMPD RAMPD[7:0] 13

+0x09 RAMPX RAMPX[7:0] 14

+0x0A RAMPY RAMPY[7:0] 14

+0x0B RAMPZ RAMPZ[7:0] 14

+0x0C EIND EIND[7:0] 15

+0x0D SPL SPL[7:0] 15

+0x0E SPH SPH[7:0] 16

+0x0F SREG I T H S V N Z C 16

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4. Memories

4.1 Features

•Flash Program Memory

– One linear address space

– In-System Programmable

– Self-Programming and Bootloader support

– Application Section for application code

– Application Table Section for application code or data storage

– Boot Section for application code or bootloader code

– Separate lock bits and protection for all sections

– Built in fast CRC check of a selectable flash program memory section

•Data Memory

– One linear address space

– Single cycle access from CPU

– SRAM

– EEPROM

Byte and page accessible

Optional memory mapping for direct load and store

– I/O Memory

Configuration and Status registers for all peripherals and modules

16 bit-accessible General Purpose Register for global variables or flags

– External Memory support

SRAM

SDRAM

Memory mapped external hardware

– Bus arbitration

Safe and deterministic handling of CPU and DMA Controller priority

– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access

Simultaneous bus access for CPU and DMA Controller

•Production Signature Row Memory for factory programmed data

Device ID for each microcontroller device type

Serial number for each device

Oscillator calibration bytes

ADC, DAC and temperature sensor calibration data

•User Signature Row

One flash page in size

Can be read and written from software

Content is kept after chip erase

4.2 Overview

This section describes the different memories in XMEGA. The AVR architecture has two main

memory spaces, the Program Memory and the Data Memory. Executable code can only reside

in the Program Memory, while data can be stored both in the Program Memory and the Data

Memory. The Data Memory includes both SRAM, and an EEPROM Memory for non-volatile data

storage. All memory spaces are linear and require no paging. Non-Volatile Memory (NVM)

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XMEGA A

spaces can be locked for further write and read/write operations. This prevents unrestricted

access to the application software.

A separate memory section contains the Fuse bytes. These are used for setting important sys-

tem functions, and write access is only possible from an external programmer.

4.3 Flash Program Memory

The XMEGA contains On-chip In-System Reprogrammable Flash memory for program storage.

The Flash memory can be accessed for read and write both from an external programmer

through the PDI, or from application software running in the CPU.

All AVR instructions are 16 or 32 bits wide, and each Flash location is 16 bits wide. The Flash

memory in XMEGA is organized in two main sections, the Application Section and the Boot

Loader section, as shown in Figure 4-1 on page 19. The sizes of the different sections are fixed,

but device dependent. These two sections have separate lock bits and can have different level

of protection. The Store Program Memory (SPM) instruction used to write to the Flash from the

application software, will only operate when executed from the Boot Loader Section.

The Application Section contains an Application Table Section with separate lock settings. This

can be used for safe storage of Non-volatile data in the Program Memory.

Figure 4-1. Flash Memory sections

Application Flash

Section

0x000000

End RWW, End Application

Start NRWW, Start Boot Loader

Flashend

Read-While-Write Section

No Read-While-

Write Section

Application Table

Flash Section

Boot Loader Flash

Section

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XMEGA A

4.3.1 Application Section

The Application section is the section of the Flash that is used for storing the executable applica-

tion code. The protection level for the Application section can be selected by the Boot Lock Bits

for this section. The Application section can not store any Boot Loader code since the SPM

instruction cannot be executed from the Application section.

4.3.2 Application Table section

The Application Table section is a part of the Application Section of the Flash that can be used

for storing data. The size is identical to the Boot Loader Section. The protection level for the

Application Table section can be selected by the Boot Lock Bits for this section. The possibilities

for different protection levels on the Application Section and the Application Table Section

enable safe parameter storage in the Program Memory. If this section is not used for data, appli-

cation code can be reside here.

4.3.3 Boot Loader Section

While the Application Section is used for storing the application code, the Boot Loader software

must be located in the Boot Loader Section since the SPM instruction only can initiate program-

ming when executing from the this section. The SPM instruction can access the entire Flash,

including the Boot Loader Section itself. The protection level for the Boot Loader Section can be

selected by the Boot Loader Lock bits. If this section is not used for Boot Loader software, appli-

cation code can be stored here.

4.3.4 Production Signature Row

The Production Signature Row is a separate memory section for factory programmed data. It

contains calibration data for functions such as oscillators and analog modules. Some of the cali-

bration values will be automatically loaded to the corresponding module or peripheral unit during

reset. Other values must be loaded from the signature row and written to the corresponding

peripheral registers from software. For details on the calibration conditions such as temperature,

voltage references etc. refer to device data sheet.

The production signature row also contains a device ID that identify each microcontroller device

type, and a serial number that is unique for each manufactured device. The serial number con-

sist of the production LOT number, wafer number, and wafer coordinates for the device.

The production signature row can not be written or erased, but it can be read from both applica-

tion software and external programming.

4.3.5 User Signature Row

The User Signature Row is a separate memory section that is fully accessible (read and write)

from application software and external programming. The user signature row is one flash page

in size, and is meant for static user parameter storage, such as calibration data, custom serial

numbers or identification numbers, random number seeds etc. This section is not erased by

Chip Erase commands that erase the Flash, and requires a dedicated erase command. This

ensures parameter storage during multiple program/erase session and on-chip debug sessions.

4.4 Fuses and Lockbits

The Fuses are used to set important system function and can only be written from an external

programming interface. The application software can read the fuses. The fuses are used to con-

figure reset sources such as Brown-out Detector and Watchdog, Start-up configuration, JTAG

enable and JTAG user ID.

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XMEGA A

The Lock bits are used to set protection level on the different flash sections. They are used to

block read and/or write access of the code. Lock bits can be written from en external program-

mer and from the application software to set a more strict protection level, but not to set a less

strict protection level. Chip erase is the only way to erase the lock bits. The lock bits are erased

after the rest of the flash memory is erased.

An unprogrammed fuse or lock bit will have the value one, while a programmed flash or lock bit

will have the value zero.

Both fuses and lock bits are reprogrammable like the Flash Program memory.

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XMEGA A

4.5 Data Memory

The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped

EEPROM and external memory if available. The data memory is organized as one continuous

memory section, as shown in Figure 4-2 on page 22.

Figure 4-2. Data Memory Map

I/O Memory, EEPROM and SRAM will always have the same start addresses for all XMEGA

devices. External Memory (if exist) will always start at the end of Internal SRAM and end at

address 0xFFFFFF.

4.6 Internal SRAM

The internal SRAM is mapped in the Data Memory space, always starting at hexadecimal

address location 0x2000. SRAM is accessed from the CPU by using the load (LD/LDS/LDD) and

store (ST/STS/STD) instructions.

Start/End

Address

I/O Memory

(Up to 4 KB)

EEPROM

(Up to 4 KB)

Internal SRAM

External Memory

(0 to 16 MB)

0x000000

0x001000

0xFFFFFF

0x002000

Data Memory

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XMEGA A

4.7 EEPROM

XMEGA has EEPROM memory for non-volatile data storage. It is addressable either in as a sep-

arate data space (default), or it can be memory mapped and accessed in normal data space.

The EEPROM memory supports both byte and page access.

4.7.1 Data Memory Mapped EEPROM Access

The EEPROM address space can optionally be mapped into the Data Memory space to allow

highly efficient EEPROM reading and EEPROM buffer loading. When doing this EEPROM is

accessible using load and store instructions. Memory mapped EEPROM will always start at

hexadecimal address location 0x1000.

4.8 I/O Memory

The status and configuration registers for all peripherals and modules, including the CPU, are

addressable through I/O memory locations in the data memory space. All I/O locations can be

accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, transferring data

between the 32 general purpose registers in the Register File and the I/O memory. The IN and

OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the

address range 0x00 - 0x1F, specific bit manipulating and checking instructions are available.

The I/O memory definition for an XMEGA device is shown in "Register Summary" in the device

data sheet.

4.8.1 General Purpose I/O Registers

The lowest 16 I/O Memory addresses is reserved for General Purpose I/O Registers. These reg-

isters can be used for storing information, and they are particularly useful for storing global

variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC

instructions.

4.9 External Memory

XMEGA has up to 4 ports dedicated to External Memory, supporting external SRAM, SDRAM,

and memory mapped peripherals such as LCD displays or other memory mapped devices. For

details refer to the External Bus interface (EBI) description. The External Memory address space

will always start at the end of Internal SRAM.

4.10 Data Memory and Bus Arbitration

As the Data Memory organized as four separate sets of memories, the different bus masters

(CPU, DMA Controller read and DMA Controller write) can access different memories at the

same time. As Figure 4-3 on page 24 shows, the CPU can access the External Memory while

the DMA (DMA) Controller is transferring data from Internal SRAM to I/O Memory.

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XMEGA A

Figure 4-3. Bus Access

4.10.1 Bus Priority

When several masters request access to the same bus, the bus priority is in the following order

(from higher to lower priority)

1. Bus Master with ongoing access

2. Bus Master with ongoing burst

a. Alternating DMA Controller Read and DMA Controller Write when the they access

the same Data Memory section.

3. Bus Master requesting burst access

a. CPU has priority

4. Bus Master requesting bus access

a. CPU has priority

4.11 Memory Timing

Read and write access to the I/O Memory takes one CPU clock cycle. Write to SRAM takes one

cycle and read from SRAM takes two cycles. For burst read (DMA), new data is available every

cycle. EEPROM page load (write) takes one cycle and three cycles are required for read. For

burst read, new data is available every second cycle. External memory has multi-cycle read and

write. The number of cycles depends on type of memory and configuration of the External Bus

Interface. Refer to the instruction summary for more details on instructions and instruction

timing.

4.12 Device ID

Each device has a three-byte device ID which identifies the device. These registers identify

Atmel as the manufacturer of the device and the device type. A separate register contains the

revision number of the device.

4.13 JTAG Disable

It is possible to disable the JTAG interface from the application software. This will prevent all

external JTAG access to the memory, until the next device reset or if JTAG is enabled again

CPU

DMA Controller

Read

DMA Controller

Write

Data Memory Bus

I/O Memory

EEPROM

External

Memory

SRAM

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XMEGA A

from the application software. As long as JTAG is disabled the I/O pins required for JTAG can be

used as normal I/O pins.

4.14 IO Memory Protection

Some features in the device is regarded to be critical for safety in some applications. Due to this,

it is possible to lock the IO register related to the Event System and the Advanced Waveform

Extensions. As long as the lock is enabled, all related IO registers are locked and they can not

be written from the application software. The lock registers themselves are protected by the

Configuration Change Protection mechanism, for details refer to ”Configuration Change Protec-

tion” on page 12.

4.15 Register Description - NVM Controller

4.15.1 ADDR2 - Non-Volatile Memory Address Register 2

The ADDR2, ADDR1 and ADDR0 registers represents the 24-bit value ADDR.

• Bit 7:0 - ADDR[23:16]: NVM Address Register Byte 2

This register gives the address extended byte when accessing application and boot section.

4.15.2 ADDR1 - Non-Volatile Memory Address Register 1

• Bit 7:0 - ADDR[15:8]: NVM Address Register Byte 1

This register gives the address high byte when accessing either of the memory locations.

4.15.3 ADDR0 - Non-Volatile Memory Address Register 0

• Bit 7:0 - ADDR[7:0]: NVM Address Register Byte 0

This register gives the address low byte when accessing either of the memory locations.

Bit 76543210

+0x02 ADDR[23:16] ADDR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x01 ADDR[15:8] ADDR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x00 ADDR[7:0] ADDR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

4.15.4 DATA2 - Non-Volatile Memory Data Register Byte 2

The DATA2, DATA1 and ADDR0 registers represents the 24-bit value DATA.

• Bit 7:0 - DATA[23:16]: NVM Data Register 2

This register gives the data value byte 2 when running CRC check on application section, boot

section or combined.

4.15.5 DATA1 - Non-Volatile Memory Data Register 1

• Bit 7:0 - DATA[15:8]: NVM Data Register Byte 1

This register gives the data value byte 1 when accessing application and boot section.

4.15.6 DATA0 - Non-Volatile Memory Data Register 0

• Bit 7:0 - DATA[7:0]: NVM Data Register Byte 0

This register gives the data value byte 0 when accessing either of the memory locations.

4.15.7 CMD - Non-Volatile Memory Command Register

• Bit 7 - Reserved

This bit is unused and reserved for future use. For compatibility with future devices, always write

this bit to zero when this register is written.

• Bit 6:0 -CMD[6:0]: NVM Command

These bits define the programming commands for the flash. Bit six is set for external program-

ming commands. See "Memory Programming data sheet" for programming commands.

Bit 76543210

+0x06 DATA[23:16] DATA2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x05 DATA[15:8] DATA1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x04 DATA[7:0] DATA0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x0A - CMD[6:0] CMD

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

4.15.8 CTRLA - Non-Volatile Memory Control Register A

• Bit 7:1 - Reserved Bits

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 0 - CMDEX: Non-Volatile Memory Command Execute

Setting this bit will execute the command in the CMD register. This bit is protected by the Config-

uration Change Protection (CCP) mechanism, refer to Section 3.12 ”Configuration Change

Protection” on page 12 for details on the CCP.

4.15.9 CTRLB - Non-Volatile Memory Control Register B

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3 - EEMAPEN: EEPROM Data Memory Mapping Enable

Setting this bit will enable Data Memory Mapping of the EEPROM section. The EEPROM can

then be accessed using Load and Store instructions.

• Bit 2 - FPRM: Flash Power Reduction Mode

Setting this bit will enable power saving for the flash memory. The section not being accessed

will be turned off like in sleep mode. If code is running from Application Section, the Boot Loader

Section will be turned off and vice versa. If access to the section that is turned off is required, the

CPU will be halted equally long to the start-up time from the Idle sleep mode.

• Bit 1 - EPRM: EEPROM Power Reduction Mode

Setting this bit will enable power saving for the EEPROM memory. The EEPROM will then be

powered down equal to entering sleep mode. If access is required, the bus master will be halted

equally long as the start-up time from Idle sleep mode.

• Bit 0 - SPMLOCK: SPM Locked

The SPM Locked bit can be written to prevent all further self-programming. The bit is cleared at

reset and cannot be cleared from software. This bit is protected by the Configuration Change

Protection (CCP) mechanism, refer to Section 3.12 ”Configuration Change Protection” on page

12 for details on the CCP.

Bit 76543210

+0x0B -------CMDEXCTRLA

Read/Write RRRRRRRS

Initial Value 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

+0x0C - - - - EEMAPEN FPRM EPRM SPMLOCK CTRLB

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

4.15.10 INTCTRL - Non-Volatile Memory Interrupt Control Register

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:2 - SPMLVL[1:0]: SPM Ready Interrupt Level

These bits enable the Interrupt and select the interrupt level as described in ”Interrupts and Pro-

grammable Multi-level Interrupt Controller” on page 123. The interrupt is a level interrupt, which

will be triggered when the BUSY flag in the STATUS is set to logical 0. Since the interrupt is a

level interrupt note the following.

The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont

be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the

interrupt should be disabled in the interrupt handler.

• Bit 1:0 - EELVL[1:0]: EEPROM Ready Interrupt Level

These bits enable the EEPROM Ready Interrupt and select the interrupt level as described in

”Interrupts and Programmable Multi-level Interrupt Controller” on page 123. The interrupt is a

level interrupt, which will be triggered when the BUSY flag in the STATUS is set to logical 0.

Since the interrupt is a level interrupt note the following.

The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont

be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the

interrupt should be disabled in the interrupt handler.

4.15.11 STATUS - Non-Volatile Memory Status Register

• Bit 7 - NVMBUSY: Non-Volatile Memory Busy

The NVMBSY flag indicates whether the NVM memory (FLASH, EEPROM, Lock-bits) is busy

being programmed. Once a program operation is started, this flag will be set and it remains set

until the program operation is completed. he NVMBSY flag will automatically be cleared when

the operation is finished.

• Bit 6 - FBUSY: Flash Section Busy

The FBUSY flag indicate whether a Flash operation (Page Erase or Page Write) is initiated.

Once a operation is started the FBUSY flag is set, and the Application Section cannot be

accessed. The FBUSY bit will automatically be cleared when the operation is finished.

Bit 76543210

+0x0D - - - - SPMLVL[1:0] EELVL[1:0] INTCTRL

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 7 6 5432 1 0

+0x04 BUSYFBUSY----EELOADFLOADSTATUS

Read/Write R R RRRR R R

Initial Value 0 0 0000 0 0

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XMEGA A

• Bit 5:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1 - EELOAD: EEPROM Page Buffer Active Loading

The EELOAD status flag indicates that the temporary EEPROM page buffer has been loaded

with one or more data bytes. Immediately after an EEPROM load command is issued and byte is

written to NVMDR, or a memory mapped EEPROM buffer load operation is performed, the

EELOAD flag is set, and it remains set until an EEPROM page write- or a page buffer flush oper-

ation is executed.

• Bit 0 - FLOAD: Flash Page Buffer Active Loading

The FLOAD flag indicates that the temporary Flash page buffer has been loaded with one or

more data bytes. Immediately after a Flash load command has been issues and byte is written to

NVMDR, the FLOAD flag is set, and it remains set until an Application- or Boot page write- or a

page buffer flush operation is executed.

4.15.12 LOCKBITS - Non-Volatile Memory Lock Bit Register

This register is a direct mapping of the NVM Lockbits into the IO Memory Space, in order to

enable direct read access from the application software. Refer to ”LOCKBITS - Non-Volatile

Memory Lock Bit Register” on page 34 for description of the Lock Bits.

Bit 76543210

+0x07 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] LOCKBITS

Read/Write RRRRRRRR

Initial Value 1 1 1 1 1 1 1 1

8077H–AVR–12/09

XMEGA A

4.16 Register Description – Fuses and Lockbits

4.16.1 FUSEBYTE0 - Non-Volatile Memory Fuse Byte 0 - JTAG User ID

• Bit 7 - JTAGUID[7:0]: JTAG USER ID

These fuses can be used to set the default JTAG USER ID for the device. During reset, the

JTAGUID fuse bits will be loaded into the MCU JTAG User ID Register.

4.16.2 FUSEBYTE1 - Non-Volatile Memory Fuse Byte1 - Watchdog Configuration

• Bit 7:4 - WDWPER[3:0]: Watchdog Window Timeout Period

The WDWPER fuse bits are used to set initial value of the closed window for the Watchdog

Timer in Window Mode. During reset these fuse bits are automatically written to the WPER bits

Watchdog Window Mode Control Register, refer to Section 11.7.2 ”WINCTRL – Window Mode

Control Register” on page 120 for details.

• BIT 3:0 - WDPER[3:0]: Watchdog Timeout Period

The WDPER fuse bits are used to set initial value of the Watchdog Timeout Period. During reset

these fuse bits are automatically written to the PER bits in the Watchdog Control Register, refer

to Section 11.7.1 ”CTRL – Watchdog Timer Control Register” on page 119 for details.

4.16.3 FUSEBYTE2 - Non-Volatile Memory Fuse Byte2 - Reset Configuration

• Bit 7 - Reserved

This fuse bit is reserved. For compatibility with future devices, always write this bit to one when

this register is written.

Bit 7 6543210

+0x00 JTAGUID[7:0] FUSEBYTE0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0000000

Bit 7 6543210

+0x01 WDWPER[3:0] WDPER[3:0] FUSEBYTE1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0000000

Bit 7 6 543210

+0x02 – BOOTRST – – – – BODPD[1:0] FUSEBYTE2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 111111

8077H–AVR–12/09

XMEGA A

• Bit 6 - BOOTRST: Boot Loader Section Reset Vector

The BOOTRST fuse can be programmed so the Reset Vector is pointing to the first address in

the Boot Loader Flash Section. In this case, the device will start executing from the from Boot

Loader Flash Section after reset.

• Bit 5:2 - Reserved

These fuse bits are reserved. For compatibility with future devices, always write these bits to one

when this register is written.

• Bit 1:0 - BODPD[1:0]: BOD operation in power-down mode

The BODPD fuse bits set the BOD operation mode in all sleep modes except Idle mode.

For details on the BOD and BOD operation modes refer to ”Brown-Out Detection” on page 106.

4.16.4 FUSEBYTE4 - Non-Volatile Memory fuse Byte4 - Start-up Configuration

• Bit 7:5 - Reserved

These fuse bits are reserved. For compatibility with future devices, always write these bits to one

when this register is written.

• Bit: 4 - RSTDISBL - External Reset Disable

This fuse can be programmed to disable the external reset pin functionality. When this is done

pulling this pin low will not cause an external reset.

• Bit 3:2 - STARTUPTIME[1:0]: Start-up time

The STARTUPTIME fuse bits can be used to set at a programmable timeout period from all

reset sources are released and until the internal reset is released from the delay counter.

The delay is timed from the 1kHz output of the ULP oscillator, refer to Section 9.3 ”Reset

Sequence” on page 104 for details.

Table 4-1. Boot Reset Fuse

BOOTRST Reset Address

0 Reset Vector = Boot Loader Reset

1 Reset Vector = Application Reset (address 0x0000)

Table 4-2. BOD operation modes in sleep modes

BODPD[1:0] Description

00 Reserved

01 BOD enabled in sampled mode

10 BOD enabled continuously

11 BOD Disabled

Bit 765 4 3 2 1 0

+0x04 – – – RSTDISBL STARTUPTIME[1:0] WDLOCK JTAGEN FUSEBYTE4

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 0

8077H–AVR–12/09

XMEGA A

• Bit 1 - WDLOCK: Watchdog Timer lock

The WDLOCK fuse can be programmed to lock the Watchdog Timer configuration. When this

fuse is programmed the Watchdog Timer configuration cannot be changed, and the Watchdog

Timer cannot be disabled from the application software. When this fuse is programmed the

ENABLE bit in the watchdog CTRL register is automatically set at reset. The WEN bit in the

watchdog WINCTRL register is not set automatically and needs to be enabled from software.

• Bit 0 - JTAGEN: JTAG enabled

The JTAGEN fuse decides whether or not the JTAG interface is enabled.

When the JTAG interface is disabled all access through JTAG is prohibited, and the device can

only be accessed using the Program and Debug Interface (PDI).

The JTAGEN fuse is only available on devices with JTAG interface.

4.16.5 FUSEBYTE5 - Non-Volatile Memory Fuse Byte 5

• Bit 7:6 - Reserved

These bits are reserved. For compatibility with future devices, always write these bits to one

when this register is written.

Table 4-3. Start-up Time

STARTUPTIME[1:0] 1kHz ULP oscillator Cycles

00 64

01 4

10 Reserved

11 0

Table 4-4. Watchdog Timer locking

WDLOCK Description

0 Watchdog Timer locked for modifications

1 Watchdog Timer not locked

Table 4-5. JTAG Enable

JTAGEN Description

0 JTAG enabled

1 JTAG disabled

Bit 7654 3 2 1 0

+0x05 - - BODACT[1:0] EESAVE BODLEVEL[2:0] FUSEBYTE5

Read/Write R/W R/W R R R/W R/W R/W R/W

Initial Value 1 1 - - - - - -

8077H–AVR–12/09

XMEGA A

• Bit 5:4 - BODACT[1:0]: BOD operation in active mode

The BODACT fuse bits set the BOD operation mode when the device is in active and idle mode

of operation. For details on the BOD and BOD operation modes refer to Section 9.4.2 ”Brown-

Out Detection” on page 106.

• Bit 3 - EESAVE: EEPROM memory is preserved through the Chip Erase

A chip erase command will normally erase the Flash, EEPROM and internal SRAM. If the

EESAVE fuse is programmed, the EEPROM is not erased during chip erase. In case EEPROM

is used to store data independent of software revision, the EEPROM can be preserved through

chip erase.

Changing of the EESAVE fuse bit takes effect immediately after the write time-out elapses.

Hence, it is possible to update EESAVE and perform a chip erase according to the new setting

of EESAVE without leaving and re-entering programming mode

• Bit 2:0 - BODLEVEL[2:0] - Brown out detection voltage level

The BODLEVEL fuse bits sets the nominal BOD level value. During power-on the device is kept

in reset until the VCC level has reached the programmed BOD level. Due to this always ensure

that the BOD level is set lower than the VCC level, also if the BOD is not enabled and used during

normal operation, refer to Section 9.4 ”Reset Sources” on page 104 for details. For BOD level

nominal values, see Table 9-2 on page 106.

4.16.6 LOCKBITS - Non-Volatile Memory Lock Bit Register

• Bit 7:6 - BLBB[1:0]: Boot Lock Bit Boot Loader Section

These bits indicate the locking mode for the Boot Loader Section. Even though the BLBB bits

are writable, they can only be written to a stricter locking. Resetting the BLBB bits is only possi-

ble by executing a Chip Erase Command.

Table 4-6. BOD operation modes in Active and Idle mode

BODACT[1:0] Description

00 Reserved

01 BOD enabled in sampled mode

10 BOD enabled continuously

11 BOD Disabled

Table 4-7. EEPROM memory through Chip Erase

EESAVE Description

0 EEPROM is preserved during chip erase

1 EEPROM is not preserved during chip erase

Bit 76543210

+0x07 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] LOCKBITS

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 1

8077H–AVR–12/09

XMEGA A

• Bit 5:4 - BLBA[1:0]: Boot Lock Bit Application Section

These bits indicate the locking mode for the Application Section. Even though the BLBA bits are

writable, they can only be written to a stricter locking. Resetting the BLBA bits is only possible by

executing a Chip Erase Command.

Table 4-8. Boot Lock Bit for The Boot Loader Section

BLBB[1:0] Group Configuration Description

11 NOLOCK No Lock, no restrictions for SPM and (E)LPM accessing

the Boot Loader section.

10 WLOCK Write Lock, SPM is not allowed to write the Boot Loader

section

01 RLOCK

Read Lock, (E)LPM executing from the Application

section is not allowed to read from the Boot Loader

section.

If the interrupt vectors are placed in the Application

section, interrupts are disabled while executing from the

Boot Loader section.

00 RWLOCK

Read and Write Lock, SPM is not allowed to write to the

Boot Loader section and (E)LPM executing from the

Application section is not allowed to read from the Boot

Loader section.

If the interrupt vectors are placed in the Application

section, interrupts are disabled while executing from the

Boot Loader section

Table 4-9. Boot Lock Bit for the Application Section

BLBA[1:0] Group Configuration Description

11 NOLOCK No Lock, no restrictions for SPM and (E)LPM accessing

the Application Section.

10 WLOCK Write Lock, SPM is not allowed to write them

Application Section

01 RLOCK

Read Lock, (E)LPM executing from the Boot Loader

Section is not allowed to read from the Application

Section.

If the interrupt vectors are placed in the Boot Loader

Section, interrupts are disabled while executing from the

Application Section.

00 RWLOCK

Read and Write Lock, SPM is not allowed to write to the

Application Section and (E)LPM executing from the

Boot Loader Section is not allowed to read from the

Application section.

If the interrupt vectors are placed in the Boot Loader

Section, interrupts are disabled while executing from the

Application Section.

8077H–AVR–12/09

XMEGA A

• Bit 3:2 - BLBAT[1:0]: Boot Lock Bit Application Table Section

These bits indicate the locking mode for the Application Table Section. Even though the BLBAT

bits are writable, they can only be written to a stricter locking. Resetting the BLBAT bits is only

possible by executing a Chip Erase Command.

• Bit 1:0 - LB[1:0]: Lock Bits

These bits indicate the locking mode for the Flash and EEPROM in Programming Mode. These

bits are writable only through an external programming interface. Resetting the Lock Bits is only

possible by executing a Chip Erase Command.

Table 4-10. Boot Lock Bit for the Application Table Section

BLBAT[1:0] Group Configuration Description

11 NOLOCK No Lock, no restrictions for SPM and (E)LPM accessing

the Application Table Section.

10 WLOCK Write Lock, SPM is not allowed to write the Application

Ta ble

01 RLOCK

Read Lock, (E)LPM executing from the Boot Loader

Section is not allowed to read from the Application Table

Section.

If the interrupt vectors are placed in the Boot Loader

Section, interrupts are disabled while executing from the

Application Section.

00 RWLOCK

Read and Write Lock, SPM is not allowed to write to the

Application Table Section and (E)LPM executing from

the Boot Loader Section is not allowed to read from the

Application Table Section.

If the interrupt vectors are placed in the Boot Loader

Section, interrupts are disabled while executing from the

Application Section.

Table 4-11. Boot Lock Bit for The Boot Section

LB[1:0] Group Configuration Description

11 NOLOCK3 No Lock, no memory locks enabled.

10 WLOCK

Write lock, programming of the Flash and EEPROM is

disabled for the programming interface. Fuse bits are

locked for write from the programming interface.

00 RWLOCK

Read and Write Lock, programming and

read/verification of the flash and EEPROM is disabled

for the programming interface. The lock bits and fuses

are locked for read and write from the programming

interface.

8077H–AVR–12/09

XMEGA A

4.17 Register Description - Production Signature Row

4.17.1 RCOSC2M - Internal 2 MHz Oscillator Calibration Register

• Bit 7:0 - RCOSC2M[7:0]: Internal 2 MHz Oscillator Calibration Value

This byte contains the oscillator calibration value for the internal 2 MHz oscillator. Calibration of

the oscillator is performed during production test of the device. During reset this value is auto-

matically loaded into the Calibration Register B for the 2 MHz DFLL, refer to ”CALB - Calibration

4.17.2 RCOSC32K - Internal 32.768 kHz Oscillator Calibration Register

• Bit 7:0 - RCOSC32K[7:0]: Internal 32 kHz Oscillator Calibration Value

This byte contains the oscillator calibration value for the internal 32.768 kHz oscillator. Calibra-

tion of the oscillator is performed during production test of the device. During reset this value is

automatically loaded into the calibration register for the 32.768 kHz oscillator, refer to

”RC32KCAL - 32 KHz Oscillator Calibration Register” on page 90 for more details.

4.17.3 RCOSC32M - Internal 32 MHz RC Oscillator Calibration Register

• Bit 7:0 - RCOSC32M[7:0]: Internal 32 MHz Oscillator Calibration Value

This byte contains the oscillator calibration value for the internal 32 MHz oscillator. Calibration of

the oscillator is performed during production test of the device. During reset this value is auto-

matically loaded into the Calibration Register B for the 32 MHz DFLL, refer to ”CALB -

Calibration Register B” on page 92 for more details.

Bit 7654 3 2 1 0

+0x00 RCOSC2M[7:0] RCOSC2M

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x01 RCOSC32K[7:0] RCOSC32K

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x02 RCOSC32M[7:0] RCOSC32M

Read/Write R R R R R R R R

Initial Value x x x x x x x x

8077H–AVR–12/09

XMEGA A

4.17.4 LOTNUM0 - Lot Number Register 0

LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4 and LOTNUM5 contains the LOT

number for each device. Together with the wafer number and wafer coordinates this gives an

unique identifier or serial number for the device.

• Bit 7:0 - LOTNUM0[7:0] - LOT Number Byte 0

This byte contains byte 0 of the LOT number for the device.

4.17.5 LOTNUM1 - Lot Number Register 1

• Bit 7:0 - LOTNUM1[7:0] - LOT Number Byte 1

This byte contains byte 1 of the LOT number for the device.

4.17.6 LOTNUM2 - Lot Number Register 2

• Bit 7:0 - LOTNUM2[7:0] - LOT Number Byte 2

This byte contains byte 2 of the LOT number for the device.

4.17.7 LOTNUM3- Lot Number Register 3

• Bit 7:0 - LOTNUM3[7:0] - LOT Number Byte 3

This byte contains byte 3 of the LOT number for the device.

Bit 7654 3 2 1 0

+0x07 LOTNUM0[7:0] LOTNUM0

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x07 LOTNUM1[7:0] LOTNUM1

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x08 LOTNUM2[7:0] LOTNUM2

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x09 LOTNUM3[7:0] LOTNUM3

Read/Write R R R R R R R R

Initial Value x x x x x x x x

8077H–AVR–12/09

XMEGA A

4.17.8 LOTNUM4 - Lot Number Register 4

• Bit 7:0 - LOTNUM4[7:0] - LOT Number Byte 4

This byte contains byte 4 of the LOT number for the device.

4.17.9 LOTNUM5 - Lot Number Register 5

• Bit 7:0 - LOTNUM5[7:0] - LOT Number Byte 5

This byte contains byte 5of the LOT number for the device.

4.17.10 WAFNUM - Wafer Number Register

• Bit 7:0 - WAFNUM[7:0] - Wafer Number

This byte contains the wafer number for each device. Together with the LOT number and wafer

coordinates this gives an unique identifier or serial number for the device.

4.17.11 COORDX0 - Wafer Coordinate X Register 0

COORDX0, COORDX1, COORDY0 and COORDY1 contains the wafer X and Y coordinates for

each device. Together with the LOT number and wafer number this gives an unique identifier er

or serial number for each devicei

• Bit 7:0 - COORDX0[7:0] - Wafer Coordinate X Byte 0

This byte contains byte 0 of wafer coordinate X for the device.

Bit 7654 3 2 1 0

+0x0A LOTNUM4[7:0] LOTNUM4

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x0B LOTNUM5[7:0] LOTNUM5

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x10 WAFNUM[7:0] WAFNUM

Read/Write R R R R R R R R

Initial Value 0 0 0 x x x x x

Bit 7654 3 2 1 0

+0x12 COORDX0[7:0] COORDX0

Read/Write R R R R R R R R

Initial Value x x x x x x x x

8077H–AVR–12/09

XMEGA A

4.17.12 COORDX1 - Wafer Coordinate X Register 1

• Bit 7:0 - COORDX0[7:0] - Wafer Coordinate X Byte 1

This byte contains byte 1 of wafer coordinate X for the device.

4.17.13 COORDY0 - Wafer Coordinate Y Register 0

• Bit 7:0 - COORDY0[7:0] - Wafer Coordinate Y Byte 0

This byte contains byte 0 of wafer coordinate Y for the device.

4.17.14 COORDY1 - Wafer Coordinate Y Register 1

• Bit 7:0 - COORDY1[7:0] - Wafer Coordinate Y Byte 1

This byte contains byte 1 of wafer coordinate Y for the device

4.17.15 ADCACAL0 - ADCA Calibration Register 0

ADCACAL0 and ADCACAL1 contains the calibration value for the Analog to Digital Converter A

(ADCA). Calibration of the Analog to Digital Converters are done during production test of the

device. The calibration bytes are not loaded automatically into the ADC calibration registers, and

this must be done from software..

• Bit 7:0 - ADCACAL0[7:0] - ADCA Calibration Byte 0

This byte contains byte 0 of the ADCA calibration data, and must be loaded into the ADCA CALL

Bit 7654 3 2 1 0

+0x13 COORDX1[7:0] COORDX1

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x14 COORDY0[7:0] COORDY0

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x15 COORDY1[7:0] COORDY1

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x20 ADCACAL0[7:0] ADCACAL0

Read/Write R R R R R R R R

Initial Value x x x x x x x x

8077H–AVR–12/09

XMEGA A

4.17.16 ADCACAL1 - ADCA Calibration Register 1

• Bit 7:0 - ADCACAL1[7:0] - ADCA Calibration Byte 1

This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA

CALH register.

4.17.17 ADCBCAL0 - ADCB Calibration Register 0

ADCBCAL0 and ADCBCAL1 contains the calibration value for the Analog to Digital Converter

B(ADCB). Calibration of the Analog to Digital Converters are done during production test of the

device. The calibration bytes not loaded automatically into the ADC calibration registers, and

this must be done from software.

• Bit 7:0 - ADCBCAL0[7:0] - ADCB Calibration Byte 0

This byte contains byte 0 of the ADCB calibration data, and must be loaded into the ADCB CALL

4.17.18 ADCBCAL1 - ADCB Calibration Register 1

• Bit 7:0 - ADCBCAL0[7:0] - ADCB Calibration Byte 1

This byte contains byte 1 of the ADCB calibration data, and must be loaded into the ADCB

CALH register.

4.17.19 TEMPSENSE0 - Temperature Sensor Calibration Register 0

TEMPSENSE0 and TEMPSENSE1 contains the 12-bit ADCA value from a temperature mea-

surements done with the internal temperature sensor. The measurements is done in production

test at 85C and can be used for single- or multi-point temperature sensor calibration.

Bit 7654 3 2 1 0

+0x21 ADCACAL1[7:0] ADCACAL1

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x20 ADCBCAL0[7:0] ADCBCAL0

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x21 ADCBCAL1[7:0] ADCBCAL1

Read/Write R R R R R R R R

Initial Value x x x x x x x x

Bit 7654 3 2 1 0

+0x2E TEMPSENSE0[7:0] TEMPSENSE0

Read/Write R R R R R R R R

Initial Value x x x x x x x x

8077H–AVR–12/09

XMEGA A

• Bit 7:0 - TEMPSENSE0[7:0] - Temperature Sensor Calibration Byte 0

This byte contains the byte 0 (8 LSB) of the temperature measurement.

4.17.20 TEMPSENSE1 - Temperature Sensor Calibration Register 1

• Bit 7:0 - TEMPSENSE1[7:0] - Temperature Sensor Calibration Byte 1

This byte contains byte 1 of the temperature measurement.

4.17.21 DACAGAINCAL - DACA Gain Calibration Register

• Bit 7:0 - DACAGAINCAL[7:0] - DACA Gain Calibration Byte

This byte contains the gain calibration value for the Digital to Analog Converter A (DACA). Cali-

bration of the Digital to Analog Converters are done during production test of the device. The

calibration byte is not loaded automatically into the DAC Gain Calibration register, and this must

be done from software.

4.17.22 DACAOFFCAL - DACA Offset Calibration Register

• Bit 7:0 - DACAOFFCAL[7:0] - DACA Offset Calibration Byte

This byte contains the offset calibration value for the Digital to Analog Converter A (DACA). Cal-

ibration of the Digital to Analog Converters are done during production test of the device. The

calibration byte is not loaded automatically into the DAC Offset Calibration register, and this

must be done from software.

4.17.23 DACBGAINCAL - DACB Gain Calibration Register

Bit 7654 3 2 1 0

+0x2F TEMPSENSE1[7:0] TEMPSENSE1

Read/Write R R R R R R R R

Initial Value 0 0 0 0 x x x x

Bit 7654 3 2 1 0

+0x30 DACAGAINCAL[7:0] DACAGAINCAL

Read/Write R R R R R R R R

Initial Value 0 0 0 0 x x x x

Bit 7654 3 2 1 0

+0x31 DACAOFFCAL[7:0] DACAOFFCAL

Read/Write R R R R R R R R

Initial Value 0 0 0 0 x x x x

Bit 7654 3 2 1 0

+0x32 DACBGAINCAL[7:0] DACBGAINCAL

Read/Write R R R R R R R R

Initial Value 0 0 0 0 x x x x

8077H–AVR–12/09

XMEGA A

• Bit 7:0 - DACAGAINCAL[7:0] - DACB Gain Calibration Byte

This byte contains the gain calibration value for the Digital to Analog Converter B (DACB). Cali-

bration of the Digital to Analog Converters are done during production test of the device. The

calibration byte is not loaded automatically into the DAC Gain Calibration register, and this must

be done from software.

4.17.24 DACBOFFCAL - DACB Offset Calibration Register

• Bit 7:0 - DACBOFFCAL[7:0] - DACB Offset Calibration Byte

This byte contains the offset calibration value for the Digital to Analog Converter B (DACB). Cal-

ibration of the Digital to Analog Converters are done during production test of the device. The

calibration byte is not loaded automatically into the DAC Offset Calibration register, and this

must be done from software.

4.18 Register Description – General Purpose I/O Memory

4.18.1 GPIORn – General Purpose I/O Register n

This is a general purpose register that can be used to store data such as global variables in the

bit accessible I/O memory space.

4.19 Register Description – External Memory

Refer to ”EBI - External Bus Interface” on page 268.

4.20 Register Description – MCU Control

4.20.1 DEVID0 - MCU Device ID Register 0

The DEVID0, DEVID1 and DEVID2 contains the 3-byte identification that identify each micro-

controller device type. For details on the actual ID refer to the device data sheet.

Bit 7654 3 2 1 0

+0x33 DACBOFFCAL[7:0] DACAOFFCAL

Read/Write R R R R R R R R

Initial Value 0 0 0 0 x x x x

Bit 76543210

+n GPIORn[7:0] GPIORn

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x00 DEVID0[7:0] DEVID0

Read/Write RRRRRRRR

Initial Value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

8077H–AVR–12/09

XMEGA A

• Bit 7:0 - DEVID0[7:0]: MCU Device ID Byte 1

This byte will always be read as 0x1E. This indicates that the device is manufactured by Atmel

4.20.2 DEVID1 - MCU Device ID Register 1

• Bit 7:0 - DEVID[7:0]: MCU Device ID Byte 1

Byte 1 of the device ID indicates the flash size of the device.

4.20.3 DEVID2 - MCU Device ID Register 2

• Bit 7:0 - DEVID2[7:0]: MCU Device ID Byte 2

Byte 0 of the device ID indicates the device number.

4.20.4 REVID - MCU Revision ID

• Bit 7:4 - Reserved

These bits are reserved and will always read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 3:0 - REVID[3:0]: MCU Revision ID

These bits contains the device revision. 0=A, 1=B and so on.

4.20.5 JTAGUID – JTAG User ID Register

Bit 76543210

+0x01 DEVID1[7:0] DEVID1

Read/Write RRRRRRRR

Initial Value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

Bit 76543210

+0x02 DEVID2[7:0] DEVID2

Read/Write RRRRRRRR

Initial Value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

Bit 76543210

+0x03 -- - - REVID[3:0] REVID

Read/Write RRRRRRRR

Initial Value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

Bit 76543210

+0x04 JTAGUID[7:0] JTAGUID

Read/Write RRRRRRRR

Initial Value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

8077H–AVR–12/09

XMEGA A

• Bit 7:0 - JTAGUID[7:0]: JTAG User ID

The JTAGUID can be used to identify two devices with identical Device ID in a JTAG scan chain.

The JTAGUID will during reset automatically be loaded from flash and placed in these registers.

4.20.6 MCUCR – MCU Control Register

• Bit 7:1 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 0 - JTAGD: JTAG Disable

Setting this bit will disable the JTAG interface. This bit is protected by the Configuration Change

Protection mechanism, for details refer to Section 3.12 ”Configuration Change Protection” on

page 12.

4.20.7 EVSYSLOCK – Event System Lock Register

• Bit 7:5 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 4 - EVSYS1LOCK:

Setting this bit will lock all registers in the Event System related to event channels 4 to 7 for fur-

ther modifications. The following registers in the Event System are locked: CH4MUX,

CH4CTRL, CH5MUX, CH5CTRL, CH6MUX, CH6CTRL, CH7MUX, CH7CTRL. This bit is pro-

tected by the Configuration Change Protection mechanism, for details refer to Section 3.12

”Configuration Change Protection” on page 12.

• Bit 3:1 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 0 - EVSYS0LOCK:

Setting this bit will lock all registers in the Event System related to event channels 0 to 3 for fur-

ther modifications. The following registers in the Event System are locked: CH0MUX,

CH0CTRL, CH1MUX, CH1CTRL, CH2MUX, CH2CTRL, CH3MUX, CH3CTRL. This bit is pro-

Bit 76543210

+0x06 -------JTAGD MCUCR

Read/Write RRRRRRRR/W

Initial Value 0 0 0 0 0 0 0 0

Bit 765 4 321 0

+0x08 –––EVSYS1LOCK –––EVSYS0LOCK EVSYS_LOCK

Read/Write R R R R/W R R R R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

tected by the Configuration Change Protection mechanism, for details refer to Section 3.12

”Configuration Change Protection” on page 12.

4.20.8 AWEXLOCK – Advanced Waveform Extension Lock Register

• Bit 7:3 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 2 - AWEXELOCK: Advanced Waveform Extension Lock for TCE0

Setting this bit will lock all registers in the AWEXE module for Timer/Counter E0 for further mod-

ifications. This bit is protected by the Configuration Change Protection mechanism, for details

refer to Section 3.12 ”Configuration Change Protection” on page 12.

• Bit 1 - Reserved

This bit is reserved and will always be read as zero. For compatibility with future devices, always

write this bit to zero when this register is written.

• Bit 0 - AWEXCLOCK: Advanced Waveform Extension Lock for TCC0

Setting this bit will lock all registers in the AWEXC module for Timer/Counter C0 for further mod-

ifications. This bit is protected by the Configuration Change Protection mechanism, for details

refer to Section 3.12 ”Configuration Change Protection” on page 12.

Bit 76543 2 1 0

+0x09 —————AWEXELOCK —AWEXCLOCK AWEX_LOCK

Read/Write RRRRR R/W R R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

4.21 Register Summary - NVM Controller

4.22 Register Summary - Fuses and Lockbits

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 ADDR0 NVM Address Byte 0 25

+0x01 ADDR1 NVM Address Byte 1 25

+0x02 ADDR2 NVM Address Byte 2 25

+0x03 Reserved

+0x04 DATA0 NVM Data Byte 0 26

+0x05 DATA1 NVM Data Byte 1 26

+0x06 DATA2 NVM Data Byte 2 26

+0x07 Reserved

+0x08 Reserved

+0x09 Reserved

+0x0A CMD CMD[6:0] 26

+0x0B CTRLA CMDEX 27

+0x0C CTRLB EEMAPEN FPRM EPRM SPMLOCK 27

+0x0D INTCTRL SPMLVL[1:0] EELVL[1:0] 28

+0x0E Reserved

+0x0F STATUS NVMBUSY FBUSY EELOAD FLOAD 28

+0x10 LOCKBITS BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] 29

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 FUSEBYTE0 JTAGUID 30

+0x01 FUSEBYTE1 WDWPER3:0] WDPER[3:0] 30

+0x02 FUSEBYTE2 BOOTRST BODPD[1:0] 30

+0x03 Reserved

+0x04 FUSEBYTE4 RSTDISBL STARTUPTIME[1:0] WDLOCK JTAGEN 31

+0x05 FUSEBYTE5 BODACT[1:0] EESAVE BODLEVEL[2:0] 32

+0x06 Reserved

+0x07 LOCKBITS BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] 34

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4.23 Register Summary - Production Signature Row

Address Auto Load Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 YES RCOSC2M RCOSC2M[7:0] 36

+0x01 Reserved

+0x02 YES RCOSC32K RCOSC32K[7:0] 36

+0x03 YES RCOSC32M RCOSC32M[7:0] 37

+0x04 Reserved

+0x05 Reserved

+0x06 Reserved

+0x07 Reserved

+0x08 NO LOTNUM0 LOTNUM0[7:0] 37

+0x09 NO LOTNUM1 LOTNUM1[7:0] 37

+0x0A NO LOTNUM2 LOTNUM2[7:0] 37

+0x0B NO LOTNUM3 LOTNUM3[7:0] 38

+0x0C NO LOTNUM4 LOTNUM4[7:0] 38

+0x0D NO LOTNUM5 LOTNUM5[7:0] 38

+0x0E Reserved

+0x0F Reserved

+0x10 NO WAFNUM WAFNUM[7:0] 38

+0x11 Reserved

+0x12 NO COORDX0 COORDX0[7:0] 39

+0x13 NO COORDX1 COORDX1[7:0] 39

+0x14 NO COORDY0 COORDY0[7:0] 39

+0x15 NO COORDY1 COORDY1[7:0] 39

+0x16 Reserved

+0x17 Reserved

+0x18 Reserved

+0x19 Reserved

+0x1A Reserved

+0x1B Reserved

+0x1C Reserved

+0x1D Reserved

+0x0E Reserved

+0x1E Reserved

+0x20 NO ADCACAL0 ADCACAL0[7:0] 39

+0x21 NO ADCACAL1 ADCACAL1{7:0] 40

+0x22 Reserved

+0x23 Reserved

+0x24 NO ADCBCAL0 ADCBCAL0[7:0] 40

+0x25 NO ADCBCAL1 ADCBCAL1[7:0] 40

+0x26 Reserved

+0x27 Reserved

+0x28 Reserved

+0x29 Reserved

+0x2A Reserved

+0x2B Reserved

+0x2C Reserved

+0x2D Reserved

+0x2E NO TEMPSENSE0 TEMPSENSE[7:0] 41

+0x2F NO TEMPSENSE1 TEMPSENE[11:8] 41

+0x30 NO DACAOFFCAL DACAOFFCAL[7:0] 41

+0x31 NO DACACAINCAL DACACAINCAL[7:0] 41

+0x32 NO DACBOFFCAL DACBOFFCAL[7:0] 42

+0x33 NO DACBCAINCAL DACBCAINCAL[7:0] 42

+0x34 Reserved

+0x35 Reserved

+0x36 Reserved

+0x37 Reserved

+0x38 Reserved

+0x39 Reserved

0x3A Reserved

+0x3B Reserved

+0x3C Reserved

+0x3D Reserved

+0x3E Reserved

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XMEGA A

4.24 Register Summary - General Purpose I/O Registers

4.25 Register Summary - MCU Control

4.26 Interrupt Vector Summary - NVM Controller

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 GPIOR0 GPIOR[7:0] 42

+0x01 GPIOR1 GPIOR[7:0] 42

+0x02 GPIOR2 GPIOR[7:0] 42

+0x03 GPIOR3 GPIOR[7:0] 42

+0x04 GPIOR4 GPIOR[7:0] 42

+0x05 GPIOR5 GPIOR[7:0] 42

+0x06 GPIOR6 GPIOR[7:0] 42

+0x07 GPIOR7 GPIOR[7:0] 42

+0x08 GPIOR8 GPIOR[7:0] 42

+0x09 GPIOR9 GPIOR[7:0] 42

+0x0A GPIOR10 GPIOR[7:0] 42

+0x0B GPIOR11 GPIOR[7:0] 42

+0x0C GPIOR12 GPIOR[7:0] 42

+0x0D GPIOR13 GPIOR[7:0] 42

+0x0E GPIOR14 GPIOR[7:0] 42

+0x0F GPIOR15 GPIOR[7:0] 42

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 DEVID0 DEVID0[7:0] 43

+0x01 DEVID1 DEVID1[7:0] 43

+0x02 DEVID2 DEVID2[7:0] 43

+0x03 REVID – – – – REVID[3:0] 43

+0x04 JTAGUID JTAGUID[7:0] 44

+0x05 Reserved – – – – – – – –

+0x06 MCUCR – – – – – – – JTAGD 48

+0x07 Reserved – – – – – – – –

+0x08 EVSYSLOCK – – – EVSYS1LOC – – – EVSYS0LOCK

+0x09 AWEXLOCK – – – – – AWEXELOCK – AWEXCLOCK

+0x0A Reserved – – – – – – – –

+0x0B Reserved – – – – – – – –

Table 4-12. NVM Interrupt vectors and their word offset address from the NVM Controller interrupt base

Offset Source Interrupt Description

0x02 SPM_vect Non-Volatile Memory SPM Interrupt vector

0x00 EE_vect Non-Volatile Memory EEPROM Interrupt vector

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5. DMA - Direct Memory Access Controller

5.1 Features

•The DMA Controller allows high-speed transfers with minimal CPU intervention

– from one memory area to another

– from memory area to peripheral

– from peripheral to memory area

– from peripheral to another peripheral

•Four DMA Channels with separate

– transfer triggers

– interrupt vectors

– addressing modes

•From 1 byte to 16M bytes data transfer in a single transaction

•Up to 64 KByte block transfers with repeat

•1, 2, 4, or 8 byte burst transfers

•Internal and external transfer triggers

•Multiple addressing modes

– Static

–Increment

– Decrement

•Optional reload of source and destination address at the end of each

–Burst

–Block

– Transaction

•Optional Interrupt on end of transaction

•Programmable channel priority

5.2 Overview

The XMEGA Direct Memory Access (DMA) Controller is a highly flexible DMA Controller capable

of transferring data between memories and peripherals with minimal CPU intervention. The

DMA controller has flexible channel priority selection, several addressing modes, double buffer-

ing capabilities and large block sizes.

The DMA Controller can move data between memories and peripherals, between memories and

between peripheral registers directly.

There are four DMA channels that have individual source, destination, triggers and block sizes.

The different channels also have individual control settings and individual interrupt settings and

interrupt vectors. Interrupt requests may be generated both when a transaction is complete or if

the DMA Controller detects an error on a DMA channel. When a DMA channel requests a data

transfer, the bus arbiter will wait until the AVR CPU is not using the data bus and permit the DMA

Controller to transfer data. Transfers are done in bursts of 1, 2, 4 or 8 bytes. Addressing can be

static, incremental or decremental. Automatic reload of source and/or destination address can

be done after each burst transfer, block transfer, when transmission is complete, or disabled.

Both application software, peripherals and Events can trigger DMA transfers.

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XMEGA A

5.3 DMA Transaction

A complete DMA read and write operation between memories and/or peripherals is called a

DMA transaction. A transaction is done in data blocks and the size of the transaction (number of

bytes to transfer) is selectable from software and controlled by the block size and repeat counter

settings. Each block transfer is divided into smaller bursts.

5.3.1 Block Transfer and Repeat

The size of the block transfer is set by the Block Transfer Count Register, and can be anything

from 1 byte to 64 KBytes.

A repeat counter can be enabled to set a number of repeated block transfers before a transac-

tion is complete. The repeat is from 1 to 255 and unlimited repeat count can be achieved by

setting the repeat count to zero.

5.3.2 Burst Transfer

As the AVR CPU and DMA controller use the same data buses a block transfer is divided into

smaller burst transfers. The burst transfer is selectable to 1, 2, 4, or 8 bytes. This means that, if

the DMA acquires a data bus and a transfer request is pending it will occupy the bus until all

bytes in the burst transfer is transferred.

A bus arbiter controls when the DMA controller and the AVR CPU can use the bus. The CPU

always has priority, so as long as the CPU request access to the bus, any pending burst transfer

must wait. The CPU requests bus access when it executes an instruction that write or read data

to SRAM, I/O memory, EEPROM and the External Bus Interface. For more details on memory

access bus arbitration, refer to ”Data Memory” on page 22.

Figure 5-1. DMA transaction.

5.4 Transfer Triggers

DMA transfers can only be started when a DMA transfer request is detected. A transfer request

can be triggered from software, from an external trigger source (peripheral) or from an event.

There are dedicated source trigger selections for each DMA channel. The available trigger

sources may vary from device to device, depending on the modules or peripherals that exist in

the device. Using a transfer trigger for a module or peripherals that does not exist will have no

effect, for a list of all transfer triggers refer to ”TRIGSRC - DMA Channel Trigger Source” on

page 58.

Four-byte burst mode Block size: 12 bytes Repeat count: 2

Burst transfer Block transfer

DMA transaction

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XMEGA A

By default, a trigger starts a block transfer operation. The transfer continues until one block is

transferred. When the block is transferred, the channel will wait for the next trigger to arrive

before it start transferring the next block. It is possible to select the trigger to start a burst transfer

instead of a block transfer. This is called a single shot transfer. A new trigger will then start a new

burst transfer. When repeat mode is enabled, the start of transfer of the next block does not

require a transfer trigger. It will start as soon as the previous block is done.

If the trigger source generates a transfer request during an ongoing transfer this will be kept

pending, and the transfer can start when the ongoing one is done. Only one pending transfer

can be kept, so if the trigger source generates more transfer requests when one is already pend-

ing, these will be lost.

5.5 Addressing

The source and destination address for a DMA transfer can either be static, incremental or dec-

remental with individual selections for source and destination. When address increment or

decrement is used, the default behaviour is to update the address after each access. The origi-

nal source and destination address is stored by the DMA controller, so the source and

destination addresses can be individually configured to be reloaded at the following points:

• End of each burst transfer

• End of each block transfer

• End of transaction

• Never reload

5.6 Priority Between Channels

If several channels request data transfer at the same time a priority scheme is available to deter-

mine which channel is allowed to transfer data. Application software can decide whether one or

more channels should have a fixed priority or if a round robin scheme should be used. A round

robin scheme means that the channel that last transferred data will have the lowest priority.

5.7 Double Buffering

To allow for continuous transfer, two channels can be interlinked so that the second takes over

the transfer when the first is finished and vice versa. This is called double buffering. When a

transmission is completed for the first channel, the second channel is enabled. When a request

is detected on the second channel, the transfer starts and when this is completed the first chan-

nel is enabled again.

5.8 Transfer Buffers

Each DMA channel has an internal transfer buffer that is used for 2, 4 and 8 byte burst transfers.

When a transfer is triggered, a DMA channel will wait until the transfer buffer contains two bytes

before the transfer starts. For 4 or 8 byte transfer, any remaining bytes is transferred as soon as

they are ready for a DMA channel. The buffer is used to reduce the time the DMA controller

occupy the bus. When the DMA controller or a DMA channel is disabled from software, any

remaining bytes in the buffer will be transferred before the DMA controller or DMA channel is

disabled. This ensures that the source and destination address registers are kept synchronized.

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XMEGA A

5.9 Error detection

The DMA controller can detect erroneous operation. Error conditions are detected individually

for each DMA channel, and the error conditions are:

• Write to memory mapped EEPROM memory locations.

• Reading EEPROM memory when the EEPROM is off (sleep entered).

• DMA controller or a busy channel is disabled in software during a transfer.

5.10 Software Reset

Both the DMA controller and a DMA channel can be reset from the user software. When the

DMA controller is reset, all registers associated with the DMA controller is cleared. A software

reset can only be done when the DMA controller is disabled. When a DMA channel is reset, all

registers associated with the DMA channel are cleared. A software reset can only be done when

the DMA channel is disabled.

5.11 Protection

In order to insure safe operation some of the channel registers are protected during a transac-

tion. When the DMA channel Busy flag (CHnBUSY) is set for a channel, the user can only

modify these registers and bits:

• CTRL register

• INTFLAGS register

• TEMP registers

• CHEN, CHRST, TRFREQ, REPEAT bits of the Channel CTRL register

• TRIGSRC register

5.12 Interrupts

The DMA Controller can generate interrupts when an error is detected on a DMA channel or

when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt

vector, and there are different interrupt flags for error and transaction complete.

If repeat is not enabled the transaction complete flag is set at the end of the Block Transfer. If

unlimited repeat is enabled, the transaction complete flag is also set at the end of each Block

Transfer.

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XMEGA A

5.13 Register Description – DMA Controller

5.13.1 CTRL - DMA Control Register

• Bit 7 - ENABLE: DMA Enable

Setting this bit enables the DMA Controller. If the DMA Controller is enabled and this bit is writ-

ten to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty and the

DMA data transfer is aborted.

• Bit 6 - RESET: DMA Software Reset

Setting this bit enables the software reset. This bit is automatically cleared when reset is com-

pleted. This bit can only be set when the DMA Controller is disabled (ENABLE = 0).

• Bit 5:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:2 - DBUFMODE[1:0]: DMA Double Buffer Mode

These bits enables the double buffer on the different channels according to Table 5-1.

• Bit 1:0 - PRIMODE[1:0]: DMA Channel Priority Mode

These bits determine the internal channel priority according to Table 5-2.

Bit 76543210

+0x00 ENABLE RESET - - DBUFMODE[1:0] PRIMODE[1:0] CTRL

Read/Write R/W R/W R R R/W R/W R/W R/W

Initial Value00000000

Table 5-1. DMA Double Buffer settings

DBUFMODE[1:0] Group Configuration Description

00 DISABLED No double buffer enabled

01 CH01 Double buffer enabled on channel0/1

10 CH23 Double buffer enabled on channel2/3

11 CH01CH23 Double buffer enabled on channel0/1 and channel2/3

Table 5-2. DMA Channel Priority settings

PRIMODE[1:0] Group Configuration Description

00 RR0123 Round Robin

01 CH0RR123 Channel0 > Round Robin (Channel 1, 2 and 3)

10 CH01RR23 Channel0 > Channel1 > Round Robin (Channel 2 and

11 CH0123 Channel0 > Channel1 > Channel2 > Channel3

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XMEGA A

5.13.2 INTFLAGS - DMA Interrupt Status Register

• Bit 7:4 - CHnERRIF[3:0]: DMA Channel n Error Interrupt Flag

If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one

to this bit location will clear the flag.

• Bit 3:0 - CHnTRNFIF[3:0]: DMA Channel n Transaction Complete Interrupt Flag

When a transaction on channel n has been completed, the CHnTRFIF flag will set. If unlimited

repeat count is enabled, this flag is read as one after each block transfer. Writing a one to this bit

location will clear the flag.

5.13.3 STATUS - DMA Status Register

• Bit 7:4 - CHnBUSY[3:0]: DMA Channel Busy

When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is

automatically cleared when the DMA channel is disabled, when the Channel n transaction Com-

plete Interrupt Flag is set or if the DMA Channel n Error Interrupt flag is set.

• Bit 3:0 - CHnPEND[3:0]: DMA Channel Pending

If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This

flag is automatically cleared when the block transfer starts, or if the transfer is aborted.

5.13.4 TEMPH - DMA Temporary Register High

• Bit 7:0 - TEMP[7:0]: DMA Temporary Register

This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of

the 24-bit register is stored when it is written by the CPU. Byte 2 of the 24-bit register is stored

here when byte 1 is read by the CPU. This register can also be read and written from the user

software.

Reading and writing 24-bit register requires special attention, for details refer to Section 3.11

”Accessing 16-bits Registers” on page 12.

Bit 7654 3 2 1 0

+0x04 CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNFIF CH2TRNFIF CH1TRNFIF CH0TRNFIF INTFLAGS

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x05 CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND STATUS

Read/WriteRRRRRRRR

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x07 DMTEMP[15:8] TEMPH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

5.13.5 TEMPL - DMA Temporary Register Low

• Bit 7:0 - TEMP[7:0]: DMA Temporary Register 0

This register is used when reading 24- and 16-bit registers in the DMA controller. Byte 1 of the

16/24-bit registers is stored here when it is written by the CPU. Byte 1 of the 16/24-bit registers

are stored when byte 0 is read by the CPU. This register can also be read and written from the

user software.

Reading and writing 16- and 24-bit registers requires special attention. Please see detailed

description in the AVR Core manual.

5.14 Register Description – DMA Channel

5.14.1 CTRLA - DMA Channel Control Register A

• Bit 7- CHEN: DMA Channel Enable

Setting this bit enables the DMA channel. This bit is automatically cleared when the transaction

is completed. If the DMA channel is enabled and this bit is written to zero, the CHEN bit is not

cleared before the internal transfer buffer is empty and the DMA transfer is aborted.

• Bit 6 - CHRST: DMA Channel Software Reset

Setting this bit enables the channel reset. This bit is automatically cleared when reset is com-

pleted. This bit can only be set when the DMA channel is disabled (CHEN = 0).

• Bit 5 - REPEAT: DMA Channel Repeat Mode

Setting this bit enables the repeat mode. In repeat mode, this bit is cleared by hardware in the

beginning of the last block transfer. The REPCNT register should be configured before setting

the REPEAT bit.

• Bit 4 - TRFREQ: DMA Channel Transfer Request

Setting this bit requests a data transfer on the DMA Channel. This bit is automatically cleared at

the beginning of the data transfer. Writing this bit does not have any effect unless the channel is

enabled.

• Bit 3 - Reserved

This bit is unused and reserved for future use. For compatibility with future devices, always write

this bit to zero when this register is written.

Bit 76543210

+0x06 DMTEMP[7:0] TEMPL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x00 CHEN CHRST REPEAT TRFREQ - SINGLE BURSTLEN[1:0] CTRLA

Read/Write R/W R/W R/W R/W R R/W R/W R/W

Initial Value00000000

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XMEGA A

• Bit 2 - SINGLE: DMA Channel Single Shot Data transfer

Setting this bit enables the single shot mode. The channel will then do a burst transfer of

BURSTLEN bytes on the transfer trigger. This bit can not be changed if the channel is busy.

• Bit 1:0 - BURSTLEN[1:0]: DMA Channel Burst Mode

These bits decide the DMA channel burst mode according to Table 5-3 on page 56. These bits

can not be changed if the channel is busy.

5.14.2 CTRLB - DMA Channel Control Register B

• Bit 7- CHBUSY - DMA Channel Busy

When the DMA Channel starts a DMA transaction, the CHBUSY flag will be read as one. This

flag is automatically cleared when the DMA channel is disabled, when the Channel Transaction

Complete Interrupt Flag is set or if the Channel Error Interrupt flag is set.

• Bit 6 - CHPEND - DMA Channel Pending

If a block transfer is pending on the DMA channel, the CHPEND flag will be read as one. This

flag is automatically cleared when the transfer starts, or if the transfer is aborted

• Bit 5 - ERRIF - DMA Channel Error Interrupt Flag

If an error condition is detected the DMA channel the ERRIF flag will be set, and the optional

interrupt is generated. Since the DMA Channel Error Interrupt share interrupt address with DMA

Channel Transaction Complete, the ERRIF will not be cleared when the interrupt vector is exe-

cuted. This flag is cleared by writing a one to the bit location.

• Bit 4 - TRNIF - DMA Channel n Transaction Complete Interrupt Flag

When a transaction on the DMA Channel has been completed, the TRNIF flag will set, and the

optional interrupt is generated. When repeat is not enabled the transaction is complete and the

TRNIFR is set after the block transfer. When unlimited repeat is enabled the TRNIF is also set

after each block transfer.

Since the DMA Channel Transaction Complete Channel Error Interrupt share interrupt address

with DMA Channel Error Interrupt, the TRNIF will not be cleared when the interrupt vector is exe-

cuted. This flag is cleared by writing a one to the bit location.

Table 5-3. DMA channel burst mode

BURSTLEN[1:0] Group Configuration Description

00 1BYTE 1 byte burst mode

01 2BYTE 2 bytes burst mode

10 4BYTE 4 bytes burst mode

11 8BYTE 8 bytes burst mode

Bit 76543210

+0x04 CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0] CTRLB

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

• Bit [3:2] - ERRINTLVL[1:0]: DMA Channel Error Interrupt Level

These bits enable the interrupt for DMA channel transfer error select the interrupt level as

described in Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page

123. The enabled interrupt will trigger for the conditions when the ERRIF is set.

• Bit [1:0] - TRNINTLVL[1:0]: DMA Channel Transaction Complete Interrupt Level

These bits enable the interrupt for DMA channel transaction complete and select the interrupt

level as described in Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller”

on page 123. The enabled interrupt will trigger for the conditions when the TRNIF is set.

5.14.3 ADDRCTRL - DMA Channel Address Control Register

• Bit 7:6 - SRCRELOAD[1:0]: DMA Channel Source Address Reload

These bits decide the DMA channel source address reload according to Table 5-4. These bits

can not be changed if the channel is busy.

• Bit 5:4 - SRCDIR[1:0]: DMA Channel Source Address Mode

These bits decide the DMA channel source address mode according to Table 5-5. These bits

can not be changed if the channel is busy.

• Bit 3:2 - DESTRELOAD[1:0]: DMA Channel Destination Address Reload

These bits decide the DMA channel destination address reload according to Table 5-6 on page

58. These bits can not be changed if the channel is busy.

Bit 76543210

+0x02 SRCRELOAD[1:0] SRCDIR[1:0] DESTRELOAD[1:0] DESTDIR[1:0] ADDRCTRL

Read/Write R/W R/W R/W R/W R R/W R/W R/W

Initial Value00000000

Table 5-4. DMA channel source address reload settings

SRCRELOAD[1:0] Group Configuration Description

00 NONE No reload performed.

01 BLOCK DMA source address register is reloaded with initial

value at end of each block transfer.

10 BURST DMA source address register is reloaded with initial

value at end of each burst transfer.

11 TRANSACTION DMA source address register is reloaded with initial

value at end of each transaction.

Table 5-5. DMA channel source address mode settings

SRCDIR[1:0] Group Configuration Description

00 FIXED Fixed

01 INC Increment

10 DEC Decrement

11 - Reserved

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XMEGA A

• Bit 1:0 - DESTDIR[1:0]: DMA Channel Destination Address Mode

These bits decide the DMA channel destination address mode according to Table 5-7 on page

58. These bits can not be changed if the channel is busy.

5.14.4 TRIGSRC - DMA Channel Trigger Source

• Bit 7:0 - TRIGSRC[7:0]: DMA Channel Trigger Source Select

These bits select which trigger source is used for triggering a transfer on the DMA channel. A

zero value means that the trigger source is disabled. For each trigger source the value to put in

the TRIGSRC register is the sum of the module or peripheral’s base value, and the offset value

for the trigger source in the module or peripherals. Table 5-8 on page 59 shows the base value

for all module and peripherals. Table 5-9 on page 59 to Table 5-12 on page 60 shows the offset

value for the trigger sources in the different modules and peripheral types. For modules or

peripherals which does not exist for a device, the transfer trigger does not exist. Refer to the

device data sheet for the list of peripherals available.

Table 5-6. DMA channel destination address reload settings

DESTRELOAD[1:0] Group Configuration Description

00 NONE No reload performed.

01 BLOCK DMA channel destination address register is reloaded

with initial value at end of each block transfer.

10 BURST DMA channel destination address register is reloaded

with initial value at end of each burst transfer.

11 TRANSACTION DMA channel destination address register is reloaded

with initial value at end of each transaction.

Table 5-7. DMA channel destination address mode settings

DESTDIR[1:0] Group Configuration Description

00 FIXED Fixed

01 INC Increment

10 DEC Decrement

11 - Reserved

Bit 76543210

+0x03 TRIGSRC[7:0] TRIGSRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

Table 5-8. DMA Trigger Sources, base value for all modules and peripherals

TRIGSRC base value Group Configuration Description

0x00 OFF Software triggers only

0x01 SYS System DMA triggers base value

0x10 ADCA ADCA DMA triggers base value

0x15 DACA DACA DMA trigger bas

0x20 ADCB ADCB DMA triggers base value

0x25 DACB DACB DMA triggers base value

0x40 TCC0 Timer/Counter C0 DMA triggers base value

0x46 TCC1 Timer/Counter C1 triggers base value

0x4A SPIC SPI C DMA triggers value

0x4B USARTC0 USART C0 DMA triggers base value

0x4E USARTC1 USART C1 DMA triggers base value

0x60 TCD0 Timer/Counter D0 DMA triggers base value

0x66 TCD1 Timer/Counter D1 triggers base value

0x6A SPID SPI D DMA triggers value

0x6B USARTD0 USART D0 DMA triggers base value

0x6E USARTD1 USART D1 DMA triggers base value

0x80 TCE0 Timer/Counter E0 DMA triggers base value

0x86 TCE1 Timer/Counter E1 triggers base value

0x8A SPIE SPI E DMA triggers value

0x8B USARTE0 USART E0 DMA triggers base value

0x8E USARTE1 USART E1 DMA triggers base value

0xA0 TCF0 Timer/Counter F0 DMA triggers base value

0xA6 TCF1 Timer/Counter F1 triggers base value

0xAA SPIF SPI F DMA trigger value

0xAB USARTF0 USART F0 DMA triggers base value

0xAE USARTF1 USART F1 DMA triggers base value

Table 5-9. DMA Trigger sources, offset values for Event System triggers

TRGSRC offset value Group Configuration Description

+0x00 CH0 Event Channel 0

+0x01 CH1 Event Channel 1

+0x02 CH2 Event Channel 2

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XMEGA A

Notes: 1. For DAC only Channel 0 and 1 exists and can be used as triggers

2. Channel 4 equals ADC Channel 0 to 3 OR'ed together.

Note: 1. CC Channel C and D triggers are only available for Timer/Counter 0.

The Group Configuration is the “base_offset”, for example TCC1_CCA for the Timer/Counter C1

CC Channel A the transfer trigger.

5.14.5 TRFCNTH - DMA Channel Block Transfer Count Register H

The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT

defines the number of bytes in a block transfer. The value of TRFCNT is decremented after each

byte read by the DMA channel. When TRFCNT reaches zero, the register is reloaded with the

last value written to it.

Reading and writing 16-bit values requires special attention, for details refer to Section 3.11

”Accessing 16-bits Registers” on page 12.

Table 5-10. DMA Trigger sources, offset values for DAC and ADC triggers

TRGSRC offset value Group Configuration Description

+0x00 CH0 ADC/DAC Channel 0

+0x01 CH1 ADC/DAC Channel 1

+0x02 CH2(1) ADC Channel 2

+0x03 CH3 ADC Channel 3

+0x04 CH4(2) ADC Channel 0, 1, 2, 3

Table 5-11. DMA Trigger sources, offset values for Timer/ Counter triggers

TRGSRC offset value Group Configuration Description

+0x00 OVF Overflow/Underflow

+0x01 ERR Error

+0x02 CCA Compare or Capture Channel A

+0x03 CCB Compare or Capture Channel B

+0x04 CCC(1) Compare or Capture Channel C

+0x05 CCD Compare or Capture Channel D

Table 5-12. DMA Trigger sources, offset values for USART triggers

TRGSRC offset value Group Configuration Description

0x00 RXC Receive complete

0x01 DRE Data Register Empty

Bit 76543210

+0x05 TRFCNT[15:8] TRFCNTH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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XMEGA A

• Bit 7:0 - TRFCNT[15:8]: DMA Channel n Block Transfer Count Register High byte

These bits hold the 8 MSB of the 16-bits block transfer count.

The default value of this register is 0x1. If a user write 0x0 to this register and fire a DMA trigger,

DMA will be doing 0xFFFF transfers.

5.14.6 TRFCNTL - DMA Channel Block Transfer Count Register L

• Bit 7:0 - TRFCNT[7:0]: DMA Channel n Block Transfer Count Register Low byte

These bits hold the 8 LSB of the 16-bits block transfer count.

The default value of this register is 0x1. If a user write 0x0 to this register and fire a DMA trigger,

DMA will be doing 0xFFFF transfers.

5.14.7 REPCNT - DMA Channel Repeat Counter Register

REPCNTcounts how many times a block transfer is performed. For each block transfer this reg-

ister will be decremented.

When repeat mode is enabled (see REPEAT bit in ”ADDRCTRL - DMA Channel Address Con-

trol Register” on page 57), this register is used to control when the transaction is complete. The

counter is decremented after each block transfer if the DMA has to serve a limited number of

repeated block transfers. When repeat mode is enabled the channel is disabled when REPCNT

reaches zero, and the last block transfer is completed. Unlimited repeat is achieved by setting

this register to zero.

5.14.8 SRCADDR2 - DMA Channel Source Address 2

SRCADDR0, SRCADDR1 and SRCADDR2 represents the 24-bit value SRCADDR, which is the

DMA channel source address. SRCADDR2 is the most significant byte in the register.

SRCADDR may be automatically incremented or decremented based on settings in the SRCDIR

bits in ”ADDRCTRL - DMA Channel Address Control Register” on page 57.

Reading and writing 24-bit values require special attention, for details refer to Section 3.11.1

”Accessing 24- and 32-bit Registers” on page 12.

Bit 76543210

+0x04 TRFCNT[7:0] TRFCNTL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value11111111

Bit 76543210

+0x06 REPCNT[7:0] REPCNT

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x0A SRCADDR[23:16] SRCADDR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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XMEGA A

• Bit 7:0 - SRCADDR[23:16]: DMA Channel Source Address 2

These bits hold byte 2 of the 24-bits source address.

5.14.9 SRCADDR1 - DMA Channel Source Address 1

• Bit 7:0 - SRCADDR[15:8]: DMA Channel Source Address 1

These bits hold byte 1 of the 24-bits source address.

5.14.10 SRCADDR0 - DMA Channel Source Address 0

• Bit 7:0 - SRCADDR[7:0]: DMA Channel Source Address 0

These bits hold byte 0 of the 24-bits source address.

5.14.11 DESTADDR2 - DMA Channel Destination Address 2

DESTADDR0, DESTADDR1 and DESTADDR2 represents the 24-bit value DESTADDR, which

is the DMA channel destination address. DESTADDR2 holds the most significant byte in the reg-

ister. DESTADDR may be automatically incremented or decremented based on settings in the

DESTDIR bits in ”ADDRCTRL - DMA Channel Address Control Register” on page 57.

Reading and writing 24-bit values require special attention, for details refer to Section 3.11.1

”Accessing 24- and 32-bit Registers” on page 12.

• Bit 7:0 - DESTADDR[23:16]: DMA Channel Destination Address 2

These bits hold byte 2 of the 24-bits source address.

5.14.12 DESTADDR1 - DMA Channel Destination Address 1

Bit 76543210

+0x09 SRCADDR[15:8] SRCADDR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x08 SRCADDR[7:0] SRCADDR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x0E DESTADDR[23:16] DESTADDR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x0D DESTADDR[15:8] DESTADDR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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XMEGA A

• Bit 7:0 - DESTADDR[15:8]: DMA Channel Destination Address 1

These bits hold byte 1 of the 24-bits source address.

5.14.13 DESTADDR0 - DMA Channel Destination Address 0

• Bit 7:0 - DESTADDR[7:0]: DMA Channel Destination Address 0

These bits hold byte 0 of the 24-bits source address.

Bit 76543210

+0x0C DESTADDR[7:0] DESTADDR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

8077H–AVR–12/09

XMEGA A

5.15 Register Summary – DMA Controller

5.16 Register Summary – DMA Channel

5.17 DMA Interrupt Vector Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL ENABLE RESET - - DBUFMODE[1:0] PRIMODE[1:0] 53

+0x01 Reserved - - - - - - - -

+0x02 Reserved - - - - - - - -

+0x03 INTFLAGS CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNFIF CH2TRNFIF CH1TRNFIF CH0TRNFIF 54

+0x04 STATUS CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND 54

+0x05 Reserved - - - - - - - -

+0x06 TEMPL TEMP[7:0] 55

+0x07 TEMPH TEMP[15:8] 54

+0x10 CH0 Offset Offset address for DMA Channel 0

+0x20 CH1 Offset Offset address for DMA Channel 0

+0x30 CH2 Offset Offset address for DMA Channel 0

+0x40 CH3 Offset Offset address for DMA Channel 0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRLA CHEN CHRST REPEAT TRFREQ - SINGLE BURSTLEN 55

+0x01 CTRLB CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0] 56

+0x02 ADDCTRL SRCRELOAD[1:0] SRCDIR[1:0] DESTRELOAD[1:0] DESTDIR[1:0] 57

+0x03 TRIGSRC TRIGSRC[7:0] 58

+0x04 TRFCNTL TRFCNT[7:0] 61

+0x05 TRFCNTH TRFCNT[15:8] 60

+0x06 REPCNT REPCNT[7:0] 61

+0x07 Reserved - - - - - - - -

+0x08 SRCADDR0 SRCADDR[7:0] 62

+0x09 SRCADDR1 SRCADDR[15:8] 62

+0x0A SRCADDR2 SRCADDR[23:16] 61

+0x0B Reserved - - - - - - - -

+0x0C DESTADDR0 DESTADDR[7:0] 63

+0x0D DESTADDR1 DESTADDR[15:8] 62

+0x0E DESTADDR2 DESTADDR[23:16] 62

+0x0F Reserved - - - - - - - -

Table 5-13. DMA Interrupt vectors and their word offset addresses from the DMA Controller interrupt base

Offset Source Interrupt Description

0x00 CH0_vect DMA Controller Channel 0 Interrupt vector

0x02 CH1_vect DMA Controller Channel 1 Interrupt vector

0x04 CH2_vect DMA Controller Channel 2 Interrupt vector

0x06 CH3_vect DMA Controller Channel 3 Interrupt vector

8077H–AVR–12/09

XMEGA A

6. Event System

6.1 Features

•Inter peripheral communication and signalling

•CPU and DMA independent operation

•8 Event Channels allows for up to 8 signals to be routed at the same time

•100% predictable timing between peripherals

•Events can be generated by

– Timer/Counters (TCxn)

– Real Time Counter (RTC)

– Analog to Digital Converters (ADCx)

– Analog Comparators (ACx)

– Ports (PORTx)

– System Clock (ClkSYS)

•Events can be used by

– Timer/Counters (TCxn)

– Analog to Digital Converters (ADCx)

– Digital to Analog Converters (DACx)

– DMA (DMA) Controller

–Ports

•Advanced Features

– Manual Event Generation from software (CPU)

– Quadrature Decoding

– Digital Filtering

•Operative in Active and Idle mode

6.2 Overview

The Event System is a set of features for inter peripheral communication. It enables the possibil-

ity for a change of state in one peripheral to automatically trigger actions in other peripherals.

The change of state in a peripheral that will trigger actions in other peripherals is configurable in

software. It is a simple, but powerful system as it allows for autonomous control of peripherals

without any use of interrupt, CPU or DMA resources.

The indication of a change of state in a peripheral is referred to as an event. The events are

passed between peripherals using a dedicated routing network called the Event Routing Net-

work. Figure 6-1 on page 66 shows a basic block diagram of the Event System with the Event

Routing Network and the peripherals that are connected.

8077H–AVR–12/09

XMEGA A

Figure 6-1. Event System Overview and Connected Peripherals

The CPU is not part of the Event System, but it indicates that it is possible to manually generate

events from software or by using the on-chip debug system.

The Event System works in active and idle mode.

6.3 Events

In the context of the Event System, an indication that a change of state within a peripheral has

occurred is called an event. There are two main types of events: Signaling events and data

events. Signaling events only indicate a change of state while data events contain additional

information on the event.

The peripheral from where the event origin is called the Event Generator. Within each periph-

eral, for example a Timer/Counter, there can be several event sources, such as a timer compare

match or timer overflow. The peripheral using the event is called the Event User, and the action

that is triggered is called the Event Action.

Figure 6-2. Example of event source, generator, user and action

ADCx

DACx

Event Routing

Network

PORTx CPU

ACx

RTC

T/Cxn DMAIRCOM

ClkSYS

Event

Routing

Network

Compare Match

Over-/Underflow

Error

Timer/Counter

Channel Sweep

Single

Conversion

ADC

Event Generator

Event Source

Event User

Event Action

Event Action Selection

8077H–AVR–12/09

XMEGA A

Events can be manually generated by writing to the STROBE and DATA registers.

6.3.1 Signaling Events

Signaling events are the most basic type of events. A signaling event does not contain any infor-

mation apart from the indication of a change in a peripheral. Most peripherals can only generate

and use signaling events. Unless otherwise stated, all occurrences of the word 'event' is to be

understood as a signaling event.

6.3.2 Data Events

Data events differ from signaling events in that they contain additional information that event

users can decode to decide event actions based on the receiver information.

The Event Routing Network can route all events to all event users. Event users that are only

meant for using signaling events have limited decode capabilities and cannot fully utilize data.

How event users decode data events is shown in Table 6-1 on page 67.

Event users that can utilize Data Events can also use Signaling Events. This is configurable, and

is described in the data sheet module for each peripheral.

6.3.3 Manually Generating Events

Events can be generated manually by writing the DATA and STROBE register. This can be done

from software, and by accessing the registers directly during on-chip debugging. The DATA reg-

ister must be written first since writing the STROBE register triggers the operation. The DATA

and STROBE registers contain one bit for each event channel. Bit n corresponds to event chan-

nel n. It is possible to generate events on several channels at the same time by writing to several

bit locations at once.

Manually generated events last for one clock cycle and will overwrite events from other event

during that clock cycle. When manually generating events, event channels where no events are

entered will let other events through.

Table 6-1 on page 67 shows the different events, how they can be manually generated and how

they are decoded.

6.4 Event Routing Network

The Event Routing Network routes events between peripherals. It consists of eight multiplexers

(CHnMUX), where events from all event sources are routed into all multiplexers. The multiplex-

ers select which event is routed back as input to all peripherals. The output from a multiplexer is

referred to as an Event Channel. For each peripheral it is selectable if and how incoming events

should trigger event actions. Details on these are described in the data sheet for each periph-

eral. The Event Routing Network is shown on Figure 6-3 on page 68.

Table 6-1. Manually Generated Events and decoding of events

STROBE DATA Data Event User Signaling Event User

0 0 No Event No Event

0 1 Data Event 01 No Event

1 0 Data Event 02 Signaling Event

1 1 Data Event 03 Signaling Event

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XMEGA A

Figure 6-3. Event Routing Network

Having eight multiplexers means that it is possible to route up to eight events at the same time.

It is also possible to route one event through several multiplexers.

Not all XMEGA parts contain all peripherals. This only means that peripheral is not available for

generating or using events. The network configuration itself is compatible between all devices.

(48)

PORTA

PORTB

PORTC

PORTD

PORTE

PORTF

ADCA

ADCB

DACA

DACB

(PORTF)

TCF0

TCF1

(8)

(PORTE)

TCE0

TCE1

(8)

(PORTD)

TCD0

TCD1

(8)

(PORTC)

TCC0

TCC1

(8)

(16)

(13)

(4)

(8)

AC0

AC1

AC2

AC3

RTC

(8)

CH0MUX[7:0]

CH1MUX[7:0]

CH2MUX[7:0]

CH3MUX[7:0]

CH4MUX[7:0]

CH5MUX[7:0]

CH6MUX[7:0]

CH7MUX[7:0]

CH1CTRL[7:0]

CH0CTRL[7:0]

CH2CTRL[7:0]

CH3CTRL[7:0]

CH4CTRL[7:0]

CH5CTRL[7:0]

CH6CTRL[7:0]

CH7CTRL[7:0]

Event Channel 7

Event Channel 6

Event Channel 5

Event Channel 4

Event Channel 3

Event Channel 2

Event Channel 1

Event Channel 0

8077H–AVR–12/09

XMEGA A

6.5 Event Timing

An event normally lasts for one peripheral clock cycle, but some event sources, such as low

level on an I/O pin, will generate events continuously. Details on this are described in the

datasheet for each peripheral, but unless stated, an event lasts for one peripheral clock cycle

only.

It takes maximum two clock cycles from an event is generated until the event actions in other

peripherals is triggered. It takes one clock cycle from the event happens until it is registered by

the event routing network on the first positive clock edge. It takes an additional clock cycle to

route the event through the event channel to the event user.

6.6 Filtering

Each event channel includes a digital filter. When this is enabled for an event channel, an event

must be sampled with the same value for configurable number of system clock cycles before it is

accepted. This is primarily intended for pin change events.

6.7 Quadrature Decoder

The Event System includes three Quadrature Decoders (QDECs). This enables the Event Sys-

tem to decode quadrature input on I/O pins, and send data events that a Timer/Counter can

decode to trigger the appropriate event action: count up, count down or index/reset. Table 6-2

on page 69 summarizes which quadrature decoder data events are available, how they are

decoded, and how they can be generated. The QDECs and related features, control and status

6.7.1 Quadrature Operation

A quadrature signal is characterized by having two square waves phase shifted 90 degrees rela-

tive to each other. Rotational movement can be measured by counting the edges of the two

waveforms. The phase relationship between the two square waves determines the direction of

rotation.

Table 6-2. Quadrature Decoder Data Events

STROBE DATA Data Event User Signaling Event User

0 0 No Event No Event

0 1 Index/Reset No Event

1 0 Count Down Signaling Event

1 1 Count Up Signaling Event

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XMEGA A

Figure 6-4. Quadrature signals from a rotary encoder

Figure 6-4 shows typical quadrature signals from a rotary encoder. The signals QDPH0 and

QDPH90 are the two quadrature signals. When QDPH90 leads QDPH0, the rotation is defined

as positive or forward. When QDPH0 leads QDPH90, the rotation is defined as negative, or

reverse. The concatenation of the two phase signals is called the quadrature state or the phase

state.

In order to know the absolute rotary displacement a third index signal (QDINDX) can be used.

This gives an indication once per revolution.

6.7.2 QDEC Setup

For a full QDEC setup the following is required:

• I/O port pins - quadrature signal input

• The Event System - quadrature decoding

• A Timer/Counter - up, down and optional index count

The following procedure should be used for QDEC setup:

• Choose two successive pins on a port as QDEC phase inputs.

• Set pin direction for QDPH0 and QDPH90 as input.

• Set pin configuration for QDPH0 and QDPH90 to low level sense.

• Select QDPH0 pin as multiplexer input for an event channel, n.

• Enable quadrature decoding and digital filtering in the Event Channel.

• Optional:

a. Setup QDEC index (QINDX).

b. Select a third pin for QINDX input.

c. Set pin direction for QINDX as input.

d. Set pin configuration for QINDX to sense both edges.

e. Select QINDX as multiplexer input for Event Channel n+1

f. Set the Quadrature Index Enable bit in Event Channel n+1.

g. Select the Index Recognition mode for Event Channel n+1.

• Set quadrature decoding as event action for a Timer/Counter.

• Select Event Channel n as event source the Timer/Counter.

00 10 11 01

QDPH0

QDPH90

QDINDX

Forward Direction

Backward

Direction

01 11 10 00

1 cycle / 4 states

QDPH0

QDPH90

QDINDX

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XMEGA A

• Set the period register of the Timer/Counter to ('line count' * 4 - 1). (The line count of the

quadrature encoder).

• Enable the Timer/Counter by setting CLKSEL to a CLKSEL_DIV1.

The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read

directly from the Timer/Counter Count register. If the Count register is different from BOTTOM

when the index is recognized, the Timer/Counter error flag is set. Similarly the error flag is set if

the position counter passes BOTTOM without the recognition of the index.

6.8 Register Description

6.8.1 CHnMUX – Event Channel n Multiplexer Register

• Bit 7:0 - CHnMUX[7:0]: Channel Multiplexer

These bits select the event source according to Table 6-3. This table is valid for all XMEGA

devices regardless of if the peripheral is present or not. Selecting event sources from peripher-

als that are not present will give the same result as when this register is zero. When this register

is zero no events are routed through. Manually generated events will override the CHnMUX and

be routed to the event channel even if this register is zero.

Bit 76543210

CHnMUX[7:0] CHnMUX

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Table 6-3. CHnMUX[7:0] Bit Settings

CHnMUX[7:4] CHnMUX[3:0] Group Configuration Event Source

0000 0000 None (manually generated events

only)

0000 0001 (Reserved)

0000 0 0 1 X (Reserved)

0000 0 1 X X (Reserved)

0000 1000RTC_OVF RTC Overflow

0000 1001RTC_CMP RTC Compare March

0000 1 0 1 X (Reserved)

0000 1 1 X X (Reserved)

0001 0000ACA_CH0 ACA Channel 0

0001 0001ACA_CH1 ACA Channel 1

0001 0010ACA_WIN ACA Window

0001 0011ACB_CH0 ACB Channel 0

0001 0100ACB_CH1 ACB Channel 1

0001 0101ACB_WIN ACB Window

0001 0 1 1 X (Reserved)

8077H–AVR–12/09

XMEGA A

Note: 1. The description of how PORTS generate events are described in ”Port Event” on page 136.

0001 1 X X X (Reserved)

0010 0 0 n ADCA_CHn ADCA Channel n (n =0, 1, 2 or 3)

0010 0 1 n ADCB_CHn ADCB Channel n (n=0, 1, 2 or 3)

0010 1 X X X (Reserved)

0011 XXXX (Reserved)

0100 XXXX (Reserved)

0101 0 n PORTA_PINn(1) PORTA Pin n (n= 0, 1, 2 ... or 7)

0101 1 n PORTB_PINn(1) PORTB Pin n (n= 0, 1, 2 ... or 7)

0110 0 n PORTC_PINn(1) PORTC Pin n (n= 0, 1, 2 ... or 7)

0110 1 n PORTD_PINn(1) PORTD Pin n (n= 0, 1, 2 ... or 7)

0111 0 n PORTE_PINn(1) PORTE Pin n (n= 0, 1, 2 ... or 7)

0111 1 n PORTF_PINn(1) PORTF Pin n (n= 0, 1, 2 ... or 7)

1000 M PRESCALER_M ClkPER divide by M (M=1 to 32768)

1001 XXXX (Reserved)

1010 XXXX (Reserved)

1011 XXXX (Reserved)

1100 0 E See Table 6-4 Timer/Counter C0 event type E

1100 1 E See Table 6-4 Timer/Counter C1 event type E

1101 0 E See Table 6-4 Timer/Counter D0 event type E

1101 1 E See Table 6-4 Timer/Counter D1 event type E

1110 0 E See Table 6-4 Timer/Counter E0 event type E

1110 1 E See Table 6-4 Timer/Counter E1 event type E

1111 0 E See Table 6-4 Timer/Counter F0 event type E

1111 1 E See Table 6-4 Timer/Counter F1 event type E

Table 6-4. Timer/Counter Events

T/C Event E Group Configuration Event Type

0 0 0 TCxn_OVF Over-/Underflow (x = C, D, E or F) (n= 0 or 1)

0 0 1 TCxn_ERR Error (x = C, D, E or F) (n= 0 or 1)

0 1 X (Reserved)

1 0 0 TCxn_CCA Capture or Compare A (x = C, D, E or F) (n= 0 or 1)

1 0 1 TCxn_CCA Capture or Compare B (x = C, D, E or F) (n= 0 or 1)

1 1 0 TCxn_CCA Capture or Compare C (x = C, D, E or F) (n= 0 or 1)

1 1 1 TCxn_CCA Capture or Compare D (x = C, D, E or F) (n= 0 or 1)

Table 6-3. CHnMUX[7:0] Bit Settings (Continued)

CHnMUX[7:4] CHnMUX[3:0] Group Configuration Event Source

8077H–AVR–12/09

XMEGA A

6.8.2 CHnCTRL – Event Channel n Control Register

• Bit 7 - Reserved

This bit is reserved and will always be read as zero. For compatibility with future devices, always

write this bit to zero when this register is written.

• Bit 6:5 - QDIRM[1:0]: Quadrature Decode Index Recognition Mode

These bits determine the quadrature state for the QDPH0 and QDPH90 signals where a valid

index signal is recognized and the counter index data event is given according to Table 6-5 on

page 73. These bits is only needed to set when a quadrature encoed with a connected index sig-

nal is used.

These bits are only available for CH0CTRL, CH2CTRL and CH4CTRL

• Bit 4 - QDIEN: Quadrature Decode Index Enable

When this bit is set the event channel will be used as QDEC index source, and the index data

event will be enabled.

These bit is only available for CH0CTRL, CH2CTRL and CH4CTRL.

• Bit 3 - QDEN: Quadrature Decode Enable

Setting this bit enables QDEC operation.

These bits is only available for CH0CTRL, CH2CTRL and CH4CTRL.

• Bit 2:0 - DIGFILT[2:0]: Digital Filter Coefficient

These bits define the length of digital filtering used. Events will be passed through to the event

channel only when the event source has been active and sampled with the same level for a a

number of peripheral clock for the number of cycles as defined by DIGFILT.

Bit 76543210

- QDIRM[1:0] QDIEN QDEN DIGFILT[2:0] CHnCTRL

Read/Write R R/W R/W R/W R/W R/W R/W R

Initial Value00000000

Table 6-5. QDIRM Bit Settings

QDIRM[1:0] Index Recognition State

0 0 {QDPH0, QDPH90} = 0b00

0 1 {QDPH0, QDPH90} = 0b01

1 0 {QDPH0, QDPH90} = 0b10

1 1 {QDPH0, QDPH90} = 0b11

8077H–AVR–12/09

XMEGA A

6.8.3 STROBE – Event Strobe Register

If the STROBE register location is written, each event channel will be set according to the

STROBE[n] and corresponding DATA[n] bit setting if any are unequal to zero.

A single event lasting for one peripheral clock cycle will be generated.

6.8.4 DATA – Event Data Register

This register contains the data value when manually generating a data event. This register must

be written before the STROBE register, for details See ”STROBE – Event Strobe Register” on

page 74.

Table 6-6. Digital Filter Coefficient values

DIGFILT[2:0] Group Configuration Description

000 1SAMPLE 1 sample

001 2SAMPLES 2 samples

010 3SAMPLES 3 samples

011 4SAMPLES 4 samples

100 5SAMPLES 5 samples

101 6SAMPLES 6 samples

110 7SAMPLES 7 samples

111 8SAMPLES 8 samples

Bit 76543210

+0x10 STROBE[7:0] STROBE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Bit 76543210

+0x11 DATA[7:0] DATA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

8077H–AVR–12/09

XMEGA A

6.9 Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CH0MUX CH0MUX[7:0] 71

+0x01 CH1MUX CH1MUX[7:0] 71

+0x02 CH2MUX CH2MUX[7:0] 71

+0x03 CH3MUX CH3MUX[7:0] 71

+0x04 CH4MUX CH4MUX[7:0] 71

+0x05 CH5MUX CH5MUX[7:0] 71

+0x06 CH6MUX CH6MUX[7:0] 71

+0x07 CH7MUX CH7MUX[7:0] 71

+0x08 CH0CTRL - QDIRM[1:0] QDIEN QDEN DIGFILT[2:0] 73

+0x09 CH1CTRL - - - - - DIGFILT[2:0] 73

+0x0A CH2CTRL - QDIRM[1:0] QDIEN QDEN DIGFILT[2:0] 73

+0x0B CH3CTRL - - - - - DIGFILT[2:0] 73

+0x0C CH4CTRL - QDIRM[1:0] QDIEN QDEN DIGFILT[2:0] 73

+0x0D CH5CTRL - - - - - DIGFILT[2:0] 73

+0x0E CH6CTRL - - - - - DIGFILT[2:0] 73

+0x0F CH7CTRL - - - - - DIGFILT[2:0] 73

+0x10 STROBE STROBE[7:0] 74

+0x11 DATA DATA[7:0] 74

8077H–AVR–12/09

XMEGA A

7. System Clock and Clock options

7.1 Features

•Fast start-up time

•Safe run-time clock switching

•Internal Oscillators:

– 32 MHz run-time calibrated RC oscillator

– 2 MHz run-time calibrated RC oscillator

– 32.768 kHz calibrated RC oscillator

– 32 kHz Ultra Low Power (ULP) oscillator with 1 kHz output

•External clock options

– 0.4 - 16 MHz Crystal Oscillator

– 32.768 kHz Crystal Oscillator

– External clock

•PLL with internal and external clock options with 1 to 31x multiplication

•Clock Prescalers with 1 to 2048x division

•Fast peripheral clock running at 2 and 4 times the CPU clock speed

•Automatic Run-Time Calibration of internal oscillators

•Crystal Oscillator failure detection

7.2 Overview

XMEGA has a flexible clock system, supporting a large number of clock sources. It incorporates

both accurate integrated oscillators, and external crystal oscillators and resonators. A high fre-

quency Phase Locked Loop (PLL) and clock prescalers can be used to generate a wide range of

clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-

time calibration of the internal oscillators. A Crystal Oscillator Failure Monitor can be enabled to

issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator fails.

After reset, the device will always start up running from the 2 MHz internal oscillator. During nor-

mal operation, the System Clock source and prescalers can be changed from software at any

time.

Figure 7-1 on page 77 presents the principal clock system in the XMEGA. All of the clocks do not

need to be active at a given time. The clocks to the CPU and peripherals can be stopped using

sleep modes and power reduction registers as described in ”Power Management and Sleep” on

page 95.

8077H–AVR–12/09

XMEGA A

Figure 7-1. The Clock system, clock sources and clock distribution

7.3 Clock Distribution

Figure 7-1 on page 77 presents the principal clock distribution in the XMEGA.

7.3.1 System Clock - clkSYS

The System Clock is the output from the main system clock selection. This is fed into the pres-

calers that are used to generate all internal clocks except the Asynchronous Clock.

7.3.2 CPU Clock - clkCPU

The CPU Clock is routed to the CPU and Non-Volatile Memory. Halting the CPU Clock inhibits

the CPU from executing instructions.

32 kHz

Int. ULP

System Clock

Prescalers

2 MHz

Int. Osc.

32 MHz

Int. Osc.

32.768 kHz

Int. Osc.

Watchdog

Timer

Brown-out

Detection

System Clock Multiplexer

Real Time

Counter Peripherals RAM AVR CPU Non-Volatile

Memory

clkPER

clkSYS

clkPER4

clkPER2

clkCPU

clkrtc

XTAL

32 kHz

XTAL

0.4-16 Mhz

External

Clock

PLL

TOSC2

TOSC1

XTAL2

XTAL1

DIV4

DIV32

8077H–AVR–12/09

XMEGA A

7.3.3 Peripheral Clock - clkPER

The majority of peripherals and system modules use the Peripheral Clock. This includes the

DMA Controller, Event System, Interrupt Controller, External Bus Interface and RAM. This clock

is always synchronous to the CPU Clock but may run even if the CPU Clock is turned off.

7.3.4 Peripheral 2x/4x Clocks clkPER2/clkPER4

Modules that can run at two or four times the CPU Clock frequency can use the Peripheral 2x

and Peripheral 4x clocks.

7.3.5 Asynchronous Clock - clkASY

The Asynchronous Clock allows the Real Time Counter (RTC) to be clocked directly from an

external 32.768 kHz crystal oscillator, or the 32 times prescaled output from the internal

32.768 kHz oscillator or ULP oscillator. The dedicated clock domain allows operation of this

peripheral, even if the device is in sleep mode where the rest of the clocks are stopped.

7.4 Clock Sources

The clock sources are divided in two main groups: internal oscillators and external clock

sources. Most of the clock sources can be directly enabled and disabled from software, while

others are automatically enabled or disabled dependent on current peripheral settings. After

reset the device starts up running from the 2 MHz internal oscillator. The DFLLs and PLL are

turned off by default.

7.4.1 Internal Oscillators

The internal oscillators do not require any external components to run. For details on character-

istics and accuracy of the internal oscillators refer to the device data sheet.

7.4.1.1 32 kHz Ultra Low Power Oscillator

This oscillator provides an approximate 32 kHz clock. The 32 kHz Ultra Low Power (ULP) Inter-

nal Oscillator is a very low power clock source, and it is not designed for high accuracy.The

oscillator employs a built in prescaler providing both a 32 kHz output and a 1 kHz output. The

oscillator is automatically enabled/disabled when used as clock source for any part of the

device. This oscillator can be selected as clock source for the RTC.

7.4.1.2 32.768 kHz Calibrated Internal Oscillator

This RC oscillator provides an approximate 32.768 kHz clock. A factory-calibrated value is writ-

ten to the 32.768 kHz oscillator calibration register during reset to ensure that the oscillator is

running within its specification. The calibration register can also be written from software for run-

time calibration of the oscillator frequency. The oscillator employs a built in prescaler providing

both a 32.768 kHz output and a 1.024 kHz output.

7.4.1.3 32 MHz Run-time Calibrated Internal Oscillator

This RC oscillator provides an approximate 32 MHz clock. The oscillator employs a Digital Fre-

quency Locked Loop (DFLL) that can be enabled for automatic run-time calibration of the

oscillator. A factory-calibrated value is written to the 32 MHz DFLL Calibration Register during

reset to ensure that the oscillator is running within its specification. The calibration register can

also be written from software for manual run-time calibration of the oscillator.

8077H–AVR–12/09

XMEGA A

7.4.1.4 2 MHz Run-time Calibrated Internal Oscillator

This RC oscillator provides an approximate 2 MHz clock. The oscillator employs a Digital Fre-

quency Looked Loop (DFLL) that can be enabled for automatic run-time calibration of the

oscillator. A factory-calibrated value is written to the 2 MHz DFLL Calibration Register during

reset to ensure that the oscillator is running within its specification. The calibration register can

also be written from software for manual run-time calibration of the oscillator.

7.4.2 External Clock Sources

The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or

a ceramic resonator. XTAL1 can be used as input for an external clock signal. The TOSC1 and

TOSC2 pins is dedicated for driving a 32.768 kHz crystal oscillator.

7.4.2.1 0.4 - 16 MHz Crystal Oscillator

This oscillator can operate in four different modes, optimized for different frequency ranges, all

within 0.4 - 16 MHz. Figure 7-2 shows a typical connection of a crystal oscillator or resonator.

Figure 7-2. Crystal Oscillator Connection

Two capacitors, C1 and C2, may be added to match the required load capacitance for the con-

nected crystal.

7.4.2.2 External Clock Input

To drive the device from an external clock source, XTAL1 must be driven as shown in Figure 7-

3 on page 79. In this mode, XTAL2 can be used as a general I/O pin.

Figure 7-3. External Clock Drive Configuration

7.4.2.3 32.768 kHz Crystal Oscillator

A 32.768 kHz crystal oscillator can be connected between TOSC1 and TOSC2 by enabling a

dedicated Low Frequency Oscillator input circuit. A typical connection is shown in Figure Figure

XTAL2

XTAL1

GND

General

Purpose

I/O

XTAL2

XTAL1

External

Clock

Signal

8077H–AVR–12/09

XMEGA A

7-4 on page 80. A low power mode with reduced voltage swing on TOSC2 is available. This

oscillator can be used as clock source for the System Clock, RTC and as the DFLL reference.

Figure 7-4. 32.768 kHz crystal oscillator connection

Two capacitors, C1 and C2, may be added to match the required load capacitance for the con-

nected crystal.

7.5 System Clock Selection and Prescalers

All the calibrated internal oscillators, the external clock sources (XOSC) and the PLL output can

be used as the System Clock source. The System Clock source is selectable from software, and

can be changed during normal operation. Built-in hardware protection prevents unsafe clock

switching. It is not possible to select a non-stable or disabled oscillator as clock source, or to dis-

able the oscillator currently used as system clock source. Each oscillator option has a status flag

that can be read from software to check that the oscillator is ready.

The System Clock is fed into a prescaler block that can divide the clock signal by a factor from 1

to 2048 before it is routed to the CPU and peripherals. The prescaler settings can be changed

from software during normal operation. The first stage, prescaler A, can divide by a factor of 1 to

512. Then prescaler B and C can be individually configured to either pass the clock through or

divide it by a factor of 1 to 4. The prescaler guarantees that derived clocks are always in phase,

and that no glitches or intermediate frequencies occur when changing the prescaler setting. The

prescaler settings are always updated in accordance to the rising edge of the slowest clock.

Figure 7-5. System Clock Selection and Prescalers

Prescaler A divides the System Clock and the resulting clock is the clkPER4. Prescaler B and

prescaler C can be enabled to divide the clock speed further and enable peripheral modules to

run at twice or four times the CPU Clock frequency. If Prescaler B and C are not used all the

clocks will run at the same frequency as output from Prescaler A.

TOSC2

TOSC1

GND

Prescaler A

1, 2, 4, ... , 512 Prescaler B

1, 2, 4 Prescaler C

1, 2

Internal 2 MHz Osc.

Internal 32.768 kHz Osc.

Internal 32 MHz Osc.

External Oscillator or Clock.

ClkCPU

Cloc k S e le c t io n

ClkPER

ClkSYS

ClkPER2

ClkPER4

Internal PLL.

8077H–AVR–12/09

XMEGA A

The System Clock selection and prescaler registers are protected by the Configuration Change

Protection mechanism, employing a timed write procedure for changing the system clock and

prescaler settings. For details refer to ”Configuration Change Protection” on page 12.

7.6 PLL with 1-31x Multiplication Factor

A built-in Phase Locked Loop (PLL) can be used to generate a high frequency system clock. The

PLL has a user selectable multiplication factor from 1 to 31. The output frequency, fOUT is given

by the input frequency, fIN multiplied with the multiplication factor, PLL_FAC. The PLL must have

a minimum output frequency of 10 MHz.

Four different reference clock sources can be chosen as input to the PLL:

• 2 MHz internal oscillator

• 32 MHz internal oscillator divided by 4

• 0.4 - 16 MHz Crystal Oscillator

• External clock

To enable the PLL the following procedure must be followed:

1.Enable clock reference source.

2.Set the multiplication factor and select the clock reference for the PLL.

3.Wait until the clock reference source is stable.

4.Enable the PLL.

Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The

PLL must be disabled before a new configuration can be written.

It is not possible to use the PLL before the selected clock source is stabile and the PLL has

locked.

If using PLL and DFLL the active reference cannot be disabled.

7.7 DFLL 2 MHz and DFLL 32 MHz

Two built-in Digital Frequency Locked Loops (DFLLs) can be used to improve the accuracy of

the 2 MHz and 32 MHz internal oscillators. The DFLL compares the oscillator frequency with a

more accurate reference clock to do automatic run-time calibration of the oscillator. The choices

for the reference clock sources are:

• 32.768 kHz Calibrated Internal Oscillator

• 32.768 kHz Crystal Oscillator connected to the TOSC pins

The DFLLs divide the reference clock by 32 to use a 1.024 kHz reference. The reference clock is

individually selected for each DFLL as shown on Figure 7-6 on page 82.

fOUT fIN PLL_FAC⋅=

8077H–AVR–12/09

XMEGA A

Figure 7-6. Figure 5-5. DFLL reference clock selection

When the DFLL is enabled it will count each oscillator clock cycle, and for each reference clock

edge, the counter value is compared to the fixed ideal relationship between the reference clock

and the 1kHz reference frequency. If the internal oscillator runs too fast or too slow, the DFLL

will decrement or increment the corresponding DFLL Calibration Register value by one to adjust

the oscillator frequency slightly. When the DFLL is enabled the DFLL Calibration Register can-

not be written from software.

The ideal counter value representing the number of oscillator clock cycles for each reference

clock cycle is loaded to the DFLL Oscillator Compare Register during reset. The register can

also be written from software to change the frequency the internal oscillator is calibrated to.

The DFLL will stop when entering a sleep-mode where the oscillators are stopped. After wake-

up the DFLL will continue with the calibration value found before entering sleep. For the DFLL

Calibration Register to be reloaded with the default value it has after reset, the DFLL must dis-

abled before entering sleep and enabled the again after leaving sleep.

The active reference cannot be disabled when the DFLL is enabled.

When the DFLL is disabled the DFLL calibration Register can be written from software for man-

ual run-time calibration of the oscillator.

For details on internal oscillator accuracy when the DFLL is enabled, refer to the device data

sheet.

7.8 External Clock Source Failure Monitor

To handle external clock source failures, there is a built-in monitor circuit monitoring the oscilla-

tor or clock used to derive the XOSC clock. The External Clock Source Failure Monitor is

disabled by default, and it must be enabled from software before it can be used. If an external

TOSC1

TOSC2

32.768 kHz Crystal Osc.

32.768 kHz Int. Osc.

2 MHz Int. Osc.

32 MHz Int. Osc.

DFLL

8077H–AVR–12/09

XMEGA A

clock or oscillator is used to derive the System Clock (i.e clock reference for the PLL when this is

used as the active system clock) and an clock or oscillator fails (stops), the device will:

• Switch to the 2 MHz internal oscillator, independently of any clock system lock setting.

• Reset the Oscillator Control Register and System Clock Selection Register to their default

values.

• Set the External Clock Source Failure Detection Interrupt Flag.

• Issue a non-maskable interrupt (NMI).

If the external oscillator fails when it is not used as the System Clock source, the external oscil-

lator is automatically disabled while the system clock will continue to operate normally.

If the external clock is below 32 kHz then the failure monitor mechanism should not be enabled

in order to avoid unintentional fail detection.

When the failure monitor is enabled, it cannot be disabled until next reset.

The failure monitor is automatically disabled in all sleep modes where the external clock or oscil-

lator is stopped. During wake-up from sleep it is automatically enabled again.

The External Clock Source Failure Monitor setting is protected by the Configuration Change Pro-

tection mechanism, employing a timed write procedure for changing the system clock and

prescaler settings. For details refer to ”Configuration Change Protection” on page 12.

8077H–AVR–12/09

XMEGA A

7.9 Register Description - Clock

7.9.1 CTRL - System Clock Control Register

• Bit 7:3 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 2:0 - SCLKSEL[2:0]: System Clock Selection

SCLKSEL is used to select the source for the System Clock. See Table 7-1 for the different

selections. Changing the system clock source will take 2 clock cycles on the old clock source

and 2 clock cycles on the new clock source. These bits are protected by the Configuration

Change Protection mechanism, for details refer to Section 3.12 ”Configuration Change Protec-

tion” on page 12.

SCLKSEL cannot be changed if the new source is not stable.

7.9.2 PSCTRL - System Clock Prescaler Register

• Bit 7 - Reserved

This bit is reserved and will always be read as zero. For compatibility with future devices, always

write this bit to zero when this register is written.

Bit 76543210

+0x00 ----- SCLKSEL[2:0] CTRL

Read/WriteRRRRRR/WR/WR/W

Initial Value00000000

Table 7-1. System Clock Selection

SCLKSEL[2:0] Group Configuration Description

000 RC2MHz 2 MHz Internal RC Oscillator

001 RC32MHz 32 MHz Internal RC Oscillator

010 RC32KHz 32 kHz Internal RC Oscillator

011 XOSC External Oscillator or Clock

100 PLL Phase Locked Loop

101 - Reserved

110 - Reserved

111 - Reserved

Bit 76543210

+0x01 - PSADIV[4:0] PSBCDIV PSCTRL

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

8077H–AVR–12/09

XMEGA A

• Bit 6:2 - PSADIV[4:0]: Prescaler A Division Factor

These bits define the division ratio of the clock prescaler A according to Table 7-2. These bits

can be written run-time to change the clock frequency of the clkPER4 clock relative to the System

clock, clkSYS .

• Bit 1:0 - PSBCDIV: Prescaler B and C Division Factor

These bits define the division ratio of the clock prescaler B and C according to Table 7-3. Pres-

caler B will set the clock frequency for the clkPER2 clock relative to the clkPER4. Prescaler C will

set the clock frequency for the clkPER and clkCPU clocks relative to the clkPER2 clock. Refer to Fig-

ure 7-5 on page 80 fore more details.

Table 7-2. Prescaler A division factor

PSADIV[4:0] Group Configuration Description

00000 1 No division

00001 2 Divide by 2

00011 4 Divide by 4

00101 8 Divide by 8

00111 16 Divide by 16

01001 32 Divide by 32

01011 64 Divide by 64

01101 128 Divide by 128

01111 256 Divide by 256

10001 512 Divide by 512

10101 Reserved

10111 Reserved

11001 Reserved

11011 Reserved

11101 Reserved

11111 Reserved

Table 7-3. Prescaler B and C division factor

PSBCDIV[1:0] Group Configuration Prescaler B division Prescaler C division

00 1_1 No division No division

01 1_2 No division Divide by 2

10 4_1 Divide by 4 No division

11 2_2 Divide by 2 Divide by 2

8077H–AVR–12/09

XMEGA A

7.9.3 LOCK - Clock System Lock Register

• Bit 7:1 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 0 - LOCK: Clock System Lock

When the LOCK bit is written to one the CTRL and PSCTRL registers cannot be changed, and

the system clock selection and prescaler settings is protected against all further updates until

after the next reset. This bits are protected by the Configuration Change Protection mechanism,

for details refer to Section 3.12 ”Configuration Change Protection” on page 12.

The LOCK bit will only be cleared by a system reset.

7.9.4 RTCCTRL - RTC Control Register

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:1 - RTCSRC[2:0]: Clock Source

These bits select the clock source for the Real Time Counter according to Table 7-4..

Bit 76543210

+0x02 ------- LOCK LOCK

Read/WriteRRRRRRRR/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x03 ---- RTCSRC[2:0] RTCENRTCCTRL

Read/WriteRRRRR/WR/WR/WR/W

Initial Value00000000

Table 7-4. RTC Clock Source

RTCSRC[2:0] Group Configuration Description

000 ULP 1 kHz from internal 32 kHz ULP

001 TOSC 1.024 kHz from 32.768 kHz Crystal Oscillator on TOSC

010 RCOSC 1.024 kHz from internal 32.768 kHz RC Oscillator

011 - Reserved

100 - Reserved

101 TOSC32 32.768 kHz from 32.768 kHz Crystal Oscillator on TOSC

110 - Reserved

111 - Reserved

8077H–AVR–12/09

XMEGA A

• Bit 0 - RTCEN: RTC Clock Source Enable

Setting the RTCEN bit enables the selected clock source for the Real Time Counter.

7.10 Register Description - Oscillator

7.10.1 CTRL - Oscillator Control Register

• Bit 7:5 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 4 - PLLEN: PLL Enable

Setting this bit enables the PLL. Before the PLL is enabled, it should be configured with the

desired multiplication factor and input source. See ”STATUS - Oscillator Status Register” on

page 88..

• Bit 3 - XOSCEN: External Oscillator Enable

Setting this bit enables the selected external clock source, refer to ”XOSCCTRL - XOSC Control

external clock source should be allowed time to become stable before it is selected as source for

the System Clock. See ”STATUS - Oscillator Status Register” on page 88.

• Bit 2 - RC32KEN: 32.768 kHz Internal RC Oscillator Enable

Setting this bit enables the 32.768 kHz internal RC oscillator. The oscillator must be stable

before it is selected as source for the System Clock. See ”STATUS - Oscillator Status Register”

on page 88.

• Bit 1- RC32MEN: 32 MHz Internal RC Oscillator Enable

Setting this bit will enable the 32 MHz internal RC oscillator. The oscillators should be allowed

time to become stable before wither is selected as source for the System Clock. See ”STATUS -

Oscillator Status Register” on page 88.

• Bit 0 - RC2MEN: 2 MHz Internal RC Oscillator enable

Setting this bit enables the 2MHz internal RC oscillator. The oscillator should be allowed time to

become stable before wither is selected as source for the System Clock. See ”STATUS - Oscil-

lator Status Register” on page 88.

By default the 2 Mhz Internal RC Oscillator is enabled and this bit is set.

Bit 76543210

+0x00 - - - PLLEN XOSCEN RC32KEN RC32MEN RC2MEN CTRL

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000001

8077H–AVR–12/09

XMEGA A

7.10.2 STATUS - Oscillator Status Register

• Bit 7:5 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 4 - PLLRDY: PLL Ready

The PLLRDY flag is set when the PLL has locked on selected frequency and ready to be used

as he System Clock source.

• Bit 3 - XOSCRDY: External clock source Ready

The XOSCRDY flag is set when the external clock source is stable and ready to be used as the

System Clock source.

• Bit 2 - RC32KRDY: 32.768 kHz Internal RC Oscillator Ready

The RC32KRDY flag is set when the 32.768 kHz internal RC oscillator is stable and ready to be

used as the System Clock source.

• Bit 1 - RC32MRDY: 32 MHz Internal RC Oscillator Ready

The R32MRFY flag is set when the 32 MHz internal RC oscillator is stable and ready to be used

as the System Clock source.

• Bit 0 - RC2MRDY: 2 MHz Internal RC Oscillator Ready

The RC2MRDY flag is set when the 2 MHz internal RC oscillator is stable and is ready to be

used as the System Clock source.

7.10.3 XOSCCTRL - XOSC Control Register

• Bit 7:6 - FRQRANGE[1:0]: Crystal Oscillator Frequency Range Select

These bits select the frequency range for the connected crystal oscillator according to Table 7-5

on page 89.

Bit 765 4 3 2 1 0

+0x01 - - - PLLRDY XOSCRDY RC32KRDY R32MRDY RC2MRDY STATUS

Read/Write R R R R R R R R

Initial Value 0 0 0 0 0 0 0 0

Bit 76 5 43210

+0x02 FRQRANGE[1:0] X32KLPM - XOSCSEL[3:0] XOSCCTRL

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

8077H–AVR–12/09

XMEGA A

• Bit 5 - X32KLPM: Crystal Oscillator 32.768 kHz Low Power Mode

Setting this bit enables low power mode for the 32.768 kHz Crystal Oscillator. This will reduce

the swing on the TOSC2 pin.

• Bit 4 - Reserved

This bit is reserved and will always be read as zero. For compatibility with future devices, always

write this bit to zero when this register is written.

• Bit 3:0 - XOSCSEL[3:0]: Crystal Oscillator Selection

These bits select the type and start-up time for the crystal or resonator that is connected to the

XTAL or TOSC pins. See Table 7-6 for crystal selections. If external clock or external oscillator is

selected as source for System Clock, see ”CTRL - Oscillator Control Register” on page 87, this

configuration can not be changed.

Notes: 1. This option should only be used when frequency stability at start-up is not important for the

application. The option is not suitable for crystals.

2. This option is intended for use with ceramic resonators and will ensure frequency stability at

start-up. It can also be used when the frequency stability at start-up is not important for the

application.

7.10.4 XOSCFAIL - XOSC Failure Detection Register

Table 7-5. Oscillator frequency range selection

FRQRANGE[1:0] Group Configuration Frequency range

Recommended range

for capacitors C1 and C2 (pF)

00 04TO2 0.4 MHz - 2 MHz 100

01 2TO9 2 MHz - 9 MHz 15

10 9TO12 9 MHz - 12 MHz 15

11 12TO16 12 MHz - 16 MHz 10

Table 7-6. External Oscillator selection and Startup Time

XOSCSEL[3:0] Group Configuration Selected Clock Source Start-up time

0000 EXTCLK External Clock 6 CLK

0010 32KHZ 32.768 kHz TOSC 16K CLK

0011 XTAL_256CLK(1) 0.4 - 16 MHz XTAL 256 CLK

0111 XTAL_1KCLK(2) 0.4 - 16 MHz XTAL 1K CLK

1011 XTAL_16KCLK 0.4 - 16 MHz XTAL 16K CLK

Bit 765432 1 0

+0x03 ––––––XOSCFDIFXOSCFDENXOSCFAIL

Read/WriteRRRRRRR/WR/W

Initial Value000000 0 0

8077H–AVR–12/09

XMEGA A

• Bit 7:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1 - XOSCFDIF: Failure Detection Interrupt Flag

If the external clock source oscillator failure monitor is enabled, the XOSCFDIF is set when a

failure is detected. Writing logic one to this location will clear XOSCFDIF. Note that having this

flag set will not stop the fail monitor circuit to request a new interrupt if the external clock sources

are re-enabled and a new failure occurs.

• Bit 0 - XOSCFDEN: Failure Detection Enable

Setting this bit will enable the failure detection monitor, and a Non-Maskable Interrupt will be

issued when the XOSCFDIF is set.

This bit is protected by the Configuration Change Protection mechanism, refer to Section 3.12

”Configuration Change Protection” on page 12 for details. Once enabled, the failure detection

will only be disabled by a reset.

7.10.5 RC32KCAL - 32 KHz Oscillator Calibration Register

• Bit 7:0 - RC32KCAL[7:0]: 32.768 KHz Internal Oscillator Calibration Register

This register is used to calibrate the Internal 32.768 kHz Oscillator. A factory-calibrated value is

loaded from the signature row of the device and written to this register during reset, giving an

oscillator frequency close to 32.768 kHz. The register can also be written from software to cali-

brate the oscillator frequency during normal operation.

7.10.6 PLLCTRL - PLL Control Register

• Bit 7:6 - PLLSRC[1:0]: Clock Source

The PLLSRC bits select the input source for the PLL according to Table 7-7 on page 91.

Bit 76543210

+0x04 RC32KCAL[7:0] RC32KCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Valuexxxxxxxx

Bit 76543210

+0x05 PLLSRC[1:0] - PLLFAC[4:0] PLLCTRL

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value00000000

8077H–AVR–12/09

XMEGA A

Notes: 1. 32 kHz TOSC cannot be selected as source for the PLL. An external clock must be minimum

0.4 MHz to be used as source clock.

• Bit 5 - Reserved

This bit is reserved and will always be read as zero. For compatibility with future devices, always

write this bit to zero when this register is written.

• Bit 4:0 - PLLFAC[4:0]: Multiplication Factor

The PLLFAC bits set the multiplication factor for the PLL. The multiplication factor can be in the

range from 1x to 31x. The output frequency from the PLL should not exceed 200 MHz. The PLL

must have a minimum output frequency of 10 MHz.

7.10.7 DFLLCTRL - DFLL Control Register

• Bit 7:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1 - RC32MCREF: 32 MHz Calibration Reference

This bit is used to select the calibration source for the 32 MHz DFLL. By default this bit is zero

and the 32.768 kHz internal RC oscillator is selected. If this bit is set to one the 32.768 kHz Crys-

tal Oscillator connected to TOSC selected as reference. The XOSCEN bit in the CTRL register

must be set to enable the external oscillator, and the XOSCLSEL bits in the XOSCCTRL register

must be set to 32.768 kHz TOSC when this clock source is selected as the the 32 MHz DFLL

reference.

• Bit 0 - RC2MCREF: 2 MHz Calibration Reference

This bit is used to select the calibration source for the 2 MHz DFLL. By default this bit is zero and

the 32.768 kHz internal RC oscillator is selected. If this bit is set to one the 32.768 kHz Crystal

Oscillator on TOSC is selected as reference. The XOSCEN bit in the CTRL register must be set

to enable the external oscillator, and the XOSCLSEL bits in the XOSCCTRL register must be set

to 32.768 kHz TOSC when this clock source is selected as the the 2 MHz DFLL reference.

Table 7-7. PLL Clock Source

CLKSRC[1:0] Group Configuration PLL input source

00 RC2M 2 MHz Internal RC Oscillator

01 - Reserved

10 RC32M 32 MHz Internal RC Oscillator

11 XOSC External Clock Source(1)

Bit 765432 1 0

+0x06 – – – – – – R32MCREF RC2MCREF DFLLCTRL

Read/Write R R R R R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

8077H–AVR–12/09

XMEGA A

7.11 Register Description - DFLL32M/DFLL2M

7.11.1 CTRL - DFLL Control Register

• Bit 7:1 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 0 - ENABLE: DFLL Enable

Setting this bit enables the DFLL and auto-calibration of the internal oscillator

7.11.2 CALA - Calibration Register A

CALA and CALB register holds the 13 bit DFLL calibration value that is used for automatic run-

time calibration the internal oscillator. When the DFLL is disabled, the calibration registers can

be written by software for manual run-time calibration of the oscillator. The oscillators will be cal-

ibrated according to the calibration value in these registers also when the DFLL is disabled.

• Bit 7:0 - CALL[7:0]: DFLL Calibration bits

These bits hold the 7 Least Significant Bits (LSB) of the calibration value for the oscillator. After

reset CALL is set to its middle value, and during automatic runtime calibration of the oscillator

these bits are use to change the oscillator frequency. The bits are controlled by the DFLL when

the DFLL is enabled.

7.11.3 CALB - Calibration Register B

• Bit 7:4 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

Bit 76543210

+0x00 –––––––ENABLE CTRL

Read/WriteRRRRRRRR/W

Initial Value00000000

Bit 76543210

+0x02 CALL[7:0] CALA

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value01000000

Bit 76543210

+0x03 – – – CALH[12:8] CALB

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 x x x x x

8077H–AVR–12/09

XMEGA A

• Bit 4:0 - CALH[12:8]: DFLL Calibration bits

These bits hold the 6 Most Significant Bits (MSB) of the calibration value for the oscillator. A fac-

tory-calibrated value is loaded from the signature row of the device and written to this register

during reset, giving an oscillator frequency approximate to the nominal frequency for the oscilla-

tor. These bits are not changed during automatic runtime calibration of the oscillator.

7.11.4 COMP0 - Oscillator Compare Register 0

COMP0, COMP1 and COMP2 represent the register value COMP that hold the oscillator com-

pare value. During reset COMP is loaded with the default value representing the ideal

relationship between oscillator frequency and the 1.024 kHz reference clock. It is possible to

write these bits from software, and then enable the oscillator to tune to a frequency different than

its nominal frequency. These bits can only be written when the DFLL is disabled.

• Bit 7:0 - COMP[7:0]

These bits are the low byte of the COMP register.

7.11.5 COMP1 - Oscillator Compare Register 1

• Bit 7:0 - COMP[15:8]

These bits are the middle byte of the COMP register.

7.11.6 COMP2 - Oscillator Compare Register 2

7.11.6.1 COMP2 - Oscillator Compare Register 2, 2 MHz DFLL /32 MHz DFLL

• Bit 7:0 - COMP[23:16]

These bits are the highest bits of the COMP register.

Bit 76543210

+0x04 COMP[7:0] COMP0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x05 COMP[15:8] COMP1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x06 COMP[23:16] COMP2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

8077H–AVR–12/09

XMEGA A

7.12 Register Summary - Clock

7.13 Register Summary - Oscillator

7.14 Register Summary - DFLL32M/DFLL2M

7.15 Crystal Oscillator Failure Interrupt Vector Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL – – – – – SCLKSEL[2:0] 84

+0x01 PSCTRL – PSADIV[4:0] PSBCDIV[1:0] 84

+0x02 LOCK – – – – – – – LOCK 86

+0x03 RTCCTRL – – – – RTCSRC[2:0] RTCEN 86

+0x04 Reserved – – – – – – – –

+0x05 Reserved – – – – – – – –

+0x06 Reserved – – – – – – – –

+0x07 Reserved – – – – – – – –

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL – – – PLLEN XOSCEN RC32KEN R32MEN RC2MEN 87

+0x01 STATUS – – – PLLRDY XOSCRDY RC32KRDY R32MRDY RC2MRDY 87

+0x02 XOSCCTRL FRQRANGE[1:0] X32KLPM – XOSCSEL[3:0] 88

+0x03XOSCFAIL–– –––– – –89

+0x04 RC32KCAL RC32KCAL[7:0] 90

+0x05 PLLCTRL PLLSRC[1:0] - PLLFAC[4:0] 90

+0x06 DFLLCTRL – – – – – – – – 91

+0x07 Reserved – – – – – – – –

+0x08 Reserved – – – – – – – –

+0x09 Reserved – – – – – – – –

+0x0A Reserved – – – – – – – –

+0x0B Reserved – – – – – – – –

+0x0C Reserved – – – – – – – –

+0x0D Reserved – – – – – – – –

+0x0E Reserved – – – – – – – –

+0x0F Reserved – – – – – – – –

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL – ENABLE 92

+0x01 Reserved – – – – – – – –

+0x02 CALA CALL[7:0] 92

+0x03 CALB – – – CALH[11:8] 92

+0x04 COMP0 COMP[7:0] 92

+0x05 COMP1 COMP[15:8] 93

+0x06 COMP2 COMP[23:16] 93

+0x07 COMP2 COMP[7:0] 93

Table 7-8. Crystal Oscillator Failure Interrupt vector and its word offset address Crystal Oscillator Failure interrupt base

Offset Source Interrupt Description

0x00 OSCF_vect Crystal Oscillator Failure Interrupt Vector (NMI)

8077H–AVR–12/09

XMEGA A

8. Power Management and Sleep

8.1 Features

•5 sleep modes

–Idle

– Power-down

–Power-save

–Standby

– Extended standby

•Power Reduction register to disable clock to unused peripherals

8.2 Overview

XMEGA provides various sleep modes and software controlled clock gating in order to tailor

power consumption to the application's requirement. Sleep modes enables the microcontroller to

shut down unused modules to save power. When the device enters sleep mode, program exe-

cution is stopped and interrupts or reset is used to wake the device again. The individual clock to

unused peripherals can be stopped during normal operation or in sleep, enabling a much more

fine tuned power management than sleep modes alone.

8.3 Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order

to save power. XMEGA has five different sleep modes. A dedicated Sleep instruction (SLEEP) is

available to enter sleep. Before executing SLEEP, the selected sleep mode to enter must be

configured. The available interrupt wake-up sources is dependent on the selected sleep mode.

When an enabled interrupt occurs the device will wake up and execute the interrupt service rou-

tine before continuing normal program execution from the first instruction after the SLEEP

instruction. If other higher priority interrupts are pending when the wake-up occurs, their interrupt

service routines will be executed according to their priority before the interrupt service routine for

the wake-up interrupt is executed. After wake-up the CPU is halted for four cycles before execu-

tion starts.

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XMEGA A

Table 8-1 on page 96 shows the different sleep modes and the active clock domains, oscillators

and wake-up sources.

The wake-up time for the device is dependent on the sleep mode and the main clock source.

The start-up time for the system clock source must be added to the wake-up time for sleep

modes where the clock source is stopped. For details on the start-up time for the different oscil-

lators options refer to ”System Clock and Clock options” on page 76.

The content of the Register File, SRAM and registers are kept during sleep. If a reset occurs

during sleep, the device will reset, start up and execute from the Reset Vector.

8.3.1 Idle Mode

In Idle mode the CPU and Non-Volatile Memory are stopped, (note that any active programming

will be completed) but all peripherals including the Interrupt Controller, Event System and DMA

Controller are kept running. Any interrupt request interrupts will wake the device.

8.3.2 Power-down Mode

In Power-down mode all system clock sources, including the Real Time Counter clock source

are stopped. This allows operation of asynchronous modules only. The only interrupts that can

wake up the MCU are the Two Wire Interface address match interrupts, and asynchronous port

interrupts.

8.3.3 Power-save Mode

Power-save mode is identical to Power-down, with one exception:

If the Real Time Counter (RTC) is enabled, it will keep running during sleep and the device can

also wake up from either RTC Overflow or Compare Match interrupt.

Table 8-1. Active clock domains and wake-up sources in the different sleep modes.

Active clock domain Oscillators Wake-up sources

Sleep modes

CPU clock

Peripheral clock

RTC clock

System clock source

RTC clock source

Asynchronous Port Interrupts

TWI Address match

interrupts

Real Time Clock

Interrupts

All interrupts

Idle X X X X XXXX

Power-down X X

Power-save X X X X X

Standby X X X

Extended Standby X X X X X X

8077H–AVR–12/09

XMEGA A

8.3.4 Standby Mode

Standby mode is identical to Power-down with the exception that the enabled system clock

sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces

the wake-up time.

8.3.5 Extended Standby Mode

Extended Standby mode is identical to Power-save mode with the exception that the enabled

system clock sources are kept running while the CPU and Peripheral clocks are stopped. This

reduces the wake-up time.

8.4 Power Reduction Registers

The Power Reduction (PR) registers provides a method to stop the clock to individual peripher-

als. When this is done the current state of the peripheral is frozen and the associated I/O

registers cannot be read or written. Resources used by the peripheral will remain occupied;

hence the peripheral should in most cases be disabled before stopping the clock. Enabling the

clock to a peripheral again, puts the peripheral in the same state as before it was stopped. This

can be used in Idle mode and Active mode to reduce the overall power consumption signifi-

cantly. In all other sleep modes, the peripheral clock is already stopped.

Not all devices have all the peripherals associated with a bit in the power reduction registers.

Setting a power reduction bit for a peripheral that is not available will have no effect.

8.5 Register Description – Sleep

8.5.1 CTRL- Sleep Control Register

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:1 - SMODE[2:0]: Sleep Mode Selection

These bits select sleep modes according to Table 8-2 on page 97.

Bit 76543210

+0x00 ---- SMODE[2:0] SENCTRL

Read/WriteRRRRR/WR/WR/WR/W

Initial Value00000000

Table 8-2. Sleep mode

SMODE[2:0] SEN Group Configuration Description

XXX 0 OFF No sleep mode enabled

000 1 IDLE Idle Mode

001 1 - Reserved

010 1 PDOWN Power-down Mode

011 1 PSAVE Power-save Mode

100 1 - Reserved

8077H–AVR–12/09

XMEGA A

• Bit 1 - SEN: Sleep Enable

This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruc-

tion is executed. To avoid unintentional entering of sleep modes, it is recommended to write

SEN just before executing the SLEEP instruction, and clearing it immediately after waking up.

8.6 Register Description – Power Reduction

8.6.1 PRGEN - General Power Reduction Register

• Bit 7:5 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 4 - AES: AES Module

Setting this bit stops the clock to the AES module. When the bit is cleared the peripheral should

be reinitialized to ensure proper operation.

• Bit 3 - EBI: External Bus Interface

Setting this bit stops the clock to the External Bus Interface. When the bit is cleared the periph-

eral should be reinitialized to ensure proper operation. Note that the EBI is not present for all

devices.

• Bit 2 - RTC: Real-Time Counter

Setting this stops the clock to the Real Time Counter. When the bit is cleared the peripheral

should be reinitialized to ensure proper operation.

• Bit 1 - EVSYS: Event System

Setting this stops the clock to the Event System. When the bit is cleared the module will continue

like before the shutdown.

• Bit 0 - DMA: DMA Controller

Setting this stops the clock to the DMA Controller. This bit can only be set if the DMA Controller

is disabled.

101 1 - Reserved

110 1 STDBY Standby Mode

111 1 ESTDBY Extended Standby Mode

Table 8-2. Sleep mode

SMODE[2:0] SEN Group Configuration Description

Bit 76543210

+0x00 - - - AES EBI RTC EVSYS DMA PRGEN

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

8077H–AVR–12/09

XMEGA A

8.6.2 PRPA/B - Power Reduction Port A/B Register

Note: Disabling of analog modules stops the clock to the analog blocks themselves and not only the

interfaces.

• Bit 7:3 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 2 - DAC: Power Reduction DAC

Setting this bit stops the clock to the DAC. The DAC should be disabled before shut down.

• Bit 1 - ADC: Power Reduction ADC

Setting this bit stops the clock to the ADC. The ADC should be disabled before shut down.

• Bit 0 - AC: Power Reduction Analog Comparator

Setting this bit stops the clock to the Analog Comparator. The AC should be disabled before shut

down.

8.6.3 PRPC/D/E/F - Power Reduction Port C/D/E/F Register

• Bit 7 - Reserved

This bit is reserved and will always be read as zero. For compatibility with future devices, always

write this bit to zero when this register is written.

• Bit 6 - TWI: Two-Wire Interface

Setting this bit stops the clock to the Two-Wire Interface. When the bit is cleared the peripheral

should be reinitialized to ensure proper operation.

•Bit 5 - USART1

Setting this bit stops the clock to the USART1. When the bit is cleared the peripheral should be

reinitialized to ensure proper operation.

•Bit 4 - USART0

Setting this bit stops the clock to the USART0. When the bit is cleared the peripheral should be

reinitialized to ensure proper operation.

Bit 765432 1 0

+0x01/+0x02 -----DACADCACPRPA/B

Read/WriteRRRRRR/WR/WR/W

Initial Value000000 0 0

Bit 76543210

- TWI USART1 USART0 SPI HIRES TC1 TC0 PRPC/D/E/F

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

100

8077H–AVR–12/09

XMEGA A

• Bit 3 - SPI: Serial Peripheral Interface

Setting this bit stops the clock to the SPI. When the bit is cleared the peripheral should be reini-

tialized to ensure proper operation.

• Bit 2 - HIRES: Hi-Resolution Extension

Setting this bit stops the clock to the Hi-Resolution Extension for the Timer/Counters. When the

bit is cleared the peripheral should be reinitialized to ensure proper operation.

• Bit 1 - TC1: Timer/Counter 1

Setting this bit stops the clock to the Timer/Counter 1. When the bit is cleared the peripheral will

continue like before the shut down.

• Bit 0 - TC0: Timer/Counter 0

Setting this bit stops the clock to the Timer/Counter 0. When the bit is cleared the peripheral will

continue like before the shut down.

101

8077H–AVR–12/09

XMEGA A

8.7 Register Summary - Sleep

8.8 Register Summary - Power Reduction

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL - - - - SMODE[2:0] SEN 97

+0x01 Reserved - - - - - - - -

+0x02 Reserved - - - - - - - -

+0x03 Reserved - - - - - - - -

+0x04 Reserved - - - - - - - -

+0x05 Reserved - - - - - - - -

+0x06 Reserved - - - - - - - -

+0x07 Reserved - - - - - - - -

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 PRGEN - - - AES EBI RTC EVSYS DMA 98

+0x01 PRPA - - - - - DAC ADC AC 99

+0x02 PRPB - - - - - DAC ADC AC 99

+0x03 PRPC - TWI USART1 USART0 SPI HIRES TC1 TC0 99

+0x04 PRPD - TWI USART1 USART0 SPI HIRES TC1 TC0 99

+0x05 PRPE - TWI USART1 USART0 SPI HIRES TC1 TC0 99

+0x06 PRPF - TWI USART1 USART0 SPI HIRES TC1 TC0 99

+0x07 Reserved - - - - - - - -

102

8077H–AVR–12/09

XMEGA A

9. Reset System

9.1 Features

•Power-on reset source

•Brown-out reset source

•Software reset source

•External reset source

•Watchdog reset source

•Program and Debug Interface reset source

9.2 Overview

The Reset System will issue a system reset and set the device to its initial state if a reset source

goes active. All IO registers will be set to their initial value, and the program counter is reset to

the Reset Vector location. The reset controller is asynchronous, hence no running clock is

required to reset the device.

XMEGA has seven different reset sources. If more than one reset source is active, the device

will be kept in reset until all reset sources have released their reset. After reset is released from

all reset sources, the default oscillator is started and calibrated before the internal reset is

released and the device starts running.

The reset system has a status register with individual flags for each reset source. The Status

issued a reset since the last power-on. A software reset feature makes it possible to issue a sys-

tem reset from the user software.

An overview of the reset system is shown in Figure 9-1 on page 103.

103

8077H–AVR–12/09

XMEGA A

Figure 9-1. Reset system overview

Reset Delay Counter

Oscillator Startup

Oscillator Calibration

Power - On

Detection

Reset

Brown - Out

Detection Reset

External Reset

Watchdog

Reset

Program and

Debug Interface

Reset

Software Reset

Reset Status Register

Internal Reset

TimeoutCounter Reset

104

8077H–AVR–12/09

XMEGA A

9.3 Reset Sequence

Reset request from any reset source immediately reset the device, and keep it in reset as long

as the request is active. When all reset requests are released, the device will go through three

stages before the internal reset is released and the device starts running.

• Reset Counter Delay

• Oscillator startup

• Oscillator calibration

If one of the reset request occur during this, the reset sequence will start over again.

9.3.1 Reset Counter Delay

The Reset Counter Delay is the programmable period from all reset requests are released and

until the reset counter times out and releases reset. The Reset Counter Delay is timed from the

1 kHz output of the Ultra Low Power (ULP) Internal Oscillator, and the number of cycles before

the timeout is set by the STARTUPTIME fuse bits. The selectable delays are shown in Table 9-

9.3.2 Oscillator Startup

After the Reset Counter Delay, the default clock is started. This is the 2 MHz internal RC oscilla-

tor, and this uses 6 clock cycles to startup and stabilize.

9.3.3 Oscillator Calibration

After the default oscillator has stabilized, oscillator calibration values are loaded from Non-Vola-

tile Memory into the Oscillator Calibration registers. Loading the calibration values takes 24

clock cycles on the internal 2 MHz oscillator. The 2 MHz, 32 MHz and 32 kHz internal RC oscil-

lators are calibrated. When this is done the device will enter active mode and program execution

will begin.

9.4 Reset Sources

9.4.1 Power-On Reset

A Power-on detection circuit will give a Power-On Reset (POR) when supply voltage (VCC) is

applied to the device and the VCC slope is increasing in the Power-on Slope Range (VPOSR).

Power-on reset is released when the VCC stops rising or when the VCC level has reached the

Power-on Threshold Voltage (VPOT) level.

When VCC is falling, the POR will issue a reset when the Vpot level is reached. The Vpot level is

lower than the minimum operating voltage for the device, and is only used for power-off function-

Table 9-1. Reset Counter Delay

SUT[1:0] Number of 1 kHz ULP oscillator clock cycles

00 64

01 4

10 Reserved

11 0

105

8077H–AVR–12/09

XMEGA A

ality and not to ensure safe operation. The Brown-out detection (BOD) must be enabled to

ensure safe operation and detect if VCC voltage drops below minimum operating voltage.

Only the Power-on reset Flag will be set after Power-on reset. The Brown-out Reset Flag is not

set even though the BOD circuit is used.

Figure 9-2. Power-On Reset (POR).

Figure 9-3. Increasing VCC slope in the Power-on slope range.

For characterization data on the VPOT level for rising and falling VCC, and VPOSR slope consult the

device data sheet.

Note that the Power-on detection circuit is not designed to detect drops in the VCC voltage.

Brown-out detection must be enabled to detect falling VCC voltage, even if the VCC level falls

below the VPOT level.

TIMEOUT

INTERNAL

RESET

TOUT

BOT

POT

VPOT

VPOSR,MAX

VCC

VCC dV

106

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XMEGA A

9.4.2 Brown-Out Detection

The Brown-Out Detection (BOD) circuit monitors that the VCC level is kept above a configurable

trigger level, VBOT. When the BOD is enabled, a BOD reset will be given if the VCC level falls bel-

low the trigger level for a minimum time, tBOD. The reset is kept active until the VCC level rises

above the trigger level again.

Figure 9-4. Brown-out Detection reset.

For characterization data on tBOD consult the device data sheet. The trigger level is determined

by a programmable BODLEVEL setting, see Table 9-2.

Notes: 1. The values here are nominal values only. For typical, maximum and minimum numbers consult

the device data sheet.

2. Changing these fuse bits will have no effect until leaving programming mode.

The BOD circuit has 3 modes of operation:

•Disabled: In this mode there is no monitoring of the VCC level, and hence it is only

recommended for applications where the power supply is stable.

•Enabled: In this mode the VCC level is continuously monitored, and a drop in VCC below VBOT

for at least tBOD will give a brown-out reset.

Table 9-2. Programmable BODLEVEL setting

BODLEVEL[2:0] (1) VBOT UNIT

111 1.6

110 1.8

101 2.0

100 2.2

011 2.4

010 2.7

001 2.9

000 3.2

TIME-OUT

INTERNAL

RESET

BOT-

BOT+

TOUT

BOD

107

8077H–AVR–12/09

XMEGA A

•Sampled: In this mode the BOD circuit will sample the VCC level with a period identical to

the 1 kHz output from the Ultra Low Power (ULP) oscillator. Between each sample the BOD is

turned off. This mode will reduce the power consumption compared to the enabled mode, but

a fall in the VCC level between 2 positive edges of the 1 kHz ULP output will not be detected.

If a brown-out is detected in this mode, the BOD circuit is set in enabled mode to ensure that

the device is kept in reset until VCC is above VBOT again.

The BODACT fuse determines the BOD setting for active mode and idle mode, while the

BODPD fuse determines the brown-out detection setting for all sleep modes except idle mode.

9.4.3 External reset

The External reset circuit is connected to the external RESET pin. The external reset will trigger

when the RESET pin is driven below the RESET pin threshold voltage, VRST, for longer than the

minimum pulse period tEXT. The reset will be held as long as the pin is kept low. The reset pin

includes an internal pull-up resistor.

Figure 9-5. External reset characteristics.

For characterization data on VRST and tEXT and pull-up resistor values consult the device data

sheet.

9.4.4 Watchdog reset

The Watchdog Timer (WDT) is a system function for monitoring correct program operation. If the

WDT is not reset from the software within a programmable timout period, a Watchdog reset will

be given. The Watchdog reset is active for 1-2 clock cycles on the 2 MHz internal RC oscillator.

Table 9-3. BOD setting Fuse Decoding

BODACT[1:0]/ BODPD[1:0] Mode

00 Reserved

01 Sampled

10 Enabled

11 Disabled

EXT

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Figure 9-6. Watchdog reset.

For information on configuration and use of the WDT, refer to the Section 11. ”WDT – Watchdog

Timer” on page 117.

9.4.5 Software reset

The Software reset makes it possible to issue a system reset from software by writing to the

Software Reset bit in the Reset Control Register.The reset will be issued within 1-2 system clock

CPU cycles after writing the bit. It is not possible to execute any instruction from a software reset

is requested and until it is issued.

Figure 9-7. Software reset

9.4.6 Program and Debug Interface Reset

The Program and Debug Interface reset contains a separate reset source that is used to reset

the device during external programming and debugging. This reset source is only accessible

from debuggers and programmers.

1-2 2MHz

Cycles

SOFTWARE

1-2 2MHz Cycle

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9.5 Register Description

9.5.1 STATUS - Reset Status Register

• Bit 7 – 6: Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 5 – SRF: Software Reset Flag

This flag is set if a Software reset occurs. The flag will be cleared by a power-on reset or by writ-

ing a one to the bit location.

• Bit 4 - PDIRF: Program and Debug Interface Reset Flag

This flag is set if a Programming interface reset occurs. The flag will be cleared by a power-on

reset or by writing a one to the bit location.

• Bit 3 - WDRF: Watchdog Reset Flag

This flag is set if a Watchdog reset occurs. The flag will be cleared by a power-on reset or by

writing a one to the bit location.

• Bit 2 - BORF: Brown Out Reset Flag

This flag is set if a Brown out reset occurs. The flag will be cleared by a power-on reset or by

writing a one to the bit location.

• Bit 1 - EXTRF: External Reset Flag

This flag is set if an External reset occurs. The flag will be cleared by a power-on reset or by writ-

ing a one to the bit location.

• Bit 0 - PORF: Power On Reset Flag

This flag is set if a Power-on reset occurs. Writing a one to the flag will clear the bit location.

9.5.2 CTRL - Reset Control Register

• Bit 7:1 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 0 - SWRST: Software Reset

When this bit is set, a Software reset will occur. The bit is cleared when a reset is issued. This bit

is protected by the Configuration Change Protection, for details refer to Section 3.12 ”Configura-

tion Change Protection” on page 12.

Bit 76543210

+0x00 – – SRF PDIRF WDRF BORF EXTRF PORF STATUS

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value--------

Bit 76543210

+0x01 –––––––SWRSTCTRL

Read/WriteRRRRRRRR/W

Initial Value00000000

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9.6 Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 STATUS – – SRF PDIRF WDRF BORF EXTRF PORF 109

+0x01CTRL–– – ––– –SWRST109

10. Battery Backup System

10.1 Features

•Battery Backup voltage supply from dedicated VBAT power pin for:

– One Ultra Low-power 32-bit Real Time Counter

– One 32.768 kHz crystal oscillator with failure detection monitor

– Two Battery Backup Registers

•Automatic switching from main power to battery backup power at:

– Brown-Out Detection (BOD)

•Automatic switching from battery backup power to main power:

– Device reset after Brown-Out Reset (BOR) is released

– Device reset after Power-On Reset (POR) and BOR is released

10.2 Overview

The Battery Backup System includes functionality that enables automatic power switching

between main power and a battery backup power. Figure 10-1 on page 112 shows an overview

of the system.

The Battery Backup Module supports connection of a backup battery to the dedicated VBAT

power pin. This will ensure power to the 32-bit Real Time Counter, a 32.768 kHz crystal oscilla-

tor with failure detection monitor and two battery backup registers when the main power source

is unavailable.

Upon main power loss the device will detect this and automatically switch the Battery Backup

Module to be powered from the VBAT pin. After main power has been restored and both main

POR and BOR are released, the Battery Backup Module will automatically switch back to be

powered from main power again. The main BOD is used to detect the Vcc voltage levels, and

this must be enabled for the power switching to work.

The 32-bit Real Time Counter (RTC) must be clocked from the 1 Hz or 1.024 kHz output of a

32.768 kHz crystal oscillator connected between the TOSC1 and TOSC2 pins when running

from VBAT. For more details on the 32-bit RTC refer to the “32-bit Real Time Counter” section in

the XMEGA A Manual.

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10.3 Battery Backup Module

Figure 10-1. Battery Backup Module and its power domain implementation

The Battery Backup Module consists of the following:

•A V

BAT power supervisor that ensures correct operation and detection of falling power in the

backup battery power domain. It includes

– A Battery Backup Power-On Detector (BBPOD).

– A sampled Battery Backup Brown-Out Detector (BBBOD).

• A Power-switch for switching power to the battery backup domain between main power and the

VBAT pin.

• A 32.768 kHz Crystal Oscillator (XOSC) with 32.768 kHz, 1.024 kHz and 1 Hz output.

• A XOSC Failure Monitor for detecting failure on the Crystal Oscillator.

• A 32-bit Real Time Counter.

• Two Battery Backup registers.

The main BOD is used to detect Brown-Out on the main power so this must be enabled for the

power switching to work.

When main BOD is detected, the Battery Backup Module will switch to be powered from the VBAT

pin. When main power is restored and/or the device is reset, software must enable access to the

Battery Backup Module by writing a dedicated Access Enable bit in the module.

10.3.1 Battery Backup Power-On Detection

The Battery Backup Power-On Detection circuit will set the POD Flag (BBPODF) when power is

connected to the VBAT pin.

Power

switch VCC

Level shifters / Isolation

VBAT

TOSC1

TOSC2

VBAT

power

supervisor

XOSC

RTC

XOSC

monitor

Backup

Registers

Main

power

supervision

Oscillator &

sleep

controller

FLASH,

EEPROM

& Fuses

CPU

Peripherals

Watchdog w/

independent

RCOSC

Internal

RAM

GPIO

XTAL2

XTAL1

OCD &

Programming

Interface

The the 32-kHz crystal oscillator, oscillator failure detection and Real Time Counter must be

enabled from software before they can be used.

10.3.2 Battery Backup Brown-Out Detection

The Battery Backup Brown-Out Detector (BBBOD) ensures detection of falling power in the Bat-

tery Backup Module before the oscillator stops. When the VBAT pin voltage drops below the

BBBOD threshold voltage, the BOD Flag (BBBODF) will be set.

The BBBOD is sampled from the 1 Hz output of an ultra low power oscillator, and only designed

for detecting slow changes in the VBAT pin voltage level.

The BBBOD is turned off when the device runs from the main power. It is enabled when the Bat-

tery Backup Module is switched to be powered from the VBAT pin after a main power BOD.

10.4 Main Power Loss

When the main power drops below the programmed BOD threshold voltage, the device will:

1. Switch the Battery Backup Module to be powered from the VBAT pin. The BBBOD is

enabled.

2. Ignore any input signals to the Battery Backup Module.

3. The part of the device that is only powered from VCC will be reset.

10.5 Main Reset and Start-up Sequence

The Battery Backup System adds some considerations regarding main reset and start-up

sequence. At every start-up after main reset the software should:

1. Check for sufficient power on VBAT pin by reading the BBPWR flag.

2. Check the Battery Backup Module status by reading the BBPODF and BBBODF flags.

3. Enable access to the Battery Backup Module, by setting the Access Enable (ACCEN) bit.

Based on the status in Battery Backup Module, two different things should be done after the ini-

tial sequence. Each is described in the two sections below.

10.5.1 Battery Backup enabled

If BBPODF and/or BBBODF is not set, it indicates that the Battery Backup Modules has not had

any power loss. Then the device should:

1. Set the Access Enable (ACCEN) bit

2. Check for 32-Khz Crystal Oscillator failure by reading the XOSC Failure flag.

If the XOSC Failure flag is cleared no further actions is required.

If the XOSC Failure flag is set, this indicates a failure on the external oscillator in the Battery

Backup Module. The software should assume that the RTC counter value is invalid and take

appropriate action.

10.5.2 Battery Backup failed and not enabled

If BBPODF and/or BBBODF is set this indicate that voltage on the VBAT pin has had a drop

sometime during the period when the rest of the device was unpowererd. The following proce-

dure should be followed:

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1. Set the ACCEN bit and apply a RESET

1. Enable the Crystal oscillator.

2. Wait until Crystal Oscillator ready flag is set.

3. Enable XOSC Fault Detection.

4. Configure and enable the RTC32.

10.6 Register Description

10.6.1 CTRL: Battery Backup Control Register

• Bit [7:5] - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 4- XOSCSEL: 32-kHz Crystal Oscillator Output Selection

This bit selects which clock output from the 32.768 kHz crystal oscillator that will be used as

clock input for the 32-bit Real Time Counter (RTC).

By default this bit is zero, and the 1 Hz clock output is used as input for the RTC. Setting this bit

will select the 1.024 kHz clock output as input for the RTC. The Crystal Oscillator must be

enabled before the output is available. This bit cannot be changed when XOSCEN is set.

• Bit 3- XOSCEN: Crystal Oscillator Enable

Setting this bit will enable the 32.768 kHz crystal oscillator, and thSetting this bite default 1 Hz

output from the oscillator. Writing the bit to zero will have no effect. The oscillator will remain

enabled until a Battery Backup RESET is issued.

• Bit 2- XOSCFDEN: Crystal Oscillator Failure DSetting this bitetection Enable

Setting this bit will enable the 32.768 kHz crystal oscillator monitor. Writing the bit to zero will

have no effect. When enabled, the Crystal Oscillator Monitor will remain enabled until a Battery

Backup RESET is issued.

• Bit 1- ACCEN: Battery Backup Module Access Enable

Setting this bit will enable access to the Battery Backup Module. After main reset this bit must be

set in order to access (read from and write to) the battery backup domain functions and register

settings, except for the BBPODF, the BBBODF and the BBPWR flag.

• Bit 0- RESET: Battery Backup Reset

Setting this bit will force a reset of the Battery Backup Module. Writing the bit to zero will have no

effect. Writing a one to the XOSCEN or the XOSCFDEN bit the same time will block writing to

this bit. When this bit is set XOSCEN, XOSCFDEN, XOSCSEL, and XOSCRDY in STATUS will

be cleared.

Bit 76543 210

+0x00 - - - XOSCSEL XOSCEN XOSCFDEN ACCEN RESET CTRL

Read/Write R R R R/W R/W R/W R/W R/W

Reset Value 0 0 0 0 0 0 0 0

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These bits are protected by the Configuration Change Protection mechanism, for detailed

description refer to ”Configuration Change Protection” on page 12.

10.6.2 STATUS: Battery Backup Status Register

• Bit 7 - BBPWR: Battery Backup Power

The Power on the VBAT pin is automatically checked each time the main domain is powered. The

BBPWR flag will be set to one when no VBAT pin power is detected. The flag can be cleared by

writing a one to its bit location.

• Bit [6:4] - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3- XOSCRDY: Crystal Oscillator Ready

When the 32 kHz crystal oscillator is stable and ready to be used, this flag is set. This flag can

be cleared by writing a one to its bit location.

• Bit 2 - XOSCFAIL: Crystal Oscillator Failure

If the 32 kHz crystal oscillator has had an failure, the flag will be read as one. This flag can be

cleared by applying a RESET to the battery backup module.

• Bit 1 - BBBODF: Battery Backup Brown-Out Detection Flag

This flag is read one if a Battery Backup BOD is detected when the Battery Backup Module is

powered from the VBAT pin. This flag can be cleared by writing a one to its bit location. This flag

is not valid when BBPWR is set.

• Bit 0 - BBPODF: Battery Backup Power-On Detection Flag

This flag is set if a Battery Backup Power-On is detected, i.e when power is connected to VBAT.

This flag can be cleared by writing a one to its bit location. This flag is not valid when BBPWR is

set.

10.6.3 BACKUP0: Battery Backup Register 0

Bit 76543210

+0x01 BBPWR - - - XOSCRDY XOSCFAIL BBBODF BBPODF STATUS

Read/Write R/W R R R R/W R/W R/W R/W

Reset Value 0 0 0 0 x x 0 0

Bit 76543210

+0x02 BACKUP0[7:0] BACKUP0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Reset Valuexxxxxxxx

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• Bit [7:0] - BACKUP0: Battery Backup Register 0

This register can be used to store data in the Battery Backup Module before the main power is

lost or removed.

10.6.4 BACKUP1: Battery Backup Register 1

• Bit [7:0] - BACKUP0: Battery Backup Register 1

This register can be used to store data in the Battery Backup Module before the main power is

lost or removed.

10.7 Register Summary

Bit 76543210

+0x03 BACKUP1[7:0] BACKUP1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Reset Valuexxxxxxxx

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL XOSCSEL XOSCEN XOSCFDEN ACCEN RESET 114

+0x01 STATUS BBPWR XOSCRDY OSCFAIL BBBODF BBPODF 115

+0x02 BACKUP0 BACKUP0[7:0] 115

+0x03 BACKUP1 BACKUP1[7:0] 116

+0x04

+0x05

+0x06

+0x07

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11. WDT – Watchdog Timer

11.1 Features

•11 selectable timeout period, from 8 ms to 8s

•Two operation modes

– Standard mode

– Window mode

•Runs from 1 kHz Ultra Low Power clock reference

•Configuration lock

11.2 Overview

The Watchdog Timer (WDT) is a system function for monitoring correct program operation, mak-

ing it possible to recover from error situations, for instance run-away code. The WDT is a timer,

configured to a predefined timeout period and is constantly running when enabled. If the WDT is

not reset within the timeout period, it will issue a system reset. The WDT is reset by executing

the WDR (Watchdog Timer Reset) instruction from the application code.

The WDT also has a window mode that enables the user to define a time slot where WDT must

be reset within. If the WDT is reset too early or too late, a system reset will be issued.

The WDT will run in all power modes if enabled. It runs from a CPU independent clock source,

and will continue to operate to issue a system reset even if the main clocks fail.

The Configuration Change Protection mechanism ensures that the WDT settings cannot be

changed by accident. In addition the settings can be locked by a fuse.

11.3 Normal Mode Operation

In normal mode operation a single timeout period is set for the WDT. If the WDT is not reset from

the application code before the timeout occurs the WDT will issue a system reset. There are 11

possible WDT timeout (TOWDT) periods selectable from 8 ms to 8s, and the WDT can be reset at

any time during the period. After each reset, a new timeout period is started. The default timeout

period is controlled by fuses. Normal mode operation is illustrated in Figure 11-1.

Figure 11-1. Normal mode operation.

t [ms]

WDT Count

510

15 20 25 30 35

TOWDT = 16

Timely WDT

Reset

TOWDT

WDT Timeout

System Reset

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11.4 Window Mode Operation

In window mode operation the WDT uses two different timeout periods, a "closed" window time-

out period (TOWDTW) and the normal timeout period (TOWDT). The closed window timeout period

defines a duration from 8 ms to 8s where the WDT cannot be reset: if the WDT is reset in this

period the WDT will issue a system reset. The normal WDT timeout period, which is also 8 ms to

8s, defines the duration of the "open" period, in which the WDT can (and should) be reset. The

open period will always follow the closed period, so the total duration of the timeout period is the

sum of the closed window and the open window timeout periods. The default closed window tim-

eout period is controlled by fuses. The window mode operation is illustrated in Figure 11-2.

Figure 11-2. Window mode operation.

11.5 Watchdog Timer clock

The WDT is clocked from the 1 kHz output from the internal 32 kHz Ultra Low Power (ULP) oscil-

lator. Due to the ultra low power design, the oscillator is not very accurate so the exact timeout

period may vary from device to device. When designing software which uses the WDT, this

device-to-device variation must be kept in mind to ensure that the timeout periods used are valid

for all devices. For more information on the ULP oscillator accuracy, consult the device data

sheet.

11.6 Configuration Protection and Lock

The WDT is designed with two security mechanisms to avoid unintentional changes of the WDT

settings.

The first mechanism is the Configuration Change Protection mechanism, employing a timed

write procedure for changing the WDT control registers. In addition, for the new configuration to

be written to the control registers, the register’s Change Enable bit must be written at the same

time.

The second mechanism is to lock the configuration by setting the WDT lock fuse. When this fuse

is set, the Watchdog Time Control Register can not be changed, hence the WDT can not be dis-

abled from software. After system reset the WDT will resume at configured operation. When the

WDT lock fuse is programmed the window mode timeout period cannot be changed, but the win-

dow mode itself can still be enabled or disabled.

t [ms]

WDT Count

510

15 20 25 30 35

TOWDTW = 8

TOWDT = 8

Timely WDT

Reset

Closed

TOWDTW

Open

TOWDT

Early WDT Reset

System Reset

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11.7 Registers Description

11.7.1 CTRL – Watchdog Timer Control Register

• Bits 7:6 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bits 5:2 - PER[3:0]: Watchdog Timeout Period

These bits determine the Watchdog timeout period as a number of 1 kHz ULP oscillator cycles.

In window mode operation, these bits define the open window period. The different typical time-

out periods are found in Table 11-1. The initial values of these bits are set by the Watchdog

Timeout Period (WDP) fuses, and will be loaded at power-on.

In order to change these bits the CEN bit must be written to 1 at the same time. These bits are

protected by the Configuration Change Protection mechanism, for detailed description refer to

Section 3.12 ”Configuration Change Protection” on page 12.

Bit 76543210

+0x00 - - PER[3:0] ENABLE CEN CTRL

Read/Write

(unlocked) R R R/W R/W R/W R/W R/W R/W

Read/Write

(locked) RRRRRRRR

Initial Value

(x = fuse) 0 0XXXXX0

Table 11-1. Watchdog timeout periods

PER[3:0] Group Configuration Typical timeout periods

0000 8CLK 8 ms

0001 16CLK 16 ms

0010 32CLK 32 ms

0011 64CLK 64 ms

0100 125CLK 0.125 s

0101 250CLK 0.25 s

0110 500CLK 0.5 s

0111 1KCLK 1.0 s

1000 2KCLK 2.0 s

1001 4KCLK 4.0 s

1010 8KCLK 8.0 s

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

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• Bit 1 - ENABLE: Watchdog Enable

This bit enables the WDT.

In order to change this bit the CEN bit in ”CTRL – Watchdog Timer Control Register” on page

119 must be written to one at the same time. This bit is protected by the Configuration Change

Protection mechanism, for detailed description refer to Section 3.12 ”Configuration Change Pro-

tection” on page 12.

• Bit 0 - CEN: Watchdog Change Enable

This bit enables the possibility to change the configuration of the ”CTRL – Watchdog Timer Con-

trol Register” on page 119. When writing a new value to this register, this bit must be written to

one at the same time for the changes to take effect. This bit is protected by the Configuration

Change Protection mechanism, for detailed description refer to Section 3.12 ”Configuration

Change Protection” on page 12.

11.7.2 WINCTRL – Window Mode Control Register

• Bits 7:6 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bits 5:2 - WPER[3:0]: Watchdog Window Mode Timeout Period

These bits determine the closed window period as a number of 1 kHz ULP oscillator cycles in

window mode operation. The typical different closed window periods are found in Table 11-2.

The initial values of these bits are set by the Watchdog Window Timeout Period (WDWP) fuses,

and will be loaded at power-on. In normal mode these bits are not in use.

In order to change these bits the WCEN bit must be written to one at the same time. These bits

are protected by the Configuration Change Protection mechanism, for detailed description refer

to Section 3.12 ”Configuration Change Protection” on page 12.

Bit 76543210

+0x01 - - WPER[3:0] WEN WCEN WINCTRL

Read/Write

(unlocked) R R R/W R/W R/W R/W R/W R/W

Read/Write

(locked) RRRRRRR/WR/W

Initial Value

(x = fuse) 00XXXXX0

Table 11-2. Watchdog closed window periods

WPER[3:0] Group Configuration Typical closed window periods

0000 8CLK 8 ms

0001 16CLK 16 ms

0010 32CLK 32 ms

0011 64CLK 64 ms

0100 125CLK 0.125 s

0101 250CLK 0.25 s

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• Bit 1 - WEN: Watchdog Window Mode Enable

This bit enables the Watchdog Window Mode. In order to change this bit the WCEN bit in

”WINCTRL – Window Mode Control Register” on page 120 must be written to one at the same

time. This bit is protected by the Configuration Change Protection mechanism, for detailed

description refer to Section 3.12 ”Configuration Change Protection” on page 12.

• Bit 0 - WCEN: Watchdog Window Mode Change Enable

This bit enables the possibility to change the configuration of the ”WINCTRL – Window Mode

Control Register” on page 120. When writing a new value to this register, this bit must be written

to one at the same time for the changes to take effect. This bit is protected by the Configuration

Change Protection mechanism, but not protected by the WDT lock fuse.

11.7.3 STATUS – Watchdog Status Register

• Bit 7:1 - Res:Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 0 - SYNCBUSY

When writing to the CTRL or WINCTRL registers, the WDT needs to be synchronized to the

other clock domains. During synchronization the SYNCBUSY bit will be read as one. This bit is

automatically cleared after the synchronization is finished. Synchronization will only take place

when the ENABLE bit for the Watchdog Timer is set.

0110 500CLK 0.5 s

0111 1KCLK 1.0 s

1000 2KCLK 2.0 s

1001 4KCLK 4.0 s

1010 8KCLK 8.0 s

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

Table 11-2. Watchdog closed window periods (Continued)

WPER[3:0] Group Configuration Typical closed window periods

Bit 7654321 0

+0x02 -------SYNCBUSYSTATUS

Read/Write RRRRRRR R

Initial Value 0 0 0 0 0 0 0 0

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11.8 Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL - - PER[3:0] ENABLE CEN 119

+0x01 WINCTRL - - WPER[3:0] WEN WCEN 120

+0x02 STATUS - - - - - - - SYNCBUSY 121

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12. Interrupts and Programmable Multi-level Interrupt Controller

12.1 Features

•Separate interrupt vector for each interrupt

•Short, predictable interrupt response time

•Programmable Multi-level Interrupt Controller

– 3 programmable interrupt levels

– Selectable priority scheme within low level interrupts (round-robin or fixed)

– Non-Maskable Interrupts (NMI)

•Interrupt vectors can be moved to the start of the Boot Section.

12.2 Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execu-

tion. Peripherals can have one or more interrupts, and all are individually enabled. When the

interrupt is enabled and the interrupt condition is present this will generate a corresponding inter-

rupt request. All interrupts have a separate interrupt vector address.

The Programmable Multi-level Interrupt Controller (PMIC) controls the handling of interrupt

requests, and prioritizing between the different interrupt levels and interrupt priorities. When an

interrupt request is acknowledged by the PMIC, the program counter is set to point to the inter-

rupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts; low, medium

or high. Medium level interrupts will interrupt low level interrupt handlers. High level interrupts

will interrupt both medium and low level interrupt handlers. Within each level, the interrupt prior-

ity is decided from the interrupt vector address, where the lowest interrupt vector address has

the highest interrupt priority. Low level interrupts have an optional round-robin scheduling

scheme to ensure that all interrupts are serviced within a certain amount of time.

Non-Maskable Interrupts (NMI) are also supported.

12.3 Operation

Interrupts must be globally enabled for any interrupts to be generated. This is done by setting

the global interrupt enable bit (I-bit) in the CPU Status Register. The I-bit will not be cleared

when an interrupt is acknowledged. Each interrupt level must also be enabled before interrupts

with the corresponding level can be generated.

When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the

interrupt request. Based on the interrupt level and interrupt priority of any ongoing interrupts, the

interrupt is either acknowledged or kept pending until it has priority. When the interrupt request

is acknowledged, the program counter is updated to point to the interrupt vector. The interrupt

vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.

After returning from the interrupt handler, program execution continues from where it was before

the interrupt occurred. One instruction is always executed before any pending interrupt is

served.

The PMIC status register contains state information that ensures that the PMIC returns to the

correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an

interrupt handler. Returning from an interrupt will return the PMIC to the state it had before enter-

ing the interrupt. The Status Register (SREG) is not saved automatically upon an interrupt

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request. The RET (subroutine return) instruction cannot be used when returning from the inter-

rupt handler routine, as this will not return the PMIC to its right state.

12.4 Interrupts

All interrupts and the reset vector each have a separate program vector address in the program

memory space. The lowest address in the program memory space is the reset vector. All inter-

rupts are assigned individual control bits for enabling and setting the interrupt level, and this is

set in the control registers for each peripheral that can generate interrupts. Details on each inter-

rupt are described in the peripheral where the interrupt is available.

All interrupts have an interrupt flag associated to it. When the interrupt condition is present, the

interrupt flag will be set, even if the corresponding interrupt is not enabled. For most interrupts,

the interrupt flag is automatically cleared when executing the interrupt vector. Writing a logical

one to the interrupt flag will also clear the flag. Some interrupt flags are not cleared when execut-

ing the interrupt vector, and some are cleared automatically when an associated register is

accessed (read or written). This is described for each individual interrupt flag.

If an interrupt condition occurs while another higher priority interrupt is executing or pending, the

interrupt flag will be set and remembered until the interrupt has priority. If an interrupt condition

occurs while the corresponding interrupt is not enabled, the interrupt flag will be set and remem-

bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more

interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag

will be set and remembered until global interrupts are enabled. All pending interrupts are then

executed according to their order of priority.

Interrupts can be blocked when executing code from a locked section, e.g. when the Boot Lock

bits are programmed. This feature improves software security, refer to memory programming for

details on lock bit settings.

Interrupts are automatically disabled for up to 4 CPU clock cycles when the Configuration

Change Protection register is written with the correct signature, refer to Section 3.12 ”Configura-

tion Change Protection” on page 12 for more details.

12.4.1 NMI – Non-Maskable Interrupts

Non-Maskable Interrupts (NMI) are hardwired. It is not selectable which interrupts represent NMI

and which represent regular interrupts. Non-Maskable Interrupts must be enabled before they

can be used. Refer to the device data sheet for NMI present on each the device.

A NMI will be executed regardless of the setting of the I-bit, and it will never change the I-bit. No

other interrupts can interrupt a NMI interrupt handler. If more than one NMI is requested at the

same time, priority is static according to interrupt vector address where lowest address has high-

est priority.

12.4.2 Interrupt Response Time

The interrupt response time for all the enabled interrupts is five CPU clock cycles minimum. Dur-

ing these five clock cycles the program counter is pushed on the stack. After five clock cycles,

the program vector for the interrupt is executed. The jump to the interrupt handler takes three

clock cycles.

If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the device is in sleep mode, the inter-

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rupt execution response time is increased by five clock cycles. In addition the response time is

increased by the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles,

the program counter is popped from the stack and the stack pointer is incremented.

12.5 Interrupt level

The interrupt level is independently selected for each interrupt source. For any interrupt request,

the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre-

sponding bit values for the interrupt level configuration of all interrupts is shown in Table 12-1.

The interrupt level of an interrupt request is compared against the current level and status of the

interrupt controller. An interrupt request on higher level will interrupt any ongoing interrupt han-

dler from a lower level interrupt. When returning from the higher level interrupt handler, the

execution of the lower level interrupt handler will continue.

12.6 Interrupt priority

Within each interrupt level, all interrupts have a priority. When several interrupt requests are

pending, the order of which interrupts are acknowledged is decided both by the level and the pri-

ority of the interrupt request. Interrupts can be organized in a static or dynamic (round-robin)

priority scheme. High and Medium level interrupts and the NMI will always have static priority.

For Low level interrupts, static or dynamic priority scheduling can be selected.

12.6.1 Static priority

Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector

address decides the priority within one interrupt level where the lowest interrupt vector address

has the highest priority. Refer to the device data sheet for interrupt vector table with the base

address for all modules and peripherals with interrupt. Refer to the interrupt vector summary of

each module and peripheral in this manual for a list of interrupts and their corresponding offset

address within the different modules and peripherals.

Table 12-1. Interrupt level

Interrupt level

configuration Group Configuration Description

00 OFF Interrupt disabled.

01 LO Low level interrupt

10 MED Medium level interrupt

11 HI High level interrupt

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Figure 12-1. Static priority.

12.6.2 Round-robin scheduling

To avoid the possible starvation problem for low level interrupts with static priority, the PMIC

gives the possibility for round-robin scheduling for low level interrupts. When round-robin sched-

uling is enabled, the interrupt vector address for the last acknowledged low level interrupt will

have the lowest priority next time one or more interrupts from the low level is requested.

Figure 12-2. Round-robin scheduling.

IVEC 0

IVEC x

IVEC x+1

IVEC N Lowest Priority

Highest Priority

Lowest Address

Highest Address

Highest Priority

IV EC 0

IV EC x

IV EC x +1

IV EC N

IV EC 0

IV EC x

IV EC x +1

IV EC N

Highest Priority

Low est Priority

IV EC x +2

IVEC x+1 last acknowledged

interrupt

Low est Priority

IVEC x last acknowledged

interrupt

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12.7 Moving Interrupts Between Application and Boot Section

The interrupt vectors can be moved from the default location in the Application Section in Flash

to the start of the Boot Section.

12.8 Register Description

12.8.1 STATUS - PMIC Status Register

• Bit 7 - NMIEX: Non-Maskable Interrupt Executing

This flag is set if a Non-Maskable Interrupt is executing. The flag will be cleared when returning

(RETI) from the interrupt handler.

• Bit 6:3 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 2 - HILVLEX: High Level Interrupt Executing

This flag is set if a high level interrupt is executing or the interrupt handler has been interrupted

by an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.

• Bit 1 - MEDLVLEX: Medium Level Interrupt Executing

This flag is set if a medium level interrupt is executing or the interrupt handler has been inter-

rupted by an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI)

from the interrupt handler.

• Bit 0 - LOLVLEX: Low Level Interrupt Executing

This flag is set if a low level interrupt is executing or the interrupt handler has been interrupted by

an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the

interrupt handler.

12.8.2 INTPRI - PMIC Priority Register

• Bit 7:0 - INTPRI: Interrupt Priority

When round-robin scheduling is enabled, this register stores the interrupt vector of the last

acknowledged low-level interrupt. The stored interrupt vector will have the lowest priority next

time one or more low-level interrupts are pending. The register is accessible from software to

Bit 765432 1 0

+0x00 NMIEX - - - - HILVLEX MEDLVLEX LOLVLEX STATUS

Read/Write RRRRRR R R

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x01 INTPRI[7:0] INTPRI

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

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change the priority queue. This register is not reinitialized to its initial value if round-robing

scheduling is disabled, so if default static priority is needed the register must be written to zero.

12.8.3 CTRL - PMIC Control Register

• Bit 7 - RREN: Round-robin Scheduling Enable

When the RREN bit is set the round-robin scheduling scheme is enabled for low level interrupts.

When this bit is cleared, the priority is static according to interrupt vector address where the low-

est address has the highest priority.

• Bit 6 - IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Applica-

tion section in flash. When this bit is set (one), the interrupt vectors are moved to the beginning

of the Boot section of the Flash. Refer to the device data sheet for the absolute address.

This bit is protected by the Configuration Change Protection mechanism, refer to Section 3.12

”Configuration Change Protection” on page 12 for details.

• Bit 5:3 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 2 - HILVLEN: High Level Interrupt Enable

When this bit is set all high level interrupts are enabled. If this bit is cleared, high level interrupt

requests will be ignored.

• Bit 1 - MEDLVLEN: Medium Level Interrupt Enable

When this bit is set all medium level interrupts are enabled. If this bit is cleared, medium level

interrupt requests will be ignored.

• Bit 0 - LOLVLEN: Low Level Interrupt Enable

When this bit is set all low level interrupts are enabled. If this bit is cleared, low level interrupt

requests will be ignored.

12.9 Register Summary

Bit 765432 1 0

+0x02 RREN IVSEL - - - HILVLEN MEDLVLEN LOLVLEN CTRL

Read/Write R/W R/W R R R R/W R/W R/W

Initial Value 000000 0 0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 STATUS NMIEX - - - - HILVLEX MEDLVLEX LOLVLEX 127

+0x01 INTPRI INTPRI[7:0] 127

+0x02 CTRL RREN IVSEL - - - HILVLEN MEDLVLEN LOLVLEN 128

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13. I/O Ports

13.1 Features

•Selectable input and output configuration for each pin individually

•Flexible pin configuration through dedicated Pin Configuration Register

•Synchronous and/or asynchronous input sensing with port interrupts and events

•Asynchronous wake-up signalling

•Highly configurable output driver and pull settings:

– Totem-pole

– Pull-up/-down

– Wired-AND

– Wired-OR

– Bus keeper

– Inverted I/O

•Slew rate control

•Flexible pin masking

•Configuration of multiple pins in a single operation

•Read-Modify-Write (RMW) support

•Toggle/clear/set registers for OUT and DIR registers

•Clock output on port pin

•Event Channel 0 output on port pin 7

•Mapping of port registers (virtual ports) into bit accessible I/O memory space

13.2 Overview

XMEGA has flexible General Purpose I/O (GPIO) Ports. A port consists of up to 8 pins ranging

from pin 0 to 7, where each pin can be configured as input or output with highly configurable

driver and pull settings. The ports also implement several functions including interrupts, synchro-

nous/asynchronous input sensing and asynchronous wake-up signalling.

All functions are individual per pin, but several pins may be configured in a single operation. All

ports have true Read-Modify-Write (RMW) functionality when used as general purpose I/O ports.

The direction of one port pin can be changed without unintentionally changing the direction of

any other pin. The same applies when changing drive value when configured as output, or

enabling/disabling of pull-up or pull-down resistors when configured as input.

Figure 13-1 on page 130 shows the I/O pin functionality, and the registers that is available for

controlling a pin.

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Figure 13-1. General I/O pin functionality.

13.3 Using the I/O Pin

Use of an I/O pin is controlled from the user software. Each port has one Data Direction (DIR),

Data Output Value (OUT) that is used for port pin control. The Data Input Value (IN) register is

used for reading the port pins. In addition each pin has a Pin Configuration (PINnCTRL) register

for additional pin configuration.

Direction of the pin is decided by the DIRn bit in the DIR register. If DIRn is written to one, pin n

is configured as an output pin. If DIRn is written to zero, pin n is configured as an input pin.

When direction is set as output, the OUTn bit in OUT is used to set the value of the pin. If OUTn

is written to one, pin n is driven high. If OUTn is written to zero, pin n is driven low.

The IN register is used for reading the pin value. The pin value can always be read regardless of

the pin being configured as input or output, except if digital input is disabled.

I/O pins are tri-stated when reset condition becomes active, even if no clocks are running.

Synchronizer

DIRn

OUTn

PINnCTRL

INn

Pxn

Input Disable

Wired AND/OR

Slew Rate Limit

Digital Input Pin

Analog Input/Output

Inverted I/O

Pull Enable

Pull Keep

Pull Direction

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13.4 I/O Pin Configuration

The Pin n Configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin

can be set in a totem-pole, wired-AND, or wired-OR configuration. It is also possible to enable

inverted input and output for the pin.

For totem-pole output there are four possible pull configurations: Totem-pole (Push-pull), Pull-

down, Pull-up and Bus-keeper. The bus-keeper is active in both directions. This is to avoid oscil-

lation when disabling the output. The totem-pole configurations with pull-up and pull-down only

have active resistors when the pin is set as input. This feature eliminates unnecessary power

consumption. For wired-AND and wired-OR configuration, the optional pull-up and pull-down

resistors are active in both input and output direction.

Since pull configuration is configured through the pin configuration register, all intermediate port

states during switching of pin direction and pin values are avoided.

The I/O pin configurations are summarized with simplified schematics from Figure 13-2 on page

131 to Figure 13-7 on page 133.

13.4.1 Totem-pole

When configured for Totem-pole (push-pull), the pin is driven low or high according to the corre-

sponding bit setting in OUT. In this configuration there is no current limitation for sink or source

other than what the pin is capable of. If the pin is configured for input, the pin will float if no exter-

nal pull is connected.

Figure 13-2. I/O pin configuration - Totem-pole (push-pull)

13.4.1.1 Totem-pole with Pull-down

In this mode, the configuration is as for Totem-pole, expect the pin is configured with internal

pull-down when set as input.

Figure 13-3. I/O pin configuration - Totem-pole with pull-down (on input)

INn

OUTn

DIRn

INn

OUTn

DIRn

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13.4.1.2 Totem-pole with Pull-up

In this mode, the configuration is as for Totem-pole, expect the pin is configured with internal

pull-up when set as input.

Figure 13-4. I/O pin configuration - Totem-pole with pull-up (on input).

13.4.2 Bus-keeper

When the pin is configured for bus-keeper, it provides a weak bus-keeper that will keep the pin

at its logic level when the pin is no longer driven to any logic state. If last level on the pin/bus was

1, the bus-keeper will use the internal pull resistor to keep the bus high. If last logic level on the

pin/bus was 0, the bus-keeper will use the internal pull resistor to keep the bus high.

The bus-keeper’s week output produces the same logical level as the last output level. It acts as

a pull-up if the last level was '1', and pull-down if the last level was '0'.

Figure 13-5. I/O pin configuration - Totem-pole with bus-keeper

13.4.3 Wired-OR

With Wired-OR configuration, the pin will be driven high when the corresponding bit in OUT is

written to one. When OUT is set to zero, the pin is released allowing the pin to be pulled low with

the internal or an external pull-resistor. If internal pull-down is used, this is also active if the pin is

set as input.

INn

OUTn

DIRn

INn

OUTn

DIRn

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Figure 13-6. Output configuration - Wired-OR with optional pull-down.

13.4.4 Wired-AND

With Wired-AND configuration, the pin will be driven low when the corresponding bit in OUT is

written to zero. When OUT is set to one, the pin is released allowing the pin to be pulled low with

the internal or an external pull-resistor. If internal pull-up is used, this is also active if the pin is

set as input.

Figure 13-7. Output configuration - Wired-AND with optional pull-up.

13.5 Reading the Pin value

Independent of the pin data direction, the pin value can be read from the IN register as shown in

Figure 13-1 on page 130. If the digital input is disabled, the pin value cannot be read. The IN

avoid metastability if the physical pin changes value near the edge of the internal clock. The

Synchronizer introduces a delay on the internal signal line. Figure 13-8 on page 134 shows a

timing diagram of the synchronization when reading an externally applied pin value. The maxi-

mum and minimum propagation delays are denoted tpd,max and tpd,min respectively.

INn

OUTn

INn

OUTn

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Figure 13-8. Synchronization when reading an externally applied pin value.

13.6 Input Sense Configuration

Input sensing is used to detect an edge or level on the I/O pin input. The different sense configu-

rations that are available for each pin are detection of rising edge, falling edge or both edges, or

detection of low level. High level can be detected by using inverted input. Input sensing can be

used to trigger interrupt requests (IREQ) or s when there is a change on the pin.

The I/O pins support synchronous and asynchronous input sensing. Synchronous sensing

requires presence of the peripheral clock, while asynchronous sensing does not require any

clock.

Figure 13-9. Input sensing.

PERIPHERAL CLK

INSTRUCTIONS

SYNC FLIPFLOP

r17

xxx xxx lds r17, PORTx+IN

tpd, max

tpd, min

0x00 0xFF

INV E RTE D I/O

Interrupt

Control IREQ

Event

Synchronizer

INn

EDGE

DETECT

Asynchronous sensing

Synchronous sensing

EDGE

DETECT

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13.7 Port Interrupt

Each port has two interrupt vectors, and it is configurable which pins on the port that can be

used to trigger each interrupt request. Port interrupts must be enabled before they can be used.

Which sense configurations that can be used to generate interrupts is dependent on whether

synchronous or asynchronous input sensing is used.

For synchronous sensing, all sense configurations can be used to generate interrupts. For edge

detection, the changed pin value must be sampled once by the peripheral clock for an interrupt

request to be generated.

For asynchronous sensing, only port pin 2 on each port has full asynchronous sense support.

This means that for edge detection, pin 2 will detect and latch any edge and it will always trigger

an interrupt request. The other port pins have limited asynchronous sense support. This means

that for edge detection the changed value must be held until the device wakes up and a clock is

present. If the pin value returns to its initial value before the end of the device start-up time, the

device will still wake up, but no interrupt request will be generated.

A low level can always be detected by all pins, regardless of a peripheral clock being present or

not. If a pin is configured for low level sensing, the interrupt will trigger as long as the pin is held

low. In active mode the low level must be kept until the completion of the currently executing

instructions for an interrupt to be generated. In all sleep modes the low level must be kept until

the end of the device start-up time for an interrupt to be generated. If the low level disappears

before the end of the start-up time, the device will still wake up, but no interrupt will be

generated.

Table 13-1, Table 13-2, and Table 13-3 on page 136 summarizes when interrupts can be trig-

gered for the various input sense configurations.

Table 13-1. Synchronous sense support

Sense settings Supported Interrupt description

Rising edge Yes Always Triggered

Falling edge Yes Always Triggered

Both edges Yes Always Triggered

Low level Yes Pin-level must be kept unchanged.

Table 13-2. Full asynchronous sense support

Sense settings Supported Interrupt description

Rising edge Yes Always Triggered

Falling edge Yes Always Triggered

Both edges Yes Always Triggered

Low level Yes Pin-level must be kept unchanged.

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13.8 Port Event

Port pins can generate an event when there is a change on the pin. The sense configurations

decide when each pin will generate events. Event generation requires the presence of a periph-

eral clock, hence asynchronous event generation is not possible. For edge sensing, the

changed pin value must be sampled once by the peripheral clock for an event to be generated.

A level sensing, a low level pin value will not generate events, and a high pin value will continu-

ously generate events. For events to be generated on low level, the pin configuration mst be set

to inverted I/O.

13.9 Alternate Port Functions

Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When

an alternate function is enabled this might override the normal port pin function or pin value. This

happens when other peripherals that require pins are enabled or configured to use pins. If, and

how a peripheral will override and use pins is described in section for that peripheral.

The port override signals and related logic (grey) is shown in Figure 13-10 on page 137. These

signals are not accessible from software, but are internal signals between the overriding periph-

eral and the port pin.

Table 13-3. Limited asynchronous sense support

Sense settings Supported Interrupt description

Rising edge No -

Falling edge No -

Both edges Yes Pin value must be kept unchanged.

Low level Yes Pin-level must be kept unchanged.

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Figure 13-10. Port override signals and related logic

13.10 Slew-rate Control

Slew-rate control can be enabled for all I/O pins individually. Enabling the slew rate limiter will

typically increase the rise/fall time by 50-150% depending on voltage, temperature and load. For

information about the characteristics of the slew-rate limiter, please refer to the device data

sheet.

13.11 Clock and Event Output

It is possible to output both the Peripheral Clock and the signaling event from Event Channel 0

to pin. Output port pin is selected from software. If an event occur on Event Channel 0, this will

Synchronizer

DIRn

OUTn

PINnCTRL

INn

Pxn

Digital Input Disable (DID)

Wired AND/OR

Slew Rate Limit

Digital Input Pin

Analog Input/Output

Inverted I/O

DID Override Value

OUT Override Enable

OUT Overri de Value

DIR Override Value

DIR Override Enable

DID Override Enable

Pull Enable

Pull Keep

Pull Direction

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be visible on the port pin as long as the event last. Normally this is one peripheral clock cycle

only.

13.12 Multi-configuration

MPCMASK can be used to set a bit mask for the pin configuration registers. When setting bit n in

MPCMASK, PINnCTRL is added to the pin configuration mask. During the next write to any of

the port's pin configuration registers, the same value will be written to all the port's pin configura-

tion registers set by the mask. The MPCMASK register is cleared automatically after the write

operation to the pin configuration registers is finished.

13.13 Virtual Port Registers

Virtual port registers allow for port registers in the extended I/O memory space to be mapped vir-

tually in the I/O memory space. When mapping a port, writing to the virtual port register will be

the same as writing to the real port register. This enables use of I/O memory specific instructions

for bit-manipulation, and the I/O memory specific instructions IN and OUT on port register that

normally resides in the extended I/O memory space. There are four virtual ports, so up to four

ports can be mapped virtually at the same time. The mapped registers are IN, OUT, DIR and

INTFLAGS.

13.14 Register Description – Ports

13.14.1 DIR - Data Direction Register

• Bit 7:0 - DIR[7:0]: Data Direction

This register sets the data direction for the individual pins in the port. If DIRn is written to one, pin

n is configured as an output pin. If DIRn is written to zero, pin n is configured as an input pin.

13.14.2 DIRSET - Data Direction Set Register

• Bit 7:0 - DIRSET[7:0]: Port Data Direction Set

This register can be used instead of a Read-Modify-Write to set individual pins as output. Writing

a one to a bit will set the corresponding bit in the DIR register. Reading this register will return

the value of the DIR register.

Bit 76543210

+0x00 DIR[7:0] DIR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x01 DIRSET[7:0] DIRSET

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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13.14.3 DIRCLR - Data Direction Clear Register

• Bit 7:0 - DIRCLR[7:0]: Port Data Direction Clear

This register can be used instead of a Read-Modify-Write to set individual pins as input. Writing

a one to a bit will clear the corresponding bit in the DIR register. Reading this register will return

the value of the DIR register.

13.14.4 DIRTGL - Data Direction Toggle Register

• Bit 7:0 - DIRTGL[7:0]: Port Data Direction Toggle

This register can be used instead of a Read-Modify-Write to toggle the direction on individual

pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. Reading this reg-

ister will return the value of the DIR register.

13.14.5 OUT - Data Output Value

• Bit 7:0 - OUT[7:0]: Port Data Output value

This register sets the data output value for the individual pins in the port. If OUTn is written to

one, pin n is driven high. If OUTn is written to zero, pin n is driven low. For this setting to have

any effect the pin direction must be set as output.

13.14.6 OUTSET - Data Output Value Set Register

Bit 76543210

+0x02 DIRCLR[7:0] DIRCLR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x03 DIRTGL[7:0] DIRTGL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x04 OUT[7:0] OUT

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x05 OUTSET[7:0] OUTSET

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 7:0 - OUTSET[7:0]: Data Output Value Set

This register can be used instead of a Read-Modify-Write to set the output value on individual

pins to one. Writing a one to a bit will set the corresponding bit in the OUT register. Reading this

13.14.7 OUTCLR - Data Output Value Clear Register

• Bit 7:0 - OUTCLR[7:0]: Data Output Value Clear

This register can be used instead of a Read-Modify-Write to set the output value on individual

pins to zero. Writing a one to a bit will clear the corresponding bit in the OUT register. Reading

this register will return the value in the OUT register.

13.14.8 OUTTGL - Data Output Value Toggle Register

• Bit 7:0 - OUTTGL[7:0]: Port Data Output Value Toggle

This register can be used instead of a Read-Modify-Write to toggle the output value on individual

pins. Writing a one to a bit will toggle the corresponding bit in the OUT register. Reading this reg-

ister will return the value in the OUT register.

13.14.9 IN - Data Input Value Register

• Bit 7:0 - IN[7:0]: Data Input Value

This register shows the value present on the pins if the digital input driver is enabled. INn shows

the value of pin n on the port.

Bit 76543210

+0x06 OUTCLR[7:0] OUTCLR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x07 OUTTGL[7:0] OUTTGL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x08 IN[7:0] IN

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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13.14.10 INTCTRL - Interrupt Control Register

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:2/1:0 - INTnLVL[1:0]: Interrupt n Level

These bits enable interrupt request for port interrupt n and select the interrupt level as described

in Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page 123.

13.14.11 INT0MASK - Interrupt 0 Mask Register

• Bit 7:0 - INT0MSK[7:0]: Interrupt 0 Mask Register

These bits are used to mask which pins can be used as sources for port interrupt 0. If

INT0MASKn is written to one, pin n is used as source for port interrupt 0.The input sense config-

uration for each pin is decided by the PINnCTRL-registers.

13.14.12 INT1MASK - Interrupt 1 Mask Register

• Bit 7:0 - INT1MASK[7:0]: Interrupt 1 Mask Register

These bits are used to mask which pins can be used as sources for port interrupt 1. If

INT1MASKn is written to one, pin n is used as source for port interrupt 1.The input sense config-

uration for each pin is decided by the PINnCTRL-registers.

Bit 76543210

+0x09 - - - - INT1LVL[1:0] INT0LVL[1:0] INTCTRL

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x0A INT0MSK[7:0] INT0MASK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x0B INT1MSK[7:0] INT1MASK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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13.14.13 INTFLAGS - Interrupt Flag Register

• Bit 7:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1:0 - INTnIF: Interrupt n Flag

The INTnIF flag is set when a pin change according to the pin's input sense configuration

occurs, and the pin is set as source for port interrupt n. Writing a one to this flag's bit location will

clear the flag. For enabling and executing the interrupt refer to the interrupt level description.

13.14.14 PINnCTRL - Pin n Configuration Register

• Bit 7 - SRLEN: Slew Rate Limit Enable

Setting this bit will enable slew-rate limiting on pin n.

• Bit 6 - INVEN: Inverted I/O Enable

Setting this bit will enable inverting output and input data on pin n.

• Bit 5:3 - OPC: Output and Pull Configuration

These bits set the Output/Pull configuration on pin n according to Table 13-4.

Bit 76543210

+0x0C ------INT1IFINT0IFINTFLAGS

Read/WriteRRRRRRR/WR/W

Initial Value00000000

Bit 76543210

SRLEN INVEN OPC[2:0] ISC[2:0] PINnCTRL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 13-4. Output/Pull Configuration

OPC[2:0] Group Configuration

Description

Output configuration Pull configuration

000 TOTEM Totempole (N/A)

001 BUSKEEPER Totempole Bus keeper

010 PULLDOWN Totempole Pull-down (on input)

011 PULLUP Totempole Pull-up (on input)

100 WIREDOR Wired OR (N/A)

101 WIREDAND Wired AND (N/A)

110 WIREDORPULL Wired OR Pull-down

111 WIREDANDPULL Wired AND Pull-up

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• Bit 2:0 - ISC[2:0]: Input/Sense Configuration

These bits set the input and sense configuration on pin n according to Table 13-5. The sense

configuration decides how the pin can trigger port interrupts and events. When the input buffer is

not disabled, the schmitt triggered input is sampled (synchronized) and can be read in the IN

Note: 1. A low pin value will not generate events, and a high pin value will continuously generate

events.

2. Only Port A - F supports the input buffer disable option.

13.15 Register Description – Multiport Configuration

13.15.1 MPCMASK - Multi-pin Configuration Mask Register

• Bit 7:0 - MPCMASK[7:0]: Multi-pin Configuration Mask

The MPCMASK register enables several pins in a port to be configured at the same time. Writing

a one to bit n allows that pin to be part of the multi-pin configuration. When a pin configuration is

written to one of the PINnCTRL registers of the port, that value is written to all the PINnCTRL

registers of the pins matching the bit pattern in the MPCMASK register for that port. It is not nec-

essary to write to one of the registers that is set by the MPCMASK register. The MPCMASK

13.15.2 VPCTRLA - Virtual Port-map Control Register A

Table 13-5. Input/Sense Configuration

ISC[2:0] Group Configuration Description

000 BOTHEDGES Sense both edges

001 RISING Sense rising edge

010 FALLING Sense falling edge

011 LEVEL Sense low level(1)

100 Reserved

101 Reserved

110 Reserved

111 INTPUT_DISABLE Input buffer disabled(2)

Bit 76543210

+0x00 MPCMASK[7:0] MPCMASK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x02 VP1MAP[3:0] VP0MAP[3:0] VPCTRLA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 7:4 - VP1MAP: Virtual Port 1 Mapping

These bits decide which ports should be mapped to Virtual Port 1. The registers DIR, OUT, IN

and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the

actual port registers. See Table 13-6 for configuration.

• Bit 3:0 - VP0MAP: Virtual Port 0 Mapping

These bits decide which ports should be mapped to Virtual Port 0. The registers DIR, OUT, IN

and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the

actual port registers. See Table 13-6 for configuration.

13.15.3 VPCTRLB - Virtual Port-map Control Register B

• Bit 7:4 - VP3MAP: Virtual Port 3 Mapping

These bits decide which ports should be mapped to Virtual Port 3. The registers DIR, OUT, IN

and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the

actual port registers. See Table 13-6 for configuration.

• Bit 3:0 - VP2MAP: Virtual Port 2 Mapping

These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN

and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the

actual port registers. See Table 13-6 for configuration.

Bit 76543210

+0x03 VP3MAP[3:0] VP2MAP[3:0] VPCTRLB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 13-6. Virtual Port mapping.

VPnMAP[3:0] Group Configuration Description

0000 PORTA PORTA mapped to virtual Port n

0001 PORTB PORTB mapped to virtual Port n

0010 PORTC PORTC mapped to virtual Port n

0011 PORTD PORTD mapped to virtual Port n

0100 PORTE PORTE mapped to virtual Port n

0101 PORTF PORTF mapped to virtual Port n

0110 PORTG PORTG mapped to virtual Port n

0111 PORTH PORTH mapped to virtual Port n

1000 PORTJ PORTJ mapped to virtual Port n

1001 PORTK PORTK mapped to virtual Port n

1010 PORTL PORTL mapped to virtual Port n

1011 PORTM PORTM mapped to virtual Port n

1100 PORTN PORTN mapped to virtual Port n

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13.15.4 CLKEVOUT - Clock and Event Out Register

• Bit 7:6 - Reserved

These bits are reserved and will always be read as one. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 5:4 - EVOUT[1:0] - Event Output Port

These bits decide which port the Event Channel 0 from the Event System should be output to.

Pin 7 on the selected port is always used, and the CLKOUT bits must be set different from

EVOUT. The pin must be configured as an output pin for the Signaling Event to be available on

the pin.

Table 13-7 on page 145 shows the possible configurations.

• Bits 3:2 - Reserved

These bits are reserved and will always be read as one. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1:0 - CLKOUT[1:0] - Clock Output Port

These bits decide which port the Peripheral Clock should be output to. Pin 7 on the selected port

is always used. The Clock output setting, will override the Event output setting, thus if both are

enabled on the same port pin, the Peripheral Clock will be visible. The pin must be configured as

an output pin for the Clock to be available on the pin.

Table 13-8 on page 146 shows the possible configurations.

1101 PORTP PORTP mapped to virtual Port n

1110 PORTQ PORTQ mapped to virtual Port n

1111 PORTR PORTR mapped to virtual Port n

Table 13-6. Virtual Port mapping. (Continued)

VPnMAP[3:0] Group Configuration Description

Bit 76543210

+0x04 - - EVOUT[1:0] - - CLKOUT[1:0] CLKEVOUT

Read/Write R R R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 13-7. Event Channel 0 output configurations

EVOUT[1:0] Group Configuration Description

00 OFF Event out disabled

01 PC7 Event Channel 0 output on Port C pin 7

10 PD7 Event Channel 0 output on Port D pin 7

11 PE7 Event Channel 0 output on Port E pin 7

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13.16 Register Description – Virtual Port

13.16.1 DIR - Data Direction

• Bit 7:0 - DIR[7:0]: Data Direction Register

This register sets the data direction for the individual pins in the port mapped by "VPCTRLA -

Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map Control Register B". When

a port is mapped as virtual, accessing this register is identical to accessing the actual DIR regis-

ter for the port.

13.16.2 OUT - Data Output Value

• Bit 7:0 - OUT[7:0]: Data Output value

This register sets the data output value for the individual pins in the port mapped by "VPCTRLA

- Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map Control Register B".

When a port is mapped as virtual, accessing this register is identical to accessing the actual

OUT register for the port.

13.16.3 IN - Data Input Value

Table 13-8. Clock output configurations

CLKOUT[1:0] Group Configuration Description

00 OFF Clock out disabled

01 PC7 Clock output on Port C pin 7

10 PD7 Clock output on Port D pin 7

11 PE7 Clock output on Port E pin 7

Bit 76543210

+0x00 DIR[7:0] DIR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x01 OUT[7:0] OUT

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x02 IN[7:0] IN

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 7:0 - IN[7:0]: Data Input Value

This register shows the value present on the pins if the digital input buffer is enabled. The config-

uration of "VPCTRLA - Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map

Control Register B" decides the value in the register. When a port is mapped as virtual, access-

ing this register is identical to accessing the actual IN register for the port.

13.16.4 INTFLAGS - Interrupt Flag Register

• Bit 7:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1:0 - INTnIF: Interrupt n Flag

The INTnIF flag is set when a pin change according to the pin's input sense configuration

occurs, and the pin is set as source for port interrupt n. Writing a one to this flag's bit location will

clear the flag. For enabling and executing the interrupt refer to the Interrupt Level description.

The configuration of "VPCTRLA - Virtual Port-map Control Register A" or "VPCTRLB - Virtual

Port-map Control Register B" decides which the flags mapped. When a port is mapped as vir-

tual, accessing this register is identical to accessing the actual INTFLAGS register for the port.

Bit 76543210

+0x03 - - - - - - INT1IF INT0IF INTFLAGS

Read/WriteRRRRRRR/WR/W

Initial Value00000000

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13.17 Register Summary – Ports

13.18 Register Summary – Port Configuration

13.19 Register Summary – Virtual Ports

13.20 Interrupt vector Summary - Ports

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 DIR DIR[7:0] 138

+0x01 DIRSET DIRSET[7:0] 138

+0x02 DIRCLR DIRCLR[7:0] 139

+0x03 DIRTGL DIRTGL[7:0] 139

+0x04 OUT OUT[7:0] 139

+0x05 OUTSET OUTSET[7:0] 139

+0x06 OUTCLR OUTCLR[7:0] 140

+0x07 OUTTGL OUTTGL[7:0] 140

+0x08 IN IN[7:0] 140

+0x09 INTCTRL - - - - INT1LVL[1:0] INT0LVL[1:0] 141

+0x0A INT0MASK INT0MSK[7:0] 141

+0x0B INT1MASK INT1MSK[7:0] 141

+0x0C INTFLAGS - - - - - - INT1IF INT0IF 142

+0x0D Reserved - - - - - - - -

+0x0E Reserved - - - - - - - -

+0x0F Reserved - - - - - - - -

+0x10 PIN0CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x11 PIN1CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x12 PIN2CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x13 PIN3CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x14 PIN4CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x15 PIN5CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x16 PIN6CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x17 PIN7CTRL SRLEN INVEN OPC[2:0] ISC[2:0] 142

+0x18 Reserved - - - - - - - -

+0x19 Reserved - - - - - - - -

+0x1A Reserved - - - - - - - -

+0x1B Reserved - - - - - - - -

+0x1C Reserved - - - - - - - -

+0x1D Reserved - - - - - - - -

+0x1E Reserved - - - - - - - -

+0x1F Reserved - - - - - - - -

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 MPCMASK MPCMASK[7:0] 143

+0x01 Reserved - - - - - - - -

+0x02 VPCTRLA VP1MAP[3:0] VP0MAP[3:0] 143

+0x03 VPCTRLB VP3MAP[3:0] VP2MAP[3:0] 144

+0x04 CLKEVOUT EVOUT[1:0] CLKOUT[1:0] 145

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 DIR DIR[7:0] 146

+0x01 OUT OUT[7:0] 146

+0x02 IN IN[7:0] 146

+0x03 INTFLAGS - - - - - - INT1IF INT0IF 147

Table 13-9. Ports Interrupt vectors and their word offset address

Offset Source Interrupt Description

0x00 INT0_vect Port Interrupt vector 0 offset

0x02 INT1_vect Port Interrupt vector 1 offset

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14. TC - 16-bit Timer/Counter

14.1 Features

•16-bit Timer/Counter

•Double Buffered Timer Period Setting

•Up to 4 Combined Compare or Capture (CC) Channels (A, B, C, and D)

•All Compare or Capture Channels are Double Buffered

•Waveform Generation:

– Single Slope Pulse Width Modulation

– Dual Slope Pulse Width Modulation

– Frequency Generation

•Input Capture:

– Input Capture with Noise Cancelling

– Frequency capture

– Pulse width capture

•32-bit input capture Direction Control

•Timer Overflow and Timer Error Interrupts / Events

•One Compare Match or Capture Interrupt / Event per CC Channel

•Supports DMA Operation

•Hi-Res- Hi-Resolution Extension

– Increases PWM/FRQ Resolution by 2-bits (4x)

•AWeX - Advanced Waveform Extension

– 4 Dead-Time Insertion (DT) Units with separate high- and low-side settings

– Event controlled fault protection

– Single channel multiple output operation

– Pattern Generation

14.2 Overview

XMEGA has a set of high-end and very flexible 16-bit Timer/Counters (TC). Their basic capabili-

ties include accurate program execution timing, frequency and waveform generation, event

management, and time measurement of digital signals. The Hi-Resolution Extension (Hi-Res)

and Advanced Waveform Extension (AWeX) can be used together with a Timer/Counter to ease

implementation of more advanced and specialized frequency and waveform generation

features.

A block diagram of the 16-bit Timer/Counter with extensions and closely related peripheral mod-

ules (in grey) is shown in Figure 14-1 on page 150.

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Figure 14-1. 16-bit Timer/Counter and Closely Related Peripheral

The Timer/Counter consists of a Base Counter and a set of Compare or Capture (CC) channels.

The Base Counter can be used to count clock cycles or events. It has direction control and

period setting that can be used for timing. The CC channels can be used together with the Base

Counter to do compare match control, waveform generation (FRQ or PWM) or various input cap-

ture operations.

Compare and capture cannot be done at the same time, i.e. a single Timer/Counter cannot

simultaneously perform both waveform generation and capture operation. When used for com-

pare operations, the CC channels is referred to as compare channels. When used for capture

operations, the CC channels are referred to as capture channels.

The Timer/Counter comes in two versions: Timer/Counter 0 that has four CC channels, and

Timer/Counter 1 that has two CC channels. Hence, all registers and register bits that are related

to CC channel 3 and CC channel 4 will only exist in Timer/Counter 0.

All Timer/Counter units are connected to the common peripheral clock prescaler, the Event Sys-

tem, and their corresponding general purpose I/O port.

Some of the Timer/Counters will have Extensions. The function of the Timer/Counter Extensions

can only be performed by these Timers. The Advanced Waveform Extension (AWeX) can be

used for Dead Time Insertion, Pattern Generation and Fault Protection. The AWeX Extension is

only available for Timer/Counter 0.

Waveform outputs from a Timer/Counter can optionally be passed through to a Hi-Resolution

(Hi-Res) Extension before forwarded to the port. This extension, running at up to four times the

Peripheral Clock frequency, to enhance the resolution by four times. All Timer/Counters will

have the Hi-Res Extention.

AWeX

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

Waveform

Generation

Buffer

Comparator

Hi-Res

Fault

Protection

Capture

Control

Base Counter

Counter Control Logic

Timer Period

Prescaler

DTI

Dead-Time

Insertion

Pattern

Generation

clkPER4

PORTS

Event

System

clkPER

Timer/Counter

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14.2.1 Definitions

The following definitions are used extensively throughout the Timer/Counter documentation:

In general the term Timer is used when the Timer/Counter clock control is handled by an internal

source and the term Counter is used if the clock is given externally (from an event).

14.3 Block Diagram

Figure 14-2 on page 152 shows a detailed block diagram of the Timer/Counter without the

extensions.

Table 14-1. Timer/Counter definitions

Name Description

BOTTOM The Counter reaches the BOTTOM when it becomes zero.

MAX The Counter reaches MAXimum when it becomes all ones.

TOP

The Counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be equal to the period (PER) or the Compare

Channel A (CCA) register setting. This is selected by the Waveform Generator Mode.

UPDATE The Timer/Counter signalizes an update when it reaches BOTTOM or TOP

dependent of the Waveform Generator Mode.

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Figure 14-2. Timer/Counter Block Diagram

The Counter Register (CNT), the Period Registers w/buffer (PER and PERBUF), and the com-

pare and Capture registers w/buffers (CCx and CCxBUF) are 16-bit registers.

During normal operation the counter value is continuously compared to zero and the period

(PER) value to determine whether the counter has reached TOP or BOTTOM.

The counter value is also compared to the CCx registers. These comparators can be used to

generate interrupt requests or request DMA transactions. They also generate events for the

Event System. The waveform generator modes use the comparators to set the waveform period

or pulse width.

A prescaled peripheral clock and events from the Event System can be used for controlling the

counter. The Event System is also used as source to the input capture. Combined with the

Quadrature Decoding functionality in the Event System QDEC, the Timer/Counter can be used

for high speed Quadrature Decoding.

Base Counter

Bus Bridge

Compare/Capture

(x = {A,B,C ,D} )

Counter

CCx

CCxBUF

Waveform

Generation

PERBUF

PER

CNT

= 0

"count"

"clear"

"direction"

"load" Control Logic

EVSEL

Event Select

CKSEL

Clock Select

OVF/UNF

(INT/DMA Req.)

ERRIF

(INT Req.)

TOP

"match" CCxIF

(INT/DMA

Req.)

Control Logic

"capture"

I/O Data Bus (16-bit)

I/O Da ta B u s (8 -b it)

"ev"

UPDATE

BOTTOM

TEMP CTRL

A B D

OCx Out

C E INTCTRL

A BG INTFLAGS

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14.4 Clock and Event Sources

The Timer/Counter can be clocked from the Peripheral Clock (clkPER) and from the Event Sys-

tem, and Figure 14-3 shows the clock and event selection logic.

Figure 14-3. Clock and Event Selection

The Peripheral Clock is fed into the Common Prescaler (common for all Timer/Counters in a

device). A selection of the prescaler outputs is directly available for the Timer/Counter. In addi-

tion the whole range from 1 to 215 times prescaling is available through the Event System.

Each Timer/Counter has separate clock selection (CLKSEL), to select one of the prescaler out-

puts directly or an event channel as the Counter (CNT) input. This is referred to as Normal

Operation for the Counter, for details refer to ”Normal Operation” on page 155. By using the

Event System, any event source such as an external clock signal on any I/O pin can be used as

clock input.

In addition the Timer/Counter can be controlled via the Event System. The Event Selection

(EVSEL) and Event Action (EVACT) settings can be used to trigger an event action from one or

more events. This is referred to as Event Action Controlled Operation for the Counter, for details

refer to ”Event Action Controlled Operation” on page 155. When Event Action Controlled Opera-

tion is used, the clock selection must be set to us an event channel as the Counter input.

By default no clock input is selected and the Timer/Counter is not running (OFF state).

14.5 Double Buffering

The Period Register and the CC registers are all double buffered. Each buffer registers have an

associated Buffer Valid (BV) flag, which indicate that the buffer contains a valid, i.e. a new value

that is to be copied into the belonging period or compare register. For the Period register and for

the CC channels when used for compare operation, the Buffer Valid flag is set when data is writ-

ten to the buffer register and cleared on UPDATE condition. This is shown for a compare

clkPER /

2{0,...,15}

CLKSEL

CNT

EVACT

clk /

{1,2,4,8,64,256,1024}

Common

Prescaler

clkPER

event channels

(Encoding)

Event Sys tem

EVSEL

events

Control Logic

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Figure 14-4. Period and Compare Double Buffering

When the CC channels is used for capture operation a similar Double buffering mechanism is

used, but the Buffer Valid flag is set on the capture event as shown in Figure 14-5. For capture

the buffer and the corresponding CCx register acts like a FIFO. When the CC register is empty

or read, any contents in the buffer is passed to the CC register. The Buffer valid flag is passed to

the CCx Interrupt Flag (IF) which is them set and the optional interrupt is generated.

Figure 14-5. Capture Double Buffering

Both the CCx and CCxBUF registers are available in the I/O register address map. This allows

initialization and bypassing of the buffer register, and the double buffering feature.

14.6 Counter Operation

Dependent of the mode of operation, the Counter is cleared, reloaded, incremented, or decre-

mented at each Timer/Counter clock input.

BV CCxBUF

CCx

UPDATE EN

I/O Bus (16-bit)

"write enable"

"data"

CNT

"match"

I/O Bus (16-bit)

"capture"

CNT

CCxBUF

CCx

"INT/DM A

request"

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14.6.1 Normal Operation

In Normal Operation the Counter will count in the direction set by the Direction (DIR) bit for each

clock until it reaches TOP or BOTTOM. When TOP is reached when up-counting, the counter

will be set to zero when the next clock is given. When down-counting the Counter is reloaded

with Period Register value when BOTTOM is reached.

Figure 14-6. Normal Mode of Operation

As shown in Figure 14-6 changing the counter value while the counter is running is possible. The

write access has higher priority than count, clear, or reload and will be immediate. The direction

of the Counter can also be changed during normal operation.

Normal operation must be used when using the counter as timer base for the capture channels.

14.6.2 Event Action Controlled Operation

The Event Selection and Event Action settings can be used to control the Counter from the

Event System. For the Counter the event actions can be selected to:

• Event system controlled Up/Down counting.

• Event system controlled Quadrature Decode counting.

14.6.3 32-bit Operation

Two Timer/Counters can be used together to enable 32-bit counter operation. By using two

Timer/Counters the overflow event from one Timer/Counter (least significant timer) can be

routed via the Event System and used as clock input for another Timer/Counter (most significant

timer).

14.6.4 Changing the Period

The Counter period is changed by writing a new TOP value to the Period Register. If double

buffering is not used, any period update is immediate as shown in Figure 14-7 on page 156.

CNT

BOT

MAX

"update"

TOP

CNT written

DIR

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Figure 14-7. Changing The Period without Buffering

When double buffering is used, the buffer can be written at any time, but the Period Register is

always updated on the “update” condition as shown in Figure 14-8. This prevents wraparound

and generation of odd waveforms.

Figure 14-8. Changing Period using Buffering

14.7 Capture Channel

The CC channels can be used as capture channel to capture external events and give them a

time-stamp indicating time of occurrence. To use capture the Counter must be set in normal

operation.

Events are used to trigger the capture, i.e any events from the Event System including pin

change from any pin can trigger a capture operation. The Event Source Select setting, selects

the event channel that will trigger CC channel A, and the following event channels will then trig-

ger events on the following CC channels if configured. For instance setting the Event Source

Select to event channel 2 will result in CC channel A being connected to Event Channel 2, CC

channel B to event channel 3 and so on.

CNT

MAX

New T O P w ritten to

PE R th a t is h igh e r

than cu rren t C NT

Counter Wraparound

New TOP written to

PE R tha t is lo we r

than cu rren t C N T

"update"

"write"

BOT

CNT

MAX

New Period written to

PERB U F th a t is h igh er

than current CNT

New Period written to

PER B U F th a t is lo w e r

than cu rrent C N T

"update"

"write"

New PER is updated

with PERBUF value.

BOT

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Event Source Selection for capture operation

The Event Action setting in the Timer/Counter will determine the type of capture that is done.

The CC channel to use must be enabled individually before capture can be done. When the cap-

ture condition occur, the Timer/Counter will time-stamp the event by copying the current value in

the Count register into the enabled CC channel register.

When an I/O pin is used as event source for the Capture, the pin must be configured for edge

sensing. For details on sense configuration on I/O pins, refer to ”Input Sense Configuration” on

page 134. If the Period register value is set lower than 0x8000, the polarity of the I/O pin edge

will be stored in the Most Significant Bit (MSB) of the Capture register after a Capture. If the

MSB of the Capture register is zero, a falling edge generated the Capture. If the MSB is one, a

rising edge generated the Capture.

Three different types of capture are available.

14.7.1 Input Capture

Selecting the input capture event action, makes the enabled capture channel perform an input

capture on any event. The interrupt flags will be set and indicate that there is a valid capture

result in the corresponding CC register. Equally the buffer valid flags indicates valid data in the

buffer registers. Refer to ”Double Buffering” on page 153 for more details on capture double

buffering.

The counter will continuously count for BOTTOM to TOP, then restart on BOTTOM as shown in

Figure 14-9. The figure also shows four capture events for one capture channel.

Figure 14-9. Input capture timing

Event System

CH0MUX

CH1MUX

CH7MUX Rotate

Event channel 7

Event Source Selection

CCA capture

CCB capture

CCC capture

CCD capture

Event channel 0

Event channel 1

events

CNT

TOP

BOT

Capture 0 Capture 1 Capture 2 Capture 3

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14.7.2 Frequency Capture

Selecting the frequency capture event action, makes the enabled capture channel perform an

input capture and restart on positive edge events. This enables Timer/Counter to use capture to

measure the period or frequency of a signal directly. The capture result will be the time, T, from

the previous Timer/Counter restart and until the event occurred. This can be used to calculate

the frequency, f, of the signal:

Figure 14-10 on page 158 shows an example where the Period is measured twice for an exter-

nal signal.

Figure 14-10. Frequency capture of an external signal

Since all capture channels uses the same Counter (CNT), only one capture channels must be

enabled at a time. If two capture channels are used with different source, the Counter will be

restarted on positive edge events from both input sources, and the result from the input capture

will have no meaning.

14.7.3 Pulse-width Capture

Selecting the pulse-width measure event action makes the enabled compare channel perform

the input capture action on falling edge events and the restart action on rising edge events. The

counter will then start at zero at every start of a pulse and the input capture will be performed at

the end of the pulse. The event source must be an I/O pin and the sense configuration for the pin

must be set up to generate an event on both edges. Figure 14-11 on page 159 shows and exam-

ple where the pulse width is measured twice for an external signal.

---=

Period (T)

external signal

events

CNT

MAX

BOT

"capture"

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Figure 14-11. Pulse-width capture of external signal.

14.7.4 32-bit Input Capture

Two Timer/Counters can be used together to enable true 32-bit Input Capture. In a typical 32-bit

Input Capture setup the overflow event of the least significant timer is connected via the Event

System and used as clock input for the most significant timer.

Since all events are pipelined, the most significant timer will be updated one peripheral clock

period after an overflow occurs for the least significant timer. To compensate for this delay the

capture event for the most significant timer must be equally delayed by setting the Event Delay

bit for this timer.

14.7.5 Capture Overflow

The Timer/Counter can detect buffer overflow on any of the Input Capture Channels. In the case

where both the Buffer Valid flag and Capture Interrupt Flag are set, and a new capture event is

detected there is nowhere to store the new time-stamp. If a buffer overflow is detected the new

value is rejected, the Error Interrupt Flag is set and the optional interrupt is generated.

14.8 Compare Channel

Each compare channel continuously compares the counter value (CNT) with the CCx register. If

CNT equals CCx the comparator signals a match. The match will set the CC channel's interrupt

flag at the next timer clock cycle, and the event and optional interrupt is generated.

The compare buffer register provides double buffer capability equivalent to the period buffer.

The double buffering synchronizes the update of the CCx register with the buffer value to either

the TOP or BOTTOM of the counting sequence according to the UPDATE condition signal from

the Timer/Counter control logic. The synchronization prevents the occurrence of odd-length,

non-symmetrical PWM/FRQ pulses, thereby making the output glitch-free.

Pulsewitdh (tp)

external signal

events

CNT

MAX

BOT

"capture"

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14.8.1 Waveform Generation

The compare channels can be used for waveform generation on the corresponding port pins. To

make the waveform visible on the connected port pin, the following requirements must be

fulfilled:

1. A waveform generation mode must be selected.

2. Event actions must be disabled.

3. The CC channels to be used must be enabled. This will override the corresponding port

pin output register.

4. The direction for the associated port pin must be set to output.

Inverted waveform output can be achieved by setting the invert output bit for the port pin.

14.8.2 Frequency (FRQ) Waveform Generation

For frequency generation the period time (T) is controlled by the CCA register instead of PER,

which in this case is not in use. The Waveform Generation (WG) output is toggled on each com-

pare match between the CNT and CCA registers as shown in Figure 14-12 on page 160.

Figure 14-12. Frequency Waveform Generation

The waveform generated will have a maximum frequency of half of the Peripheral clock fre-

quency (fPER) when CCA is set to zero (0x0000). This also applies when using the Hi-Res

Extension since this only increase the resolution and not the frequency. The waveform fre-

quency (fFRQ)is defined by the following equation:

where N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).

14.8.3 Single Slope PWM Generation

For single slope PWM generation, the Period (T) is controlled by the PER, while CCx registers

control the duty cycle of the WG output. Figure 14-13 shows how the counter counts from BOT-

TOM to TOP then restarts from BOTTOM. The waveform generator (WG) output is set on the

compare match between the CNT and CCx registers, and cleared at TOP.

CNT

MAX

"update"

TOP

CNT writtenDirection Change

Period (T)

BOT

WG Output

fFRQ fPER

2NCCA+1()

--------------------------------=

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Figure 14-13. Single slope Pulse Width Modulation

The PER register defines the PWM resolution. The minimum resolution is 2-bit (PER=0x0003),

and maximum resolution is 16-bit (PER=MAX).

The following equation can be used for calculate the exact resolution for single-slope PWM

(RPWM_SS):

The single slow PWM frequency (fPWM_SS) depends on the period setting (PER) and the Periph-

eral clock frequency (fPER), and can be calculated by the following equation:

where N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).

14.8.4 Dual Slope PWM

For dual slope PWM generation, the Period (T) is controlled by the PER, while CCx registers

control the duty cycle of the WG output. Figure 14-14 shows how for dual slope PWM the Coun-

ter counts repeatedly from BOTTOM to TOP, and then from TOP to BOTTOM. The waveform

generator output is set on BOTTOM, cleared on compare match when upcounting and set on

compare match when down counting.

CNT

MAX

TOP

Period (T) "match"

BOT

WG Output

CCx=BOT

CCx

CCx=TOP "update"

RPWM_SS

PER 1+()log

2()log

-----------------------------------=

fPWM_SS

fPER

NPER 1+()

-------------------------------=

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Figure 14-14. Dual-slope Pulse Width Modulation

Using dual-slope PWM result in a lower maximum operation frequency compared to the single-

slope PWM operation.

The period register (PER) defines the PWM resolution. The minimum resolution is 2-bit

(PER=0x0003), and maximum resolution is 16-bit (PER=MAX).

The following equation can be used for calculate the exact resolution for dual-slope PWM

(RPWM_DS):

The PWM frequency depends on the period setting (PER) and the Peripheral Clock frequency

(fPER), and can be calculated by the following equation:

N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).

14.8.5 Port override for Waveform Generation

To make the waveform generation available on the port pins the corresponding port pin direction

must be set as output. The Timer/Counter will override the port pin values when the CC channel

is enabled (CCENx) and a waveform generation mode is selected.

Figure 14-15 on page 163 shows the port override for Timer/Counter 0 and 1. For Timer/Counter

1, CC channel A to D will override port pin 0 to 3 output value (OUTxn) on the corresponding

port pin (Pxn). For Timer/Counter 1, CC channel A and B will override port pin 4 and 5. Enabling

inverted I/O on the port pin (INVENxn) inverts the corresponding WG output.

CNT

MAX

TOP

Period (T)

BOT

WG Output

CCx=BOT

CCx

CCx=TOP "match"

"update"

RPWM_DS

PER 1+()log

2()log

-----------------------------------=

fPWM_DS

fPER

2NPER

--------------------=

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Figure 14-15. Port override for Timer/Counter 0 and 1

14.9 Interrupts and events

The T/C can generate both interrupts and events. The Counter can generate an interrupt on

overflow/underflow, and each CC channel has a separate interrupt that is used for compare or

capture. In addition the T/C can generate an error interrupt if any of the CC channels is used for

capture and a buffer overflow condition occurs on a capture channel.

Event will be generated for all conditions that can generate interrupts. For details on event gen-

eration and available events refer to ”Event System” on page 65.

OUTx0

CCENA INVENx0

OUTx1

CCENB INVENx1

Px0

Px1

OC0A

OC0B

OUTx2

CCENC INVENx2

OUTx3

CCEND INVENx3

Px2

Px3

OC0C

OC0D

OUTx4

CCENA INVENx4

OUTx5

CCENB INVENx5

Px4

Px5

OC1A

OC1B

WG 0A

WG 0B

WG 0C

WG 0D

WG 1A

WG 1B

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14.10 DMA Support.

The interrupt flags can be used to trigger DMA transactions. Table 14-2 on page 164 lists the

transfer triggers available from the T/C, and the DMA action that will clear the transfer trigger.

For more details on using DMA refer to ”DMA - Direct Memory Access Controller” on page 49.

14.11 Timer/Counter Commands

A set of commands can be given to the Timer/Counter by software to immediately change the

state of the module. These commands give direct control of the Update, Restart, and Reset

signals.

An update command has the same effect as when an update condition occurs. The update com-

mand is ignored if the Lock Update bit is set.

The software can force a restart of the current waveform period by issuing a restart command. In

this case the Counter, direction, and all compare outputs are set to zero.

A reset command will set all Timer/Counter registers to their initial values. A reset can only be

given when the Timer/Counter is not running (OFF).

Table 14-2. DMA Request Sources

Request Acknowledge Comment

OV/UNFIF DMA Controller writes to CNT

DMA Controller writes to PER

DMA Controller writes to PERBUF

ERRIF N/A

CCxIF DMA Controller access of CCx

DMA Controller access of CCxBUF

Input Capture operation

Output Compare operation

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14.12 Register Description

14.12.1 CTRLA - Control Register A

• Bit 7:4 - Reserved bits

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:0 - CLKSEL[3:0]: Clock Select

These bits select clock source for the Timer/Counter according to Table 14-3.

CLKSEL=0001 must be set to ensure a correct output from the waveform generator when the

Hi-Res extension is enabled.

14.12.2 CTRLB - Control Register B

• Bit 7:4 – CCxEN: Compare or Capture Enable

Setting these bits in FRQ or PWM waveform generation mode of operation will override of the

port output register for the corresponding OCn output pin.

When input capture operation is selected the CCxEN bits enables the capture operation for the

corresponding CC channel.

Bit 76543210

+0x00 ---- CLKSEL[3:0] CTRLA

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000000

Table 14-3. Clock Select

CLKSEL[3:0] Group Configuration Description

0000 OFF None (i.e, Timer/Counter in ‘OFF’ state)

0001 DIV1 Prescaler: clk

0010 DIV2 Prescaler: clk/2

0011 DIV4 Prescaler: clk/4

0100 DIV8 Prescaler: clk/8

0101 DIV64 Prescaler: clk/64

0110 DIV256 Prescaler: clk/256

0111 DIV1024 Prescaler: clk/1024

1xxx EVCHn Event channel n, n= [0,...,7]

Bit 76543210

+0x01 CCDEN CCCEN CCBEN CCAEN - WGMODE[2:0] CTRLB

Read/Write R/W R/W R/W R/W R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 3 – Reserved

This bit is unused and reserved for future use. For compatibility with future devices, always write

this bit to zero when this register is written.

• Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode

These bits select the Waveform Generation Mode, and control the counting sequence of the

Counter, the TOP value, the UPDATE condition, the Interrupt/event condition, and type of wave-

form that is generated, according to Table 14-4 on page 166.

No waveform generation is performed in normal mode of operation. For all other modes the

result from the waveform generator will only be directed to the port pins if the corresponding

CCxEN bit has been set to enable this. The port pin direction must be set as output.

14.12.3 CTRLC - Control Register C

• Bit 7:4 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:0 – CMPx: Compare Output Value n

These bits allow direct access to the Waveform Generator's output compare value when the

Timer/Counter is set in “OFF” state. This is used to set or clear the WG output value when the

Timer/Counter is not running.

Table 14-4. Timer Waveform Generation Mode

WGMODE[2:0]

Group

Configuration

Mode of

operation Top Update OVFIF/Event

000 NORMAL Normal PER TOP TOP

001 FRQ FRQ CCA TOP TOP

010 Reserved - - -

011 SS Single Slope

PWM PER BOTTOM BOTTOM

100 Reserved - - -

101 DS_T Dual Slope PWM PER BOTTOM TOP

110 DS_TB Dual Slope PWM PER BOTTOM TOP and BOTTOM

111 DS_B Dual Slope PWM PER BOTTOM BOTTOM

Bit 76543210

+0x02 - - - - CMPD CMPC CMPB CMPA CTRLC

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000000

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14.12.4 CTRLD - Control Register D

• Bit 7:5 – EVACT[2:0]: Event Action

These bits define the Event Action the timer will perform on an event according to Table 14-5 on

page 167.

The EVSEL setting will decide which event source or sources that have the control in this case.

Selecting the any of the capture event action changes the behavior of the CCx registers and

related status and control bits to be used as for capture. The error status flag (ERRIF) will in this

configuration indicate a buffer overflow.

• Bit 4 – EVDLY: Timer Delay Event

When this bit is set, the selected event source is delayed by one peripheral clock cycle. This fea-

ture is intended for 32-bit input capture operation. Adding the event delay is necessary for

compensating for the carry propagation delay that is inserted when cascading two counters via

the Event System.

• Bit 3:0 – EVSEL[3:0]:Timer Event Source Select

These bits select the event channel source for the Timer/Counter. For the selected event chan-

nel to have any effect the Event Action bits (EVACT) must be set according to Table 14-6. When

the Event Action is set to capture operation, the selected event channel n will be the event chan-

nel source for CC channel A, and event channel (n+1)%8, (n+2)%8 and (n+3)%8 will be the

event channel source for CC channel B, C and D.

Bit 76543210

+0x03 EVACT[2:0] EVDLY EVSEL[3:0] CTRLD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 14-5. Timer Event Action Selection

EVACT[2:0] Group Configuration Event Action

000 OFF None

001 CAPT Input Capture

010 UPDOWN Externally Controlled Up/ Down Count

011 QDEC Quadrature decode

100 RESTART Restart waveform period

101 FRQ Frequency Capture

110 PW Pulse Width Capture

111 Reserved

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14.12.5 CTRLE - Control Register E

• Bit 7:1 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 0 - BYTEM: Byte Mode:

Enabling the Byte Mode, sets the Timer/Counter in Byte (8-bit) Mode. Setting this bit will disable

the update of the temporary register (TEMP) when any of the 16-bit Timer/Counter registers are

accessed. In addition the upper byte of the counter (CNT) register will be set to zero after each

counter clock.

14.12.6 INTCTRLA - Interrupt Enable Register A

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

Table 14-6. Timer Event Source Selection

EVSEL[3:0] Group Configuration Event Source

0000 OFF None

0001 Reserved

0010 Reserved

0011 Reserved

0100 Reserved

0101 Reserved

0110 Reserved

0111 Reserved

1xxx CHn Event channel n, n={0,...,7}

Bit 76543210

+0x04 -------BYTEMCTRLE

Read/WriteRRRRRRRR/W

Initial Value00000000

Bit 76543210

+0x06 ----ERRINTLVL[1:0]OVFINTLVL[1:0]INTCTRLA

Read/WriteRRRRR/WR/WR/WR/W

Initial Value00000000

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• Bit 3:2 - ERRINTLVL[1:0]:Timer Error Interrupt Level

These bits enable the Timer Error Interrupt and select the interrupt level as described in ”Inter-

rupts and Programmable Multi-level Interrupt Controller” on page 123.

• Bit 1:0 - OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level

These bits enable the Timer Overflow/Underflow Interrupt and select the interrupt level as

described in ”Interrupts and Programmable Multi-level Interrupt Controller” on page 123.

14.12.7 INTCTRLB - Interrupt Enable Register B

• Bit 7:0 - CCxINTLVL[1:0] - Compare or Capture x Interrupt Level:

These bits enable the Timer Compare or Capture Interrupt and select the interrupt level as

described in ”Interrupts and Programmable Multi-level Interrupt Controller” on page 123.

14.12.8 CTRLFCLR/CTRLFSET - Control Register F Clear/Set

This register is mapped into two I/O memory locations, one for clearing (CTRLxCLR) and one for

setting the register bits (CTRLxSET) when written. Both memory locations yield the same result

when read.

The individual status bit can be set by writing a one to its bit location in CTRLxSET, and cleared

by writing a one to its bit location in CTRLxCLR. This each bit to be set or cleared without using

of a Read-Modify-Write operation on a single register.

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

Bit 76543210

+0x07 CCDINTLVL[1:0] CCCINTLVL[1:0] CCBINTLVL[1:0] CCAINTLVL[1:0] INTCTRLB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x08 - - - - CMD[1:0] LUPD DIR CTRLFCLR

Read/WriteRRRRRRR/WR/W

Initial Value00000000

Bit 76543210

+0x09 - - - - CMD[1:0] LUPD DIR CTRLFSET

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000000

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• Bit 3:2 - CMD[1:0]: Timer/Counter Command

These command bits can be used for software control of update, restart, and reset of the

Timer/Counter. The command bits are always read as zero.

• Bit 1 - LUPD: Lock Update:

When this bit is set no update of the buffered registers is performed, even though an UPDATE

condition has occurred. Locking the update ensures that all buffers, including DTI buffers, are

valid before an update is performed.

This bit has no effect when input capture operation is enabled.

• Bit 0 - DIR: Counter Direction:

When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that

the counter is in down counting (decrementing) state.

Normally this bit is controlled in hardware by the waveform generation mode, or by event

actions, but this bit can also be changed from software.

14.12.9 CTRLGCLR/CTRLGSET - Control Register G Clear/Set

Refer to section ”CTRLFCLR/CTRLFSET - Control Register F Clear/Set” on page 169 for infor-

mation on how to access this type of status register.

• Bit 7:5 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 4:1 - CCxBV: Compare or Capture x Buffer Valid

These bits are set when a new value is written to the corresponding CCxBUF register. These

bits are automatically cleared on an UPDATE condition.

Note that when input capture operation is used, this bit is set on capture event and cleared if the

corresponding CCxIF is cleared.

• Bit 0 - PERBV: Period Buffer Valid

This bit is set when a new value is written to the PERBUF register. This bit is automatically

cleared on an UPDATE condition.

Table 14-7. Command selections

CMD Group Configuration Command Action

00 NONE None

01 UPDATE Force Update

10 RESTART Force Restart

11 RESET Force Hard Reset (Ignored if T/C is not in “OFF“state)

Bit 76543210

+0x0A/ +0x0B - - - CCDBV CCCBV CCBBV CCABV PERBV CTRLGCLR/SET

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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14.12.10 INTFLAGS - Interrupt Flag Register

• Bit 7:4 - CCxIF: Compare or Capture Channel x Interrupt Flag

The Compare or Capture Interrupt Flag (CCxIF) is set on a compare match or on an input cap-

ture event on the corresponding CC channel.

For all modes of operation except for capture the CCxIF will be set when a compare match

occurs between the count register (CNT) and the corresponding compare register (CCx). The

CCxIF is automatically cleared when the corresponding interrupt vector is executed.

For input capture operation the CCxIF will be set if the corresponding compare buffer contains

valid data (i.e. when CCxBV is set). The flag will be cleared when the CCx register is read. Exe-

cuting the Interrupt Vector will in this mode of operation not clear the flag.

The flag can also be cleared by writing a one to its bit location.

The CCxIF can be used for requesting a DMA transfer. A DMA read or write access of the corre-

sponding CCx or CCxBUF will then clear the CCxIF and releases the request.

• Bit 3:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1 - ERRIF: Error Interrupt Flag

The ERRIF is set on multiple occasions depending on mode of operation.

In FRQ or PWM waveform generation mode of operation the ERRIF is set on a fault detect con-

dition from the fault protection feature in the AWeX Extention. For Timer/Counters which do not

have the AWeX extention available, this flag is never set in FRQ or PWM waveform generation

mode.

For capture operation the ERRIF is set if a buffer overflow occurs on any of the CC channels.

For event controlled QDEC operation the ERRIF is set when an incorrect index signal is given.

The ERRIF is automatically cleared when the corresponding interrupt vector is executed. The

flag can also be cleared by writing a one to its bit location.

• Bit 0 - OVFIF: Overflow/Underflow Interrupt Flag

The OVFIF is set either on a TOP (overflow) or BOTTOM (underflow) condition depending on

the WGMODE setting. The OVFIF is automatically cleared when the corresponding interrupt

vector is executed. The flag can also be cleared by writing a one to its bit location.

The OVFIF can also be used for requesting a DMA transfer. A DMA write access of CNT, PER,

or PERBUF will then clear the OVFIF bit.

14.12.11 TEMP - Temporary Register for 16-bit Access

The TEMP register is used for single cycle 16-bit access to the 16-bit Timer/Counter registers

from the CPU. The DMA controller has a separate temporary storage register. There is one com-

mon TEMP register for all the 16-bit Timer/Counter registers.

Bit 76543210

+0x0C CCDIF CCCIF CCBIF CCAIF - - ERRIF OVFIF INTFLAGS

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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For more details refer to Section 3.11 ”Accessing 16-bits Registers” on page 12.

14.12.12 CNTH - Counter Register H

The CNTH and CNTL register pair represents the 16-bit value CNT. CNT contains the 16-bit

counter value in the Timer/Counter. The CPU and DMA write access has priority over count,

clear, or reload of the counter.

For more details on reading and writing 16-bit register refer to ”Accessing 16-bits Registers” on

page 12.

• Bit 7:0 - CNT[15:8]

These bits holds the 8 MSB of the 16-bit Counter register.

14.12.13 CNTL - Counter Register L

• Bit 7:0 - CNT[7:0]

These bits holds the 8 LSB of the 16-bit Counter register.

14.12.14 PERH - Period Register H

The PERH and PERL register pair represents the 16-bit value PER. PER contains the 16-bit

TOP value in the Timer/Counter.

• Bit 7:0 - PER[15:8]

These bits holds the 8 MSB of the 16-bit Period register.

Bit 76543210

+0x0F TEMP[7:0] TEMP

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x21 CNT[15:8] CNTH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x20 CNT[7:0] CNTL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x27 PER[15:8] PERH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value11111111

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14.12.15 PERL - Period Register L

• Bit 7:0 - PER[7:0]

These bits holds the 8 LSB of the 16-bit Period register.

14.12.16 CCxH - Compare or Capture Register n H

The CCxH and CCxL register pair represents the 16-bit value CCx.

These 16-bit registers have two functions dependent of mode of operation. For capture opera-

tion these registers constitute the second buffer level and access point for the CPU and DMA.

For compare operation these registers are all continuously compared to the counter value. Nor-

mally the outputs form the comparators are then used for generating waveforms.

CCx are updated with the buffer value from the corresponding CCxBUF register when an

UPDATE condition occurs.

• Bit 7:0 - CCx[15:8]

These bits holds the 8 MSB of the 16-bit Compare or Capture register.

14.12.17 CCxL - Compare or Capture Register n L

• Bit 7:0 - CCx[7:0]

These bits holds the 8 LSB of the 16-bit Compare or Capture register.

14.12.18 PERBUFH - Timer/Counter Period Buffer H

The PERBUFH and PERBUFL register pair represents the 16-bit value PERBUF. This 16-bit

DMA will affect the PERBUFV flag.

Bit 76543210

+0x26 PER[7:0] PERL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 1

Bit 76543210

CCx[15:8] CCxH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

CCx[7:0] CCxL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 7:0 - PERBUF[15:8]

These bits holds the 8 MSB of the 16-bit Period Buffer register.

14.12.19 PERBUFL - Timer/Counter Period Buffer L

• Bit 7:0 - PERBUF[7:0]

These bits holds the 8 LSB of the 16-bit Period Buffer register.

14.12.20 CCxBUFH - Compare or Capture x Buffer Register H

The CCxBUFH and CCxBUFL register pair represents the 16-bit value CCxBUF. These 16-bit

registers serve as the buffer for the associated compare or capture registers (CCx). Accessing

any of these register using CPU or DMA will affect the corresponding CCxBV status bit.

• Bit 7:0 - CCxBUF[15:8]

These bits holds the 8 MSB of the 16-bit Compare or Capture Buffer register.

14.12.21 CCxBUFL - Compare or Capture x Buffer Register L

• Bit 7:0 - CCxBUF[7:0]

These bits holds the 8 LSB of the 16-bit Compare or Capture Buffer register.

Bit 76543210

+0x37 PERBUF[15:8] PERBUFH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 1

Bit 76543210

+0x36 PERBUF[7:0] PERBUFL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value11111111

Bit 76543210

CCxBUF[15:8] CCxBUFH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

CCxBUFx[7:0] CCxBUFL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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14.13 Register Summary

14.14 Interrupt Vector Summary

Note: 1. Only available on Timer/Counter with 4 Compare or Capture channels 16-bit.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRLA CLKSEL[3:0] 165

+0x01 CTRLB CCDEN CCCEN CCBEN CCAEN - WGMODE[2:0] 165

+0x02 CTRLC - - - - CPMD CPMC CPMB CPMA 166

+0x03 CTRLD EVACT[2:0] EVDLY EVSEL[3:0] 167

+0x04 CTRLE - - - - - - - BYTEM 168

+0x05 Reserved - - - - - - - -

+0x06 INTCTRLA - - - - ERRINTLVL[1:0] OVINTLVL[1:0] 168

+0x07 INTCTRLB CCCINTLVL[1:0] CCCINTLVL[1:0] CCBINTLVL[1:0] CCAINTLVL[1:0] 168

+0x08 CTRLFCLR - - - - CMD[1:0] LUPD DIR 169

+0x09 CTRLFSET - - - - CMD[1:0] LUPD DIR 170

+0x0A CTRLGCLR - - - CCDBV CCCBV CCBBV CCABV PERBV 170

+0x0B CTRLGSET - - - CCDBV CCCBV CCBBV CCABV PERBV 170

+0x0C INTFLAGS CCDIF CCCIF CCBIF CCAIF - - ERRIF OVFIF 171

+0x0D Reserved - - - - - - - -

+0x0E Reserved - - - - - - - -

+0x0F TEMP TEMP[7:0] 171

+0x10 to +0x1F Reserved - - - - - - - -

+0x20 CNTL CNT[7:0] 172

+0x21 CNTH CNT[15:8] 172

+0x22 to +0x25 Reserved - - - - - - - -

+0x26 PERL PER[7:0] 173

+0x27 PERH PER[8:15] 172

+0x28 CCAL CCA[7:0] 173

+0x29 CCAH CCA[15:8] 173

+0x2A CCBL CCB[7:0] 173

+0x2B CCBH CCB[15:8] 173

+0x2C CCCL CCC[7:0] 173

+0x02D CCCH CCC[15:8] 173

+0x2E CCDL CCD[7:0] 173

+0x2F CCDH CCD[15:8] 173

+0x30 to +0x35 Reserved - - - - - - - -

+0x36 PERBUFL PERBUF[7:0] 174

+0x37 PERBUFH PERBUF[15:8] 173

+0x38 CCABUFL CCABUF[7:0] 174

+0x39 CCABUFH CCABUF[15:8] 174

+0x3A CCBBUFL CCBBUF[7:0] 174

+0x3B CCBBUFH CCBBUF[15:8] 174

+0x3C CCCBUFL CCCBUF[7:0] 174

+0x3D CCCBUFH CCCBUF[15:8] 174

+0x3E CCDBUFL CCDBUF[7:0] 174

+0x3F CCDBUFH CCDBUF[15:8] 174

Table 14-8. Timer/Counter Interrupt vectors and their word offset address

Offset Source Interrupt Description

0x00 OVF_vect Timer/Counter Overflow/Underflow Interrupt vector offset

0x02 ERR_vect Timer/Counter Error Interrupt vector offset

0x4 CCA_vect Timer/Counter Compare or Capture Channel A Interrupt vector offset

0x6 CCB_vect Timer/Counter Compare or Capture Channel B Interrupt vector offset

0x8 CCC_vect(1) Timer/Counter Compare or Capture Channel C Interrupt vector offset

0x0A CCD_vect(1) Timer/Counter Compare or Capture Channel D Interrupt vector offset

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15. AWeX – Advanced Waveform Extension

15.1 Features

•4 Dead-Time Insertion (DTI) Units (8-pin)

– 8-bit Resolution

– Separate High and Low Side Dead-Time Setting

– Double Buffered Dead-Time

– Halts Timer During Dead-Time (Optional)

•Event Controlled Fault Protection

•Single Channel Multiple Output Operation (for BLDC control)

•Double Buffered Pattern Generation

•The Hi-Resolution Timer Extension Increases PWM/FRQ Resolution by 2-bits (4x)

15.2 Overview

The Advanced Waveform Extention (AWeX) provides extra features to the Timer/Counter in

Waveform Generation (WG) modes. The AWeX enables easy and robust implementation of

advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.

Figure 15-1. Advanced Waveform eXtention and closely related peripherals (grey)

As shown in Figure 15-1 on page 176 each of the waveform generator outputs from the

Timer/Counter 0 are split into a complimentary pair of outputs when any AWeX features is

enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that enables genera-

tion of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output with dead

time insertion between LS and HS switching. The DTI output will override the normal port value

according to the port override setting. Optionally the final output can be inverted by using the

invert I/O (INVEN) bit setting for the port pin (Pxn).

PORTxTimer/Counter 0

AWeX

Channel A DTI

Channel A

Channel B DTI

Channel B

Channel C DTI

Channel C

Channel D DTI

Channel D

Port

Override

Pattern

Generation

Px0

Px1

Px2

Px3

Px4

Px5

Px6

Px7

INVEN

Event

System Fault

Protection

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The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is

connected to. In addition, the waveform generator output from the Compare Channel A can be

distributed to and override all the port pins. When the Pattern Generator unit is enabled the DTI

unit is bypassed.

The Fault Protection unit is connected to the Event System, enabling any event to trigger a fault

condition that will disable the AWeX output.

15.3 Port Override

Common for all the timer/counter extensions is the port override logic. Figure 15-2 on page 178

shows a schematic diagram of the port override logic. When the dead-time enable (DTIENx) bit

is set the timer/counter extension takes control over the pin pair for the corresponding channel.

Given this condition the Output Override Enable (OOE) bits takes control over the CCxEN.

Note that timer/counter 1 (TCx1) can still be used even when DTI channels A, B, and D are

enabled.

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Figure 15-2. Timer/Counter extensions and port override logic

PORTx0

OOE0

CCENA

DTIENA

INVx0

PORTx1

OOE1

CCENB INVx1

Px0

Px1

Channel

DTI

OC0A

OC0B

OCLSA

OCHSA

WG 0A

WG 0B

WG 0A CWCM

PORTx2

OOE2

CCENC

DTIENB

INVx2

PORTx3

OOE3

CCEND INVx3

Px2

Px3

Channel

DTI

OC0C

OC0D

OCLSB

OCHSB

WG 0C

WG 0D

PORTx4

OOE4

CCENA

DTIENC

INVx4

PORTx5

OOE5

CCENB INVx5

Px4

Px5

Channel

DTI

OC1A

OC1B

OCLSC

OCHSC

WG 1A

WG 1B

PORTx6

OOE6

DTIEND

INVx6

PORTx7

OOE7

INVx7

Px6

Px7

Channel

DTI

OCLSD

OCHSD

WG 0B

WG 0D

WG 0C

"0"

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15.4 Dead Time Insertion

The Dead Time Insertion (DTI) unit enables generation of “off” time where both the non-inverted

Low Side (LS) and inverted High Side (HS) of the WG output is low. This “off” time is called

dead-time, and dead-time insertion ensure that the LS and HS does not switch simultaneously.

The DTI unit consists of four equal dead time generators, one for each of the capture or com-

pare channel in Timer/Counter 0. Figure 15-3 on page 179 shows the block diagram of one dead

time generator. The dead time registers that define the number of peripheral clock cycles the

dead time is going to last, are common for all four channels. The High Side and Low Side can

have independent dead time setting and the dead time registers are double buffered.

Figure 15-3. Dead Time Generator block diagram

As shown in Figure 15-4 on page 180, the 8-bit Dead Time Counter (dti_cnt) is decremented by

one for each peripheral clock cycle until it reaches zero. A non-zero counter value will force both

the Low Side and High Side outputs into their “off” state. When a change is detected on the WG

output, the Dead Time Counter is reloaded with the DTx register value according to the edge of

the input. Positive edge initiates a counter reload of the DTLS Register and a negative edge a

reload of DTHS Register.

Dead Time Generator

Edge Detect

V V

= 0

DTLSBUF

DTILS

DTHSBUF

DTIHS

WG output "dtls"

(To PORT)

"dths"

(To PORT)

Counter ("dti_cnt")

LOAD

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XMEGA A

Figure 15-4. Dead Time Generator timing diagram

15.5 Pattern Generation

The pattern generator extension reuses the DTI registers to produce a synchronized bit pattern

on the port it is connected to. In addition, the waveform generator output from CC channel A

(CCA)) can be distributed to and override all the port pins. These features are primarily intended

for handling the commutation sequence in BLDC and Stepper Motor Applications.

Figure 15-5. Pattern Generator block diagram

A block diagram of the pattern generator is shown in Figure 15-5 on page 180. For each port pin

where the corresponding OOE bit is set the multiplexer will output the waveform from CCA.

As for all other types of the Timer/Counter double-buffered registers the register update is syn-

chronized to the UPDATE condition set by the waveform generation mode. If the

synchronization provided is not required by the application, the application code can simply

access the DTIOE and PORTx registers directly.

The pins direction must be set for any output from the pattern generator to be visible on the port.

"dti_cnt"

"WG ou tput"

"dtls"

"dths"

tDTILS tDTIHS

Timer/Counter 0 (TCx0)

V VDTIBLS

DTIOE[7:0]

DTIBHS

PORTx[7:0]

CCA WG output

UPDATE

ENEN

1 to 8

Expand

Px[7:0]

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15.6 Fault Protection

The Fault Protection feature enables fast and deterministic action when a fault is detected. The

fault protection is event controlled, thus any event from the Event System can be used to trigger

a fault action.

When the Fault Protection is enabled an incoming event from any of the selected event channel

can trigger the event action. Each event channel can be separately enabled as fault protection

input, and the specified event channels will be ORed together allowing multiple event sources

top be used for fault protection at the same time.

15.6.1 Fault Actions

Two different even actions can be selected:

• The Clear Override Enable action will clear the Output Override Enable register (OUTOVEN)

and disable the output override on all Timer/Counter outputs. The result is that the in the

output will be as set by the port pin configuration.

• The Direction Clear action will clear the Direction (DIR) register in the associated port, setting

all port pins as tri-stated inputs.

When a fault is detected the Fault Detection Flag is set, and the Timer/Counter’s Error Interrupt

Flag is set and the optional interrupt is generated.

From the event occurs in one peripherals until the Fault Protection triggers the event action,

there is maximum two peripheral clock cycles. The Fault Protection is fully independent of the

CPU and DMA, but it requires the Peripheral Clock to run.

15.6.2 Fault Restore Modes

After a fault, that is when the fault condition is no longer active, it is selectable how the AWeX

and Timer/Counter can return from fault state and restore with normal operation. Two different

modes are available:

• In Latched Mode the waveform output will remain in the fault state until the fault condition is

no longer active and the fault detect flag has been cleared by software. When both of these

conditions are met, the waveform output will return to normal operation at the next UPDATE

condition.

• In Cycle-by-Cycle Mode the waveform output will remain in the fault state until the fault

condition is no longer active. When this condition is met, the waveform output will return to

normal operation at the next UPDATE condition.

When entering fault state and the Clear Override Enable action is selected, the OUTOVEN[7:0]

bits are reassigned a value on the next UPDATE condition. In pattern generation mode the reg-

ister is restored with the value in the DTLSBUF register. Otherwise the register bits are restored

according to the enabled DTI channels.

When entering fault state and Direction Clear action is select is set, corresponding DIR[7:0] bits

is restored with the value in the DTLSBUF register in pattern generation mode and for the pin

pairs corresponding to enabled DTI channels otherwise.

The UPDATE condition used to restore the normal operation is the same update as in the

Timer/Counter.

15.6.3 Change Protection

To avoid unintentional changes in the fault protection setup all the control registers in the AWeX

Extension can be protected by writing the corresponding lock bit Advanced Waveform Extension

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Lock Register. For more details refer to ”IO Memory Protection” on page 25 and ”AWEXLOCK –

Advanced Waveform Extension Lock Register” on page 45.

When the lock bit is set, the Control Register A, the Output Override Enable Register and the

Fault Dedec.tion Event Mask register cannot be changed.

To avoid unintentional changes in the fault event setup it is possible to lock the Event System

channel configuration by writing the corresponding Event System Lock Register. For more

details refer to ”IO Memory Protection” on page 25 and ”EVSYSLOCK – Event System Lock

15.6.4 On-Chip Debug

When fault detection is enabled an OCD system receives a break request from the debugger,

this will by default function as a fault source. When an OCD break request is received, the

AWeX and corresponding Timer/Counter will enter fault state and the specified fault action(s) will

be performed.

After the OCD exits from the break condition, normal operation will be started again. In cycle-by-

cycle mode the waveform output will start on the first update condition after exit from break, and

in latched mode, the Fault Condition Flag must be cleared in software before the output will be

restored. This feature guarantees that the output waveform enters a safe state during break.

It is possible to disable this feature.

15.7 Register Description

15.7.1 CTRL - Control Register

• Bit 7:6 - RES - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 5 - PGM: Pattern Generation Mode

Setting this bit enables the pattern generation mode if set. This will override the DTI if enabled,

and the Pattern Generation reuses the dead-time registers for storing the pattern.

• Bit 4 - CWCM: Common Waveform Channel Mode

If this bit is set CC channel A waveform output will be used as input for all the dead-time genera-

tors. CC channel B, C, and D waveforms will be ignored.

• Bit 3:0 - DTICCxEN: Dead-Time Insertion CCx Enable

Setting these bits enables the Dead Time Generator for the corresponding CC channel. This will

override the Timer/Counter waveform outputs.

Bit 7654 3 2 1 0

+0x00 - - PGM CWCM DTICCDEN DTICCCEN DTICCBEN DTICCAEN CTRL

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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15.7.2 FDEMASK - Fault Detect Event Mask Register

• Bit 7:0 - FDEVMASK[7:0]: Fault Detect Event Mask

These bits enables the corresponding event channel as fault condition input source. Event from

all event channels will be ORed together allowing multiple sources to be used for fault detection

at the same time. When a fault is detected the Fault Detect Flag FDF is set and the fault detect

action (FDACT) will be performed.

15.7.3 FDCTRL - Fault Detection Control Register

• Bit 7:5 - RES - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 4 - FDDBD: Fault Detection on Debug Break Detection

By default, when this bit is cleared and the fault protection is enabled, and OCD break request is

treated as a fault. When this bit is set, an OCD break request will not trigger a fault condition.

• Bit 3 - RES - Reserved

This bit is unused and reserved for future use. For compatibility with future devices, always write

this bit to zero when this register is written.

• Bit 2- FDMODE: Fault Detection Restart Mode

This bit sets the fault protection restart mode. When this bit is cleared Latched Mode is use, and

when this is set Cycle-by-Cycle Mode is used.

In Latched Mode the waveform output will remain in the fault state until the fault condition is no

longer active and the FDF has been cleared by software. When both of these conditions are

met, the waveform output will return to normal operation at the next UPDATE condition.

In Cycle-by-Cycle Mode the waveform output will remain in the fault state until the fault condition

is no longer active. When this condition is met, the waveform output will return to normal opera-

tion at the next UPDATE condition.

• Bit 1:0 - FDACT[1:0]: Fault Detection Action

These bits define the action performed if a fault condition is detected, according to Table 15-1.

Bit 76543210

+0x02 FDEVMASK[7:0] FDEMASK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x03 - - - FDDBD - FDMODE FDACT[1:0] FDCTRL

Read/Write R R R R/W R R/W R/W R/W

Initial Value00000000

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15.7.4 STATUS - Status Register

• Bit 7:3 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 2 - FDF: Fault Detect Flag

This flag is set when a fault detect condition is detected, i.e. when an event is detected on one of

the event channels enabled by the FDEVMASK. This flag is cleared by writing a one to its bit

location.

• Bit 1 - DTHSBUFV: Dead-Time High Side Buffer Valid

If this bit is set the corresponding DT buffer is written and contains valid data that will be copied

into the DTLS Register on the UPDATE condition. If this bit is zero no action will be taken. The

connected Timer/Counter’s lock update (LUPD) flag also affects the update for dead time

buffers.

• Bit 0 - DTLSBUFV: Dead-Time Low Side Buffer Valid

If this bit is set the corresponding DT buffer is written and contains valid data that will be copied

into the DTHS Register on the UPDATE condition. If this bit is zero no action will be taken. Note

that the connected Timer/Counter unit's lock update (LUPD) flag also affects the update for dead

time buffers.

15.7.5 DTBOTH - Dead-time Concurrent Write to Both Sides

Table 15-1. Fault actions

FDACT[1:0] Group Configuration Description

00 NONE None (Fault protection disabled)

01 CLEAROE Clear all override enable (OUTOVEN) bits, i.e. disable

the output override.

11 CLEARDIR Clear all Direction (DIR) bits, which correspond to

enabled DTI channel(s), i.e. tri-state the outputs

Bit 76543 2 1 0

+0x04 - - - - - FDF DTHSBUFV DTLSBUFV STATUS

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x06 DTBOTH[7:0] DTBOTH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 7:0 - DTBOTH: Dead-Time Both Sides

Writing to this register will update both DTHS and DTLS registers at the same time (i.e. at the

same I/O write access).

15.7.6 DTBOTHBUF - Dead-time Concurrent Write to Both Sides Buffer

• Bit 7:0 - DTBOTHBUF: Dead-Time Both Sides Buffer

Writing to this memory location will update both DTHSBUF and DTLSBUF registers at the same

time (i.e. at the same I/O write access).

15.7.7 DTLS - Dead-Time Low Side Register

• Bit 7:0 - DTLS: Dead-Time Low Side

This register holds the number of peripheral clock cycles for the Dead-Time Low Side.

15.7.8 DTHS - Dead-Time High Side Register

• Bit 7:0 - DTHS: Dead-Time High Side

This register holds the number of peripheral clock cycles for the Dead-Time High Side.

15.7.9 DTLSBUF - Dead-Time Low Side Buffer Register

• Bit 7:0 - DTLSBUF: Dead-Time Low Side Buffer

This register is the buffer for the DTLS Register. If double buffering is used, valid contents in this

Bit 76543210

+0x07 DTBOTHBUF[7:0] DTBOTHBUF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x08 DTLS[7:0] DTLS

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x09 DTHS[7:0] DTHS

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x0A DTLSBUF[7:0] DTLSBUF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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XMEGA A

15.7.10 DTHSBUF - Dead-Time High Side Buffer Register

• Bit 7:0 - DTHSBUF: Dead-Time High Side Buffer

This register is the buffer for the DTHS Register. If double buffering is used, valid contents in this

15.7.11 OUTOVEN - Output Override Enable Register

Note: 1. Can only be written if the fault detect flag (FDF) is zero.

• Bit 7:0 - OUTOVEN[7:0]: Output Override Enable

These bits enable override of corresponding port output register (i.e. one-to-one bit relation to

pin position). The port direction is not overridden

Bit 76543210

+0x0B DTHSBUF[7:0] DTHSBUF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x0C OUTOVEN[7:0] OUTOVEN

Read/Write R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)

Initial Value00000000

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15.8 Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL - - PGM CWCM DTICDAEN DTICCCEN DTICCBEN DTICCAEN 182

+0x01 Reserved - - - - - - - -

+0x02 FDEMASK FDEVMASK[7:0] 183

+0x03 FDCTRL - - - FDDBD - FDMODE FDACT[1:0] 183

+0x04 STATUS - - - - - FDF DTBHSV DTBLSV 184

+0x05 Reserved - - - - - - - -

+0x06 DTBOTH DTBOTH[7:0] 184

+0x07 DTBOTHBUF DTBOTHBUF[7:0] 185

+0x08 DTLS DTLS[7:0] 185

+0x09 DTHS DTHS[7:0] 185

+0x0A DTLSBUF DTLSBUF[7:0] 185

+0x0B DTHSBUF DTHSBUF[7:0] 185

+0x0C OUTOVEN OUTOVEN[7:0] 186

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16. Hi-Res - High Resolution Extension

16.1 Features

•Increases Waveform Generator Resolution by 4x (2 bits)

•Supports Frequency generation, and single and dual-slope PWM operation

•Supports Dead-Time Insertion (AWeX)

•Supports Pattern Generation (AWeX)

16.2 Overview

The High-Resolution (Hi-Res) Extension can be used to increase the resolution of the waveform

generation output from a Timer/Counter by four (two bits). It can be used during Frequency and

PWM generation, and also in combination with the corresponding AWeX.

The Hi-Res Extension uses the Peripheral 4x Clock. The System Clock prescalers must be set

up so the Peripheral 4x Clock frequency is four times higher than the Peripheral and CPU clock

frequency (see ”System Clock Selection and Prescalers” on page 80) when the Hi-Res

Extension is enabled.

Figure 16-1. Timer/Counter operation with Hi-Res Extension enabled

The Hi-Res Extension is implemented by letting the Timer/Counter run at 4x its normal speed.

When Hi-Res Extension is enabled, the counter will ignore its two lowest significant bits (LSB)

and count by four for each Peripheral clock cycle. Overflow/Underflow and Compare match of

the 14 most significant bits (LSB) is done in the Timer/Counter. Count and Compare of the two

LSB is then handled and compared in the Hi-Res Extension running from the Peripheral 4x

clock.

The two LSB of the Period register must always be set to zero to ensure correct operation. If the

Count register is read, the two LSB will always be read as zero since the Timer/Counter run from

the Peripheral clock.

The Hi-Res Extension has narrow pulse deletion preventing output of any pulse shorter than one

Peripheral clock cycle, e.g. a compare value lower than foure will have no visible output.

CNT[15:2]

HiRes

CCBUFx[15:0]

== 0

"match"

PER[15:2] 0

Waveform

Generation

TOPBOTTOM

Time/Counter

CCx[15:2] [1:0]

222

AWeX

Fault

Protection

DTI

Dead-Time

Insertion

Pattern

Generation

clkPER clkPER4

Pnx

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XMEGA A

16.3 Register Description

16.3.1 CTRLA - Hi-Res Control Register A

• Bit 7:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1:0 - HREN[1:0]: Hi-Resolution Enable

Enables Hi-Resolution mode for a Timer/Counter according to Table 16-1.

Setting one or both HREN bits will enable Hi-Resolution waveform generation output for the

entire general purpose I/O port. This means that both Timer/Counters connected to the same

port must enable Hi-Res if both are used for generating PWM or FRQ output on pins.

16.4 Register Summary

Bit 76543210

+0x00 – – – – – – HREN[1:0] CTRLA

Read/WriteRRRRRRR/WR/W

Initial Value00000000

Table 16-1. Hi-Resolution Enable

HREN[1:0] Hi-Resolution Enabled

00 None

01 Timer/Counter 0

10 Timer/Counter 1

11 Both Timer/Counters

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRLA HREN[1:0] 189

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17. RTC - Real Time Counter

17.1 Features

•16-bit resolution

•Selectable clock reference

– 32.768 kHz

– 1.024 kHz

•Programmable prescaler

•1 Compare register

•1 Period register

•Clear Timer on overflow

•Optional Interrupt/ Event on overflow and compare match

17.2 Overview

The Real Time Counter (RTC) is a 16-bit counter, counting reference clock cycles and giving an

event and/or an interrupt request when it reaches a configurable compare and/or top value. The

reference clock is typically generated from a high accuracy crystal of 32.768 kHz, and the design

is optimized for low power consumption. The RTC typically operate in low power sleep modes,

keeping track of time and waking up the device at regular intervals.

The RTC reference clock may be taken from an 32.768 kHz or 1.024 kHz input. Both an external

32.768 kHz crystal oscillator or the 32 kHz internal RC oscillator can be selected as clock

source. For details on reference clock selection to the RTC refer to ”RTCCTRL - RTC Control

scale down the reference clock before it reaches the Counter.

The RTC can generate both compare and overflow interrupt request and/or events.

Figure 17-1. Real Time Counter overview.

10-bit

prescaler 16-bit Counter

16-bit Period

16-bit Compare

Overflow

Compare Match

1.024 kHz

32.768 kHz

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17.2.1 Clock domains

The RTC is asynchronous, meaning it operates from a different clock source and independently

of the main System Clock and its derivative clocks such as the Peripheral Clock. For Control and

Count register updates it will take a number of RTC clock and/or Peripheral clock cycles before

an updated register value is available or until a configuration change has effect on the RTC. This

synchronization time is described for each register.

17.2.2 Interrupts and events

The RTC can generate both interrupts and events. The RTC will give a compare interrupt

request and/or event when the counter value equals the Compare register value. The RTC will

give an overflow interrupt request and/or event when the counter value equals the Period regis-

ter value. The overflow will also reset the counter value to zero.

Due to the asynchronous clock domains event will only will only be generated for every third

overflow or compare if the period register is zero. If the period register is one, events will only be

generated for every second overflow or compare. When the period register is equal to or above

two, events will trigger at every overflow or compare just as the interrupt request.

17.3 Register Description

17.3.1 CTRL - Real Time Counter Control Register

• Bits 7:3 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bits 2:0 - PRESCALER[2:0]: RTC Clock Prescaling factor

These bits define the prescaling factor for the RTC clock before the counter according to Table

17-1 on page 191.

Bit 76543210

+0x00 - - - - - PRESCALER[2:0] CTRL

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 17-1. Real Time Counter Clock prescaling factor

PRESCALER[2:0] Group Configuration RTC clock prescaling

000 OFF No clock source, RTC stopped

001 DIV1 RTC clock / 1 (No prescaling)

010 DIV2 RTC clock / 2

011 DIV8 RTC clock / 8

100 DIV16 RTC clock / 16

101 DIV64 RTC clock / 64

110 DIV256 RTC clock / 256

111 DIV1024 RTC clock / 1024

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17.3.2 STATUS - Real Time Counter Status Register

• Bits 7:1 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 0 - SYNCBUSY: RTC Synchronization Busy Flag

This bit is set when the CNT, CTRL, PER or COMP register is busy synchronizing between the

RTC clock and system clock domains.

17.3.3 INTCTRL - Real Time Counter Interrupt Control Register

• Bits 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bits 3:2 - COMPINTLVL[1:0]: RTC Compare Match Interrupt Enable

These bits enable the RTC Compare Match Interrupt and select the interrupt level as described

in Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page 123. The

enabled interrupt will trigger when the COMPIF in the INTFLAGS register is set.

• Bits 1:0 - OVFINTLVL[1:0]: RTC Overflow Interrupt Enable

These bits enable the RTC Overflow Interrupt and select the interrupt level as described in Sec-

tion 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page 123. The enabled

interrupt will trigger when the OVFIF in the INTFLAGS register is set.

Bit 7654321 0

+0x01 -------SYNCBUSYSTATUS

Read/WriteRRRRRRRR/W

Initial Value0000000 0

Bit 76543210

+0x02 - - - - COMPINTLVL[1:0] OVFINTLVL[1:0] INTCTRL

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000000

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17.3.4 INTFLAGS - RTC Interrupt Flag Register

• Bits 7:2 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 1 - COMPIF: RTC Compare Match Interrupt Flag

This flag is set on the next count after a Compare Match condition occurs. The flag is cleared

automatically when RTC compare match interrupt vector is executed. The flag can also be

cleared by writing a one to its bit location.

• Bit 0 - OVFIF: RTC Overflow Interrupt Flag

This flag is set on the next count after an Overflow condition occurs. The flag is cleared automat-

ically when RTC overflow interrupt vector is executed. The flag can also be cleared by writing a

one to its bit location.

17.3.5 TEMP - RTC Temporary Register

• Bits 7:0 - TEMP[7:0]: Real Time Counter Temporary Register

This register is used for 16-bit access to the counter value, compare value and top value regis-

ters. The low byte of the 16-bit register is stored here when it is written by the CPU. The high

byte of the 16-bit register is stored when low byte is read by the CPU. For more details refer to

”Accessing 16-bits Registers” on page 12.

17.3.6 CNTH - Real Time Counter Register H

The CNTH and CNTL register pair represents the 16-bit value CNT. CNT counts positive clock

edges on the prescaled RTC clock. Reading and writing 16-bit values require special attention,

refer to ”Accessing 16-bits Registers” on page 12 for details.

Due to synchronization between RTC clock and the system clock domains, there is a latency of

two RTC clock cycles from updating the register until this has an effect. Application software

needs to check that the SYNCBUSY flag in the ”STATUS - Real Time Counter Status Register”

on page 192 is cleared before writing to this register.

Bit 76543210

+0x03 ------COMPIFOVFIFINTFLAGS

Read/WriteRRRRRRR/WR/W

Initial Value00000000

Bit 76543210

+0x04 TEMP[7:0] TEMP

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x09 CNT[15:8] CNTH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bits 7:0 - CNT[15:8]: Real Time Counter value High byte

These bits hold the 8 MSB of the 16-bit Real Time Counter value.

17.3.7 CNTL - Real Time Counter Register L

• Bits 7:0 - CNT[7:0]: Real Time Counter value Low byte

These bits hold the 8 LSB of the 16-bit Real Time Counter value.

17.3.8 PERH - Real Time Counter Period Register High

The PERH and PERL register pair represents the 16-bit value PER. PER is constantly com-

pared with the counter value (CNT). A match will set the OVFIF in the INTFLAGS register and

clear CNT. Reading and writing 16-bit values require special attention, refer to ”Accessing 16-

bits Registers” on page 12 for details.

Due to synchronization between RTC clock and the system clock domains, there is a latency of

two RTC clock cycles from updating the register until this has an effect. Application software

needs to check that the SYNCBUSY flag in the ”STATUS - Real Time Counter Status Register”

on page 192 is cleared before writing to this register.

• Bits 7:0 - PER[15:8]: Real Time Counter Period High byte

These bits hold the 8 MSB of the 16-bit RTC top value.

17.3.9 PERL - Real Time Counter Period Register L

• Bits 7:0 - PER[7:0]: Real Time Counter Period Low byte

These bits hold the 8 LSB of the 16-bit RTC top value.

Bit 76543210

+0x08 CNT[7:0] CNTL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

+0x0B PER[15:8] PERH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value11111111

Bit 76543210

+0x0A PER[7:0] PERL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 1

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17.3.10 COMPH - Real Time Counter Compare Register H

The COMPH and COMPL register pair represent the 16-bit value COMP. COMP is constantly

compared with the counter value (CNT). A compare match will set the COMPIF in the INT-

FLAGS register. Reading and writing 16-bit values require special attention, refer to

”Configuration Change Protection” on page 12 for details.

Due to synchronization between RTC clock and the system clock domains, there is a latency of

two RTC clock cycles from updating the register until this has an effect. Application SW needs to

check that the SYNCBUSY flag in the ”STATUS - Real Time Counter Status Register” on page

192 is cleared before writing to this register.

If the COMP value is higher than the PER value, no RTC Compare Match interrupt requests or

events will ever be generated.

• Bits 7:0 - COMP[15:8]: Real Time Counter Compare Register High byte

These bits hold the 8 MSB of the 16-bit RTC compare value.

17.3.11 COMPL - Real Time Counter Compare Register L

• Bits 7:0 - COMP[7:0]: Real Time Counter Compare Register Low byte

These bits hold the 8 LSB of the 16-bit RTC compare value.

Bit 76543210

+0x0D COMP[15:8] COMPH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

+0x0C COMP[7:0] COMPL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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17.4 Register Summary

17.5 Interrupt Vector Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

+0x00 CTRL - - - - - PRESCALER[2:0] 191

+0x01 STATUS - - - - - - - SYNCBUSY 192

+0x02 INTCTRL - - - - COMPINTLVL[1:0] OVFINTLVL[1:0] 192

+0x03 INTFLAGS - - - - - - COMPIF OVFIF 193

+0x04 TEMP TEMP[7:0] 193

+0x08 CNTL CNT[7:0] 193

+0x09 CNTH CNT[15:8] 194

+0x0A PERL PER[7:0] 194

+0x0B PERH PER[15:8] 194

+0x0C COMPL COMP[7:0] 195

+0x0D COMPH COMP[15:8] 195

Table 17-2. RTC Interrupt vectors and their word offset address

Offset Source Interrupt Description

0x00 OVF_vect Real Time Counter Overflow Interrupt vector

0x02 COMP_vect Real Time Counter Compare Match Interrupt vector

18. RTC32 - 32-bit Real Time Counter

18.1 Features

•32-bit resolution

•Selectable clock reference

– 1.024 kHz

–1 Hz

•One Compare register

•One Period register

•Clear Timer on overflow

•Optional Interrupt/ Event on overflow and compare match

•Isolated VBAT power domain with dynamic switch over from/to VCC power domain

18.2 Overview

The 32-bit Real Time Counter is a 32-bit counter, counting reference clock cycles and giving an

event and/or an interrupt request when it reaches a configurable compare and/or top value. The

reference clock is generated from a high accuracy 32.768 kHz crystal, and the design is opti-

mized for low power consumption. The Real Time Counter (RTC) typically operates in low power

sleep modes, keeping track of time and waking up the device at regular intervals.

The RTC input clock can be taken from a 1.024 kHz or 1 Hz prescaled output from the 32.768

kHz reference clock. The RTC will give a compare interrupt request and/or event when the coun-

ter value equals the Compare register value. The RTC will give an overflow interrupt request

and/or event when the counter value equals the Period register value. Counter overflow will also

reset the counter value to zero.

The RTC can generate both compare and overflow interrupt request and/or events.

Figure 18-1. 32-bit Real Time Counter Overview

32-bit Period

32-bit Counter

32-bit Compare

Overflow

1 Hz

1.024 kHz

Compare Match

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18.2.1 Clock selection

An external 32.768 kHz crystal oscillator must be used as clock source. Two different frequency

outputs are available form this, and the RTC clock input can be 1.024 kHz or 1 Hz.

18.2.2 Clock domains

The RTC is asynchronous, meaning it operates from a different clock source and independently

of the main System Clock and its derivative clocks such as the Peripheral Clock. For Control and

Count register updates it will take a number of RTC clock and/or Peripheral clock cycles before

an updated register value is available or until a configuration change has effect on the RTC. This

synchronization time is described for each register.

The Peripheral clock must be eight times faster than the RTC clock (1.024 kHz or 1 Hz) when

any the Control and Count register is accessed (read or written), expect 12 times faster when

the Count register is written.

18.2.3 Power domains

For devices where the RTC is located in the VBAT power domain this enables the RTC to function

correctly with no VCC available. When running from the VBAT power domain, only the 1 Hz clock

source is available. A dynamic power-switch is used to automatically switch from VCC domain to

the VBAT domain if VCC falls below the operating voltage level for the device. When the VCC volt-

age is restored, the power is automatically switched back to VCC.

18.2.4 Interrupts and events