DRF1203
1000V, 12A, 30MHz
The DRF1203 hybrid includes a high power gate driver and the power
MOSFET. The driver output can be confi gured as Inverting and Non-
Inverting. It was designed to provide the system designer increased
fl exibility and lowered cost over a non-integrated solution.
TYPICAL APPLICATIONS
• Class C, D and E RF Generators
• Switch Mode Power Amplifi ers
• Pulse Generators
• Ultrasound Transducer Drivers
• Acoustic Optical Modulators
FEATURES
• Switching Frequency: DC TO 30MHz
• Low Pulse Width Distortion
• Single Power Supply
• 1V CMOS Schmitt Trigger Input 1V
Hysteresis
• Inverting Non-Inverting Select
• RoHS Compliant
• Switching Speed 3-4ns
• BVds = 1Kv
• Ids = 12A avg.
• Rds(on) ≤ .90 Ohm
• PD = 560W
Symbol Parameter Ratings Unit
VDD Supply Voltage 15 V
IN, FN Input Single Voltages -.7 to +5.5
IO PK Output Current Peak 8A
TJMAX Operating and Storage Temperature 175 °C
MOSFET Driver Hybrid
Driver Absolute Maximum Ratings
Driver Specifi cations
Symbol Parameter Min Typ Max Unit
VDD Supply Voltage 10 15 V
IN Input Voltage 3 5.5
IN(R) Input Voltage Rising Edge 3
ns
IN(F) Input Voltage Falling Edge 3
IDDQ Quiescent Current 2mA
IOOutput Current 8A
Ciss Input Capacitance 3
RIN Input Parallel Resistance 1MΩ
VT(ON) Input, Low to High Out (See Truth Table) 0.8 1.1 V
VT(OFF) Input, High to Low Out (See Truth Table) 1.9 2.2
TDLY Time Delay (throughput) 38 ns
trRise Time 5
ns
tf Fall Time 5
TDProp. Delay 35
Microsemi Website - http://www.microsemi.com
050-4974 Rev E 6-2012
DRF1203
MOSFET Absolute Maximum Ratings
Symbol Parameter Min Typ Max Unit
BVDSS Drain Source Voltage 1000 V
IDContinuous Drain Current THS = 25°C 12 A
RDS(on) Drain-Source On State Resistance 0.90 Ω
Tjmax Operating Temperature 175 °C
MOSFET Dynamic Characteristics
Symbol Parameter Min Typ Max Unit
Ciss Input Capacitance 2000
pF
Coss Output Capacitance 165
Crss Reverse Transfer Capacitance 75
MOSFET Thermal Characteristics
Symbol Parameter Min Type Max Unit
RθJC Thermal Resistance Junction to Case 0.53 °C/W
RθJHS Thermal Resistance Junction to Heat Sink 0.141
TJSTG Storage Temperature -55 to 150 °C
PDHS Maximum Power Dissipation @ TSINK = 25°C 1060
W
PDC Total Power Dissipation @ TC = 25°C 2830
Microsemi reserves the right to change, without notice, the specifi cations and information contained herein.
050-4974 Rev E 6-2012
Figure 1, DRF1203 Simplifi ed Circuit Diagram
The Simplifi ed DRF1203 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitor (C1), their contribution
to the internal parasitic loop inductance of the driver output is greatly reduced. This, coupled with the tight geometry of the hybrid, allows
optimal gate drive to the MOSFET. This low parasitic approach, coupled with the Schmitt trigger input (IN), Kelvin signal ground (SG) and the
Anti-Ring Function, provide improved stability and control in Kilowatt to Multi-Kilowatt, high Frequency applications. The IN pin is the input for
the control signal and is applied to a Schmitt Trigger. Both the FN and IN pins are referenced to the Kelvin ground (SG.) The signal is then ap-
plied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifi cally for the ring abatement. The
power drivers provide high current to the gate of the MOSFETS.
Symbol Parameter Min Typ Max Unit
Cout Output Capacitance 2500 pF
Rout Output Resistance .8 Ω
Lout Output Inductance 3 nH
FMAX Operating Frequency CL = 3000nF + 50Ω30
MHz
FMAX Operating Frequency RL = 50Ω50
Driver Output Characteristics
Symbol Parameter Min Typ Max Unit
RθJC Thermal Resistance Junction to Case 1.5 °C/W
RθJHS Thermal Resistance Junction to Heat Sink 2.5
TJSTG Storage Temperature -55 to 150 °C
PDJHS Maximum Power Dissipation @ TSINK = 25°C 60
W
PDJC Total Power Dissipation @ TC = 25°C 100
Driver Thermal Characteristics
The Function (FN, pin 3) is the invert or non-invert select Pin, it is Internally held high.
DRF1203
050-4974 Rev E 6-2012
The Test Circuit illustrated above was used to evaluate the DRF1203 (available as an evaluation Board DRF12XX / EVALSW.) The input
control signal is applied to the DRF1203 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the
signal ground currents.
The +VDD inputs (2,6) are by-passed (C1,C2, C4-C9), this is in addition to the internal by-passing mentioned previously. The capacitors used
for this function must be capable of supporting the RMS currents and frequency of the gate load. RL set for IDM at VDS max this load is used to
evaluate the output performance of the DRF1203.
Figure 2, DRF1203 Test Circuit
Truth Table *Referenced to SG
FN (pin 3)* IN (pin 4)* MOSFET
HIGH HIGH ON
HIGH LOW OFF
LOW HIGH OFF
LOW LOW ON
Figure 3, DRF1203 Mechanical Outline
All dimensions are ± .005
DRF1203
050-4974 Rev E 6-2012
Pin Assignments
Pin 1 Ground
Pin 2 +Vdd
Pin 3 FN
Pin 4 IN
Pin 5 SG
Pin 6 +Vdd
Pin 7 Ground
Pin 8 Source
Pin 9 Drain
Pin 10 Source
